CN1302379C - Conditioned control management device and method - Google Patents
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- CN1302379C CN1302379C CNB2003101093151A CN200310109315A CN1302379C CN 1302379 C CN1302379 C CN 1302379C CN B2003101093151 A CNB2003101093151 A CN B2003101093151A CN 200310109315 A CN200310109315 A CN 200310109315A CN 1302379 C CN1302379 C CN 1302379C
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Abstract
The present invention provides a condition controlling and managing device used in a data processing system and a method. The managing device comprises a plurality of condition registers and a managing unit, wherein a plurality of conditional operation results are stored by the condition registers; the managing unit is provided with an operational circuit and a gating circuit. Each conditional operation result of the condition registers is operated by the operational circuit according to a condition required by a conditional instruction. The selected operation result is output by the gating circuit according to the result obtained by the operation of the operational circuit under the control of an operation gating signal so as to be used as an output control signal of the managing unit. The operation to the conditional instruction is executed by an executing unit which controls the data processing system. The conditional instruction in the present invention is a conditional execution instruction or a conditional skip instruction.
Description
Technical field
The present invention relates to field of microprocessors, especially relate to a kind of apparatus and method of management condition control in microprocessor.
Background technology
Microprocessor carries out data processing with many instructions of continuous execution, and usually can introduce many streamlines and simultaneously many instructions be operated in the same clock period, improves data processing speed with this.But the processing procedure of instruction is not always carried out in regular turn, and the instruction that has is to require will to jump to certain address behind the certain condition and carry out new instruction having satisfied, and this instruction of carrying out redirect according to certain condition is called the condition jump instruction.It is to require just to carry out some given instructions behind the certain condition having satisfied that some instructions are also arranged, and this instruction is called conditional execution instruction.Condition jump instruction and conditional execution instruction can be referred to as conditional order.
Thisly to carry out or the instruction of condition redirect in order carrying out more efficiently, condition register can be set in processor according to the certain condition condition of carrying out.Correspondingly, can some condition steering orders of specialized designs, whether certain condition satisfied judge, when condition satisfies, promptly to this condition register assignment.So just can directly utilize the value of condition register to judge whether to meet some requirements, whether carry out the operation of conditional execution instruction or condition jump instruction with decision.
Yet in the data handling procedure of reality, the condition that is used for judging is often varied, if for the condition of every kind of condition or most of kinds all is provided with a special condition steering order, obviously is real inadequately.Because most of frequencies of utilization are not too high in these instructions, that is to say that the usable range of itself just has certain restriction; Simultaneously also can make instruction set huger, and corresponding decoding unit also become and can get more complicatedly, has just reduced the whole efficiency of instruction set thus.
In more existing processors, adopted another kind of processing mode, they are not when the condition of carrying out comparatively designs special condition steering order in complexity or the instruction set or when the condition of back one conditional execution instruction may be with the value of and needs temporary transient reserve register relevant in the conditional operation result of the conditional order of preceding execution, just the value of condition register is changeed to compose and give general-purpose register, general-purpose register is carried out operations such as logical operation according to the mode of operation of general data computing, again the value that arithmetic operation obtains is composed again to condition register.This processing mode need be carried out extra arithmetic operation for condition judgment, is unfavorable for the reduction of power consumption of processing unit; To additionally increase assignment in addition, carry out arithmetic operation and write back to the time overhead of condition register, also influence instruction process speed on the whole.
In the processor of VLIW (very long instruction word) system, a plurality of sub-instructions in 1 instruction bag can parallel processing; And carry out in the system of instruction process in pipeline organization, have many instructions in the same instruction cycle and handling with pipeline system in regular turn.Under such situation, if it is conditional execution instruction or condition steering order that many sub-instructions are arranged simultaneously, just cause conflict probably for condition register, particularly comparatively complicated or do not have the system of special condition steering order for condition, if adopted the method for carrying out conditional operation with assignment to general-purpose register in the prior art, may have a plurality of sub-instructions and require to carry out conditional operation simultaneously, like this, be easy to cause the streamline conflict, cause the obstruction of streamline; Also can require the programmer to be forced to consider which instruction can executed in parallel on the other hand, how avoid the conflict of streamline, increase the weight of programmer's burden.And the programmer is the conflict of avoiding streamline, only is for the temporal delay of streamline, just need insert insignificant sky (NOP) instruction on software, all can affect from power consumption and processing speed two aspects thus.
Carry out the problem of inefficiency for overcoming the instruction of in the prior art needs foundation being handled the judged result of condition, the present invention proposes a kind of condition control management device and a kind of condition control and management method.
Summary of the invention
The object of the present invention is to provide a kind of condition control management device and a kind of condition control and management method, improve in the data processing needs such as conditional execution instruction and condition jump instruction according to the execution efficient of the instruction that the judged result of condition is handled, and the conflict of minimizing streamline.
The technical solution adopted in the present invention is that a kind of condition control management device is set in data handling system.This device comprises a plurality of condition register of depositing a plurality of conditional operation results, and administrative unit.Administrative unit has computing circuit and the gating circuit that each conditional operation result of above-mentioned a plurality of condition register is directly carried out computing according to the condition of conditional order requirement, and the gating circuit result that computing obtains according to computing circuit sends the operation of the performance element of control signal control data disposal system to conditional order under the control of computing gating signal.
Wherein above-mentioned conditional operation result is a logical value, and the computing that administrative unit is directly carried out above-mentioned conditional operation result is logical operation.
The control signal that gating circuit in the administrative unit of condition control management device sends is divided into enable signal and enable signal not.The performance element of data handling system responds control signal, when control signal is enable signal, will carry out the operation of conditional order; When control signal during, will carry out next bar instruction of this conditional order for enable signal not.
Condition control and management method provided by the invention is earlier conditional order to be decoded, and more decoded conditional order is sent into the condition control management device.The condition control management device is sent into administrative unit to a plurality of operation results of depositing in a plurality of condition register, and according to the desired condition of conditional order a plurality of conditional operation results that send into is carried out computing, generates control signal.Administrative unit is given the performance element of data handling system control signal then.If the control signal that the performance element of data handling system obtains is an enable signal, will carry out the operation of conditional order; If the control signal that performance element obtains is enable signal not, will carry out next bar instruction of this conditional order.
Among the present invention, above-mentioned logical operation be with or, non-or non-, NAND Logic computing.Above-mentioned computing circuit also can be logical not component, comparator circuit or combinational logic circuit.
Among the present invention, described conditional order is conditional execution instruction or condition jump instruction.
The invention provides a plurality of condition register, and the condition of employing control management device is directly carried out computing and control to condition register, can satisfy the demand of a plurality of conditional order executed in parallel, especially the multidiameter delay computing power with VLIW (very long instruction word) system is complementary, help reducing multiple instruction issuable conflict when parallel, like this, not only improve the ability of algorithm optimization, also accelerated the processing speed of conditional order greatly.
Description of drawings
The following drawings is the aid illustration to exemplary embodiment of the present, to the elaboration of the embodiment of the invention, be to disclose feature of the present invention place, but do not limit the present invention in conjunction with the following drawings for further, same numeral is represented respective element or step among the embodiment among the figure, wherein:
Fig. 1 is for implementing the structural representation of a digital information processing system of the present invention.
Fig. 2 is the structural drawing of condition control management device of the present invention.
Fig. 3 is the process flow diagram of condition control and management method of the present invention.
Embodiment
Figure 1 shows that a kind of structural representation of exemplary digital information processing system.This system comprises data-carrier store 11, command memory 12, instruction buffer 13, demoder 14, data address generation unit 15, control register 16 and performance element 17.Data-carrier store and command memory be loading data and instruction respectively.During execution command, earlier, send into instruction buffer, send into demoder from the instruction buffer order again and instruct decoding from the corresponding address instruction fetch of command memory.The instruction that has also can directly instruction fetch from instruction buffer, directly sends into demoder again and instructs decoding.Send the data address generation unit after the instruction decoding to and produce data address, corresponding data address is fetched data and is loaded into performance element and carries out computing in data-carrier store then.Instruct decoded control signal to be sent to control register, order that control register is carried out instruction or state etc. are coordinated and are managed.Can comprise address register, offset register, delivery register etc. in the disclosed control register, also can comprise various zone bit registers, as overflow indicator bit register, carry flag bit register etc.And in order to judge and to carry out various conditional orders (comprising conditional execution instruction and condition jump instruction), also can be in control register the configuration condition register, the result of storage condition computing.Like this, to conditional execution instruction or the condition jump instruction that will carry out, can directly utilize and the condition in the condition register judged determine whether carrying out or redirect.And for after conditional order, if consistent in the condition that requires and the condition register, then no longer need to carry out again conditional operation, and can directly utilize the value of depositing of condition register to judge.As those of skill in the art are known, also can not exclusively comprise data-carrier store, command memory, instruction buffer, demoder, data address generation unit etc. in the digital information processing system, on the other hand, digital information processing system also can be realized with microprocessor.
In an embodiment of the present invention, control register has the condition control management device.As shown in Figure 2, the condition control management device comprises first condition register T0, second condition register T1 and administrative unit 20.First condition register T0 and second condition register T1 are 1 zone bit register.Instruction set can be provided with various condition steering orders and carry out all kinds of logical operations, and operation result then sends into first condition register T0 and second condition register T1 deposits.And instructions such as assignment statement can be rewritten the value of first condition register T0 and second condition register T1 equally.For the parallel mother's instruction of two condition sub-instructions is arranged, can send into first condition register T0 and second condition register T1 to the operation result that obtains respectively.The quantity of condition register and unrestricted in the system, for example, in the instruction set of VLIW (very long instruction word) system, article one, comprise many sub-instructions that can carry out simultaneously in female instruction, if have more condition sub-instructions parallel in female instruction, then can more condition register be set according to actual demand, therefore the present invention is not limited to only have two condition register, those of ordinary skill in the art can be provided with a plurality of condition register fully as required, and this does not exceed scope of the present invention.
At this, be that example is explained the condition steering order with " comparing data register " instruction (CMPD), and the first condition operation result deposited among first condition register T0 and the second condition register T1 and the acquisition of second condition operation result be described with this.
" comparing data register " instruction (CMPD) compares the value of data register, and gives first condition register T0 or second condition register T1 the result who relatively judges.Be provided with 8 data registers in the present embodiment, be respectively: DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7.Below be three types CMPD instruction:
(1)CMPD{GTS|LTS|EQ}<DRX>，<DRY>，<Tn>
Wherein, GTS represent " greater than ", LTS represent " less than ", EQ represents " equaling ", DRX and DRY are (wherein, X=0,1,2 ..., 7, Y=0,1,2 ..., 7, and X is not equal to Y) represent the value of first data register and the value of second data register respectively, wherein, first and second data registers can be any two the data registers in above-mentioned 8 data registers, and those skilled in the art can in the light of actual conditions select fully.Tn indicates that this condition steering order will rewrite is T0 or T1, those skilled in the art can be provided with the value of Tn and the corresponding relation of T0 and T1 fully as required, for example, Tn be indicated that this condition steering order will rewrite at 0 o'clock for T0, Tn are that indicated that this condition steering order will rewrite at 1 o'clock is T1, vice versa.This order format is as follows:
| OC | 1 | 0 | 1 | 0 | 1 | 1 | m | m | Tn | e | e | e | E | E | E |
Wherein, OC is an instruction operation code, for example can be used on the existence of this sub-instructions of indication in the parallel sub-instructions, and this is known in the art.Eee is the value of the first data register DRX, and EEE is the value of the second data register DRY.Mm optionally value is GTS/LTS/EQ, and coding is respectively 00/01/10.This instruction is that the value to the value of first data register and second data register compares, the result for mm then Tn put 1, otherwise put 0.
(2)CMPD{GTS|LTS|EQ}<DRX>，#<imm3>，<Tn>
Wherein, GTS, LTS, EQ meaning are the same; DRX represents the value of any data register in above-mentioned 8 data registers, and imm3 represents that signless 3 are counted immediately, and Tn indicates that this condition steering order will rewrite is T0 or T1.This order format is as follows:
| OC | 1 | 0 | 1 | 1 | 1 | 0 | m | m | Tn | e | e | e | I | I | I |
OC is an instruction operation code, for example can be used on the existence of this sub-instructions of indication in the parallel sub-instructions.Eee is the value of data register, and III is 3 a numerical value immediately.Mm optionally value is GTS/LTS/EQ, and coding is respectively 00/01/10.This instruction be the value of data register DRX and one signless 3 immediately number compare, the result for mm then Tn put 1, otherwise put 0.
(3)CMPD{GTU|LTU|EQ}<DRX>，#<imm16>，<Tn>
Wherein, GTU, LTU represent " greater than unsigned number " and " less than unsigned number " respectively, and the EQ meaning is the same; DRX represents the value of data register, and imm16 represents that 16 are counted immediately, and Tn indicates that this condition steering order will rewrite is T0 or T1.Order format is as follows:
| ? |
11 | 1 | 1 | 0 | 1 | m | m | Tn | i | i | i | A?A?A | oc2 | 00 | i i i i i i i i i i i i i |
OC1, OC2 are instruction operation code, for example can be used on the existence of this sub-instructions of indication in the parallel sub-instructions.AAA is the value of data register BRX, and 16 i characterize one signless 16 and count immediately.Mm optionally value is GTU/LTU/EQ, and coding is respectively 00/01/10.This instruction is that the value of data register and one are compared by the value that the number expansion immediately of 16 no symbols forms, the result for mm then Tn put 1, otherwise put 0.
First condition register T0 and second condition register T1 can deposit the conditional operation result of similar and different condition steering order respectively.The data of depositing among first condition register T0 and the second condition register T1 can be called first condition operation result and second condition operation result.After the condition steering order is made amendment to first, second condition register T0, T1, conditional order can according to first or second condition register T0 or T1 in first condition operation result or the second condition operation result deposited carry out or skip operation.If first or the value of second condition operation result be 1, the condition of expression conditional execution instruction (or condition jump instruction) is met, and can carry out the operation of conditional execution instruction (or condition jump instruction); If first or the value of second condition operation result be 0, expression conditional execution instruction (or condition jump instruction) condition does not satisfy, the no longer operation that requires of executive condition execution command (or condition jump instruction), but leap to next bar instruction of conditional execution instruction (or condition jump instruction).At this, the condition steering order is the modification of dominance to first, second condition register T0, T1, condition register is after modification, short of other condition steering order is made amendment to this first, second condition register T0, T1, can directly quote the value of first, second condition register T0, T1 according to the conditional execution instruction (or condition jump instruction) of this condition steering order after so.Therefore, can after the condition steering order, insert other instruction, and still can directly quote the value of first, second condition register T0, T1, and can there be many conditional execution instructions (or condition jump instruction) directly to quote the value of first, second condition register T0, T1 according to this condition steering order according to the conditional execution instruction (or condition jump instruction) of this condition steering order.Conditional execution instruction described here and condition jump instruction can be referred to as conditional order, and this is that those skilled in the art is to understand.
The recessive statement of administrative unit in the condition control management device is to the modification of condition register.When not dominance modification first of needs, second condition register T0, the value of T1, for example to insert a conditional order (comprising conditional execution instruction and condition jump instruction) in according to the conditional order of identical conditions steering order at many according to other condition steering orders, perhaps when the condition of conditional order institute foundation can't directly be obtained by the concentrated defined condition steering order of system directive, administrative unit can be to first, second condition register T0, T1 carries out the various logic computing, writes back to first again and needn't change to give general-purpose register and carry out computing in the arithmetic operation unit (ALU) of system, second condition register T0, T1.As shown in Figure 2, the value among first, second condition register T0, the T1 is sent into administrative unit, carry out logical operation by administrative unit after, send control signal (carry out control signal or redirect control signal).The control signal that administrative unit is sent in the present embodiment is a binary signal, be divided into enable signal (carry out enable signal or redirect enable signal) and enable signal (not carrying out signal or not redirect signal) not, control signal responded by the performance element of data handling system.In the present embodiment, when control signal is 1, be enable signal, the condition that indicates conditional order institute foundation is met, and can carry out the corresponding fill order of conditional order; When control signal is 0, be not enable signal, the condition that indicates conditional order institute foundation is not met, thereby next bar of leaping to conditional order instructs, and no longer conditional instructions requires the instruction handle, it is enable signal that yet those skilled in the art also can be arranged to when control signal is 0 as required, is enable signal not when control signal is 1.
Present embodiment is that example describes with the conditional execution instruction.Conditional execution instruction is the if*cc form, and wherein * is the Rule of judgment of conditional execution instruction in executive condition order time institute foundation, and cc is the operation that will carry out after satisfying condition.* Rule of judgment mainly contains following several arithmetic type:
(1) [T0], it is encoded to 00010, and implication is if T0 True do, and promptly T0 is a true time, and condition satisfies;
(2) [! T0], it is encoded to 00011, and implication is if T0 False do, and promptly T0 is a fictitious time, and condition satisfies;
(3) [T1], it is encoded to 00110, and implication is if T1 True do, and promptly T1 is a true time, and condition satisfies;
(4) [! T1], it is encoded to 00111, and implication is if T1 False do, and promptly T1 is a fictitious time, and condition satisfies;
(5) [T0||T1], it is encoded to 01000, implication is if[T1, T0]!=00 do, promptly one of them is a true time at least for T0 or T1, condition satisfies;
(6) [! T0||T1], it is encoded to 01001, implication is if[T1, T0]!=01 do, promptly! One of them is a true time at least for T0 or T1, and condition satisfies;
(7) [T0||! T1], it is encoded to 01010, implication is if[T1, T0]!=10 do, promptly T0 or! At least one of them is a true time to T1, and condition satisfies;
(8) [! T1], it is encoded to 01011, implication is if[T1, T0]!=11 do, promptly! T0 or! At least one of them is a true time to T1, and condition satisfies;
(9) [T0﹠amp; ﹠amp; T1], it is encoded to 01111, implication is if[T1, T0]==11 do, promptly T0 and T1 the two be true time, condition satisfies;
(10) [! T0﹠amp; ﹠amp; T1], it is encoded to 01110, implication is if[T1, T0]==10 do, promptly! T0 and T1 person are true time, and condition satisfies;
(11) [T0﹠amp; ﹠amp; T1], it is encoded to 01101, implication is if[T1, T0]==01 do, promptly T0 and! The two is true time T1, and condition satisfies;
(12) [! T0﹠amp; ﹠amp; T1], it is encoded to 01100, implication is if[T1, T0]==00 do, promptly! T0 and! The two is true time T1, and condition satisfies.
12 types coding of conditional execution instruction wherein is directly corresponding to the computing gating signal, and the computing circuit of administrative unit also comprises the logical circuit of above-mentioned 12 kinds of arithmetic types accordingly.The operation result that computing gating signal control multiplexer selects the logical circuit of corresponding arithmetic type to send, thereby arithmetic type that can the controlled condition register.In one embodiment of the invention, for each arithmetic type is provided with special logical circuit, therefore can satisfy actual computing demand in the computing circuit by the quantity increase and decrease of logical circuit.Because with or, logical circuit such as non-is technology well known in the art, do not do too much description at this.In other embodiments, arithmetic type also can be adjusted according to the computing demand of reality, for example can directly connect up by the physical circuit that changes computing circuit and realize that this implementation method also is known in the art.
The prefix part of conditional execution instruction (prefix) characterizes instruction with T and whether carries out and adopt what kind of executive mode, like this, to conditional execution instruction the decode stage of multi-stage pipeline can be according to first condition register T0 or/and the value of second condition register T1 determine whether carrying out.For there being many different condition execution commands to require situation about handling on the multi-stage pipeline simultaneously, at least just can utilize the condition register of two dominance, be first condition register T0 and second condition register T1, have recessive administrative unit to come Rule of judgment whether to satisfy in addition.On the other hand, the quantity of condition register can dispose according to the requirement of system and instruction set, and this is that those skilled in the art institute is understandable.
Be understandable that, utilization conditions such as condition jump instruction do to judge that the instruction of handling is similar to conditional execution instruction, be after certain condition has been satisfied in judgement, promptly to have jumped to other instruction, therefore, can be applicable to these condition jump instructions so that Rule of judgment is effectively controlled like the condition control and management unit class of the present invention, this is conspicuous for the person of ordinary skill of the art, therefore, repeats no more here for the description of condition jump instruction.
The execution in step of condition control and management method provided by the invention can be referring to Fig. 3.Step S1 in this method is that the conditional order of utilizing demoder that instruction buffer is sent is deciphered.Step S2 sends into the condition control management device to the conditional order after deciphering.Among the step S3 condition control management device according to the desired condition of conditional order first condition register T0 or/and the conditional operation result of second condition register T1 sends into the administrative unit of condition control management device, the gating control signal selects corresponding computing circuit to carry out computing in administrative unit through the gating circuit (being multiplexer) of administrative unit.Step S4 generates control signal to the operation result of computing circuit in the administrative unit after via multiplexer, gives performance element.Performance element is according to control signal among the step S5, and control is to the operation of instruction, and described control signal is a binary signal, represent not enable signal with 1 expression enable signal, 0, or vice versa.The control signal that the performance element of data handling system obtains is an enable signal, operation that will conditional instructions; The control signal that performance element obtains is enable signal not, next bar instruction that will conditional instructions.In the method, described conditional order is conditional execution instruction or condition jump instruction.
Present embodiment is just in order further more clearly to describe the present invention, but not limitation of the present invention.For example, the present invention is not limited to specific digital information processing system, equally also can use the present invention in other different control system or data handling system.Be to be understood that the present invention is not limited to the elaboration that embodiment does, anyly all should be included within the spirit and scope in this invention based on modification of the present invention and equivalent of the present invention.
Claims (10)
1. condition control management device that is used for data handling system, described data handling system has control register and performance element, described condition control management device is contained in the described control register, it is characterized in that, described condition control management device comprises:
Deposit a plurality of condition register of a plurality of conditional operation results; And
Administrative unit,
Wherein, described administrative unit has computing circuit and gating circuit, the condition that described computing circuit requires according to conditional order is carried out computing to each conditional operation result of above-mentioned a plurality of condition register, the result that described gating circuit obtains according to described computing circuit computing exports the operation result the chosen output control signal as administrative unit under the control of a computing gating signal, carry out operation to conditional order with the performance element that is used to control described data handling system.
2. condition control management device as claimed in claim 1 is characterized in that, described computing circuit is a logical operation circuit, and described conditional operation result is a logical value.
3. condition control management device as claimed in claim 2 is characterized in that, described logical operation circuit comprise with or, in non-or non-, the and not circuit one or more.
4. condition control management device as claimed in claim 1 is characterized in that, described computing circuit is any in logical not component, comparator circuit or the combinational logic circuit.
5. condition control management device as claimed in claim 1 is characterized in that, described gating circuit is a multiplexer.
6. as the described condition control management device of above-mentioned each claim, it is characterized in that, the output control signal of described administrative unit is divided into enable signal and enable signal not, the performance element of described data handling system responds described output control signal, when described output control signal is enable signal, carry out the operation of conditional order,, carry out next bar instruction of this conditional order when described output control signal during for enable signal not.
7. condition control management device as claimed in claim 6 is characterized in that, described conditional order is conditional execution instruction or condition jump instruction.
8. condition control and management method that is used for data handling system, described data handling system has control register and performance element, includes the condition control management device in described control register, it is characterized in that, said method comprising the steps of:
Conditional order is decoded;
Decoded conditional order is sent into the condition control management device, and wherein said condition management devices has a plurality of condition register and an administrative unit;
The a plurality of conditional operation results that deposit in described a plurality of condition register are sent into administrative unit, have computing circuit and gating circuit in the administrative unit, described computing circuit carries out computing to a plurality of conditional operation results that sent into, and gating circuit is selected the output control signal of operation result as the administrative unit of condition management devices according to the computing gating signal;
Administrative unit is given the performance element of data handling system the output control signal;
The performance element of data handling system is according to the operation of described output control signal conditional instructions.
9. condition control and management method as claimed in claim 8, it is characterized in that, the output control signal of described administrative unit is divided into enable signal and enable signal not, the performance element of described data handling system responds described output control signal, when described output control signal is enable signal, carry out the operation of conditional order,, carry out next bar instruction of this conditional order when described output control signal during for enable signal not.
10. condition control and management method as claimed in claim 8 or 9 is characterized in that described conditional order is conditional execution instruction or condition jump instruction.
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| US8069339B2 (en) * | 2009-05-20 | 2011-11-29 | Via Technologies, Inc. | Microprocessor with microinstruction-specifiable non-architectural condition code flag register |
| CN101859325B (en) * | 2010-06-07 | 2012-07-11 | 华为技术有限公司 | Method and device for searching and processing data table items |
| CN102566975A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Device, method and processor for processing branch skipping of skipping path |
| EP2508980B1 (en) * | 2011-04-07 | 2018-02-28 | VIA Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
| CN113485748B (en) * | 2021-05-31 | 2022-08-12 | 上海卫星工程研究所 | Satellite condition instruction system and execution method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001344100A (en) * | 2000-06-02 | 2001-12-14 | Sharp Corp | Central processing unit equipped with plural flag registers |
| US6647489B1 (en) * | 2000-06-08 | 2003-11-11 | Ip-First, Llc | Compare branch instruction pairing within a single integer pipeline |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001344100A (en) * | 2000-06-02 | 2001-12-14 | Sharp Corp | Central processing unit equipped with plural flag registers |
| US6647489B1 (en) * | 2000-06-08 | 2003-11-11 | Ip-First, Llc | Compare branch instruction pairing within a single integer pipeline |
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