CN1275416C

CN1275416C - Automatic-protecting switching device for multi-point clock synchronizing system

Info

Publication number: CN1275416C
Application number: CN 01112721
Authority: CN
Inventors: 朱波
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2001-04-26
Filing date: 2001-04-26
Publication date: 2006-09-13
Anticipated expiration: 2021-04-26
Also published as: CN1383287A

Abstract

The present invention provides an automatic protection switching device of a multipoint clock synchronization system, which comprises two identical clock source units and a plurality of clock allocation units, wherein the clock source units are arranged on a clock plate which comprises a PECL clock source and a distributor of a PECL clock phase locked loop. The clock allocation units are positioned on each system single plate which comprises a PECL phase locked loop driver with a redundant clock source and a plurality of PECL-TTL level switch clock distributors. The present invention has the advantages of stronger interference rejection, low deflection and high stability, and can realize the smooth switchover between main clock sources and backup clock sources.

Description

The automatic-protecting switching device of multi-point clock synchronizing system

Technical field

The present invention relates to multi-point clock synchronizing system in the communication field, relate in particular to the system synchronization clock automatic-protecting switching device in this field.

Background technology

Along with the rapid expansion with the application of electronic technology scope of improving constantly of electronic technology level, the requirement to synchronised clock in circuit design is also more and more higher.Especially at communication field, arrival along with digital Age, requirement to the bandwidth of transfer of data and processing is more and more higher, thereby make that the frequency of synchro system is also more and more higher, this has just proposed more and more higher requirement to the clock of system, because each unit in the clock system is to distribute on the veneer that spatially comparatively disperses, so be called multi-point clock synchronizing system.At present, the synchronised clock of multi-point clock synchronizing system directly adopts the clock source of Transistor-Transistor Logic level, drive after backboard is transferred to each veneer by clock distributor, on the veneer through a phase-locked loop after reallocation use for the next stage device.Simultaneously, in the design of active and standby auto switching, just realize the masterslave switchover control of clock by the active and standby control signal of system with an either-or switch controller.So make the clock system of design in this way exist following deficiency: 1,, to be subjected to the interference of external environment easily owing on backboard, the Transistor-Transistor Logic level signal is grown Distance Transmission; 2, in whole clock system, owing to do not compensate through multistage transmission and distribution, just might be because the difference that the length of each veneer wiring exists, thus cause arriving the final bigger deflection that occurs when using device at clock; 3, in the reversed process of master/backup clock,, may cause clock phase sudden change in handoff procedure, to occur owing to be between active and standby two-way clock, directly to switch.

Summary of the invention

The objective of the invention is to propose a kind ofly to have stronger antijamming capability and low deflection, high stability and can be implemented in the multi-point clock synchronizing system automatic-protecting switching device that takes over seamlessly between the master/backup clock source, effectively to overcome the clock that in the process of active and standby switching, occurs in the prior art significantly deflection and unsettled shortcoming.

The automatic-protecting switching device of multi-point clock synchronizing system of the present invention comprises two clock source units and a plurality of clock distribution unit;

Described two clock source units have identical structure, lay respectively at the master of system, be equipped with on two clock boards, each clock source unit comprises: PECL (Positive Emitter Coupled Logic, positive emitter coupled logic) clock source and the phase-locked distributor of PECL clock, described PECL clock source (adopting the differential clocks crystal oscillator) produces a pair of PECL clock signal, send the phase-locked distributor of described PECL clock to, the phase-locked distributor of described PECL clock converts received PECL clock signal to many to the PECL clock signal, and these PECL clock signals are transferred to each system single board respectively as the clock source through System Backplane;

Described clock distribution unit is positioned on each system single board, clock distribution unit on each system single board comprises: PECL phase-locked loop driver and a plurality of PECL-TTL level conversion clock distributor in a band redundancy clock source, the PECL phase-locked loop driver in described band redundancy clock source receives the master simultaneously, be equipped with two pairs of PECL clock signals, between two pairs of PECL clocks, switch dynamically according to signal quality, the PECL clock signal of phase-locked input simultaneously, output multichannel PECL clock signal is given each PECL-TTL level conversion clock distributor, and described PECL-TTL level conversion clock distributor uses each device that the conversion of signals that receives becomes the clock signal of Transistor-Transistor Logic level to export on this plate.

Description of drawings

Below in conjunction with drawings and Examples the automatic-protecting switching device that the present invention constructed is described further:

Fig. 1 is the clock source unit structured flowchart in the device of the present invention;

Fig. 2 is the clock distribution cellular construction block diagram in the device of the present invention;

Fig. 3 is the automatic-protecting switching device structured flowchart that the present invention constructs.

Embodiment

Automatic-protecting switching device of the present invention shown in Figure 3 comprises clock source unit that is positioned on the clock board and the clock distribution unit that is positioned on the veneer, respectively as depicted in figs. 1 and 2.

In the clock source unit structure chart of clock board shown in Figure 1, the clock source of each veneer in the whole system is all provided by active and standby clock board redundancy.On clock board, produce a pair of PECL clock signal by a differential clocks crystal oscillator (PECL clock source), phase-locked and distributor can obtain a plurality of stable PECL clocks through PECL clock, and these PECL signals are transferred to the clock source of each veneer as each veneer through System Backplanes.If PECL clock is phase-locked and the quantity of the PECL clock signal of distributor output can not satisfy the needs of system, can be with a plurality of, but should reduce the distributor number and with the big distributor of distribution ratio as far as possible.When wiring, must guarantee length of arrangement wire unanimity from the differential clocks crystal oscillator to the phase-locked distributor of each PECL clock, and the output pin of the phase-locked distributor of each PECL clock so just can make the deflection between the PECL clock source that offers each veneer reduce to the length of arrangement wire unanimity of backboard pin.

Shown in Figure 2 is the clock distribution cellular construction schematic diagram of each veneer.The clock distribution unit is positioned on each veneer of system.With a veneer is example, mainly comprises: PECL phase-locked loop driver and a plurality of PECL-TTL level conversion clock distributor in a band redundancy clock source.Each veneer receives active and standby two pairs of PECL clock signals simultaneously by the PECL phase-locked loop driver in band redundancy clock source, at any time between two pairs of PECL clocks, switch according to signal quality, and the clock signal of phase-locked input, output multichannel PECL clock signal is given different PECL-TTL level conversion clock distributors.The difference of mating length of arrangement wire on the different veneers by a pair of PECL clock feedback signal on PECL phase-locked loop driver can be reduced in the deflection (description that will be detailed in the principle of ensuing clock line length coupling) between each PECL clock that arrives PECL-TTL level conversion clock distributor on the veneer like this.PECL clock signal from the output of PECL phase-locked loop driver, be responsible for reception by PECL-TTL level conversion clock distributor, and each device that the clock signal that converts Transistor-Transistor Logic level to is exported on this plate uses, why will be after PECL clock source is input to each veneer through a TTL circuit, be because need carry out shaping to input clock, taking over seamlessly when can be implemented in clock active/standby in addition and switch.Comprise a TTL circuit on the PECL-TTL level conversion clock distributor,, mate with at the difference of distributor to length of arrangement wire between the different components, thus the deflection between the clock of each device of reduction arrival.The PECL phase-locked loop driver in the band redundancy clock source on each veneer need be controlled by the CPU of system, simultaneously with the CPU of the clock source state notifying system of this plate.The signal of Jiao Liuing comprises between the two: one is the reset signal of the PECL phase-locked loop driver in band redundancy clock source, and system CPU is given reset signal of each veneer.If in the original PECL clock signal in back working properly since external interference occur undesired, then the PECL phase-locked loop distributor with the redundancy clock source can switch to the clock source the second road PECL clock, notify CPU simultaneously, provide the PECL phase-locked loop distributor in reseting signal reset band redundancy clock source by CPU, if original PECL clock has recovered normal (generally being like this) this moment, then the clock source can be switched back original PECL clock.If original PECL clock does not still have recovery normal this moment, then still select for use the second road PECL clock as the clock source.Be two PECL clock source status signals in addition, the PECL phase-locked loop distributor in the band redundancy clock source on each veneer, by these two PECL clock source status signal reporting system CPU, report this moment two-way clock source good or bad.

The principle of the line length coupling of once following in wiring is described below in conjunction with clock protection changeover apparatus of the present invention shown in Figure 3.For the design of plate level, if the synchronised clock frequency is higher, and stability and deflection there are requirement, in the clock circuit wiring, just should consider the coupling of line length so.The PECL phase-locked loop distributor and the PECL-TTL transducer in the band redundancy clock source on each veneer all should be selected identical device for use, can guarantee less deflection like this.The length of arrangement wire on the identifier list timberline road on each clock line feeds back by two-stage on veneer and compensates because the caused clock length of layout of each device inconsistent.Its basic principle is as follows:

The PECL phase-locked loop distributor in described band redundancy clock source contains phase-locked loop circuit, so under the situation of steady operation, the reference clock input and the feedback clock input of the PECL phase-locked loop distributor in band redundancy clock source are homophases, can draw following formula:

Suppose that clock transfer is Ta to the time that a is ordered, being transferred to the time that b orders is Tb, then:

Ta+Y’＝Tb-P’+Y’+P’

Can draw Ta=Tb thus.

As can be seen, in full accord for do not need restraint their the clock line wiring of different veneers, still can guarantee that the b point has identical phase place with a point on each veneer, as long as guarantee the length of arrangement wire unanimity of the output pin of the phase-locked distributor of each PECL clock to the backboard pin on clock board, the b point that just can obtain on all veneers has identical phase place.Like this, can eliminate because the deflection of the different caused clock phases of veneer wiring.In PECL-TTL transducer part, adopted the method for same feedback compensation to eliminate the delay variation that wiring brings, the circuit delay of the identical sign representative in the same veneer shown in Fig. 3 is identical, can be different between the different veneers.

Below in conjunction with embodiment the device that the present invention constructed is further described.

The band redundancy clock source PECL phase-locked loop distributor of this device has been selected the PECL clock phase-locked loop distributor of a Motorola for use.This device receives two different (active and standby) PECL clock inputs, the input signal of its alternative is provided with by hardware by an input signal on the device, when detecting PECL clock source quality and degenerate, can automatically switch to another clock source, road, because the phase-locked loop circuit that adopts has clamping action, can make that the phase place of each veneer is progressively consistent with clock board, so this process is automatic, level and smooth.The PECL phase-locked loop distributor in the band redundancy clock source on each veneer is good or bad by status signal notice CPU two-way clock this moment source, two PECL clock sources.The PECL phase-locked loop distributor in this band redundancy clock source also has a reset signal to be used for removing PECL clock source because the alarm of the bad generation of signal quality is indicated simultaneously, and this signal is controlled by CPU.

The workflow of this clock system automatic-protecting switching device is as follows: at first be reseting procedure; system powers on; each Board Power up; two clock boards are stably exported two-way PECL clock source; PECL phase-locked loop distributor choosing folding one road PECL clock signal in band redundancy clock source on each veneer, on each veneer by being set to select identical PECL clock source on the hardware.CPU provides the PECL phase-locked loop distributor in signal reset strap redundancy clock source, and after this whole clock system just is in steady-working state.After working properly, if original PECL clock signal is because the external interference appearance is undesired, then the PECL phase-locked loop distributor with the redundancy clock source can switch to the clock source the second road PECL clock, notify CPU simultaneously, provide the PECL phase-locked loop distributor in reseting signal reset band redundancy clock source by CPU, if original PECL clock has recovered normal (generally being like this) this moment, then the clock source can be switched back original PECL clock.If original PECL clock does not still have recovery normal this moment, then still select for use the second road PECL clock as the clock source.Because the PECL phase-locked loop distributor in band redundancy clock source has a phase-locked loop circuit after the input of two-way PECL clock source, so this process is automatic, level and smooth, can make clock phase from former clock source phase place progressively to new clock source phase alignment.

The automatic-protecting switching device of the multi-point clock synchronizing system that the present invention proposes adopts the PECL signal to grow the transmission of distance on backboard, has improved the ability of clock system opposing external interference, has advantages of higher stability.While retrains and compensates clock line in the process of the wiring of the circuit of clock circuit, can guarantee lower phase skew.In addition, the present invention has realized taking over seamlessly of clock signal in the process that clock active/standby is switched, and has reduced because the system failure probability that the flip-flop of clock phase causes.Especially many for synchronised clock quantity, the system of long transmission distance, a kind of especially good solution of the present invention.

Comprehensively above-mentioned, the present invention is that high-velocity electrons system, especially high rate data communication system have proposed when a kind of Clock reaches the solution of APS synchronously, has low deflection, high stability, active and standby switching automatic smoothing Characteristics.

Claims

1, a kind of automatic-protecting switching device of multi-point clock synchronizing system is characterized in that, comprises two clock source units and a plurality of clock distribution unit;

Described two clock source units have identical structure, lay respectively on active and standby two clock boards of system, each clock source unit comprises: PECL clock source and the phase-locked distributor of PECL clock, described PECL clock source produces a pair of PECL clock signal, send the phase-locked distributor of described PECL clock to, the phase-locked distributor of described PECL clock converts received PECL clock signal to many to the PECL clock signal, and these PECL clock signals are transferred to each system single board respectively as the clock source through System Backplane;

Described clock distribution unit is positioned on each system single board, clock distribution unit on each system single board comprises: PECL phase-locked loop driver and a plurality of PECL-TTL level conversion clock distributor in a band redundancy clock source, the PECL phase-locked loop driver in described band redundancy clock source receives the master simultaneously, be equipped with each a pair of PECL clock signal, leading dynamically according to signal quality, be equipped with the PECL clock signal between switch, the PECL clock signal of phase-locked input simultaneously, output multichannel PECL clock signal is given each PECL-TTL level conversion clock distributor, and described PECL-TTL level conversion clock distributor uses each device that the conversion of signals that receives becomes the clock signal of Transistor-Transistor Logic level to export on the native system veneer.

2, automatic-protecting switching device according to claim 1 is characterized in that, the differential clocks crystal oscillator is adopted in described PECL clock source.

3, automatic-protecting switching device according to claim 1 is characterized in that, the output pin of the phase-locked distributor of described PECL clock is to the length of arrangement wire unanimity of backboard pin.

4, automatic-protecting switching device according to claim 1 is characterized in that, the PECL phase-locked loop driver in the band redundancy clock source on each veneer is controlled by the CPU of system.

5, automatic-protecting switching device according to claim 1 is characterized in that, the PECL phase-locked loop driver in the band redundancy clock source on each veneer all adopts identical device.

6, automatic-protecting switching device according to claim 1 is characterized in that, the PECL-TTL level conversion clock distributor on each veneer all adopts identical device.