CN1272993A - Packet assembly hardware for data communication switch - Google Patents
Packet assembly hardware for data communication switch Download PDFInfo
- Publication number
- CN1272993A CN1272993A CN99800960.1A CN99800960A CN1272993A CN 1272993 A CN1272993 A CN 1272993A CN 99800960 A CN99800960 A CN 99800960A CN 1272993 A CN1272993 A CN 1272993A
- Authority
- CN
- China
- Prior art keywords
- half width
- width
- logical block
- grouping
- full duration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
An ''on the fly'' packet assembly for a data communication switching engine assembles headers and stripped packets which are separately-sourced in multi-bit bursts while correcting any misalignment created by such ''chunky'' transfer. When an inbound header and corresponding outbound header initially have a half-width divergence (i.e., one ends on a full-width and the other ends on a half-width), an alignment unit realigns the stripped packet by a half-width to align the last half-width of the outbound header and the first half-width of the stripped packet. Also, when an outbound header ends on a half-width, a merger multiplexor combines the last half-width of the outbound header and the first half-width of the stripped packet to bridge the gap which would otherwise remain between the outbound header and the stripped packet. The serially-implemented alignment and merger operations format the outbound header and stripped packet into an encapsulated packet which may be readily transferred in a contiguous manner on an output. An update unit may be implemented in the packet assembly to perform ''on the fly''updates of selective fields in the outbound header and stripped packet.
Description
The present invention relates to data communication switching technology and more specifically, relate to and be used to assemble each grouping so that the data communication switching hardware that sends at output.
Data communication exchange has switching engine, and this switching engine receives network (inbound) at input and divides into groups and exchange these data to divide into groups for the net that goes out at output.Usually, the grouping that networks has a networking title, and this title comprises: media interviews control (MAC) address (2 layers of exchange), the network address (3 layers of exchange) or transport layer identifier (4 layers of exchange).From this grouping, segregate into network mark topic and be contained in address in this title or identifier is broken down into going out during network mark inscribes of the suitable translation of this grouping by " next jumping " of network.This goes out network mark topic and appends in the separated grouping, and the net (outbound) that goes out that forms " encapsulation " divides into groups.
In order to improve exchange velocity, go out network mark topic and the grouping that separates often from different sources, press grouping set of a series of " pulse train " composition of K bit width, wherein K is greater than 1.This " in a large number " transmission packets some technical problems occur under the environment of " awing (on the fly) " encapsulation.One of them problem, if the networking title finishes (promptly in full duration, two half widths for the last pulse train that contains data of networking title comprise effective title data), but the corresponding network mark topic that goes out finishes (promptly on half width, only a half width for the last pulse train that contains data that goes out the network mark topic comprises effective title data), otherwise or, if shift to an earlier date (or lag behind) inadequately, the grouping of separation begin (or leading) half width that will lag.The another one problem finishes in half width if go out network mark topic, if separated grouping does not shift to an earlier date (or hysteresis), then will lag (or leading) or half width or full duration.If this error by " in a large number " transmission generation from multiple source is not proofreaied and correct, then each grouping will be encapsulated improperly and may be caused pseudo-data or system errors.
With regard to its most basic characteristics, the invention provides a kind of grouping mounting technology that is used for " awing " of data communication switching engine, the assembling of this technology is proofreaied and correct any error by " in a large number " transmission generation simultaneously from each unit with the grouping of many bit pulse string mode in source respectively.When the networking title and corresponding when going out the network mark topic and having the deviation of half width (, one is ended at full duration and another and ends at half width), half point from grouping by a half width aim at out the last half width of network mark topic and half point from first half width of grouping aim at again.In addition, when going out network mark topic when half width finishes, this go out the last half width of network mark topic and half point from grouping first half width combine, bridge joint otherwise may be retained in out that network mark is inscribed and half point from grouping between the gap.Aligning and combination operation that series connection is implemented, form dissolve network mark topic and half point from the grouping that is grouped into a kind of encapsulation, this grouping can be carried out attachable transmission at output.
Each above-mentioned advantage can utilize the way of the aligned units that then merges multiplexer to realize.Aligned units can be arranged to the half width register of optionally making that is connected to one or more full duration registers thereafter.When the networking title is realized on full duration and when going out network mark topic and on half width, realizing, the half width of the grouping that the half width registers capture is separated, and other half width is allowed to flow directly into the full duration register.This operate in the separated grouping produce one with the skew that goes out network mark topic coupling (that is, going out end of network mark topic and separated being grouped on the half width later on begins).Equally, when the networking title is finishing on the half width and is going out the network mark topic when full duration finishes, the half width of the grouping that the half width registers capture is separated, and other half width is allowed to flow directly into the full duration register.This operate in the separated grouping produces and the skew that goes out network mark topic coupling (that is, go out later on that the network mark topic finishes and the separated whole pulse train that is grouped in begins).When the networking title with go out network mark topic beginning when not having the half width deviation, the half width register is allowed to flow directly into the full duration register by the full duration of bypass and separated grouping.
Merging multiplexer can be arranged as the multiplexer of two width to a width, this register can be chosen as given two a width input or from the full duration that goes out the network mark topic, from the output of the full duration of separated grouping, perhaps from each the output of half width.More specifically,, merge multiplexer and select full duration from going out the network mark topic all the time, be transferred and this pulse train of selection from the grouping that separates then, be transferred until the grouping of this separation until whole title when going out network mark topic when full duration finishes.When going out network mark topic when half width finishes, be formed outside the available input except when go out the half width of last half width that network mark inscribes and separated grouping, follow identical selection sequence.Between this tour, merge multiplexer and select the last half width of network mark topic and first half width of separated grouping, " mergings " one-tenth has the output header of discrete packets.Owing to optionally carry out this alignment function in advance by aligned units, each half width can merge multiplexer to be combined the locked arrival of the desired mode of multiplexer all the time, merges network mark topic and the grouping through encapsulation that is fit to be connected transmission that is grouped into that separates.
Of the present invention other aspect, can insert a updating block, optionally upgrade the multi-width chaacter section in half width, full duration or the grouping.
By in conjunction with below each accompanying drawing and following detailed part of summary, these and other purpose of the present invention can be better understood.Certain actual range of the present invention is limited by the accompanying Claim book.
Fig. 1 is the block diagram of data communication switching engine;
Fig. 2 is the more detailed block diagram of grouping assembly unit of the switching engine of Fig. 1;
Fig. 3 A represents the combination of different networking title/go out network mark topic to 3D, and the grouping assembly unit of Fig. 2 is arranged to attempt forming differently the grouping through encapsulation valuably in these combinations;
Fig. 4 is the more detailed block diagram of aligned units of the switching engine of Fig. 1;
Fig. 5 is the more detailed block diagram of updating block of the switching engine of Fig. 1;
Fig. 6 is the merging multiplexer of switching engine of Fig. 1 and the more detailed block diagram of continuous logic thereof;
Fig. 7 A is illustrated in the networking title and goes out network mark topic not to be had the half width deviation and goes out the network mark topic under the situation that full duration finishes, aligned units and merge the operation in tandem of multiplexer;
Fig. 7 B is illustrated in the networking title and goes out network mark topic not to be had the half width deviation and goes out the network mark topic under the situation that half width finishes, aligned units and merge the operation in tandem of multiplexer;
Fig. 7 C is illustrated in the networking title and goes out network mark topic to be had the half width deviation and goes out the network mark topic under the situation that half width finishes, aligned units and merge the operation in tandem of multiplexer;
Fig. 7 D is illustrated in the networking title and goes out network mark topic to be had the half width deviation and goes out the network mark topic under the situation that full duration finishes, aligned units and merge the operation in tandem of multiplexer.
In Fig. 1, express the switching engine 100 that the present invention can implement.The grouping that networks arrives and receives FIFO 110.Identifier in the title of grouping that networks is sent to exchange logic circuit 120, just to exchange judgement.Shifted if should exchange the judgement indication, then exchange logic circuit 120 sends a transfer and indexes header sheet 140, retrieves a suitable network mark that goes out and inscribes.The identifier that sends to exchange logic circuit 120 can comprise for example each address and the identifier of OSI(Open Systems Interconnection) layer, 2 (bridge joint) layer, 3 (networks) layer and 4 (transmission) layer.Exchange logic circuit 120 can be made the exchange judgement by carrying out such as the correlation ratio of the known identifier in these identifiers and the memory that is stored in the exchange logic circuit 120.Sort memory can be that the memory (CAM) of content addressing maybe can be a random-access memory (ram).Example that with RAM is exchange logic circuit 120 is implemented on the basis be described in belong to this assignee, name be called " CUSTOMCIRCUITRY FOR ADAPTIVE HARDWARE ROUTING ENGINE ", application number is in the U.S. Patent application of No.08/964597.The data in the grouping that networks of not utilizing out the network mark topic to rewrite are stored among the FIFO (first-in first-out device) 130, are suspended at the exchange court verdict in the exchange logic circuit 120.In such a way, such data are avoided being arrived the networking grouping rewriting that receives FIFO 120 by other.Packet assembler 150 receives respectively from title FIFO's 145 and from the pulse train of grouping FIFO 130, and the data that make up these " awing " are each grouping through encapsulation, these data can be transferred to transmission FIFO 160 by connected mode, arrive suitable grouping destination (or " next jumping ").
Title and grouping are shifted by the pulse train of K bit width, and wherein K is greater than 1.In in each pulse train each whole, half or all may be effectively, can be not yet effective position.When all bits when being effective, a pulse train shifts whole data width.When half of all bits when being effective, the half width of pulse train transferring data.Therefore, be the mode of 16 example by K, each pulse train shifts two effective bytes (full duration), an effective byte (half width) or do not have effective byte can be for conversion.Certainly, the K value can be different in other embodiment that does not depart from the scope of the present invention.
Referring now to Fig. 2, express packet assembler 150 in more detail.Aligned units 210 receives the separated grouping of pressing the pulse train form from grouping FIFO 130, carry out necessary aligning again and shift these data to updating block 220.Separated grouping comprises the networking packet content, does not contain separated networking title.Updating block 220 is inscribed data from the network mark that goes out that title FIFO 145 is received in the pulse train respectively.The data of 220 pairs of receptions of updating block carry out necessary renewal and the data of transfer in pulse train arrive merging multiplexer 230.Merge multiplexer 230 will go out network mark topic data and separated grouping merge into through encapsulation be adapted at sending the grouping that FIFO 160 sends in succession, and transmit by the pulse train form and assemble register 240 through being grouped into of encapsulating.Upgrade and merge and assist to carry out by mux controller 250.Mux controller 250 is indicated the multiplexer in updating block 220 and is merged multiplexer 230 and select each suitable half width from current available data width, realizes desirable renewal (under the situation of updating block 220) and the formation grouping (merging under the situation of multiplexer 230) through encapsulation.
Remarkable advantage of the present invention is that " awing " optionally aims at and the different merging that go out network mark topic and separated grouping of originating, and forms the grouping through encapsulation.Represent to require the different situations of aiming at and merging the application of rule at Fig. 3 A to 3D.In Fig. 3 A, networking title 310 and go out network mark topic 311 both finish in full duration.Therefore, separated grouping 312 and go out network mark topic 311 both begin and can aim at or merge in full duration, and can be combined into grouping 313 through encapsulation.In Fig. 3 B, networking title 320 and go out network mark topic 321 both finish in half width.Therefore, separated grouping 323 and go out network mark topic 321 both begin and can aim at and be combined into grouping 323 through encapsulation in half width, but require to merge is so that form grouping 323 through encapsulation.In Fig. 3 C, networking title 330 finishes in full duration, finishes in half width and go out network mark topic 331.Therefore, separated grouping 332 requires to aim at and merge both with going out network mark topic 331, so that form the grouping 333 through encapsulation.At last, in Fig. 3 D, networking title 340 finishes in half width, finishes in full duration and go out network mark topic 341.Therefore, separated grouping 342 requires to aim at going out network mark topic 341, but does not require merging, so that form the grouping 343 through encapsulation.
Forward Fig. 4 now to, describe aligned units 210 in more detail.Aligned units 210 comprises the half width register 410 that is connected to full duration register 420,430 thereafter.Separated grouping arrives unit 210 by the pulse string sequence from grouping FIFO 130, and it is right that these data operationally are treated to half pulse train.In case arrive unit 210, the half width of the half pulse train centering that bypass logic circuit 440 one of is controlled in 3 paths, this control depend on (i) whether the networking title with go out the deviation that network mark exists half width between inscribing; If (ii) exist the half width deviation, then going out the network mark topic is to finish in half width, still finishes in full duration.In a preferred embodiment, bypass logic circuit 440 is made these two and is determined, describedly determine that (this field indicates whether that the beginning of separated grouping once was offset from the beginning of networking title by the deviation field of inquiry in separated grouping, with therefore separated grouping from half width, still begin from full duration) least significant bit and the least significant bit the length for heading field that goes out the network mark topic (this field indicates the network mark topic and finishes in half width, still in full duration).Select all paths to come by on two burst cycle, shifting to an earlier date half width half pulse train centering by aligned units 210, under the situation that does not depart from notion of the present invention, can configuration requirement burst cycle different or variable number.
Referring now to Fig. 5, wherein express updating block 220 in more detail.Updating block 220 receives separated grouping by the pulse string sequence from aligned units 210, and it is right and receive from title FIFO 145 and to go out the network mark topic by whole burst sequence that these groupings operationally are treated to half pulse train.Each half width of separated grouping is imported into half width multiplexer 520, and the full duration that goes out network mark topic is imported into full duration multiplexer 530.Multiplexer 520,530 also has as upgrading the input data of register 510 from each.In each burst cycle, each of mux controller 250 indication multiplexers 520,530 selects one of each input as output, and updating mark and comparative result when the preceding burst counting are depended in this selection.For this reason, mux controller 250 upgrades each sign, is enough to indicate each to upgrade register 510, and multiplexer will be selected to upgrade the register input as output from each on which burst cycle.The burst counter that is associated with mux controller 250 to each burst cycle add 1 and the value of current counter be carried out comparison so that find value with the tag match of upgrading.When the value of coupling when finding, both or suitable one of mux controller 250 indication multiplexers 520,530 select input from the renewal register corresponding to the updating mark of coupling.When can not find coupling, multiplexer 520,530 is selected input respectively from aligned units 210 and/or title FIFO 145.By above-mentioned operation, require to be updated by the grouping field of dividing into groups one by one to make amendment.Require each field of grouping concrete modification for example can comprise: several or its life-span remaining time of the field of the length of indication block length or packet header and/or " jumpings " of indicating a grouping to tide over is than the field of (time-to-live).Though updating block 220 is expressed to be connected on and merges before the multiplexer 230 in a preferred embodiment, it can be included in and merge after the multiplexer 230 in other embodiments.
Forward Fig. 6 to, express merging multiplexer 230 and its interrelated logic among the figure in more detail.Merging multiplexer 230 receives as the separated grouping of input and goes out network mark topic (as what revised by updating block 220).Separated grouping arrives sequence by half pulse train and goes out the network mark topic and arrives by whole burst sequence, described whole pulse train can by operationally by multiplexer 230 by half pulse train to handling.To each pulse train, mux controller 250 indication merges multiplexers 230 and selects two of 4 half widths inputs as output, and this selection depends on that selection is to the application when the matrix of preceding burst counting.For this reason, mux controller 250 addressable pooling informations are enough to the total length (in half width) that indication (i) goes out the network mark topic; (ii) whether once there was the networking title and went out half width deviation between the network mark topic; (iii) going out the network mark topic is to finish in full duration, still finishes in half width.By above-mentioned information, solve the complete selection matrix of a grouping that is used to encapsulate.To each burst cycle, the burst counter that is associated with mux controller 250 is added on each burst cycle and selection matrix is applied to and obtains a selection instruction on the current Counter Value.This selection instruction is used to control and merges multiplexer 230 and select the output of two half widths inputs as current burst cycle, and described two half widths input need be used for successfully will originate and different go out the network mark topic and the grouping through encapsulating that is arranged to transmission is in succession merged in separated grouping (by what revised by updating block 220).The output of the full duration of selecting is sent to assembling register 240, arrives transmission FIFO160 so that temporarily store, select the footpath.
, in 7D, express the selectivity for the combination of 4 kinds of possible networkings/go out network mark topic of the present invention and aim at and union operation at Fig. 7 A.For make Fig. 7 A to 7D clear for the purpose of, suppose (for example in updating block, do not have the replaced half width of half width (for example, A, B, C, D), A ', B ', C ', D ') substitute and the arrival of half width assembling register is postponed by the fixed qty U of burst cycle.
Fig. 7 A represent to network title and go out the network mark topic and do not have the half width deviation and go out the situation that the network mark topic finishes in full duration.In this state, separated be grouped in to be arranged at full duration A/B among the grouping FIFO 701A begin, be arranged at full duration Y/Z and finish and in title FIFO 711A, go out the network mark topic.In burst cycle N, initial as shown in the figure full duration A/B is stored among the grouping FIFO 701A.Owing to do not have the half width deviation, so do not require the aligning again of separated grouping.Therefore, at burst cycle N+1, full duration A/B bypass half width register 702A and inflow full duration register 703A.Respectively, in burst cycle N+1, the end points full duration Y/Z that goes out the network mark topic is aligned, as shown in the figure so that arrive from title FIFO 711A.At burst cycle N+2, the full duration A/B of initial separated grouping advances to full duration register 704A.At burst cycle N+2+U, the end points full duration Y/Z that goes out the network mark topic selects and is sent to the assembling register by merging multiplexer 721A.At burst cycle N+3+U, the end points full duration Y/Z that goes out the network mark topic selects and is sent to assembling register 722A by merging multiplexer 721A.
Fig. 7 B represent to network title and go out network mark topic and do not have the half width deviation, but go out the situation that the network mark topic finishes in half width.In this case, the half width A that separated grouping is arranged at grouping FIFO 701A begins, and finishes at half width Z and go out the network mark topic.At burst cycle N, initial as shown in the figure half width A and back to back full duration B/C line up in grouping FIFO 701B.Because there is not the half width deviation, so do not require the aligning again of separated grouping.Therefore, at burst cycle N+1, half width A bypass half width register 702B and inflow full duration register 703B.At burst cycle N+2, half width A advances to full duration register 704B, and full duration B/C bypass half width register 702B and inflow full duration register 703B.Respectively, at burst cycle N+2, the end points half width Z that goes out the network mark topic as shown in the figure is aligned for the arrival from title FIFO 711B.At burst cycle N+3, the full duration B/C of separated grouping advances to full duration register 704B.At burst cycle N+3+U, go out the end points half width Z of network mark topic and the initial half width A of separated grouping and select and be sent to assembling register 722B by merging multiplexer 721B.At burst cycle N+4+U, the full duration B/C of separated grouping selects and is sent to assembling register 722B by merging multiplexer 721B.
Fig. 7 C represent to network title and go out the network mark topic and have the half width deviation and go out the situation that the network mark topic finishes in half width.In this state, FIFO 701C in the middle of separated grouping is arranged at, A/B begins in full duration, finishes at half width Z and go out the network mark topic.At burst cycle N, initial as shown in the figure full duration A/B and back to back full duration C/D are in grouping FIFO 701C queuing.Finish in half width because have the half width deviation and go out the network mark topic, require the aligning of the full duration of separated grouping to half width.Therefore, at burst cycle N+1, half width B is stored in half width register 702C, and half width A flows into full duration register 703C.At burst cycle N+2, half width A advances to full duration register 704C, and the full duration B/C that is aimed at again flows into full duration register 703B.Respectively, at burst cycle N+2, the end points half width Z that goes out network mark topic for the arrival from title FIFO 711C is carried out aligning as shown in the figure.At burst cycle N+3, the full duration B/C of separated grouping advances to full duration register 704C.At burst cycle N+3+U, the initial half width A that goes out the end points half width Z of network mark topic and grouping is merged multiplexer 721C and is selected and be sent to assembling register 722C.At burst cycle N+4+U, the full duration B/C of separated grouping selects and is sent to assembling register 722C by merging multiplexer 721C.
At last, Fig. 7 D represent to network title and go out the network mark topic and have the half width deviation and go out the situation that the network mark topic finishes in full duration.In this case, separated grouping is arranged at grouping FIFO 701, and A begins in half width, finishes at full duration Y/Z and go out the network mark topic.Finish in full duration because have the half width deviation and go out the network mark topic, require the half width of separated grouping to aim to full duration.Therefore, at burst cycle N+1, half width A is stored in half width memory 702D.Respectively, at burst cycle N+1, be carried out aligning for the full duration Y/Z that goes out the network mark topic from title FIFO 711D arrival end points as shown in the figure.At burst cycle N+2, the full duration A/B of Dui Zhuning advances to full duration register 704D and half width C inflow half width register 702D again.At burst cycle N+2+U, the full duration Y/Z that end points goes out the network mark topic selects and is sent to assembling register 722D by merging multiplexer 721D.At burst cycle N+3+U, the full duration A/B of grouping base selects and is sent to assembling register 722D by merging multiplexer 721D.
For the professional and technical personnel, obviously find out, by carrying out above-mentioned aligning and union operation, go out network mark topic and the grouping that separates accordingly according to allowing them will be combined into the grouping of encapsulation valuably by mode by transmission with being adjacent to its each destination that is decomposed.Therefore, scope of the present invention represent by appending claims and all fall into equivalent of the present invention include with scope all be considered to belong to protection scope of the present invention.
Claims (15)
1. first and second logical blocks of the data that receive from the input that separates of a combination are the logical blocks of data of adjacency so that output to the method for shared output, wherein first and second logical blocks are to import continuously by half width with the speed up to a full duration of every burst cycle, first and second logical blocks or begin and finish wherein in half width or in full duration, this method may further comprise the steps:
(a) determine whether there is the half width deviation between first and second logical blocks;
(b), utilize half width to aim at each input of second logical block again if there is the half width deviation;
(c) if each burst cycle before the last half width of first logical block is available to transmission, the width that transmits this first logical block is to output;
(d) the last half width at first logical block is available burst cycle to transmission, if first logical block finishes in half width, the half width that transmits the half width of first logical block and second logical block is to output, otherwise the width that transmits first logical block is to output;
(e) if each burst cycle before the last half width of second logical block is available to transmission, the width that transmits second logical block is to output; With
(f) the last half width at second logical block is available burst cycle to transmission, if second logical block is aimed at according to being carried out in step (b) again, if finish in half width, the half width that then transmits second logical block is to output, otherwise the full duration that transmits second logical block is to output.
2. according to the method for claim 1, also comprise:
(g) burst cycle to selecting utilizes an alternative half width to substitute the half width of first or second logical block.
3. according to the method for claim 1, also comprise:
(g) burst cycle to selecting utilizes an alternative half width to substitute the full duration of first or second logical block.
4. first and second logical blocks of the data that receive from the input that separates of a combination are the logic data block of adjacency so that output to the method for shared output, wherein import first and second logical blocks and import, begin or finish in half width or full duration, this method may further comprise the steps:
(a) aim at first and second logical blocks to identical half width;
(b) transmit the output that is input to of first logical block, comprise the last half width of first logical block until the input of current first logical block that is used to transmit;
(c) when the input of the first current logical block that is used to transmit comprises the last half width of this first logical block, if the first current logical block that is used to transmit be input as half width, transmit the output that is input to of the input of current first logical block that is used to transmit and current second logical block that is used to transmit, otherwise transmit the output that is input to of current first logical block that is used to transmit; With
(d) after this, transmit the output that is input to of second logical block, be transmitted until whole second logical block.
5. according to the method for claim 4, also comprise:
(e) utilize an alternative half width to replace the half width of the selection of first and second logical blocks input.
6. according to the method for claim 4, also comprise:
(e) utilize an alternative input to replace first and second logical blocks input of selecting.
One kind will from divide that other input receives go out network mark topic and separated packet assembling for the grouping that encapsulates so that output to the method for shared output, wherein go out network mark topic and the grouping that separates to import by the continuation mode of half width up to the speed of a width of every burst cycle, wherein go out the network mark topic and finish to begin, may further comprise the steps with the grouping that separates in half width or under full duration:
(a) determine the networking title that from the grouping that networks, separates and go out network mark and whether have the half width deviation between inscribing;
(b) if at the networking title and go out between the network mark topic to exist the half width deviation, then utilize half width to aim at each input of the grouping of separation again;
(c) each burst cycle before going out the last half width of network mark topic is that the width of sending out the network mark topic is to output under the available situation to transmission;
(d) the last half width that goes out network mark topic is available burst cycle to transmission, if going out the network mark topic finishes in half width, first half width of sending out the last half width of network mark topic and the grouping that separates is to output, otherwise the last width of sending out the network mark topic is to output;
(e) if each burst cycle before the last half width of the grouping that separates is available to transmission, the width that transmits the grouping that separates is to output; With
(f) the last half width in the grouping that separates is available burst cycle to transmission, if the grouping that separates is aimed at according to being carried out in step (b) again, if finish in half width, the half width that then transmits the grouping that separates is to output, otherwise the width of the grouping that transmission separates is to output.
8. according to the method for claim 7, also comprise:
(g), utilize the half width that substitutes to substitute out the half width of the grouping of network mark topic or separation in the burst cycle of selecting.
9. according to the method for claim 7, also comprise:
(g), utilize the full duration that substitutes to substitute out the full duration of the grouping of network mark topic or separation in the burst cycle of selecting.
10. one kind will be combined as the system of the logical block of the adjacency that is sent to shared output from first and second logical blocks that divide other input to receive, wherein first and second logical blocks are with up to the continuous half width input of the speed of a width of every burst cycle, wherein begin, comprising in half width or in the end of full duration first logical block and second logical block:
Aligned units, full duration register with half width register and series connection, this aligned units is arranged to each width that receives second logical block, realize that optionally the half width register stores the half width of second logical block, each width of storing second logical block sends each width from second data block of full duration register in the neutralization of full duration register; With
Be connected in series merging multiplexer, merge multiplexer and be arranged to each width that receives first logical block and second logical block, from each width that receives, select two half widths and send selected each width in aligned units.
11., wherein only when between first and second logical blocks, existing the half width deviation, realize the half width register according to the system of claim 10.
12. according to the system of claim 10, wherein aligned units has the second full duration register, this second full duration register is that selectivity is implemented.
13. according to the system of claim 12, wherein except that first logical block full duration finish and second logical block half width begins, implement the second full duration register.
14. the system according to claim 10 also comprises:
Updating block, the half width that arrange to receive each width and substitute is selected each width and is sent selected each width from each full duration that receives and half width.
15. the system according to claim 10 also comprises:
Be connected on after the aligned units and before merging multiplexer, connect updating block, each half width that updating block is arranged to receive each full duration of first and second logical blocks and substitutes first and second logical blocks, from each full duration of receiving and each half width, select each width of first and second logical blocks, and the width that sends selected first and second logical blocks is to merging multiplexer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US9789898A | 1998-06-16 | 1998-06-16 | |
| US09/097,898 | 1998-06-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1272993A true CN1272993A (en) | 2000-11-08 |
Family
ID=22265668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99800960.1A Pending CN1272993A (en) | 1998-06-16 | 1999-06-15 | Packet assembly hardware for data communication switch |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1004187A1 (en) |
| JP (1) | JP2002518938A (en) |
| CN (1) | CN1272993A (en) |
| WO (1) | WO1999066678A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1206099A3 (en) * | 2000-11-14 | 2003-10-22 | Sancastle Technologies Ltd. | Network interface |
| US7543142B2 (en) | 2003-12-19 | 2009-06-02 | Intel Corporation | Method and apparatus for performing an authentication after cipher operation in a network processor |
| US7512945B2 (en) | 2003-12-29 | 2009-03-31 | Intel Corporation | Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor |
| US7529924B2 (en) * | 2003-12-30 | 2009-05-05 | Intel Corporation | Method and apparatus for aligning ciphered data |
| KR100617696B1 (en) * | 2004-03-12 | 2006-08-28 | 삼성전자주식회사 | Receiving method and apparatus and Transmitting method and apparatus for concatenated data units and structure for the data burst |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5491802A (en) * | 1992-05-29 | 1996-02-13 | Hewlett-Packard Company | Network adapter for inserting pad bytes into packet link headers based on destination service access point fields for efficient memory transfer |
-
1999
- 1999-06-15 EP EP99928014A patent/EP1004187A1/en not_active Withdrawn
- 1999-06-15 JP JP2000555396A patent/JP2002518938A/en active Pending
- 1999-06-15 CN CN99800960.1A patent/CN1272993A/en active Pending
- 1999-06-15 WO PCT/EP1999/004377 patent/WO1999066678A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999066678A9 (en) | 2000-03-30 |
| WO1999066678A1 (en) | 1999-12-23 |
| JP2002518938A (en) | 2002-06-25 |
| EP1004187A1 (en) | 2000-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6088777A (en) | Memory system and method for dynamically allocating a memory divided into plural classes with different block sizes to store variable length messages | |
| EP1019833B1 (en) | Mechanism for packet field replacement in a multi-layered switched network element | |
| US6430184B1 (en) | System and process for GHIH-speed pattern matching for application-level switching of data packets | |
| CN103067353B (en) | The method that data stream from long-range sender is delivered to long-range destination | |
| AU664494B2 (en) | Asynchronous transfer mode communication system | |
| US7685121B2 (en) | Structure and method for maintaining ordered linked lists | |
| CN1155210C (en) | Segmentation protocol supporting compressed segmentation headers | |
| US5216670A (en) | Message stripping protocol for a communication network | |
| US6317415B1 (en) | Method and system for communicating information in a network | |
| US7447234B2 (en) | Method for the reconstitution of messages conveyed by one or more packet-switched transmission networks | |
| US20060268913A1 (en) | Streaming buffer system for variable sized data packets | |
| US7991006B2 (en) | Filtering redundant packets in computer network equipments | |
| US7801183B2 (en) | Synchronous transmission over packet based network | |
| WO2000019650A1 (en) | Method and system for communication with a network | |
| WO2000019666A1 (en) | Method and system for scheduling network communication | |
| EP2490380B1 (en) | Cell processing method, source line card, and network card in switching network | |
| SE516871C2 (en) | Method for flow control in a data communication network | |
| JP2003229907A (en) | Method and apparatus to reassemble data blocks within network processor | |
| CN1099794C (en) | Method of assigning addresses in nodes of telecommunication network | |
| CA2248509A1 (en) | Mechanism for dispatching data units via a telecommunications network | |
| EP0683949B1 (en) | A method for handling redundant switching planes in packet switches and a switch for carrying out the method | |
| CN1272993A (en) | Packet assembly hardware for data communication switch | |
| WO2000019683A1 (en) | Method and system for managing storage of data | |
| US20010006520A1 (en) | Data Communications | |
| CN1559126A (en) | Method for operating an isochronous cyclic communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |