CN1269339C - Carrier recovery equipment of digital QAM receiver - Google Patents
Carrier recovery equipment of digital QAM receiver Download PDFInfo
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- CN1269339C CN1269339C CN 02122280 CN02122280A CN1269339C CN 1269339 C CN1269339 C CN 1269339C CN 02122280 CN02122280 CN 02122280 CN 02122280 A CN02122280 A CN 02122280A CN 1269339 C CN1269339 C CN 1269339C
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Abstract
The present invention discloses carrier recovery equipment for a quadrature amplitude modulation (QAM) receiver. The carrier recovery equipment comprises a phase detector, a control locking device, a frequency locking device and a phase loop wave filter. Phase /frequency error information is supplied to a numerical control oscillator (NCO) to generate a recovery carrier. The phase detector detects signal energy information and phase error information for extracting a signal, which are obtained by an I/Q extracting device. The control locking device monitors signal energy output by the phase detector and divides the extracted signal into an effective part and an ineffective part. A control mark of an effective signal is output to the frequency locking device and the phase loop wave filter, and searching in a large range, and a favorable tracking effect can be achieved. The control locking device controls the calculation of the frequency locking device and the phase loop wave filter in three calculation stages. Detecting frequency deviation and phase deviation respectively obtained by the frequency locking device and the phase loop wave filter are fed in the numerical control oscillator to restore carrier deviation.
Description
Technical field
The present invention is meant a kind of quadrature amplitude modulation (quadrature amplitude modulation, QAM) carrier resetting device of receiver of being applied to especially relevant for a kind of carrier resetting device that is applied in integrated circuit or the receiving system.
Background technology
In a communication system, be positioned at that unavoidable ground always has frequency departure and phase deviation between each local oscillator of transmitting terminal and receiving terminal, at the quadrature amplitude modulation system, this deviation can cause rotation and the deflection of aspect figure, and has seriously destroyed the signal of transmission.
See also Figure 1A to Fig. 1 C, these three figure have shown three kinds of aspect figure of demodulation QAM-16 signal, wherein Figure 1A is desirable aspect figure, Figure 1B is because the phase deviation between transmitting terminal and receiving terminal causes aspect figure deflection, Fig. 1 C then is because the frequency departure between transmitting terminal and receiving terminal causes aspect figure rotation, if distortion as the aspect figure of restituted signal such as Figure 1B or Fig. 1 C, we just can't correctly decode these restituted signals to obtain original information, therefore, all effort of a lot of researchs towards addressing these problems.
See also Fig. 2, this figure is the functional block diagram of conventional orthogonal amplitude modulation receiver, tuner 11 becomes intermediate frequency (intermediate frequency with the RF conversion of signals that receives earlier, IF) signal, utilize analog-digital converter 12 it to be taken a sample and digitlization then with sampling interval T, voltage-controlled oscillator (voltage controlled oscillator then, VCO) 13 further convert digitized intermediate frequency sampling to a base band (baseband) signal, suitably filter out wherein unwanted HFS, so resultant is exactly restituted signal, if the centre frequency of voltage-controlled oscillator 13 and intermediate frequency carrier are not simultaneously, cross-talk (cross talk) phenomenon appears in the homophase wave band of baseband signal and the intersegmental meeting of quadrature wave, carrier resetting device 14 is exactly a value of estimating Δ θ [n] according to these carrier informations, allow voltage-controlled oscillator 13 adjust its phase place, to improve the cross-talk phenomenon of base band sampling, U.S. Patent number 5,058,136,5,519,356,5,940,450 disclose traditional carrier recovering method of some relevant these class devices, it provides the parameter relevant with phase deviation essence, local oscillator in order to the corrected received end, eliminate phase deviation well, yet, if have frequency departure in addition simultaneously, to revise phase deviation and frequency departure simultaneously, just must use more parameter and revise step, therefore revise the part of relevant phase deviation,, use up long time for update the system and make system's convergence, moreover, revise speed and the choice between accuracy as a result and also be difficult for grasping.
Summary of the invention
The purpose of this invention is to provide a kind of carrier resetting device, can improve the problem of phase deviation and frequency departure simultaneously, and take into account and revise speed and accuracy as a result.
The relevant a kind of carrier resetting device that is applied to the communication system demodulating end of the present invention, in a preferred embodiment, carrier resetting device is positioned among the quadrature amplitude modulation receiver of the usefulness that supplies reception carrier.
According to first conception of the present invention, carrier resetting device comprises phase detectors, frequency locking device, locking-controller.Phase detectors are first part and second parts that are used to detect signal to be demodulated, and export a phase error parameter according to the correlation between first part and second part; The frequency locking device is electrically connected with phase detectors, is used for the response phase error parameter and produces a frequency adjusted value and a frequency error estimated value; Locking-controller is electrically connected with the frequency locking device, export the first flag state signal to the frequency locking device according to the comparative result of the frequency adjusted value and first set point, and respond the first flag state signal and the change state of control frequency error estimate, the frequency error estimated value is handled according to the change state, the carrier frequency generator of communication system demodulating end will be provided to, to produce the reinsertion of carrier; And phase loop filter, it is electrically connected with phase detectors and locking-controller, be used for the response phase error parameter and the output phase error estimated value, and receive the 3rd flag state signal from locking-controller, according to the comparative result of frequency adjusted value and the 3rd set point, the change state of control phase error estimate.
Best, phase detectors can respond first part and second of quadrature amplitude modulated (QAM) signal and partly further export a power parameter to locking-controller, locking-controller is also exported the second flag state signal according to the comparative result of the power parameter and second set point, when power parameter was not less than second set point, the second flag state signal was indicated an effective status.
Best, can the first comparison frequency adjusted value and first set point before second marking signal is pointed out effective status.
Similarly, can first comparison frequency adjusted value and the 3rd set point before second marking signal is pointed out effective status.
In one embodiment, the 3rd set point is bigger than first set point, when frequency adjusted value during greater than first set point, first flag state signal indication frequency locking device is positioned at active state, and when the frequency adjusted value was not more than first set point, first flag state signal indication frequency locking device was positioned at no active state.When the frequency adjusted value was not more than the 3rd set point, the 3rd flag state signal indication phase loop filter was positioned at active state, and when frequency adjusted value during greater than the 3rd set point, the 3rd flag state signal indicates the phase loop filter to be positioned at no active state.
When first flag state signal indication frequency locking device is positioned at no active state, the original value of the change state indication reserve frequency error estimate of frequency error estimated value; On the contrary, when first flag state signal indication frequency locking device was positioned at active state, then the change state representation of the frequency error estimated value factor that will import a frequency adjusted value was come the renewal frequency error estimate.
Best, the frequency locking device can be exported an average frequency error according to the comparative result of phase error parameter and the 4th set point, the frequency locking device comprises counter, when rolling counters forward to a predetermined value, the frequency locking device is understood the positive negative value of response frequency adjusted value and average frequency error and is produced the frequency error estimated value, continuous three average frequency errors of exporting when phase detectors have same positive negative value, then the frequency adjusted value is doubled, if continuous three average frequency error alternate positive and negatives then reduce by half the frequency adjusted value.
On the other hand, when the 3rd flag state signal indication phase loop filter was positioned at no active state, it was original value that the change state representation of phase error estimation and phase error value keeps the phase error estimated value; On the contrary, indicate the phase loop filter when the 3rd flag state signal and be positioned at active state, then the change state representation of phase error estimation and phase error value need be upgraded phase error, and it reaches by the search frequency range factor that imports the input phase loop filter.
Best, the phase loop filter comprises filter and multiplexer.No. one time filter is electrically connected with phase detectors, is used for the receiving phase error parameter, and handles phase error parameter and search frequency range, and gets a phase error estimation and phase error value of upgrading; Multiplexer is electrically connected with a filter, and response the second and the 3rd flag state signal is selected an output from the phase error estimation and phase error value of original phase error estimation and phase error value and renewal.
Best, the carrier frequency generator be a numerical value control generator (numerically controlledoscillator, NCO).
According to second viewpoint of the present invention, the carrier resetting device that is used for the quadrature amplitude modulation receiver comprises phase detectors, response homophase of quadrature amplitude modulated (QAM) signal and quadrature portion and export a phase error parameter; A frequency locking device is electrically connected with phase detectors, is used for the response phase error parameter and produces a frequency adjusted value and a frequency error estimated value; A phase loop filter is electrically connected with phase detectors, is used for the response phase error parameter and exports a phase error estimation and phase error value; And locking-controller, be electrically connected with frequency locking device and phase loop filter, export the first flag state signal to the frequency locking device according to the comparative result of the frequency adjusted value and first set point, and export the second flag state signal to the phase loop filter according to the comparative result of the frequency adjusted value and second set point, the first change state of control frequency error estimate to respond first marking signal, respond second marking signal simultaneously and the second change state of control phase error estimate, here be to handle frequency error estimated value and phase error estimation and phase error value according to the first change state and the second change state respectively, it is provided to the carrier frequency generator of communication system demodulating end, to produce a reinsertion of carrier.
Best, phase detectors also can respond the homophase of quadrature amplitude modulated (QAM) signal and quadrature portion and export a power parameter to locking-controller, and export the 3rd flag state signal according to the comparative result of power parameter and the 3rd set point, if power parameter is not more than the 3rd set point, then the 3rd flag state signal is indicated an effective status, can the first comparison frequency adjusted value and first set point before the 3rd flag state signal is designated as effective status.
Description of drawings
The present invention is able to more deep understanding by following accompanying drawing and DETAILED DESCRIPTION OF THE PREFERRED:
Figure 1A to Fig. 1 C is three kinds of aspect figure of demodulation QAM-16 signal;
Fig. 2 is the functional block diagram of conventional orthogonal amplitude modulation receiver;
Fig. 3 is the functional block diagram of quadrature amplitude modulation receiver of the present invention;
Fig. 4 is the computing calcspar of the preferred embodiment of carrier resetting device of the present invention;
Fig. 5 A is the computing calcspar of the preferred embodiment of phase detectors among Fig. 4;
Fig. 5 B is the computing calcspar of another preferred embodiment of phase detectors among Fig. 4;
Fig. 6 is the flow chart of locking-controller 32 computing principles in the key diagram 4;
Fig. 7 is the orientation diagram of 64-AQM signal, adds the selected preset value that uses that detects for signal energy according to the present invention;
Fig. 8 is the orientation diagram of 256-AQM signal, adds the selected preset value that uses that detects for signal energy according to the present invention;
Fig. 9 A and Fig. 9 B are the flow charts of frequency locking device 33 computing principles in the key diagram 4;
Figure 10 is the computing calcspar of phase loop filter among Fig. 4; And
The 11st figure is the flow chart of phase loop filter 34 computing principles among explanation Figure 10.
Each assembly label declaration is as follows in the accompanying drawing:
11,21: tuner 12,22: analog-digital converter
13: voltage-controlled oscillator 14,24: carrier resetting device
23: Numerical Control oscillator 31: phase detectors
32: locking-controller 33: the frequency locking device
34: phase loop filter 331: counter
341: filters 342: multiplexer
Embodiment
As mentioned above, if when between each local oscillator of transmitting terminal and receiving terminal, having phase deviation or frequency departure, the orientation diagram of quadrature amplitude modulated (QAM) signal has the phenomenon of deflection or rotation, in other words, as long as have phase deviation or frequency departure to exist therebetween, have the cross-talk phenomenon between in-phase signal ' I ' that is extracted by the I/Q withdrawal device of digital quadrature amplitude modulation receiver and orthogonal signalling ' Q ', thereby reduce its performance, so must detect frequency and the phase deviation that is positioned between transmitting terminal and receiving terminal local oscillator with carrier resetting device, with the deflection and the rotation situation of compensating signal orientation diagram.
We explain the situation of carrier deviation earlier, see also Fig. 3, this figure is the functional block diagram of quadrature amplitude modulation receiver of the present invention, the quadrature amplitude modulation receiver comprises a tuner 21, can convert the RF signal down that receives to intermediate-freuqncy signal, analog-digital converter 22 is taken a sample and digitlization to these signals then, and obtaining sample time is the discontinuous signal of T, and each is through digitized sampling x[n] can be write as
F wherein
cIt is the centre frequency of intermediate frequency carrier, Numerical Control oscillator 23 can further become baseband signal with digitized intermediate frequency sampling down converted, then suitably filter out unwanted high frequency partly, transmission rate (symbol k) according to system, signal after the filtration is through conversion, can have new sampling rate, so be the intact estimated signal of demodulation
Yet, if have frequency deviation f[n between the centre frequency of Numerical Control oscillator 23 and intermediate frequency carrier] and phase deviation Δ θ [n], then the intersegmental cross-talk phenomenon that has of homophase wave band and quadrature wave takes place in the baseband signal after the down converted, and this influence is described as follows.
Carrier deviation Δ f[n is arranged] and the sampling of the digitlization intermediate frequency of Δ θ [n] can be write as
If do not use any carrier resetting device, signal can produce disagreeable twisted phenomena:
I′[n]＝I[n]·cos(2π·Δf[n]·nT+Δθ[n])-Q[n]·sin(2π·Δf[n]·nT+Δθ[n])
Q′[n]＝Q[n]·cos(2π·Δf[n]·nT+Δθ[n])+I[n]·sin(2π·Δf[n]·nT+Δθ[n])。
We must use carrier resetting device 24 to come estimated bias Δ f[n] and Δ θ [n], by these carrier informations, Numerical Control oscillator 23 can be adjusted its frequency and phase place, to eliminate the cross-talk phenomenon of harmful rotation and base band sampling (I[n], Q[n]).
See also Fig. 4, this figure is the functional block diagram of carrier resetting device preferred embodiment of the present invention, and carrier resetting device comprises phase detectors 31, locking-controller 32, frequency locking device 33, phase loop filter assembly 34.The homophase that phase detectors 31 extract from signal is [k] and quadrature portion partly
In produce two kinds of information, one extraction signal wherein
Detected energy
By feed-in locking-controller 32, another detected phase error " cur_phase " then is sent to frequency locking device 33 and phase loop filter 34, locking-controller 32 utilize control signal " FL_out_flag ", " PLF_out_flag " and " valid_flag " state of leading frequency locking device 33 and phase loop filter 34, use its search of control and tracking pattern, partly we will be in being illustrated after a while for this; Simultaneously, FSS are to locking-controller 32 for its operating state of frequency locking device 33 feedback, and then, frequency locking device 33 and phase loop filter 34 are exported Δ f[k respectively] and Δ θ [k] arrive Numerical Control oscillator 23 (Fig. 3).
See also Fig. 5 A now, this figure is the computing calcspar of the preferred embodiment of phase detectors 31 among Fig. 4, we can with [k] and
Be considered as complex vector located
Extract signal on orientation diagram quadrant and another is complex vector located
Identical, the sign of homophase part and quadrature portion decides its quadrant in the utilization extraction signal exactly, and we can utilize following formula to derive this phase relation of two complex vector located:
Through normalization (normlization) and simplification, we select imaginary part as phase error information, and formula is:
According to the present invention, frequency locking device 33 and phase loop filter 34 are not all to be under the compute mode always, carrier resetting device of the present invention is divided into three main operation stages, the firstth, under search pattern, the secondth, in search and follow the trail of under the merging patterns, the 3rd be under the tracking pattern.Suppose when carrier resetting device begins to activate, the frequency departure of intermediate frequency is greatly to several ten thousand hertz, at this moment the aspect figure of homophase and quadrature portion can seriously rotate, and at this moment the estimated value Δ θ [k] of phase deviation does not have any help to the compensation carrier deviation, so in the phase I, it is effective having only frequency locking device 33, and to obtain the information of frequency departure, locking-controller 32 then control phase loop filter 34 is in no active state.When the variation of estimated frequency has been pulled to small range, phase loop filter 34 begins to add the computing line, searches for fast, and in other words, in second stage, frequency locking device 33 and phase loop filter 34 act on simultaneously.After one period processing time, when frequency locking device 33 trends are stablized, it is very little that the variation of estimated frequency also becomes, finely tune phase loop filter 34 compensating remaining phase error this moment, after, locking-controller 32 is closed frequency locking device 33, the fixing output valve Δ f[k of frequency locking device 33], avoid carrier resetting device to produce unnecessary vibrations, in the phase III, have only phase loop filter 34 that effect is arranged.
The computing principle of the flowchart text locking-controller 32 of Fig. 6, in carrier resetting device of the present invention, not every extraction signal
The capital is used to search rate and phase error information, if signal energy
" PWR_THRES " is little than predetermined set value, and carrier resetting device can keep original Δ f[k] and Δ θ [k] value, this device focused energy can be avoided newly-increased interference of noise by strengthening system greater than the signal of preset value.
About selecting the set point of 64-QAM and 256-QAM " PWR_THRES " please refer to the example of Fig. 7 and Fig. 8, set point " PWR_THRES " selection mode be to allow the extraction quadrature modulation signal that is positioned at the corner in the orientation diagram
In suitable quantity incoming carrier recovery device can be arranged, if the selection of set point " PWR_THRES " is suitable, can carry out fastish search, one skilled in the art will recognize that quick search meeting adds noise in the detected phase error, utilize the mean value of a succession of detected phase error can filter out these noises.
Please consult Fig. 6 again, locking-controller 32 receives the detection signal energy from phase detectors 31, if the detection signal energy is greater than set point " PWR_THRES ", then control signal " valid_flag " is set as " TRUE ", on the contrary, if the detection signal energy then is set as control signal " valid_flag " not greater than set point " PWR_THRES " " FALSE "." valid_flag " is when control signal " TRUE " time, carry out the three stages computing that the front is narrated, locking-controller 32 can monitoring frequency locking devices 33 output " FSS ", and with set point " PLF_THRES " and " FL_LOCK " comparison, wherein the value of " PLF_THRES " greater than " FL_LOCK "." FSS " is greater than preset value " PLF_THRES " be illustrated between local value control generator and intermediate frequency carrier frequency and still have very big frequency departure, at this moment, locking-controller 32 can force carrier resetting device to remain on the search phase, " FL_out_flag " is set as with control signal " TRUE ", allow frequency locking device 33 act on, control signal " PLF_out_flag " is set to simultaneously " FALSE ", make not effect of phase loop filter 34.When " FSS " is equal to or less than set point " PLF_THRES ", but during still greater than another set point " FL_LOCK " (it defines less than " PLF_THRES "), locking-controller 32 order carrier resetting devices enter second operation stages, " PLF_out_flag " is set as " TRUE " with control signal, makes phase loop filter 34 begin effect.If " FSS " is equal to or less than this second set point " FL_LOCK ", that will enter the 3rd operation stages exactly, and carrier resetting device is set as " FALSE " with control signal " FL_out_flag ", positive closing frequency locking device 33.
The computing principle of the flowchart text frequency locking device 33 of Fig. 9 A and Fig. 9 B after carrier resetting device activates, just earlier is set as predetermined value with all control marks in the frequency locking device 33 at the beginning in steps A, initial conditions are:
counnt_pnt＝0
over_flag＝“FALSE”
AFE＝0
pre_AFE＝0
FSS＝FSS_INIT
sflag1＝0
sflag2＝0
Δf[0]＝0
In step 91, frequency locking device 33 at first detects control signal " FL_out_flag " from locking-controller 32, if control signal " FL_out_flag " is " FALSE ", the expression carrier resetting device is in the 3rd operation stages, close frequency locking device 33, then in step 92, frequency is adjusted step number value " FSS " set preset value " FL_LOCK " for, frequency locking device 33 is fixed output Δ f[k simultaneously] be last estimated value, carry out step B again, output " FSS " is to locking-controller 32; Another side at flow chart, if control signal " FL_out_flag " is " TRUE ", the expression carrier resetting device is in aforesaid first or second operation stages, in step 93, the output " count_pnt " of frequency locking device 33 inside counting devices 331 (Fig. 4) can add 1, then in step 94, frequency locking device 33 can be checked the state of control signal " valid_flag ", " valid_flag " is if frequency locking device 33 detects control signal " FALSE ", then carry out step C, this partly will be explained below, otherwise, " valid_flag " is when control signal " TRUE " time, then activate the function that detects frequency error.
In step 96, load detected phase error " cur_phase " from phase detectors 31 earlier, the step that detects frequency departure is as follows:
Step 97: if the absolute value of " cur_phase " does not have less than preset value " THRES_PHASE ", then execution in step 98, otherwise execution in step 101.
Step 98: check control signal " over_flag ", this be used for the explanation " cur_phase " absolute value whether greater than " THRES_PHASE ", if " over_flag " is " TRUE ", then execution in step 99, if " over_flag " is " FALSE ", then execution in step 100.
Step 99: " AFE " added " pre_FE ",, arrive step C then as the updating value of " AFE ".
Step 100: " pre_FE " is set as set point " THRES_PHASE ", its sign is then identical with " cur_phase ", equally " AFE " is added then " pre_FE ", to upgrade " AFE ", and " over_flag " be set as " TRUE ", enter step C.
Step 101: the value of " AFE " is updated to the value that " AFE " adds " cur_phase ", and " over_flag " is set as " FALSE ", enter step C.
Step C: the step of adjusting frequency value " FSS ", output " FSS " and Δ f[k] and, its step is described further below.
In the step 102 of Fig. 9 B, frequency locking device 33 checks whether the value of " count_pnt " has arrived " CAL_PNT ", if also do not have, in step 103, keep " FSS " and Δ f[k] original value, if the value of " count_pnt " has arrived " CAL_PNT ", upgrade " FSS " and Δ f[k] as following step.
Step 104: check whether " sflag1 " and " sflag2 " all is ' 0 ', if not, execution in step 105; If in step 106, " sflag2 " is set at ' 1 ', execution in step 107.
Step 105: the value that loads " sflag1 " is to " sflag2 ", and the value of renewal " sflag1 " is that " AFE " multiply by the sign of " pre_AFE ", execution in step 108.
Step 108: check whether " sflag1 " and " sflag2 " all is ' 1 ', if that represents that continuous three " AFE " have identical sign, and " FSS " be multiply by 2, execution in step 107 then; If not, execution in step 109.
Step 109: check whether " sflag1 " and " sflag2 " all is ' 1 ', if that represents that continuous three " AFE " are alternate positive and negatives, in step 111, with " FSS " divided by 2; If not, then do not change " FSS " and value, execution in step 107.
Step 107: " pre_AFE " is set as " AFE ", with Δ f[k] add that " FSS " multiply by the sign of " AFE ", as Δ f[k] updating value, the value with " count_pnt " and " AFE " all is set as 0 then.
In step 112, no matter " FSS " and Δ f[k] whether be updated, frequency locking device 33 all can output to it locking-controller 32 and Numerical Control oscillator 23 respectively.
See also Figure 10 now, Figure 10 is the circuit block diagram of phase loop filter among Fig. 4, phase loop filter 34 comprises primary circuit filter 341 and output multiplexer 342, multiplexer 342 detections are from control signal " PLF_out_flag " and " valid_flag " that locking-controller 32 comes out, and responding these control signals decision phase loop filters is to export updating value or original value.See also the flow chart of the 11 figure, this figure has illustrated the computing principle of phase loop filter 34, and parameter " Cp " and " Ci " representative search frequency range are if the value of " Cp " and " Ci " is big more, then search rate is also fast more, but also can produce bigger vibrations; On the contrary, if select less " Cp " and " Ci ", then shake less, but system needs long time convergence.We can at the beginning, select bigger " Cp " and " Ci ", after through the default processing time, make less " Cp " and " Ci " into then, can reach quick search so simultaneously and follow the trail of effect preferably.
The 11st figure is the flow chart of explanation phase loop filter 34 computing principles, and flow chart is from step D, and initial conditions are:
Δθ[0]＝0
D_reg[0]＝0
In step 113, phase loop filter 34 at first detects from two control signals " valid_flag " and " PLF_out_flag " of locking-controller 32 outputs, as previously mentioned, whether control signal " valid_flag " points out to extract signal effective, and control signal " PLF_out_flag " points out whether to activate phase loop filter 34, when these two control signals all are " TRUE ", execution in step 114 and 115, phase loop filter 34 can pass to low pass filter (not drawing) with phase error information " cur_phase ", through after the computing, to upgrade its output, this can help to be avoided newly-increased noise; On the contrary, if " valid_flag " or " PLF_out_flag " is " FALSE ", in step 116, phase loop filter 34 can keep original output valve, in step 117, phase loop filter 34 output Δ θ [k] are to Numerical Control oscillator 23 then.
In summary, even digital quadrature amplitude modulation receiver has very big frequency departure and phase deviation ([π, π]), carrier resetting device of the present invention also helps to extract undistorted signal
The present invention not only is applicable to broad lock-in range, the ability that quick search is also arranged simultaneously, but because the convergence of above-mentioned phase loop filter can cause 0 °, 90 °, 180 °, 270 ° phase place indeterminate, so need extra device, not bad existing known signal technique of alignment can overcome the indefinite problem of phase place, or can utilize the differential code method in addition, allow the rotation among the aspect figure fix.
Under the situation that does not break away from the described protection range of claim, the present invention can carry out various modifications by those skilled in the art.
Claims (20)
1. carrier resetting device is applied to the demodulating end of communication system, and it comprises:
One phase detectors are used to detect first component and the second component of a signal to be demodulated, and export a phase error parameter according to the correlation between this first component and this second component;
One frequency locking device, it is electrically connected to this phase detectors, is used to respond this phase error parameter and produces a frequency adjusted value and a frequency error estimated value;
One locking-controller, it is electrically connected to this frequency locking device, be used for exporting the first flag state signal according to the comparative result between this frequency adjusted value and first set point, and respond this first flag state signal and control the change state of this frequency error estimated value, this frequency error estimated value is handled according to this change state, and be provided to a carrier frequency generator of this communication system demodulating end, to generate a reinsertion of carrier; And
One phase loop filter, it is electrically connected to these phase detectors and this locking-controller, be used to respond this phase error parameter and export a phase error estimation and phase error value, and according to the comparative result of this frequency adjusted value and the 3rd set point and receive the 3rd flag state signal, to control the change state of this phase error estimation and phase error value from this locking-controller.
2. carrier resetting device as claimed in claim 1, wherein the demodulating end of this communication system is a quadrature amplitude modulation receiver, this signal to be demodulated is a quadrature amplitude modulated (QAM) signal.
3. carrier resetting device as claimed in claim 2, wherein this quadrature amplitude modulation receiver also comprises an I-withdrawal device, be used to extract the homophase part of this quadrature amplitude modulated (QAM) signal, as this first component, also comprise a Q-withdrawal device in addition, be used to extract a quadrature portion of this quadrature amplitude modulated (QAM) signal, as this second component.
4. carrier resetting device as claimed in claim 3, wherein these phase detectors respond this first component of this quadrature amplitude modulated (QAM) signal and second component and export a power parameter to this locking-controller, and export the second flag state signal according to the comparative result between this power parameter and second set point, when this power parameter was not less than this second set point, this second flag state signal was indicated an effective status.
5. carrier resetting device as claimed in claim 4, wherein before this second flag state signal is pointed out this effective status, relatively this frequency adjusted value and this first set point earlier.
6. carrier resetting device as claimed in claim 1, wherein before the second flag state signal is pointed out this effective status, can be not earlier relatively this frequency adjusted value and the 3rd set point.
7. carrier resetting device as claimed in claim 6, wherein the 3rd set point is greater than this first set point.
8. carrier resetting device as claimed in claim 7, wherein when this frequency adjusted value during greater than this first set point, this first flag state signal points out that this frequency locking device is positioned at an active state, when this frequency adjusted value was not more than this first set point, then this first flag state signal pointed out that this frequency locking device is positioned at no active state.
9. carrier resetting device as claimed in claim 8, wherein when this frequency adjusted value is not more than the 3rd set point, the 3rd flag state signal points out that this phase loop filter is positioned at an active state, when this frequency adjusted value during greater than the 3rd set point, then the 3rd flag state signal points out that this phase loop filter is positioned at a no active state.
10. carrier resetting device as claimed in claim 9, wherein when this first flag state signal points out that this frequency locking device is positioned at this no active state, then will to keep this frequency error estimated value be preceding value to the change state representation of this frequency error estimated value.
11. carrier resetting device as claimed in claim 10, wherein when this first flag state signal pointed out that this frequency locking device is positioned at this active state, then the change state representation of this frequency error estimated value was upgraded this frequency error estimated value by the factor that adds this frequency adjusted value.
12. carrier resetting device as claimed in claim 11, wherein this frequency locking device is exported an average frequency error according to the comparative result of this phase error parameter and the 4th set point.
13. carrier resetting device as claimed in claim 12, wherein this frequency locking device comprises a counter, and when this rolling counters forward during to a predetermined value, this frequency locking device responds the sign of this frequency adjusted value and this average frequency value and produces this frequency error estimated value.
14. carrier resetting device as claimed in claim 13, wherein continuous three average frequency errors of exporting when these phase detectors have identical sign, then this frequency adjusted value is doubled, and when continuous three average frequency errors are alternate positive and negative, this frequency adjusted value is reduced by half.
15. carrier resetting device as claimed in claim 14, wherein when the 3rd flag state signal pointed out that this phase loop filter is positioned at this no active state, it was preceding value that the change state representation of this phase error estimation and phase error value keeps this phase error estimation and phase error value.
16. carrier resetting device as claimed in claim 12, wherein when the 3rd flag state signal pointed out that this phase loop filter is positioned at this active state, the change state of this phase error estimation and phase error value promptly upgraded this phase error estimation and phase error value by a search frequency range factor that imports this phase loop filter of input.
17. carrier resetting device as claimed in claim 16, wherein this phase loop filter comprises:
No. one filters, it is electrically connected with these phase detectors, is used to receive this phase error parameter, and handles this phase error parameter and this search frequency range to obtain a phase error estimation and phase error value of upgrading; And
One multiplexer, filter of itself and this is electrically connected, and is used to respond this second flag state signal and the 3rd flag state signal, selects an output from the phase error estimation and phase error value of the phase error estimation and phase error value of this reservation and this renewal.
18. carrier resetting device as claimed in claim 1, wherein the carrier frequency generator is a Numerical Control oscillator.
19. a carrier resetting device is applied to a quadrature amplitude modulation receiver, it comprises:
One phase detectors are used to respond an in-phase component of a quadrature amplitude modulated (QAM) signal and a quadrature component and export a phase error parameter;
One frequency locking device, it is electrically connected with these phase detectors, is used to respond this phase error parameter and produces a frequency adjusted value and a frequency error estimated value;
One phase loop filter, it is electrically connected with these phase detectors, is used to respond this phase error parameter and exports a phase error estimation and phase error value; And
One locking-controller, it is electrically connected to this frequency locking device and this phase loop filter, be used for exporting the first flag state signal to this frequency locking device according to the comparative result between this frequency adjusted value and first set point, and export the second flag state signal according to the comparative result between this frequency adjusted value and second set point and arrive this phase loop filter, control the first change state of this frequency error estimated value to respond this first flag state signal, and respond this second flag state signal and control the second change state of this phase error estimation and phase error value, wherein this frequency error estimated value and this phase error estimation and phase error value are handled according to this first change state and this second change state respectively, and be provided to the interior carrier frequency generator of this quadrature amplitude modulation receiver, to generate a reinsertion of carrier.
20. carrier resetting device as claimed in claim 19, wherein these phase detectors respond this in-phase component of this quadrature amplitude modulated (QAM) signal and this quadrature component and export a power parameter to this locking-controller, and export the 3rd flag state signal according to the comparative result between this power parameter and the 3rd set point, when this power parameter is not less than the 3rd set point, the 3rd flag state signal is indicated an effective status, before the 3rd flag state signal is pointed out this effective status, not first relatively this frequency adjusted value and this first set point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02122280 CN1269339C (en) | 2002-06-03 | 2002-06-03 | Carrier recovery equipment of digital QAM receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02122280 CN1269339C (en) | 2002-06-03 | 2002-06-03 | Carrier recovery equipment of digital QAM receiver |
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| CN1464708A CN1464708A (en) | 2003-12-31 |
| CN1269339C true CN1269339C (en) | 2006-08-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02122280 Expired - Fee Related CN1269339C (en) | 2002-06-03 | 2002-06-03 | Carrier recovery equipment of digital QAM receiver |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4729564B2 (en) * | 2004-05-12 | 2011-07-20 | トムソン ライセンシング | Correction of carrier phase ambiguity |
| CN100518155C (en) * | 2004-12-16 | 2009-07-22 | 上海乐金广电电子有限公司 | Carrier redactor |
| WO2008017205A1 (en) * | 2006-08-02 | 2008-02-14 | Trident Microsystems (Far East) Ltd, Hong Kong Branch | Device and process for data rate acquisition |
| CN101447971B (en) * | 2007-11-27 | 2011-12-28 | 锐迪科科技有限公司 | Automatic frequency control method of digital audio broadcasting receiver and tuner and channel decoding chip |
| CN101615994B (en) * | 2008-06-23 | 2014-04-16 | 晨星软件研发(深圳)有限公司 | Phase detecting module and detecting method thereof |
| TWI424719B (en) | 2009-06-03 | 2014-01-21 | Realtek Semiconductor Corp | Carrier recovery device and method thereof |
| CN109547091B (en) * | 2018-11-27 | 2020-06-30 | 上海航天电子通讯设备研究所 | Processing system for multi-channel detection based on VDE |
| CN112565134B (en) * | 2020-11-27 | 2022-03-15 | 北京北广科技股份有限公司 | Carrier phase fixed compensation method for radio frequency signal of receiving end |
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