CN1268092C - Interface device and method for direct match of Ethernet with physical channel - Google Patents

Abstract

The present invention relates to an interface device and a method for directly matching Ethernet with a physical channel, which pack MAC frames into SDH/SONETSPE/VC by LAPS. An LAPS packet comprises an initial flag sequence, an address field, a control field, an SAPI field, an information field, FCS field and a ending flag sequence. The present invention can be used for providing Ethernet interfaces or be arranged on data communication equipment so as to provide a remote access function. The Ethernet can be applied to DWDM by the simplification of SDH/SONET. The present invention has flexibility and can meet requirements for the real-time transmission of waiting time and little waiting time deviation; besides, the present invention is suitable for real time transmission service based on 32 bits.

Description

Direct and adaptive interface arrangement and the method for physical channel of Ethernet

Technical field

The present invention relates to data network and the communication network relevant with LAN with Internet/Intranet (internet/in-house network), be particularly related to direct and adaptive interface arrangement and the method for physical channel of Ethernet, it provides Ethernet interface on telecommunications SDH/SONET transmission equipment, or provides for example with mac frame and the direct adapting function of SDH/SONET for long-range access data communications equipment such as core and edge router, switching equipment, IP-based network access device, ply-yarn drill and the interface unit that adopted in high-speed applications.

Background technology

Need expansion to comprise the Ethernet application of Ethernet, Fast Ethernet and gigabit Ethernet at present.Transmitting Ethernet (by the definition of IEEE 802.3 working groups) on the physical channel based on telecommunications, is a kind of simple, inexpensive technology with LAN, the Internet/Intranet that connects in private network and the public network.

G.707, ITU-T has described advantage and the multiplexing method of SDH, stipulated the general provisions of one group of SDH bit rate, network interface node (NNI) and frame structure, 9 row N * whole frame signs, fragmentation overhead and the byte allocation thereof of 270 row, the interconnection of the world of Synchronous Transport Module level-N (STM) arrange, element is multiplexing and be mapped to the form of STM-N in the NNI unit.

In the North America, that corresponding with SDH is SONET.SONET is the synchronous data transmission standard on the light medium of the U.S. (ANSI), is called for short Synchronous Optical Network.People formulate standard so that digital network can be realized international interconnection, and existing transmission system can make full use of the advantage of light medium by branch equipment.The basic rate, one that it is 51.84Mbps that SONET has defined a speed is enclosed within the light carrier level of basic rate multiple.SONET is a kind of eight hyte synchronous multiplexing schemes, has defined a series of standard speed and form.Although name is a light carrier, it is not restricted to optical link, has also defined the electrical standard that is used for monomode fiber, multimode fiber and CATY 75 ohm coaxial cable.Transfer rate is the integral multiple of 51.84Mbps, and it can be used for carrying the T3/E3 bit synchronization signal.Its also strong suggestion employing E1/E3/E4/T1/E2/T4 interface G.703 inserts by LAN to make things convenient for the user as the physical layer of IP-over-SDH/SONET.

SDH and SONET provide the standard that is used for a series of linear speeds, and maximum line speeds is 9.953Gbps, and the maximum line speeds of actual capabilities is about 20Gbps.

The existing data communication architecture that Ethernet and SDH/SONET are combined is with PPP (peer-peer protocol) and HDLC (High-Level Data Link Control), and it is defined as RFC1619 in IETF (internet engineering task group).Yet when RFC1619 was applied to the combination of Ethernet/Fast Ethernet/gigabit Ethernet and SDH/SONET, there was following major defect in RFC1619:

(1) the unified international standard support of a whole set of application scheme neither one, it is difficult that this causes the equipment room of different manufacturers to interconnect in private network or public network;

(2) for 2.5Gb/s and above speed, hardware forwarding part expense is too big, and it is all the more so to be used for IP over WDM situation, because RFC1919 recommends to use LCP (LCP) and magic number (MagicNumber), the two is all very complicated.

When (3) using RFC1619, the default value of retransmission timer is 3 seconds in PPP, and this is too blunt for high-speed link.In concrete engineering is used, require to support the speed range (differ 4032 times) of 2Mb/s (bps), so the value of retransmission timer should be determined according to the time delay that circuit comes and goes to 10000Mb/s.But these are not all made stipulations in RFC1619, thereby uncertainty can occur when the apparatus interconnection of different vendor.

(4) LCP has 10 kinds of configuration packet (Configuration Packet), 16 kinds of incidents (Event) and 12 kinds of actions (action), reaches above 130 kinds of protocol statuss, and this causes being difficult to realize the light packet switching between MII and SDH/SONET, and the expense costliness.For above-mentioned situation is described, table 1 has been listed and has been adopted incident and the action of common PPP over SDH/SONET standard on LCP finite state machine (Finite-State Machine).

(5) almost do not use the filling field of PPP among the IP over SONET/SDH, but RFC 2615 still keeps filling field.In addition, this filling field requires receiving terminal can distinguish the filling field of information field and RFC standard definition, has increased processing expenditure so again.

The most important character of Ethernet over SDH/SONET (EOS) is:

(a) it both can be used for the SDH/SONET telecommunications network, also can be used for the data communication network based on Ethernet.

--belt length is apart from the end-to-end connection of SDH/SONET equipment of Ethernet interface;

--the Ethernet switch of band SDH/SONET interface.

(b) realize telling/inserting (add/drop) 10/100M ethernet signal in the SDH/SONET terminal with the multicore sheet.

(c) can be used for the ply-yarn drill of omen router.

Table 1. incident and action

Incident	Response
		Up＝lower?layer?is?Up Down?＝lower?layer?is?Down Open?＝administrative?Open Close＝administrative?Close TO+＝Timeout?with?counter＞0 TO-＝Timeout?with?counter?expired RCR+?＝Receive-Configure-Request (Good) RCR-＝ Receive-Configure-Request (Bad) RCA＝Receive-Configure-Ack RCN＝Receive-Configure-Nak/Rej RTR＝Receive-Terminate-Request RTA＝Receive-Terminate-Ack RUC＝Receive-Unknown-Code RXJ+＝ Receive-Code-Reject (permitted) or?Receive-Protocol-Reject RXJ-＝ Receive-Code-Reject (catastrophic) or?Receive-Protocol-Reject RXR＝Receive-Echo-Request or?Receive-Echo-Reply or?Receive-Discard-Request	tlu＝This-Layer-Up tld＝This-Layer-Down tls＝This-Layer-Started tlf＝This-Layer-Finished irc＝Initialize-Restart-Count zrc＝Zero-Restart-Count scr＝Send-Configure-Request ? ? sca＝Send-Configure-Ack scn＝Send-Configure-Nak/Rej str＝Send-Terminate-Request sta＝Send-Terminate-Ack scj＝Send-Code-Reject ? ? ? ? ser＝Send-Echo-Reply ? ? ? ? ?

Therefore, existing Ethernet and SDH/SONET association schemes complexity, implement difficulty and expense costliness, slowly, unstable, be not suitable for high-speed data transfer, the particularly application of gigabit speed.

The applicant discloses direct and adaptive interface arrangement and the method for physical channel of a kind of Ethernet in International Application PCT/CN00/00211 (international publication number WO 01/08356A1, February 1 calendar year 2001 international publication day) that July 26 in 2000, order was submitted to.The technical scheme that adopts this patent application to propose is inserted the SAPI identifier and is represented packaged data type in the address field of SDH/SONET frame, solved the adaptive problem of Ethernet and physical channel to a certain extent.But, when the IFG (frame internal clearance) of 12 eight hytes occurring, the LAPS frame can not mate fully with the IEEE802.3 frame, and be difficult to satisfy stand-by period and the little real-time Transmission demand of stand-by period deviation, and, because information field is based on 32 under Ipv4 or the Ipv6 datagram situation, therefore, need a kind ofly can have more flexibility and solution that can the real-time Transmission service data.

Summary of the invention

Therefore, main purpose of the present invention is to propose a kind of improved method and apparatus, for example is used to provide between physical layer equipment and network layer device that the real-time high speed point-to-point of Ethernet switch and SDH/SONET network is connected, full duplex, two-way simultaneous operation.The present invention proposes the little real time communication mode of stand-by period variation between a kind of new telecommunications SDH/SONET transmission equipment and long-range access data communications equipment, mac frame directly is fitted among the SDH/SONET.

For reaching top and other purpose, first purpose of the present invention provides a kind of from the data transmission device of upper layer device to lower floor's equipment transmission data bag, comprise: first receiving device, be used for receiving packet from upper layer device, convert described packet to first kind frame; First processing unit, be used for described first kind frame is packaged into the frame format of the SAPI field that comprises beginning flag, address field, control field, contains the SAPI identifier, the information field that comprises described packet, FCS field and end mark, form the second class frame; Second processing unit is used for the described second class frame is encapsulated into payload part, and inserts the suitable expense in response to described packet, forms the 3rd class frame; With first dispensing device, be used for described the 3rd class frame is outputed to lower floor's equipment.

According to a second aspect of the invention, provide a kind of from the data transmission method of upper layer device to lower floor's equipment transmission data bag, comprise the following steps: to receive and buffered data packet from described upper layer device, the speed of the speed of adaptive upper layer device and lower floor's equipment converts this packet to first kind frame; Described first kind frame is packaged into the frame format of the SAPI field that comprises beginning flag, address field, control field, contains the SAPI identifier, the information field that comprises described packet, FCS field and end mark, forms the second class frame; The described second class frame is encapsulated into payload part, and inserts suitable expense, form the 3rd class frame in response to described packet; With described the 3rd class frame is outputed to lower floor's equipment.

According to a third aspect of the invention we, provide a kind of and sent the data transmission device of the packet that is formed by first kind frame from lower floor's equipment to upper layer device, comprising: second receiving system is used for the equipment receiving data bag from described lower floor; The frame resolver is used for removing expense from described first kind frame; The 3rd processing unit, be used for extracting SAPI field and the data that are included in information field from the payload part of described first kind frame, form the second class frame, each described second class frame comprises: beginning flag, address field, control field, SAPI field, information field, FCS field and end mark; Determine device, be used for the value and the preset value of compare address field (SAPI field), and when value that address field data value equals to set, determine the data of output actual extracting; Manages device everywhere, is used for the described second class frame is converted to and corresponding the 3rd class frame of packet; With second dispensing device, the packet that is used for extracting sends to described upper layer device.

According to a forth aspect of the invention, provide a kind of and sent the packet data transmission method that forms by first kind frame to upper layer device, comprised the following steps: equipment receiving data bag from described lower floor from lower floor's equipment; From described first kind frame, remove expense; Extract SAPI field and the data that are included in the information field from the payload part of described first kind frame, form the second class frame, each described second class frame comprises: beginning flag, address field, control field, SAPI field, information field, FCS field and end mark; The value and the preset value of address field (SAPI field) are compared, when value that address field data value equals to set, determine the data of output actual extracting; The described second class frame is converted to and corresponding the 3rd class frame of described packet; Send to described upper layer device with the packet that will extract.

According to a fifth aspect of the invention, a kind of packet interface arrangement that is used for sending packet between upper layer device and lower floor's equipment is provided, has comprised according to the described data transmission device of first aspect present invention with according to the described data transmission device of third aspect present invention.

Description of drawings

By the detailed description of reference accompanying drawing to the embodiment of the invention, other aspects of the present invention and advantage will become and remove more.

By the reference accompanying drawing following detailed description, be understood that this invention:

Figure 1 shows that total schematic diagram of Ethernet over LAPS of the present invention, it provides point-to-point, full duplex, while way traffic, has adopted the relation between ethernet frame, LAPS and SDH to represent among the figure.

Figure 2 shows that the layer/protocol stack of the Ethernet over LAPS among the STM-N.

Fig. 3 is the layer/protocol stack of the Ethernet over LAPS among the sSTM.

Fig. 4 is a LAPS frame format of the present invention.

Fig. 5 is the example protocol configuration of Ethernet over LAPS.

Fig. 6 is the reconciliation sublayer/MII in Ethernet over LAPS and the relation between LAPS/SDH according to the present invention.

Figure 7 shows that the present invention realizes the exemplary configuration of gigabit Ethernet and SDH adapting function unit.

Figure 8 shows that the primitive relation between MAC, LAPS link layer and physical layer.

Shown in Figure 9ly be used for mac frame directly with SDH/SONET is adaptive or the Ethernet over SDH/SONET interface arrangement block diagram of simplification SDH/SONET according to the embodiment of the invention.

Figure 10 shows that the schematic diagram figure of IEEE 802.3 ethernet mac frame formats, define LAPS information field form at dash area among the figure.

Figure 11 shows that the LAPS frame format after the encapsulation MAC field.

Figure 12 A is depicted as the SPE/VC structure example of STM-N.

Figure 12 B is depicted as the POH schematic diagram of SONET and SDH.

Figure 12 C is depicted as STS-3c SPE or VC-4 structural representation.

Figure 13 shows that the more detailed block diagram of transducer 19 among Fig. 9.

Figure 14 shows that schematic diagram with Ethernet 2 layer switch of 2 EOS ports.

Figure 15 shows that schematic diagram according to the 10base-T of the SDH private network connecting band EOS device of the embodiment of the invention and 100BASE-T 2 layer switch, 1000BASE-x switch.

Figure 16 shows that the schematic diagram that connects IEEE 802.3 Ethernets 3 layer switch according to the SDH public network of the embodiment of the invention.

Figure 17 represents the complete matching relationship of frame internal clearance (IFP)/IEEE 802.3 frames and LAPS frame.

Embodiment

Below with reference to appended accompanying drawing, the preferred embodiment of the present invention is described in detail.In the following description, will not be described in detail for those well-known functions or structure, in order to avoid cover the present invention with unnecessary details.

The present invention is fitted to Ethernet SDH/SONET or simplifies the SDH/SONET network.Connect the very attracting mode that Ethernet switch and SDH/SONET network provide Ethernet over WAN.Connecting one or more ethernet switch ports is transparent to Ethernet.

For clarity sake, provide the abbreviation that this explanation and accompanying drawing are adopted below.

AUI accessory unit interface

The FCS Frame Check Sequence

GMII kilomegabit medium independent interface

The exchange of IPX the Internet packets

LAPS SDH Link Access Procedure

The LAN local area network (LAN)

The LLC logic link control

The access control of MAC medium

MAU medium adjunct unit

The MDI Media Dependent Interface

The MII medium independent interface

The SDH SDH (Synchronous Digital Hierarchy)

The STM Synchronous Transport Module level-N

SSTM Synchronous Transport Module level-N submodule

The VC virtual container

SAPI service access point identifier

The PLS physical layer signaling

The PCS Physical Coding Sublayer

The PMA physical medium attachment

The PHY physical layer equipment

The PMD physical medium is relevant

UITS negative response information transfer service

The HDLC High-Level Data Link Control

SPE synchronous payload envelope (envelope)

The TCP transmission control protocol

The UDP User Datagram Protoco (UDP)

Fig. 1 is an Ethernet over LAPS overall plan schematic diagram of the present invention, and it provides point-to-point, full duplex, while way traffic, and it adopts the relation between ethernet frame, LAPS and SDH to describe.

As shown in Figure 1, LAPS is used between 802.3 (802.3u/802.3z represents Ethernet/Fast Ethernet/gigabit Ethernet respectively) link layers and the media access control sublayer, physical layer is defined as the SDH that comprises various high-orders and low order VC, and the second layer is made up of three sublayers: LLC/MAC/LAPS.LAPS is a kind of typical HDLC, comprises data link traffic and protocol specification, and they have been used to adopt the IPover SDH of LAPS.

In this structure, has only an access point that offers media access control sublayer, uses for the mac frame of Ethernet/Fast Ethernet/gigabit Ethernet by the LAPS link layer.For example SAPI is " 0xfe01 (hexadecimal) ".At the whole M AC of media access control sublayer frame, when transmitting, be mapped to the LAPS link layer as the parameter of primitive.In the LAPS sublayer, the mac frame of mapping regard as the size that do not change them and sequence the LAPS information field (it comprise destination-address, source address, length/type, MAC customer data, PAD field (if any words) and the FCS field of complete mac frame).When these fields were put into LAPS as information field, its byte and bit-order remained unchanged.The adaptive UITS of LAPS link layer adopts primitive and parameter to be undertaken alternately by corresponding service access point and SDH physical layer.

LAPS is a kind of Physical Coding Sublayer, provides point-to-point to transmit by SDH virtual container and interface rate.The UITS that is supported is the connectionless-mode business.Between LAPS and SDH, adopt rate adapted.It provides a kind of mechanism of regulating ethernet mac MII speed to SDH VC speed, because SDH and MAC move with periodicity and sudden mode respectively, it also stops the mac frame that enters SDH VC to be written to the SDH expense.On the other hand, also can between LAPS sublayer and reconciliation sublayer, adopt rate adapted.

SDH transmits and is counted as a kind of synchronous point-to-point full-duplex link towards eight hytes.The SDH frame is a kind of synchronous multiplexing mapping structure towards eight hytes, and it has stipulated a series of standard speed, form and mapping method.Table 2 is depicted as the bandwidth value of VC, and table 3 is the STM interface rate of stipulating at present.Need not to use control signal.In synchronous payload envelope, inserting or therefrom during the information extraction, using motor synchronizing scrambler/descrambling (X ¹¹+ 1) function.

Table 2.SDH virtual container bandwidth

The VC type	VC bandwidth (kbit/s)	VC payload (kbit/s)
			VC-11	1,664	1,600
VC-12	2,240	2,176
			VC-2	6,848	6,784
VC-3	48,960	48,384
			VC-4	150,336	149,760
VC-4-4c	601,304	599,040
			VC-4-16c	2,405,376	2,396,160
VC-4-64c *	9,621,504	9,584,640

Table 3.STM interface rate

The STM type	STM bit rate (kbit/s)
		SSTM-11	2,880
SSTM-12	5,184
		SSTM-14	9,792
SSTM-18	19,792
		SSTM-116	37,444

SSTM-21	7,488
		SSTM-22	14,400
SSTM-24	28,224
		STM-0	51,840
STM-1	155,052
		STM-4	622,080
STM-16	2,488,320
		STM-64	9,953,280

The SONET transfer rate is the integral multiple of STS-1 (51.840Mbps), is the multiplying power that SONET uses at present below:

STS-1：51.840Mbps

STS-3：155.520Mbps

STS-9：466.560Mbps

STS-12：622.080Mbps

STS-18：933.120Mbps

STS-24：1244.160Mbps

STS-36：1866.240Mbps

STS-48：2488.320Mbps

STS-192：9953.280Mbps

Figure 2 shows that the layer/protocol stack of the Ethernet over LAPS among the STM-N.Below LAPS, have dual mode to insert VC:(1) the LAPS frame is inserted low order VC, by eight hytes are staggered high-order VC is arrived in the low order vc multiplexing according to the SDH multiplexing structure, transmit in proper order with multiplex section, regenerator section and electricity/light/radio section, then, extract the LAPS frame at receiving terminal with reverse order; (2) the LAPS frame is inserted SPE, SPE maps directly to high price VC, transmits in proper order with multiplex section, regenerator section and electricity/light/radio section, then, extracts the LAPS frame at receiving terminal with reverse order;

Fig. 3 is the layer/protocol stack of the Ethernet over LAPS among the sSTM.In this case, the LAPS frame is inserted low order VC (VC11, VC12 and VC2), by eight hytes are staggered the submultiplex section is arrived in the low order vc multiplexing according to SDH submultiplex structure, transmit them in proper order with regenerator section and electricity/light/radio section subsequently, extract the LAPS frame at receiving terminal with reverse order then;

Fig. 4 is a LAPS frame format of the present invention.As shown in Figure 4, LAPS seals by beginning flag sequence, address field, control field (0x03), SAPI (service access point identifier) (one eight hyte), information field (IPv4, IPv6 or ppp protocol data cell), FCS (Frame Check Sequence) and frame end mark sequence, and flag sequence (0x7E) is determined the starting and ending of LAPS frame.As can be seen from Figure, be connected to independent SAPI field after the control field, and address field has the purposes of itself, as described later.

Fig. 5 is the example protocol configuration of Ethernet over LAPS.In this case, Ethernet interface inserts the I/O gateway of another one Ethernet interface by SDH.Two types SDH and MAC physical interface are set on the gateway, and network layer remains unchanged, and remains IPv4/IPv6/IPX.

Fig. 6 is the reconciliation sublayer/MII in Ethernet over LAPS and the relation between LAPS/SDH according to the present invention.In this case, below MAC function sublayer, be provided with Ethernet fast/physical interface of three types of fast Ethernet/gigabit Ethernets, realize the adaptive of media access control sublayer and SDH physical layer at the SDH end by LAPS.

LAPS link entity from MAC layer received frame, does not have the address filtering function by reconciliation sublayer and of equal value MII (medium independent interface) here, the FCS of LAPS and MAC calculate respectively with reference to the ITU-T suggestion X.85/Y.1321 with IEEE 802.3 standards.The functional unit of Ethernet over LAPS connects link with its equity that the LAPS information field of all inputs is forwarded to except the link port of source, before forwarding one or more incoming frames is entered buffer.

Figure 7 shows that the exemplary configuration that realizes the adapting function unit of gigabit Ethernet and SDH according to the embodiment of the invention.As shown in the figure, only adopt full duplex mode.The functional unit of IEEE 802.3 Ethernets together with LAPS/SDH has been described among the figure.At the SDH end, realize the adaptive of media access control sublayer and SDH physical layer, gigabit Ethernet provides paired cable or 4 cable interfaces, monomode fiber interface, multimode fiber interface and the non-twisted-pair feeder interface of sheltering.

Figure 8 shows that the primitive relation between MAC, LAPS link layer and physical layer.Among the figure, LAPS provides a SAP, and the SAPI (service access point identifier) that is worth for 0xfe01 (decimal system) is used for Ethernet/Fast Ethernet/gigabit Ethernet.Primitive " DL_UNACK_ACK request " is used for sending mac frame to the LAPS link layer from the MAC layer, and primitive " DL_UNACK_DATA indication " is used for receiving packet to the MAC link layer from the LAPS link layer.Between LAPS link layer and physical layer, primitive " PH_DATA request " is used to set up the link from LAPS to the physical layer, and primitive " PH_DATAindication " expression sends the order that is used for link establishment from physical layer to the LAPS link; Primitive " PH_DATA request " is used for sending packet to physical layer from the LAPS link layer, and primitive " PH_DATA indication " is used for receiving packet to the LAPS link layer from physical layer.

Figure 9 shows that according among the Ethernet over SDH/SONET of the embodiment of the invention with mac frame directly with SDH/SONET or the adaptive interface arrangement block diagram of simplification SDH/SONET.Ethernet over SDH/SONET interface arrangement of the present invention (being abbreviated as the EOS device hereinafter) can be arranged in the telecommunications SDH/SONET transmission equipment so that Ethernet interface to be provided, or be arranged in the long-range access data communications equipment, so that the Ethernet interface of 155M, 622M, 2.5Gbps or 10G to be provided, even be connected between telecommunications SDH/SONET transmission equipment and the long-range access data communications equipment, with direct adaptive mac frame to SDH/SONET.

The EOS device is handled at the STS-3c/STM-1 that transmits and receive the both direction operative norm.

At sending direction, Ethernet speed is fitted to SDH/SONET speed, and the MII frame converts the LAPS frame to, and the LAPS frame is encapsulated among the SDH/SONET SPE/VC.Insert POH and TOH/SOH, resulting STS signal is sent to parallel/serial convertor so that eight hytes are wide, delivers to fiber optical transceiver by the line termination oral instructions then.According to the embodiment of the invention, under LAPS form situation as shown in Figure 4, the LAPS frame is packaged into the frame of form as shown in figure 11.

As shown in Figure 9, at sending direction, EOS device 1 comprises: send (TX) FIFO 8, be used for receiving gentle packet (as IPv4 or IPv6 bag or PPP bag, MPEG bag, voice packet and other packets) of bringing from ethernet side, with the speed of MII rate adapted to LAPS, for example the 100M MII frame of adaptive parallel burst is to periodic 155M LAPS frame; TX LAPS processing unit 7 is used for according to form shown in Figure 4 SAPI and data envelope being installed to the LAPS frame; Scrambler unit 6 is used for the LAPS frame is carried out scrambler; SPE/VC generation unit 5 is used to produce the pointer of indication SPE/VC position; The SDH expense is inserted unit 4, is used for inserting expense; TX SDH/SONET framer 3 is used for the LAPS frame behind the scrambler is encapsulated among the SPE/VC of SDH/SONET frame, forms the SDH/SONET frame.

At receive direction, its processing procedure in contrast.Receive the wide STS signal of eight hytes, the interface arrangement of Ethernetover SDH/SONET is given frame and TOH/SOH location, explains pointer, stops TOH/SOH and POH, extracts SPE/VC4, extracts the LAPS frame then from the SPE/VC4 payload.The SONET/SDH processor receives the SONET/SDH processor by one and a transmission SONET/SDH processor is formed.

Among Fig. 9, at receive direction, EOS device 1 comprises: receive (RX) frame parser (deframer) 9, be used for the SDH/SONET frame that receives is resolved; SDH overhead extraction unit 16 is used for removing the expense of SDH/SONET frame; Pointer processing unit 10 is used for locating and the explanation pointer, extracts SPE/VC4, isolates the LAPS frame from SPE/VC4; Descrambling unit 11 is used for the LAPS frame that extracts is carried out descrambling; Receive processing unit 12, be used for that the LAPS frame is carried out frame and resolve, extract the SAPI and the packet that are encapsulated in the LAPS frame; Receive FIFO 13, be used for buffered data packet, determine SAPI,, for example, the LAPS frame of periodic 155M is fitted to the 100M MII frame of parallel burst, send packet such as IP bag and SAPI the speed of LAPS rate adapted to MII.EOS device 1 also comprises: be used to monitor the TOH/SOH byte at the SDH of the wrong situation of change of various states expense monitoring unit 14: and monitoring POH byte is at the POH of the wrong situation of change of various states monitoring unit 15.

Receive the type that order unit (not shown) really is used for determining the packet that receives is set in the processing unit, generates one and be scheduled to SAPI accordingly, verification occurs in the mistake in the frame.

In addition, EOS device 1 also comprises: transducer 19, the packet that it makes upper layer device is synchronous at sending direction with the input packet that is input to first receiving device, and make the packet that from second dispensing device, extracts and upper layer device packet synchronous at receive direction; Line scan pickup coil side interface 2 is used for sending the SDH/SONET frame to peripheral SDH/SONET support equipment by the TX circuit, as O/E module (not shown), and by RX circuit reception SDH/SONET frame; Microprocessor I/F (interface) 18, all registers that it can make EOS device 1 insert wherein; The jtag port 12 that is used to test; And general input and output (GPIO) register 21 that is used for adhoc buffer I/O bag.

The major function of EOS device is:

● the information source of treatment S DH/SONET section, line and channel layer and the stay of two nights all have transmission/segmentation E1, E2, F1 and D1-D12 expense interface at both transmit and receive direction.

● by shining upon the LAPS frame with full duplex, realize the processing of STS-48c/STM-16 or STS-12c/STM-4 or STS-3c/STM-1 data flow to SDH/SONET or simplification SDH/SONET payload.

● with the multinomial (X of LAPS ⁴³+ 1) realizes self-synchronous scrambler/descrambler.

● a MII interface is provided.

● be provided for controlling, 8 or microprocessor of 16 bit interface of configuration and condition monitoring.

● LAPS handles with the ITU-T suggestion X.86 compatible.

● compatible to SD H/SONET standard such as ANSI T1.105, Bellcore GR-253-CORE and ITUG.707.

● IEEE 1149.1JTAG is provided test port.

● support diagnostic inloop lane testing.

● one 8 general purpose I/O (GPIO) are provided register.

Be the reception of interface arrangement of the present invention and the detailed description that sends processing below.In explanation subsequently, correlation function or operation and functional block or unit can be realized with executable program or example, in hardware.They will be omitted, to avoid unnecessary the obscuring to the main aspect of the present invention.

Receiving SDH/SONET handles

The suitable SDH/SONET receiving processor of the function of RX frame parser 9.The SDH/SONET receiving processor is used to realize framing, the descrambling of STS signal, the TOH/SOH monitoring that comprises B1 and B2 monitoring, AIS detection, pointer is handled and the POH monitoring.Receive the SDH/SONET processor and carry out following function:

● the SDH/SONET framing, detect [A1 A1 A2 A2] byte, these bytes will be used for framing, and OOF and LOF designator (single event and second incident, single event and second event) are provided.

● with the SDH/SONET frame synchronous scrambler payload is carried out scrambler, the scrambler multinomial is (X ⁷+ X ⁶+ 1).

● the B1 byte of monitoring input, the BIP-8 value that itself and restatement are calculated is compared.Error event information is provided, comprises the counting of single-bit error, erroneous frame and wrong time (Errored Second).

● the B2 byte of monitoring input, the BIP-86/24 value that itself and restatement are calculated is compared.Error event information is provided, comprises the counting of single-bit error, erroneous frame and wrong time.

● monitoring K1 and K2 byte, K1 and K2 are used for transmitting line/MS AIS or RDI, and are used for APS and post a letter.

● 4 LSB of the S1 byte that monitoring receives, to find out the homogeneity value of subsequent frame.

● monitoring M1 byte is used for definite B2 mistake number that is detected at its signal that receives by remote terminal.

● TOH/SOH separates E1, F1 and E2 byte and 2 serial D CC channels, SDCC (D1-D3) and LDCC (D4-D12) that the output of (drop) piece receives.

● pointer state determines to comprise inspection H1-H2 byte, with the state (normal, LOP, AIS) of setting up reception pointer.If pointer state is normal, then read first H1H2 byte to determine the beginning of SPE/VC.

● the POH monitoring module is made up of J1, B3, C2 and G1 monitoring, and these POH bytes are used for the wrong or variation of monitor state.

● monitor/catch j1 byte, in SONET uses, catch 64 continuous j1 bytes, in SDH used, the EOS device was searched 16 continuous j1 byte patterns of repetition.

● monitoring C2 byte, with the extension set type of check-verifying period.Check that branch is to find out 5 successive frames with identical C2 byte.

● the G1 of monitoring REI-P and RDI-P.

● the B3 byte of monitoring input compares itself and the BIP-8 value that calculates again.Error event information is provided, comprises the counting of single-bit error, erroneous frame and wrong time.

● for the error rate of determining received signal is on two different predetermined threshold value or under it, the EOS device is provided with two B2 error rate threshold pieces.When surpassing threshold value, by interrupting report signal inefficacy (SF) and signal degradation (SD) state.

Sending SDH/SONET handles

TX framer 3 realizes sending the function of SDH/SONET processor.The function that sends the SDH/SONET processor is that the LAPS frame is encapsulated among the SPE/VC.Then, it inserts suitable substance P OH and TOH/SOH, connects the serialiser of fiber optical transceiver after final STS signal is outputed to.

● synchronous payload envelope/virtual container (SPE/VC) generates piece will be multiplexing from the LAPS frame and path overhead (POH) byte of system interface, generate the SPE of SONET or the VC of SDH.

● support following POH byte: channels track (J1), channel B IP-8 (B3), signal label (C2), channel status (G1).Other POH bytes all are set to zero and transmit.

● carry out AIS and extemporal signal and insert.

● TOH/SOH generates, and comprising:

Frame byte A1A2-uses for test in order to test fixing F628 or the pressure wrong (Forced Error) by Microprocessor Interface.

Section tracking (J0)-can programme by Microprocessor Interface.

Duan Zengchang (Section Growth J0)-fixed mode 2～12.

Section BIP-8 (B1)-, use for test by calculating or the compulsory mistake of Microprocessor Interface.

Order line (Orderwire, E1E2)-external serial interface.

Section subscriber channel (F1)-external serial interface.

Data communication channel (D1-D12)-external serial interface.

Pointer byte (H1H2H3)-be fixed as 522 is forbidden NDF, and SS is able to programme.

Circuit BIP-96/24 (B2)-calculate or the compulsory mistake by Microprocessor Interface uses for test.

APS/MS AIS (K1K2)-can programme by Microprocessor Interface.

Synchronous regime (S1)-can programme by Microprocessor Interface.

Circuit/MS REI (M1)-calculate or the compulsory mistake by Microprocessor Interface is used for test.

● undefined TOH/SOH all is set to zero and transmits.To the payload scrambler, multinomial is x with the SONET/SDH frame synchronous scrambler ⁷+ x ⁶+ 1.

Describe the LAPS processing procedure below in detail

LAPS handles

EOS device 1 extracts frame/bag by the LAPS processor from SONET payload envelope (SPE).EOS device 1 also supports stream by pattern (Flow-thru mode), and this pattern allows SPE directly to pass through system interface.The LAPS processor is that LLC and other packet-based data are carried out LAPS class framing.The LAPS processor is a single channel engine, is used for X.86 data envelope being installed to the LAPS frame according to the ITU-T suggestion.The LAPS processor is only to byte-aligned data manipulation (for example the length of message is the integer byte).In the EOS pattern, the LAPS processor is divided into reception LAPS processor and sends the LAPS processor.

Encapsulation

The MII (medium independent interface) of LAPS link entity by reconciliation sublayer and equivalence receives the frame from the MAC layer.Here do not use the address filtering function.

Figure 10 shows that the schematic diagram of IEEE 802.3 ethernet mac frame formats, dash area has defined LAPS information field form among the figure.Figure 11 shows that the LAPS frame format after the encapsulation MAC field.The FCS of LAPS and MAC calculate respectively with reference to the ITU-T suggestion X.85/Y.1321 with IEEE 802.3 standards.The equity that the functional unit of Ethernet over LAPS is transmitted all input LAPS information fields except the link port of source connects link, before forwarding, allows the one or more incoming frames of buffering.What Fig. 4 was represented is the relation of reconciliation sublayer/MII and LAPS/SDH.

Receive the LAPS processor

The function that receives LAPS processor 12 is to extract the descrambling of LAPS frame, transparent elimination (TransparencyRemoval), fcs error verification, SPE/VC payload, control and deletion of address field option and performance monitoring.

After beginning/end of removing the filling of field sign and byte, remaining payload comprises data and FCS field, and more detailed details please be seen accompanying drawing.Notice that only need a flag byte at two parlors, all signs between the bag all will abandon.At receiving terminal, the basic step that LAPS handles is as follows: eight all hytes of descrambling before handling, remove the 0x7E that interframe is filled, detect beginning flag, when detection has rate adapted eight hyte { 0x7d, when existing, 0xdd} removes it, the processing of the execution transparency (comprise 0x7d, 0x5e-〉0x7e and 0x7d, 0x5d-〉0x7d), verify the validity of fields such as SAPI and address, calculate and check FCS, detect end mark, mac frame is synchronized to RX CLK, the frame structure of pressing IEEE802.3 increases lead code (Preamble) and SFD (Start Frame Delimiter), forms mac frame and hands to the MAC layer by the MII/GMII interface.

Receive the LAPS processor and carry out following function:

● alternatively to receiving payload motor synchronizing descrambling (multinomial X ⁴³+ 1).

● detect and stop the LAPS frame, delimit Mark Detection as frame.

● remove control escape code (Control Escape) and fill.

● calculate optional FCS code (32), and compare with the FCS value that receives.Performance monitoring register pair mistake is accumulated.If detect fcs error, the data markers of output is a misdata.

● (0x7D, 0x7E) detects abort sequence in byte stream.

● randomly delete address and control field.

● provide optional minimum and maximum packet length to detect (SW configuration), the RX_ERR signal of specified data is with the marked erroneous state.

● generate performance monitoring to eight hytes: fcs error, stop bag, short bag (Short Packet), long bag, because the bag that the RXFIFO mistake abandons.

● randomly deletion is used to handle the bag filling of far-end FIFO underflow situation.

● under error situation, generate and interrupt.

● deletion generates the Inter-packet gap sign automatically.

● for rate-matched, if possible, remove interframe gap byte of padding able to programme (0x7E).

● by transducer 19, make LAPS information field (MAC/GMAC frame) synchronous with the receive clock (RX_CLK) of MII/GMII interface from the SDH/SONET piece.

LAPS frame synchronization

Flag sequence (0x7E) is determined the beginning and the end of LAPS frame.To the SPE payload data that receives one by one the search of eight hytes search flag sequence so that give LAPS frame boundaries location.Be used for determining that eight octet value of flag sequence are programmable, default value is 0x7E.

Two continuous mark sequences constitute an empty frame, ignore for empty frame.Therefore, N continuous mark sequence constitutes N-1 empty frame.Abandoned dumbly for too short frame, invalid frame.If a LAPS frame belongs to following a few class, this frame is regarded as invalid frame:

A) can not delimit fully by two signs;

B) between flag of frame, be less than 6 eight hytes;

C) contain a Frame Check Sequence mistake;

D) contain one with " 4 " (based on business of IPv4), " 6 " (based on business of IPv6), " 255 " (based on business of PPP) is unmatched or the unsupported Service Access Point Identifier of receiver symbol;

E) contain the control word segment value that to discern;

F) with a EOS more than 6 " 1 " position;

LAPS eight hytes are gone to fill and are handled

LAPS eight hytes go filling process (being called the escape conversion sometimes, Escaping Transform) before FCS calculates, the LAPS frame that is applied to receive after the LAPS frame synchronization.By the beginning of detection control escape eight hytes (Control Escape Octet) flag sequence and the whole LAPS frame between end, realize the filling of going of eight hytes.In case find, remove control escape eight hytes from eight hytes stream, eight hytes thereafter go filling to shelter eight hytes (Octet De-Stuffing Masking Octet) execution or ETTHER-OR operation with one eight hyte.Should not regard terminator sequence as escape sequence (Escape Sequence).

The value of control escape eight hytes is programmable, and its default value is 0x7D.It also is programmable that eight hytes go filling to shelter eight hytes, and its default value is 0x20.As an example, 0x7E is encoded into 0x7D, 0x5E, and 0x7D is encoded into 0x7D, 0x5D.

The LAPS terminator sequence

In input LAPS frame, the detection of terminator sequence (the control escape code of heel flag sequence) is optional.Terminator sequence indicates an end that stops the LAPS frame.

Send the LAPS processor

Sending LAPS processor 7 will be inserted among the STS SPE based on the information of bag, and it provides seals dress, the generation of FCS field, parlor filling, the recovery of TXFIFO mistake and scrambler.At transmitting terminal, the basic step that LAPS handles is as follows: detect SFD (Start Frame Delimiter) and receive mac frame by the MII/GMII interface, mac frame is synchronized to the SDH/SONET clock, increase beginning flag 0x7E, with address field, control field, SAPI field and LAPS information field are range computation FCS, carry out transparency processing and (comprise 0x7d, 0x5e-〉0x7e and 0x7d, 0x5d-〉0x7d, and rate adapted, in Abort sequence and attribute field be not included in), if necessary with 0x7d, the mode of 0xdd} adds rate adapted eight hyte 0xdd (change able to programme), increase end mark, increase the 0x7E that interframe is filled if necessary, before sending, eight all hytes are carried out scrambler, be mapped to SDH/SONET again.

● will seal and install in the LAPS frame, each bag is with opening flag (0x7E), optional FCS field, optional SAPI field, address and control field, optional end mark (0x7E) encapsulation, as shown in figure 11.

● optionally (multinomial is X to motor synchronizing transmission payload scrambler ⁴³+ 1).

● by ITU-T X.85 requirement carry out transparent processing (sign and control escape code are carried out eight hytes fills).Need carry out byte between beginning and trailer field sign fills.Fill raw bytes, replace any match flag or control the byte of escape byte by the sequence of controlling two byte longs that escape forms with heel and 0x20 (hexadecimal) XOR.

● generate beginning and trailer field sign (0x7E).Note, can share single sign at two parlors.

● randomly be that Frame Check Sequence (FCS) generates 32 CRC.

● provide fcs error to insert ability, so that under software control, test.

● the TX_PRTY mistake produces interrupts.

● FIFO is provided the processing selected of underflow.When TXFIFO empties the time during early than end-of-packet, can produce FIFO underflow situation.When this situation has taken place, can cause interruption.At this moment, bag can finish by following several modes: generate fcs error, generate terminator sequence, maybe can dispose escape code by SW and insert " filling " byte during Inter-packet gap.

● generate the performance monitoring counting, comprising: the bag quantity (configurable SW) of fifo error event number, abnormal end packet count, violation minimum and maximum bag long parameter.

● by transducer 19, make the MAC/GMAC frame and the SDH/SONET piece clock synchronization that receive from MII/GMII.

● if necessary,, increase speed inter-packet gap byte of padding able to programme (0x7E) for rate-matched.

The FCS multinomial

EOS device 1 supports CRC-32 Frame Check Sequence (FCS) to generate and verification.

FCS at first transmits minimum effective eight hytes (LSB), and minimum effective eight hytes include the highest coefficient.The EOS device has two kinds of FCS account forms: according to low order order (Little endianbit order) or the high significance bit order (Big endian bit order) of LAPS.

Following multinomial is with generating and verification FCS value CRC-32:1+x+x ²+ x ⁴+ x ⁵+ x ⁷+ x ⁸+ x ¹⁰+ x ¹¹+ x ¹²+ x ¹⁶+ x ²²+ x ²³+ x ²⁶+ x ³²The FCS field is calculated by all bits of address, control, SAPI and information field, but does not comprise for transparent and any eight hytes that insert.This neither comprises flag sequence, does not also comprise FCS field itself.For two kinds of FCS methods, it all is logical one that CRC maker and checker all are initialized to.After FCS calculated and finishes, the FCS value was 1 complement code, and this just inserts this new value in the FCS field.

Below, describe according to the present invention the processing procedure of data on sending direction in detail.

The sending direction data processing

At sending direction, EOS device 1 inserts packet-based data among the STS/STM SPE.The operation of equipment pattern can be adopted by the management control interface and be provided.Register value TX_EOS=1 makes equipment be in the EOS pattern.

Send fifo interface

In the EOS pattern, the transmitting system interface moves as compatible MII interface.

1. send FIFO

TX FIFO 13 by inserting 0x7E sign or reception and transmitting terminal by synchronous TX FIFO, will convert periodic LAPS frame (as 155M) to by parallel processing from the MII burst frame (as 100M) that transducer 19 receives.

The transmitting system interface is controlled by the link layer device before being positioned at the EOS device on the sending direction of sendaisle.Link layer device provides a clock that is used for synchronous total interface transmission to the EOS device interface.This about provisioning request EOS device has a rate-matched buffer (as FIFO).The minimum value of FIFO size is 512 bytes.The EOS device also passes through the state (mistake is formed, wrapped to the last character of the beginning/end of packet/cell, grouping whether by one or two eight hyte) of FIFO transmission package.

2. transmission fifo error

In the EOS pattern, the FIFO attitude is monitored by the EOS device, when following situation occurring, announce the fifo error state to occur: 1) in the preceding MII_TX_SOP of receiving of end-of-packet (TX_EOP indication), 2) activate MII_TX_ENB following outside uncertain " send window " of TX_CLAV signal.By MII_TX_FIFOERR_E=1 being set to management interface report fifo error incident.The EOS device has 8 fifo error counters, record be subjected to the fifo error events affecting each wrap.

When the performance monitoring counter was latched, this Counter Value was by MII_TX_FIFOERR_CNT[7:0] register latchs, and empties the fifo error counter.If since the last rising edge of LATCH_EVENT, occurred one time the fifo error incident at least, fifo error event bit-MII_TX_FIFOERR_SECE then be set.In the EOS pattern (MII_TX_EOS=1), the EOS device stops wrong bag.

3.EOS erroneous packets is handled

In EOS operational mode (MII_TX_EOS=1), provide the erroneous packets processing procedure.

4.TX_ERR link layer indication

When a special grouping contains mistake and should stop or abandon (see MII_TX_ERR definition), the transmitting system interface provides a kind of link layer device can be used to refer to method to the EOS device.

EOS device 1 comprises 8 link layer error counters, and it is to each bag counting of the wrong sign that receives from link layer.When the performance monitoring counter is latched (LATCH_EVENT send be in a high position), the value of this counter is by MII_TX_EOS_LLPKT_ERRCNT[7:0] register latchs, and empties link layer bag error counter.If since the last rising edge of LATCH_EVENT, occurred link layer bag error event at least one time, link layer erroneous packets error event position then is set, MII_TX_EOS_LLPKT_ERR_SECE.

5. minimum/maximum bag is big or small

EOS has an option, if bag has surpassed minimum or maximum bag size, then the EOS device is thought that this contracts out and showed mistake, and does not send or stop this bag.The bag size only refers to the size of LAPS bag, does not comprise the byte (flag sequence, address, control, SAPI, FIFO underflow, transparent or FCS byte) that the EOS device inserts.These minimums and maximum can be by the programmings of management control interface.Register MII_TX_EOS_PMIN[3:0] comprise parcel size, its default value is 6.Register MII_TX_EOS_PMAX[15:0] comprise maximum bag size, its default value is 0x05E0.

EOS device 1 is forbidden/allows minimum by the instruction of management interface and the big or small verification of maximum bag.If MII_TX_EOS_PMIN_ENB or MII_TX_EOS_PMAX_ENB=1 allow because the bag of violation bag size restriction stops.If=0 (default setting) then ignored the big or small limitation function of bag.

EOS device 1 comprises two 8 digit counters, and the big or small restrictive condition of the minimum and maximum bag of each violation is counted.When the performance monitoring counter was latched, the value of these counters was by MII_TX_EOS_PMIN_ERRCNT[7:0] and MII_TX_EOS_PMAX_ERRCNT[7:0] register latchs, and empties the big or small fault counter of bag.If since the last rising edge of LATCH_EVENT, occurred at least once wrapping big or small fault mistake, suitable bag size fault secondary event bit then is set, MII_TX_EOS_PMIN_ERR_SECE or MII_TX_EOS_PMAX_ERR_SECE.

6. erroneous packets stops

After unwrapping beginning transmission, if receive or detect error situation, EOS device 1 can not be deleted bag, so these bags will be terminated.The EOS device is supported two kinds of systems of selection that stop erroneous packets.

Default option is to stop a bag by inserting terminator sequence 0x7d7e.The far-end receiver abandons this bag after receiving this code.Another scheme is to stop erroneous packets by inversed F CS byte simply.Termination pattern is controlled by the management control interface.MII_TX_EOS_FCSABRT_ENB=1 is the FCS inverting method, and MII_TX_EOS_FCSABRT_ENB=0 (default setting) forbids the FCS inverting method.

Line scan pickup coil side bag loopback

In order to test, EOS device 1 provides the user loopback packet function, and the bag that it will extract from the SONET/SDH signal is inserted among the FIFO of sending direction,, replaces the data that receive from system interface here.These data enter transmitting terminal LAPS processing then, send back to the SONET/SDH circuit at last.When MII_R_TO_T_LOOP was set to 1, loop fuction activated.When MII_R_TO_T_LOOP is set to 0, forbid loopback, carry out the normal handling process.This loop fuction mainly is to be used for testing of equipment.In actual motion, if receive clock faster than tranmitting data register, and the SONET/SDH payload has been filled packet, then because transmitting terminal can not hold whole speed of receiving terminal, will produce periodic fault.

Send the LAPS process

Behind the transmitting system interface, when EOS pattern (MII_TX_EOS=1), EOS device 1 is carried out following the processing:

1. wrapper in the LAPS frame

According to the LAPS frame definition that is used for EOS of the embodiment of the invention as shown in Figure 4.In the EOS pattern (MII_TX_EOS=1), each LAPS bag that receives from link layer is used in the flag sequence that ITU-T defines X.85 and describes, and flag sequence is used to refer to the beginning and the end of LAPS frame, and its value is 01111110 (hexadecimal is 0x7e).

As one of option, the EOS device can insert single sign and indicate the end of a frame and the beginning of next frame, and this function is controlled by management interface.If MII_TX_EOS_EOP_FLAG=1, then the EOS device inserts separation flags, with the beginning and the end of indication frame.If MII_TX_EOS_EOP_FLAG=0 (default setting) then inserts single flag sequence only.

Forbidding generating the FCS field in particular cases, the EOS device is ignored MII_TX_EOS_EOP_FLAG, inserts frame all the time and begins and the end mark sequence.This is a kind of non-standard operational mode, because according to ITU-T X.85, the FCS field is mandatory.This specific character requires to guarantee that receiving terminal can true(-)running in test process.During this period, ban use of FCS, might be the packet of byte.

2. address and control field

X.86 standard definition immediately following two fields after the start of frame delimiter sequence: an address field, this field is set to 0x04 or 0xff; With a control byte, this byte is defined as 00000011.In EOS pattern (MII_TX_EOS=1), the EOS device can be selected to insert these fields, if MII_TX_EOS_ADRCTL_INS=1.If MII_TX_EOS_ADRCTL_INS=0 (default setting) does not then insert these fields.

3. the transparency is handled

At EOS pattern (MII_TX_EOS=1), eight hyte filling processs carry out on a point that is known as transparent processing (Transparency Processing).Special eight hytes, one control escape code (01111101 or hexadecimal 0x7d) needs the byte of special processing at receiving terminal with indication as identifier.The control escape code is used for the appearance of any special code in the marker frames data.

After carrying out FCS calculating, the entire frame between any two flag sequences of EOS device inspection.Each any code that is masked as 0x7e or 0x7d that occurs by heel by carrying out two the eight hyte sequences replacements that control escape eight hytes of original eight hytes of XOR are formed with hexadecimal 0x20 sign indicating number.The EOS device carries out transparent processing to following byte sequence, and an exception is the flag sequence that is used for descriptor frame that the EOS device inserts.0x7e in the payload (between flag sequence) is described below:

0x7e is encoded as 0x7d, 0x5e;

0x7d is encoded as 0x7d/0x5d.

SPE generates

1.EOS operation (MII_TX_EOS=1)

EOS stream is mapped in the payload of SONET/SDH synchronous payload envelope (SPE) subsequently.EOS eight hyte borders and SPE eight hyte boundary alignments.Because the EOS frame length is variable, therefore, they are allowed to cross over the SPE border.In running, when not having to insert the LAPS frame of SPE immediately, send the time that flag sequence is filled LAPS interframe.This just just carries out two complete interframe.Available information speed to the Ethernet over SONET/SDH of STS-3c/STM-1 is 149.760Mbps.

2.FIFO underflow

In EOS pattern (MII_TX_EOS=1), natural is empty at two parlors, but should not be empty when bag sends, and it can not be empty promptly receiving after the MII_TX_SOP indication, but can be empty before receiving the MII_TX_SOP indication.If this situation has taken place, the EOS device provides two kinds of selection schemes for handling the FIFO underflow: available termination pattern stops bag; Maybe can send a special code, MII_TX_EOS_FIFOUNDR_BYTE[7:0], fill SPE, valid data appear in FIFO once more.Register MII_TX_EOS_FIFOUNDR_MODE control response; MII_TX_EOS_FIFOUNDR_MODE=0 represents that bag will be terminated, and this is a default value.When MII_TX_EOS_FIFOUNDR_MODE=1 is illustrated in the generation of underflow situation, will send special FIFO underflow code MII_TX_EOS_FIFOUNDR_BYTE[7:0].MII_TX_EOS_FIFOUNDR_BYTE[7:0] be default value 0x?

SPE/VC generates

The structure of STS-3c SPE or VC-4 is shown in Figure 12 A-C.First row of SPE/VC are POH (path overheads).Path overhead has 9 bytes.The order of these 9 bytes is J1, B3, C2, G1, F2, H4, Z3, Z4 and Z5 to SONET, is J1, B3, C2, G1, F2, H4, F3, K3 and N1 to SDH.First byte of path overhead is channels track byte J1, the position of indicating its relative SONET/SDH TOH/SOH by relevant STS/AU pointer.Define the transmission value of POH byte below.Here the byte title of SONET and SDH is different, at first lists the title of SONET.

1. channels track (J1)

In j1 byte, EOS can send the channels track message of one 16 byte or 64 bytes, and message stores is at MII_TX_J1_[63:0] _ [7:0] in.If MII_TX_J1_SEL=0, then j1 byte is with from MII_TX_J1_[15] _ [7:0] to MII_TX_J1_[0] _ 16 byte sequences of [7:0] repeat to send, otherwise with from MII_TX_J1_[63] _ [7:0] to MII_TX_J1_[0] _ 64 byte sequences of [7:0] repeat to send (common 16 byte sequences are used for the SDH pattern, and 64 bytes are used for the SONET pattern).

2. channel B IP-8 (B3)

If B3_INV=0, then Bit Interleave parity check bit 8 (BIP-8) sends as even parity position (normally), otherwise generates odd parity position (incorrect).BIP-8 calculates all positions of previous SPE/VC (comprising POH), and its value is inserted in the B3 byte of current SPE/VC.

By definition BIP-8, first primary parity check that previous all bytes of SPE/VC are provided of B3, second deputy parity check that previous all bytes of SPE/VC are provided of B3, or the like.

3. signal label (C2)

The composition of signal label byte indication SPE/VC.Preset value TX_C2[7:0] be inserted in the C2 byte of generation.

4. channel status (G1)

Passage REI

B3 bit-errors among the SPE/VC that the receiving terminal monitoring receives.The detected B3 mistake religion of each frame (0 to 8) is transferred to transmitting terminal from receiving terminal, is inserted among the sendaisle state byte G1, as remote error indication (Remote Error Indication).If FORCE_G1ERR=1, then 4 of G1 MSB (highest significant position) send (doing test uses) continuously as 1000.PERI_INH=0 else if, then they are set to equal the binary value (0000 to 1000, indication 0 to 8) of the nearest detected B3 mistake number of receiving terminal POH monitoring module.Otherwise, they all are set to zero.

Passage RDI

The 5th of G1 can be used as passage/administrative unit remote failure indication (RDI-P), perhaps the 5th, 6 and 7 of G1 the RDI-P designator as enhancing.Transmission value in the 5th, 6 and 7 of G1 or from TX_G1[2:0] register produces (if PRDI_AUTO=0), perhaps the EOS device generates RDI signal (if the PRDI_AUTO=1 of an enhancing automatically, PRDI_ENH=1), or RDI signal (if PRDI_AUTO=1, PRDI_ENH=0).The value that sends in the 5th, 6 and 7 of G1 is as shown in table 4.

Table 4 passage RDI place value

?PRDI_Auto	PRDI_ENH	RX_PAIS RX_LOP	RX_UNEQ	RX_PLM	5,6 and 7 of G1
						0	x	x	x	x	Tx_G1[2，0]
1	0	1	x	x	100
						0	x	x	000
		1	1	x	x					101
	0					1	x	110
			0	0	1				010
	0					0	0	001

If PRDI_AUTO=1, minimum transmission 20 frame of value then recited above.In case sent 20 frames with identical value, then sent the faulty indication value of the current attitude that correspondence table 4 lists.The 8th (least significant bit) of G1 do not use, and is set to 0.

5. other POH bytes

EOS device 1 is not supported the POH byte be left, and these bytes are with fixing whole zero bytes transmissions.These bytes comprise that passage subscriber channel (F2), location pointer (H4), passage growth/subscriber channel (Z3/F3), passage growth/passage APS channel (Z4/K3) and front and back connect monitoring byte (Z5/N1).

The SONET/SDH frame generates

SONET/SDH frame generation module is created STS-3c/STM-1 by generation transmission (section) expense (TOH/SOH) byte, with from the byte filling payload of SPE/VC, to all the byte scramblers except that the TOH/SOH byte of first row.

1. frame is aimed at

With respect to the TX_FRAME_IN of input, the position of delta frame is fixed.Frame begins to indicate output TX_FRAME_OUT and TX_FRAME_IN to import to have a fixing but not otherwise specified relation.The last clock cycle broad pulse of TX_FRAME_OUT and transmitting line output TX_DATA[7:0] relation of data byte is by MII_TX_FOUT_BYTE_TYPE[1:0] and TX_FOUT_BYTE_NUMBER[3:0] register controlled.

2. payload generates

SONET or SDH payload are under normal circumstances filled by the SPE/VC byte and are formed.In STS-3c/STM-1 pattern (MII_TX_SIG_MODE=0), the j1 byte of SPE/VC is placed on the 10th and is listed as in the 1st row.

Circuit (multiplex section, MS) alarm indication signal (AIS) LAIS, or passage (administrative unit, during AU) alarm indication signal (PAIS) sends, the normal generation of having hung the SONET/SDH payload.The generation of MII_TX_LAIS and MII_TX_PAIS register controlled AIS.If MII_TX_LAIS or MII_TX_PAIS=1, then whole payload (9396 or 2349 byte) is all filled with 1 byte.

Unless activated AIS, otherwise, if TX_UNEQ=1 then generates offhand SPE/VC (all SPE/VC bytes are all used zero padding).

3.TOH/SOH generate

SONET TOH byte is the same with SDH TOH byte basically.Hereinafter define all TOH/SOH byte values that generate.When the byte title of SONET and SDH is different, at first list the used title of SONET.Blank part in the standard is a undefined or SDH nonstandardized technique reserve bytes among the SONET.EOS device 1 is all used zero padding with these bytes.

In sending LAIS or PAIS process, hung the normal generation of TOH/SOH byte.If MII_TX_LAIS=1 then normally generate 3 row that TOH/SOH begins most, but TOH/SOH remainder (and all SPE/VC bytes) all is to be provided with 1 to send again.If MII_TX_PAIS=1, then in the 4th row institute's pointer byte, all row bytes of TOH/SOH all normally generate.H1, H2 and H3 byte (and all SPE/VC bytes) all are set to 1 and transmit.

With the normal delta frame byte of following fixed mode:

A1：1111_0110＝F6；

A2：0010_1000＝28。

For the purpose of testing, A1 and A2 can comprise mistake when generating.If A1A2_ERR=0 does not insert mistake.When A1A2_ERR=1, pass through A1A2_ERR_PAT[15:0] value and A1 and A2 carry out XOR and generate m successive frame in each group of 8 frames (m is equivalent to A1A2_ERR_NUM[2:0] binary number) here, the highest significant position of A1 and A1A2_ERR_PAT[15] carry out XOR, the least significant bit of A2 is A1A2_ERR_PAT[0] carry out XOR.

During 16 successive frames, the EOS device sends continuously and is included in MII_TX_J0_[15:0] _ 16 byte modes of [7:0], from MII_TX_J0[15] _ [7:0] byte begins to send by the order of successively decreasing.

The ITU-T G.707 standard code 16 bit field tracking frames of service access point identifier (SAPI) that contain the 3rd/G.831 definition sends continuously with continuous J0 byte.Note having only start of frame delimiter symbol byte to should be 1 at its highest significant position.

At present, not to SONET definition phase following function.Unless follow the tracks of field to similar section of SONET definition, otherwise all MII_TX_J0 bytes should adopt 0000_0001 to fill, and therefore, send one metric 1 continuously in J0.Z0 byte binary system order with 2 to 12 in STS-12c/STM-4 (MII_TX_SIG_MODE=1) pattern sends, and is 2 to 3 (these stipulate in GR-253) in STS-3c/STM-1 (MII_TX_SIG_MODE=0) pattern.

If MII_B1_INV=0, then B18 position Bit Interleave parity check (BIP-8) sends with even parity position (correct attitude), otherwise generates odd parity position (incorrect).BIP-8 to previous scrambler after the STS-3c/STM-1 frame all the position calculate, before scrambler, insert in the B1 byte of present frame.By definition BIP-8, first primary parity check that all bytes of former frame are provided of B1, second deputy parity check that all bytes of former frame are provided of B1, or the like.

Defined instruction line byte is used for carrying the audio digital signals of two 64kb/s.F1 byte uses to the network provider.Send piece and receive 3 serial inputs: MII_TX_E1_DATA, MII_TX_E2_DATA and TX_F1_DATA are used for being inserted among E1, the E2 and F1 byte of transmission.From single notched 64kHz clock (MII_TX_E1E2F1_CLK) of EOS device 1 output, so that provide clock reference for these three serials inputs.

First (highest significant position) of these bytes should begin pulse MII_TX_FRAME_IN with incoming frame and align.After receiving last position of E1, E2 and F1 byte, the E1 that receives, E2 and F1 byte are inserted in the SONET/SDH frame of output.

TOH/SOH has defined two kinds of DCC (data communication channel), and section/regeneration section dcc produces a notched 192kb/s channel with D1, D2 and D3 byte.Circuit/multiplexing section dcc produces a notched 576kb/s channel with D4 to the byte of D12.Transmitting terminal is imported at dual serial: MII_TX_SDCC_DATA and MII_TX_LDCC_DATA receive the DCC data.In order to guarantee bit synchronization, two clock: MII_TX_SDCC_CLK of transmitting terminal output, 192kHz (band breach); And MII_TX_LDCC_CLK, 576kHz (band breach).Clock signal can make MII_TX_SDCC_DATA and MII_TX_LDCC_DATA position relocate register, to be inserted into TOH/SOH.MII_TX_SDCC_DATA and MH_TX_LDCC_DATA input should change according to MII_TX_SDCC_CLK and MII_TX_LDCC_CLK trailing edge, because make at rising edge when resetting.

H1 and H2 byte comprise 3 fields.Because SPE/VC and TOH generate synchronously, so need not to generate variable pointer.In contrast, effectively H1 and H2 byte generate with fixed pointer value 522 (decimal system)=10_0000_1010 (binary system), and the H3 byte all is fixed as 0.Like this, j1 byte is placed on the 1st row the 10th row among the SPE/VC in STS-3c/STM-1 pattern (MII_TX_SIG_MODE=0).

If MII_TX_LAIS or TX_PAIS are in activated state, then H1, H2 and H3 byte all are set to 1 when sending.When MII_TX_LAIS or TX_PAIS were converted to 0, EOS device 1 sent first H1 byte with an effective new data flag (NDF) in next frame.In first H1 byte, generate subsequently frame with forbidden NDF field.First H1-H2 byte is to sending with positive constant pointer, at this moment:

●NDF＝0110；

●SS＝TX_SDG_PG，0；

● pointer value=10_0000_1010;

Every other H1-H2 byte is to sending with cascade indication byte, at this moment:

●NDF＝1001；

●SS＝TX_SDG_PG，0；

● pointer value=11_1111_1111;

Below in the description of B2 byte, slightly change according to different its values of equipment mode (STS-12c pattern and STS-3c).In order to describe the operation of two kinds of patterns, the agreement below adopting is distinguished the requirement of every kind of pattern: STS-3c.TOH/SOH has 12[3] individual B2 byte, they together provide BIP-96[BIP-24] error detecing capability.

Each B2 byte is the 12[3 in the previous frame] byte in 1 group of byte of group in the byte provides BIP-8 parity check.B2 byte in the j row is that the byte that is positioned at j+12k (j+3k) in the previous frame (TOH/SOH begins except 3 row) provides BIP-8 parity check, here k=0 to 89.If B2INV=0, then BIP-8 sends with even parity position (normal state), otherwise, generate odd parity position (mistake attitude).The BIP-8 value is calculated the byte in the previous STS-3c/STM-1 frame before scrambler, inserts before scrambler in the B2 byte of present frame.

5 highest significant positions of K1 and K2 are as protecting exchange (APS) signal automatically.As AIS or remote failure indication (RDI), in SONET, they are also as the APS signaling at circuit/MS layer for 3 least significant bits of K2.EOS device 1 inserts MII_TX_K1[7:0 in the K1 byte that sends], in 5 MSB bytes of the K2 that sends, insert MII_TX_K2[7:3].

3 LSB positions of K2 are controlled by 3 sources, and according to priority, they are:

● if TX_LAPS=1 during transmission, all is set to 1 (the same with all circuits/MS overhead byte) with them.

If ● LRDI_INH=0, and if any one equals 1 among (MII_RX_LOS AND NOTRX_LOS_INH), MII_RX_LOF, MII_RX_LOC or the MII_RX_LAIS, then they are with 110 yards transmissions.No matter when activate this special event, the K2 of minimum 20 frames is set to 110.

● otherwise send MII_TX_K2[2:0] sign indicating number.

RX_LOS can be activated to a high position (MII_RX_LOS_LEVEL=0, default value) or be activated to low level (MII_RX_LOS_LEVEL=1).In inside, if MII_RX_LOS_LEVEL=1 then inserts MII_RX_LOS to produce MII_RX_LOS.GR-253 R6-180 has required to stipulate that to R-182 should insert and remove RDI during the LOS that receives, the LOF of 125 μ s or LAIS detects.

4 LSB of this byte transmit Synchronication status message.The S1 byte that transmission is set equals MII_TX_S1_[7:0].

B2 bit-errors in the receiving terminal monitoring received signal, the detected B2 mistake of the every frame scope of counting is 0 to 96 B2 position of every frame in the STS-12c/STM-4 pattern, is 0 to 24 B2 position of every frame in the STS-3c/STM-1 pattern.Usually, circuit/MS remote error indication (REI) byte, M1 byte are transmitted in detected B2 error count in the received signal.

By TX_M1_ERR=1 is set, the user can force to send the indication of REI mistake.At this moment send any one (STS-3c/STM-1 pattern) in 24 numerical value in the M1 byte.If LREI_INH=0, then the M1 byte is configured to the B2 error count that equals nearest.Otherwise, the M1 byte all is set to 0.

Because Z1 and Z2 byte do not have standardization, therefore, EOS device 1 all is filled to 0 with these bytes.

Scrambler

With a synchronous scrambler sequence input data are carried out scrambler, the scrambler multinomial is x ⁷+ x ⁶+ 1.The scrambler initialization that begins place's (being positioned at the byte i of 1 row, 10 row in the STS-3c/STM-1 pattern) in first byte of SPE/VC is 1111111, and the whole SONET/SDH signal except that the first row TOH/SOH byte is carried out scrambler.For the purpose of testing, can 1 forbid scrambler by SCRINH is set.

The cell fifo (not shown) that the LAPS frame (as 155M) of the scrambler of 6 outputs is connected between scrambler unit 6 and the SPE/BC generation unit 5 from the scrambler unit converts SDH frame (as 155M) to, this cell fifo and PLL (phase-locked loop) collaborative work.

The processing procedure of data at receive direction is described below.

1. send to and receive loopback and LOC

If R_LOOP=1, EOS device 1 acceptance division can be configured to loopback and generate the transmission signal.Otherwise, select the signal that receives from the SONET/SDH interface.In loopback, the TX_SONETCLK input is used for determining the clock of receiver framer and other receiving circuits.If do not select loopback, then the RX_SONETCLK input is used for determining the clock of this circuit.

RX_SONETCLK input TX_CLK input monitoring loss of clock.Do not detect conversion if RX_SONETCLK is last 16 TX_CLK cycles, the RX_LOC position then is set.When detecting conversion, remove it.If RX_LOC is transformed into 1 or be transformed into 0 from 1 from 0, RX_LOC_D delta position is set.

2. transmit the expense monitoring

TOH/SOH monitoring piece is made up of J0, B2, K1K2, S1 and M1 monitoring byte.Wrong or the variation of these TOH/SOH byte monitor states.

2.1.J0 monitoring

The J0 monitoring has two kinds of operator schemes, and a kind of SONET that is used for uses, and a kind of SDH that is used for uses.In MII_RX_J0=0 pattern (SONET), the J0 monitoring comprises checks its value and 3 J0 byte values that receive that successive frame is consistent.When receiving the J0 value of a unanimity, it is write MII_RX_J0_[15] _ [7:0].

At MII_RX_J0=1 situation (SDH), the J0 byte is expected to comprise 16 byte section tracking frames of a repetition, and this frame comprises SAPI.The J0 monitoring comprises that following the tracks of 16 byte section tracking frames begins, checks that its value and 3 continuous segment tracking frames mate the section tracking frame value of consistent reception.When receiving the frame value of a unanimity, it is write MII_RX_J0_[15:0] _ [7:0].First byte (it comprises the frame beginning flag) of section tracking frame is write MII_RX_J0_[15] _ [7:0].

2.1.1. framing

Except that the highest significant position of frame beginning flag byte, the highest significant position of all sections tracking frame byte is 0.15 continuous J0 bytes of J0 watch-dog framer search, this byte highest significant position has one 0, after the highest significant position of the J0 byte that connects be 1.When finding this pattern, framer enters in the frame, at this moment J0_OOF=0.In case J0 watch-dog framer is interior frame, stays always and in receiving 3 continuous segment tracking frames, have 1 highest significant position (MSB) bit-errors in the frame at least.If MII_RX_J0=0, then J0 frame indication joint is constrained on interior frame state, MII_J0_OOF=0.When MII_J0_OOF changes state, MII_J0_OOF_D delta position is set.

2.1.2 pattern receives and compares

In case in frame, the J0 monitoring module is just searched the section tracking frame (MII_RX_J0=0) of 3 continuous 16 bytes (MII_RX_J0=1) or 1 byte.When receiving 3 consecutive identical frames, the frame of reception just deposits MII_RX_J0_[15:0 in] _ [7:0] (or under the SONET pattern, deposit MII_RX_J0_[15 in] _ [7:0]).The frame that receives and the content in advance of these registers compare.When having stored a new value, MII_RX_J0D delta (variation) position just is set.

2.2BIP-96 (B2) verification

In the explanation of B2, according to the difference (STS-3c) of equipment mode, the B2 value slightly changes below.For the operation of two kinds of situations is described, will utilize following agreement to come the requirement of deterministic model STS-3c.Correct BIP-8 value in the B2 byte that 1 verification of EOS device receives.(12[3] individual B2 combination of bytes form 1 BIP-96[BIP-24]) together.Remove the most preceding 3 row (being SOH among the SONET, is RSOH among the SDH) of TOH, to all 12[3 of every frame] byte batch total calculation BIP-96[BIP-24] the even check position.After the descrambling data that receive are calculated, descrambling will be worth afterwards and the B2 value of next frame compares.By relatively obtaining 0 to 96[0 to 24] do not match (B2 bit-errors).The detected B2 bit-errors of every frame number can insert the M1 byte of transmission.

2.2.1B2 error count

ROS device 1 comprises one 20 B2 error counter, and it is counted (when the BIT_BLKCNT=0) or the frame that has a B2 mistake at least is counted (as BIT_BLKCNT=1 time) each B2 mistake.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), the value of this counter is just by B2_ERRCNT[19:0] register latchs, and removing B2 error counter.If when the last rising edge of LATCH_EVENT begins to cause at least one B2 mistake, the B2 mistake second event bit B2ERR_SECE then is set, adopt B2 error threshold module.

For whether the error rate of judging received signal is higher or lower than the different predetermined thresholds (signal fault and signal degrade condition) of two regulations, EOS device 1 provides two B2 error threshold modules.If SF module or SD module decision error rate are higher than thresholding, B2_ERR_SF or B2_ERR_SD just are set.If corresponding error rate position has changed value, delta position B2_ERR_SF_D or B2_ERR_SD_D are set also.For every kind of error threshold module, the user can stipulate a BLOCK register and the 2 couples of THRSH and GROUP register.In order to allow to be provided with and to remove the hysteresis of mode bit, each error threshold module has 1 couple of THRSH and GROUP register that the state and the 1 couple of THRESH and GROUP register are set to come the removing state.Therefore the register that is used for the error threshold module is

Work as B2_ERR_SF=0, judge whether it should be provided with, use: B2_BLOCK_SF[7:0], B2_THRESH_SET_SF[7:0], and B2_GROUP_SET_SF[5:O]

Work as B2_ERR_SF=1, judge whether it should remove, use: B2_BLOCK_SF[7:0], B2_THRESH_CLR_SF[7:0], and B2_GROUP_CLR_SF[5:0]

Work as B2_ERR_SD=0, judge whether it should be provided with, use: B2_BLOCK_SD[15:0], B2_THRESH_SET_SD[5:0], and B2_GROUP_SET_SD[5:0]

Work as B2_ERR_SD=1, judge whether it should remove, use: B2_BLOCK_SD[15:0], B2_THRESH_CLR_SD[5:0], and B2_GROUP_CLR_SD[5:0]

3.K1K2 monitoring

K1 and K2 byte are to be used to send Line (circuit)/MS AIS or RDI and to be used for the APS signaling, determine the change of state by monitoring this byte.

3.1Line/MS the generation of AIS monitoring and LRDI

3 LSB of K2 byte can be used as AIS or remote defect indication (rdi) on circuit/MS layer.If receive K2_CONSEC[3:0 with " 111 "] successive frame, RX_LAIS just is set, RX_LAIS_OUT is output as a high position simultaneously; If K2_CONSEC[3:0] successive frame receives with " 111 ", just removes RX_LAIS and RX_LAIS_OUT.When the RX_LAIS state changes, the RX_LAIS_D_delta position just is set.

3.2Line/MS RDI monitoring

3 LSB of K2 byte also can be used to monitor K2_CONSEC[3:0] be to receive continuously or do not receive continuously with " 110 ", when this thing happens, just be provided with or remove RX_LRDI, RX_LRDI_D when changing state, RX_LRDI just is set.

3.3APS monitoring

4 MSB of K1 byte and K2 byte are used to send the APS request and the number of channel, when when 3 successive frames receive same numerical value, just it are write RX_K1_[7:0] and RX_K2_[7:4].The original value of value that will receive and register compares then, when new 12 place values occurring, RX_K1_D delta position just is set.

Check the stability of K1 byte.If in 12 successive frames, there are not 3 successive frames to receive with same K1 byte, the K1_UNSTAB position just is set.When receiving continuous 3 identical K1 bytes, just remove.If K1_UNSTAB changes state, K1_UNSTAB_D delta position just is set.3 of K2 comprise the APS pattern information to 0.Monitoring K2_CONSEC[3:0] these to find out continuous same sample value, just write RX_K2_[3:0 when above-mentioned situation occurring], unless 2 and 1 of K2 byte are " 11 " (representing Line/MS AIS or RDI).When writing RX_K2_[3:0] for new value the time, RX_K2_D delta position is set.

3 delta position MII_RX_K1_D, RX_K2_D and MII_K1_UNSTAB_D are all relevant with the APS monitoring, and an APS interrupt signal APS_INTB can both be provided.In addition, these delta positions can also provide the interrupt signal INTB that adds up of standard.

3.4S1 monitoring

Monitoring receives 4 LSB of S1 byte, and under the SONET pattern, MII_RX_SDH_S1=0 finds out 8 homogeneity value in the successive frame, and under the SDH pattern, MII_RX_SDH_S1=1 finds out 3 homogeneity value in the successive frame.When these comprised identical Synchronication status message, just the value that will receive was write RX_S1_[3:0], and the previous value of the value that will receive and this register compares, and when having stored a new value, MII_RX_S1_D delta position just is set.S1 byte also is used for the message fault detect.If begin not have message can satisfy above-mentioned validity criteria (whether it is identical with last received value or different) from last rising edge of LATCH_EVENT, the S1 second event bit S1_FAIL_SECE just be set.

3.5M1 monitoring

The B2 mistake number that the explanation of M1 byte is detected in received signal by remote terminal.EOS device 1 comprises 1 20 M1 error counter, and when BIT_BLKCNT=0, just counting is by each mistake of M1 indication; When BIT_BLKCNT=1, just counting is not equal to each frame of 0 with what M1 received.When MII_RX_SIG_MODE=1, the valid value range of the M1 of BIT_BLKCNT=0 is 0 to 96; Other any values all are interpreted as 0 mistake.When RX_SIG_MODE=0 and BIT_BLKCNT=0, the valid value range of M1 is 0 to 24; Any other value all is interpreted as 0 mistake.When the performance monitoring counter was latched, the value of this counter was by M1_ERRCNT[19:0] register latchs, and removing M1 error counter.

If begin to have at least 1 to receive the indication of M1 mistake from the last rising edge of LATCH_EVENT, the M1 mistake second event bit M1_ERR_SECE just be set.

4. transmit expense and separate (drop)

E1, F1 and E2 byte that the output of TOH/SOH separation module receives, and 2 serial D CC channels.

4.1 order line (E1 and E2) and section subscriber channel (F1)

3 serials output MII_RX_E1_DATA, MII_RX_E2_DATA and MII_RX_F1_DATA comprise E1, the E2 of reception and the value of F1 byte, single notched 64kHz clock reference output (MII_RX_E1E2F1_CLK) is provided simultaneously, after the RX_FRAME_OUT rising edge, the MSB of E1, E2 and F1 byte appears at first 64kHz clock cycle (band breach).

4.2 data communication channel, DCC, (D1-D12)

Two DCC have been defined among the TOH/SOH.Section/regeneration section dcc adopts D1, D2 and D3 byte to set up the channel of 1 notched 192kb/s, and circuit/multiple connection section dcc adopts D4 to set up the channel of 1 notched 576kb/s to the D12 byte.The TOH/SOH separation module is by 2 serial channel output DCC data RX_SDCC_DATA and RX_LDCC_DATA.These channels are synchronous with output MII_RX_SDCC_CLK and MII_RX_LDCC_CLK, and the output of DCC data changes at the trailing edge of RX_SDCC_CLK and RX_LDCC_CLK.

5. pointer state is judged

Judge pointer state by inspection H1-H2 byte, set up STS-3c/AU-4 reception pointer attitude.

5.1 state variation rule

Judge that in following pointer state according to the pattern (STS-3c) of equipment, number slightly changes in the explanation.For the operation of two kinds of situations is described, will utilize following agreement to come the requirement of deterministic model (STS-3c):

First pair of H1-H2 byte comprises the STS-3c/AU-4 pointer, and it is right to monitor this byte, and they can think in the following three state a kind:

Normally (NORM=00)

Alarm indication signal (AIS=01)

Loss Of Pointer ((LOP=10)

Remaining 11[2] the H1-H2 byte is used to monitor correct cascade indication.They can think in the following three state a kind:

Cascade (CONC=11)

Alarm indication signal (AISC=01)

Loss Of Pointer (LOPC=10)

State storage separately is in MII_PTR_STATE_[1:12] _ [1:0] [MI_TR_STATE_[1:3] _ [1:0]], MII_PTR_STATE_[i here] _ [1:0] expression i is to the state of H1-H2 byte.Then, merge each, determine the STS-3c/AU-4 pointer state independent H1-H2 byte.

5.2STS-3c/AU-4 pointer state

EOS device 1 provides buffer status position MII_RX_PAIS and MII_RX_LOP, is used to indicate the pointer state of the STS-3c/AU-4 pointer of reception, and they may be one of three state:

Normal (MII_PX_PAIS=0 and RX_LOP=0)-MII_PTR_STATE_[1] _ [1:0] be NORM (00), every other PTR_STATE_[i] _ [1:0] be CONC (11).

Passage/AU AIS (MII_RX_PAIS=1 and RX_LOP=0)-all PTR_STATE_[i] _ [1:0] be AIS or AISC (01).

Loss Of Pointer (MII_RX_PAJS=0 and MII_RX_LOP=1)-every other situation (PTR_STATE_[i] _ [1:0] value can not satisfy normal or passage/AU AIS standard).

MII_RX_PAIS and MII_RX_LOP signal provide passage remote failure indication (PRDI).Change by MII_RX_PAIS_D and indicating status position, MII_RX_LOP_D delta position.

6. pointer interpreter

The one H1-H2 byte is to being interpreted as using the location that begins to SPE/VC.The pointer interpreter rule is as follows:

1. at normal operation period, pointer is located the beginning of SPE/VC.

2. ignore any variation of the current pointer that receives, remove the discontinuous new pointer value that receives a unanimity for 3 times, perhaps it is prior to any one in the rule 3,4 or 5.Anyly receive consistent new pointer value for 3 times and have precedence over rule 3 or 4 continuously.

3. work as MII_RX_SDH_PI=0,, then indicate a positive justification if at least 3 couplings are forbidden the pointers of at least 8 current its I bit reversals that receive of coupling in indication (0110) and the 10 bit pointer value positions in 4 NDF positions.Think that following the byte after the H3 byte is positive byte of padding, the current pointer value that receives adds 1 (mould 783).

Work as MII_RX_SDH_PI=1, if at least 3 couplings are forbidden indication (0110) in 4 NDF positions, 3 or the pointer of 2 or current its all bit reversals that receive of position coupling still less in multidigit and the pointer value D-position more in the pointer value I-position, and the SS-position that receives is 10 or MII_RX_SS_EN=0, then indicates a positive justification.Think that following the byte after the H3 byte is positive byte of padding, the current pointer value that receives adds 1 (mould 783).

4. work as MII_RX_SDH_PI=0,, then indicate a negative justification if at least 3 couplings are forbidden the pointers of at least 8 current its D bit reversals that receive of coupling in indication (0110) and the 10 bit pointer value positions in 4 NDF positions.The H3 byte is considered to negative byte of padding (it is the part of SPE), and the current pointer value that receives subtracts 1 (mould 783).

Work as MII_RX_SDH_PI=1, if at least 3 couplings are forbidden indication (0110) in 4 NDF positions, 3 or the pointer of 2 or current its all bit reversals that receive of position coupling still less in multidigit and the pointer value I-position more in the pointer value D-position, and the SS-position that receives is 10 or MII_RX_SS_EN=0, then indicates a negative justification.The H3 byte is considered to negative byte of padding (it is the part of VC), and the current pointer value that receives subtracts 1 (mould 783).

5. work as MII_RX_SDH_PI=0, if at least 3 couplings are forbidden indication (1001) in 4 NDF positions, and pointer value is between 0 to 782, and the pointer that then receives is replaced the current pointer value that receives.

Work as MII_RX_SDH_PI=1, if at least 3 couplings are forbidden indication (1001) in 4 NDF positions, pointer value is between 0 to 782, and the SS-position that receives is 10 or MII_RX_SS_EN=0, and the pointer that then receives is replaced the current pointer value that receives.

Utilize these pointer interpreter rules, pointer interpreter device module is determined the position of SPE/VC payload and POH byte.

6.1 pointer is handled

About in EOS device 1, realizing the pointers track algorithm, please refer to the conversion definition in [G.783] and [GR-253].The pointers track state machine is based on the pointers track state machine that the ITU-T suggestion is determined, it is the same with ansi standard effective to Bellcore.In the Bellcore pattern, the state machine conversion (promptly being arranged to logical one by the BELLCORE position is set) from AIS to LOP does not appear.

EOS device 1 has used four pointers track state machines, and each AU-4/STS-3c is with one.Pointers track adopts H11 and H21 byte, and this pointer extracts from the cascade of H1n and H2n byte, is explained as follows:

N=new data flag position, in effective time=1001 or 0001/1101/1011/1000, when normal or inefficacy, it equals 0110 or 1110/0010/0100/0111 (that is tolerable single-bit error).

Size position during SS=pointers track state machine is explained is if effectively, be set to 0 by the BELLCORE control bit.When BELLCORE is set to 1, ignore these positions, but when it was set to 0, these positions were 10.

I=increases the position, is defined as the position 7 of H1n and the position 1,3,5 and 7 of H2n.

D=reduces the position, is defined as the position 8 of H1n and the position 2,4,6 and 8 of H2n.

Negative justification: 5 D-positions of counter-rotating receive majority rule.By the positive ITU position among the OR#Conf 3 (Just ITU bit) is set to 0, can start among the O3-92 of [GR-253] 8 in 10 objects.

Positive justification: 5 I-positions of counter-rotating receive majority rule.By the positive ITU position among the OR#Conf 3 (Just ITU bit) is set to 0, can start among the O3-92 of [GR-253] 8 in 10 objects.

To the STM-1/STS-3c operational mode, pointer is a binary value, and scope is 0 to 782 (decimal system).It is a 10-place value that is derived from two least significant bits of H1 byte, with the H2 byte of cascade together, form an offset field that departs from 3 bytes of H3 byte location.For example, to the STM-1 signal, pointer value is that 0 expression VC-4 3 byte position after the H3 byte begin, and 87 expression VC-4,3 bytes after the K2 byte of setovering.

In the STM-4/STS-12 pattern 4 bytes-staggered AU-4 is arranged, therefore 4 H1/H2 bytes are arranged being used for determining their beginnings of VC-4 separately (that is j1 byte position).In this case, the operation of 4 pointers track state machines is equal to operation 4 * STM-1/STS-3c.

When treatment S TS-12c/STM-4c, grand 1 pointers track state machine is used to locate the beginning of VC-4-4c.Use H11 and H21 byte to carry out pointers track, pointer extracts from H11 and the cascade of H21 byte, and pointer interpreter is as described above.But the biasing that forms is the count value of one 12 byte, and its value begins to count from the H3 byte location.For example, to the STM-12c signal, pointer value is that 0 expression VC-4 12 byte position after the H3 byte begin, and 87 expression VC-4,12 bytes after the K2 byte of setovering.In corresponding grand (grand 2-4), also check cascade indication byte, monitor corresponding to LOP and HPAIS according to each state machine among [G.783] annex C.Following state diagram has illustrated the state exchange of cascade designator.The conversion definition please refer to [G.783].

In addition, 8 digit counters are used for writing down positive and negative and adjust incident, and the NDF incident.Provide mode bit to be used to refer to the detection of negative justification, positive justification, NDF, null pointer, new pointer and cascade indication.When LOP in entering last figure or LOPC attitude, will in relevant OR#IRQ2 register, LOP interrupt requests position be set.Equally, if entered AIS or AISC attitude, will relevant HPAIS interrupt requests be set.

After handling pointer, the cell fifo (not shown) of concatenation pointer processing unit 10 and descrambling unit 11 converts SDH/SONET frame (as 155.520Mb/s) to LAPS frame (as 155.520Mb/s), finishes this action with PLL.

7. path overhead monitoring

POH (path overhead) monitoring module is made up of J1, B3, C2 and G1 monitoring.These path overhead bytes are used for the wrong of monitor state or change.

7.1 channels track (J1) is caught/is monitored

By inserting j1 byte, EOS device 1 is supported two kinds of channels track (J1) catching method.First kind is mainly used in SONET, catches 64 continuous j1 bytes in STS-3c/AU-4.Second kind is used for SDH, searches 16 continuous j1 byte patterns of repetition.When detecting 16 consistent byte modes in 3 continuous incidents, the J1 pattern storage is in the register of appointment.

7.1.1SONET J1 catches

When MII_RX_SDH_J1=0 (SONET pattern), EOS device 1 can provide catches the channels track intelligence sample.When J1_CAP converts 1 to from 0, EOS device 1 is caught 64 j1 bytes continuously from specific extension, and they are write MII_RX_J1[63:0] _ [7:0].

Do not have define channel tracking frame structure among the SONET, but a certain sequence of one 64 byte of suggestion of GR-253, this sequence is made up of a string ascii character, and null character (NUL) (00) has been filled 62 bytes, ends up being＜CR〉(0D) with＜LF (0A) byte.If be provided with the J1CRLF position, then EOS device 1 be captured in received in the j1 byte position with { first 64 byte character string that 0A, 0D} finish.If J1_CRLF=0, EOS device 1 is caught the j1 byte of ensuing 64 bytes, does not consider their content.Catch in case finish, EOS device 1 is provided with the J1_CAP_E event bit.

7.1.216 byte J1 monitoring

If MII_RX_SDH_J1=1 (generally being used for the SDH pattern), j1 byte are expected to comprise the channels track frame that 16 bytes of a repetition comprise PAPI.In this pattern, do not use J1_CAP, J1_CRLF and J1_CAP_E position.J1 monitoring comprises from motion tracking 16 byte lane tracking frames and begins, checks that receive path tracking frame value is to find out and 3 successive frames mate consistent values.When receiving the frame value of a unanimity, it is write MII_RX_J1_[15:0] _ [7:0].First byte of channels track frame (it comprises the frame beginning flag) is write MII_RX_J1_[15] _ [7:0].

Framing. except that the MSB of frame beginning flag byte, the highest significant position of all channels track frame bytes is 0.15 continuous j1 bytes of J1 watch-dog framer search have 0 in this byte highest significant position, after connect and have 1 j1 byte in the highest significant position.In case search this pattern, framer enters in the frame, at this moment J1_OOF=0.In case J1 watch-dog framer is interior frame, it is interior in receiving 3 continuous passage tracking frames that have 1 highest significant position (MSB) bit-errors at least that it just stays frame always.(in the SONET pattern, the indication of J1 frame is retained in interior frame state, J1_OOF=0).If the J1_OOF state changes, J1_OOF_D delta position is set then.

In case pattern receives and compares. in frame, the J1 monitoring module is searched the channels track frame of 3 16 continuous bytes.When receiving 3 consecutive identical frames, the frame of reception just deposits MII_RX_J1_[15:0 in] _ [7:0].

The frame that receives and the content in advance of these registers compare, and when having stored a new value, the delta position of RX_J1_D just are set.

7.2.BIP-8 (B3) verification

EOS device 1 is checked correct BIP-8 value in the B3 byte that receives.By even parity position to all calculating BIP-8 among every frame SPE/VC (comprising POH).The B3 value that receives in these values and the next frame compares then.The possibility of result relatively can be 0 to 8 not match (B3 bit-errors), and this value is inserted in the transmitting terminal G1 byte.

EOS device 1 comprises 16 B3 error counters, and this counter is to each B3 bit-errors (if BIT_BLKCNT=0) or have at least each frame of a B3 bit-errors (if BIT_BLKCNT=1) to count.When the performance monitoring counter is locked (LATCH_EVENT changes to a high position), the value of this counter locks onto B3ERRCNT_[15:0] register, remove the B3 error counter.If begin to have at least a B3 mistake, B3 mistake secondary event bit B3ERR_SECE is set then from the last rising edge of LATCH_EVENT.

7.3. signal label (C2) monitoring

The C2 byte that receives is monitored, thereby can be confirmed to receive correct payload type.When on 5 successive frames, receiving consistent C2 value, the value that receives is write MII_RX_C2[7:0] in.When receiving a new C2 value, the delta position of MII_RX_C2D is set.

The desired value of the C2 that receives is stayed EXP_C2[7:0] in.If current value that receives and desired value do not match, the value that receives do not meet yet following condition then the payload label register-bit MII_RX_PLM that do not match be set to a high position:

● all be 0, unready label;

● 01 (hexadecimal), the nonspecific label of preparation;

● FC (hexadecimal) has the payload defective labels;

● FF (hexadecimal), Hold sticker.

=00 (hexadecimal), then register-bit (the Unequipped register bit) MII_RX_UNEQ that does not prepare is set to a high position.

MII_RX_PLM and MII_RX_UNEQ signal insert at transmitting terminal for passage RDI.When MII_RX_PLM or MII_RX_UNEQ change its state, MII_RX_PLM or MII_RX_UNEQ delta position are set.

7.4. channel status (G1) monitoring

The G1 monitoring comprises passage REI monitoring and passage RDI monitoring.

7.4.1. passage REI monitoring

The position 1 of channel status byte 4 (4 highest significant positions) the indications remote terminal detected B3 mistake number in the signal that it receives that puts in place.Be legal only at 0 to 8 binary value.If the value that receives is greater than 8, it is interpreted as 0 mistake (advising the same of defined G.707 as GR-253 and ITU-T).EOS device 1 comprises one 16 G1 error counter, and it calculates each mistake (if BIT_BLKCNT=0) of G1 indication or 4 the G1 positions that receive are not equal to each frame (if BIT_BLKCNT=1) of 0.When the performance monitoring counter is locked (LATCH_EVENT converts a high position to), the value of this counter is composed to G1_ERRCNT[15:0] register, empty the G1 error counter.

If since the last rising edge of LATCH_EVENT, had a G1 mistake indication that receives at least, G1 mistake event bit G1ERR_SECE for the second time then be set.

7.4.2. passage RDI monitoring

If MII_RX_PRDI5=1, then EOS device 1 can be monitored the 5th (the RDI-P designator) of G1; If MII_RX_PRDI5=0 then can monitor the 5th, 6 and 7 of G1 (strengthening the RDI-P designator).Monitor procedure comprises checks G1_CONSEC[3:0] identical value in the continuous reception value of monitoring position.When receiving identical value, write MII_RX_G1[2:0 for G1 5,6 and 7].The value of reception value and this register front compare (all 3 all are written to, if but MII_RX_PRDI5=1, only with the 5th and the MUU_RX_G1[2 of G1] compare).When new value of storage, MII_RX_G1_D delta position is set.

7.5. other POH bytes

Other remaining bytes of 1 couple of POH of EOS device will not be monitored.These bytes comprise that passage subscriber channel (F2), location pointer (H4), passage growth/subscriber channel (Z3/F3), passage growth/passage APS channel (Z4/K3) and front and back connect monitoring (Z5/N1) byte.

8. receive the payload descrambling

After from the SONET/SDH signal, extracting payload, payload data motor synchronizing X ⁴³+ 1 descrambler carries out descrambling.In all patterns, the operation of register MII_RX_DSCR_INH control descrambler.When MII_RX_DSCR_INH=0 (default), descrambler operate as normal.Work as MII_RX_DSCR_INH=1, descrambler is forbidden work.

EOS device 1 provides one based on following generator polynomial X ⁴³+ 1 motor synchronizing descrambler.

9. receiving LAPS handles

SPE extracts from the SONET/SDH frame herein, enters the LAPS processor then and does further processing.Under the EOS pattern (MII_RX_EOS=1), the LAPS processing procedure is to extract LAPS bag/frame from SPE.

9.1LAPS framer

Under the EOS pattern (MII_RX_EOS=1), by the identification frame initial/flag sequence (0x7e) that finishes, from the SPE payload, extract the LAPS frame.

EOS device 1 is checked each eight hyte in the payload, when bit pattern is eight hytes of 0x7e when being checked through, EOS device 1 just think this be 1 bag initial/finish eight hytes after the checkmark sequence then.If still be 0x7e, think that then they are the flag sequences that are used to fill inter-packet gap, and it is abandoned.First eight hyte of following the beginning flag sequence and being not equal to 0x7e is considered to first eight hyte of LAPS frame.After the frame beginning flag, EOS device 1 continues to check each eight hyte of payload, searches flag sequence.If found bit pattern 0x7e position, and eight hytes of its front are control escape code (0x7d), then this frame abortion; Otherwise, just think the normal ending of present frame.Termination in the FCS field is in particular cases forbidden, and must detect minimum between frame signal is 2 flag sequences.

9.2 the deletion that transparent byte is filled

9.3.1EOS pattern

At EOS pattern (MII_RX_EOS=1), after the LAPS frame, EOS device 1 with transparent byte filling process conversely, to recover the original packet information flow.FIFO underflow byte sequence is inserted in FIFO underflow process by transmitting terminal, if MII_RX_EOS_FIFOUNDR_MODE=1 then needs to detect in the transparent processing process, and deletion.This default value is under an embargo: MII_RX_EOS_FIFOUNDR_MODE=0.Special FIFO underflow bytecode can utilize register MII_RX_EOS_FIFOUNDR_BYTE[7:0] programming.

9.3.2 underflow byte deletion

Under the EOS pattern, if MII_RX_EOS_FIFOUNDR_MODE=1, coupling FIFO underflow byte (MII_RX_EOS_FIFOUNDR_BYTE[7:0]) if byte thereafter immediately following control escape code (Ox7d) then be dropped.

9.4 erroneous frame

Under the EOS pattern (MII_RX_EOS=1), utilize 1 special byte code (0x7d7e) to indicate this frame and ended.If receive this bytecode, the frame that contains this bytecode is just ended.More eight hytes are not sent into FIFO; If this bag sends to link layer device, then be labeled as mistake.

EOS device 1 comprises 18 bit error count device, and each bag that wherein detects pause sequence is counted.When the counter of performance monitoring is latched (LATCH_EVENT becomes high level), the value of this counter is by register MII_RX_EOS_PABORT_ERRCNT[7:0] latch, and remove bag and end error counter.

If caused at least 1 bag to end mistake from last 1 rising edge of LATCH_EVENT, bag then need be set end the wrong second event bit MII_RX_EOS_PABORT_ERR_SECE.

As a kind of alternative, also can end 1 bag by inversed F CS byte.This only is a kind of fcs error for EOS device 1 receives the LAPS processor.Its processing procedure is as the hypomere explanation.

As a kind of option, EOS device 1 also can be considered as erroneous packets with bag, and therefore whether violates minimum or maximum bag regulation according to it, and carries out mark.The size of bag only is meant and the bag size of coming out from EOS device 1 does not comprise flag sequence, address byte, control byte, SAPI, transparent byte, FIFO underflow byte and the FCS byte removed.Can minimum and maximum length programming by management interface to these.Register MII_RX_EOS_PMIN[3:0] to comprise parcel long, and the default value of this register is 0; Register MII_RX_EOS_PMAX[15:0] contain maximum length, the default value of this register is 0x05E0.

When sending instructions by management interface, EOS device 1 can make minimum and the maximum length verifying function effective/invalid.How register MII_RX_EOS_PMIN_ENB and MII_RX_EOS_PMAX_ENB (two default values are 0) control is handled the long violation of minimum and maximum bag, when any one register is set to 1, the bag calipers of any violation correspondence is fixed, all can be labeled as mistake.

EOS device 1 comprises two 8 bit error count devices, and each fault of violating the long restriction of minimum and the longest bag is counted.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), these Counter Values are by register MII_RX_EOS_PMIN_ERRCNT[7:0] and MII_RX_EOS_PMAX_ERRCNT[7:0] latch, and remove bag fault counter.

If begin to cause at least 1 big or small fault mistake of bag from the last rising edge of LATCH_EVENT, the long second event bit MII_RX_EOS_PMIN_ERR_SECE or the MII_RX_EOS_PMAX_ERR_SECE of fault of suitable bag just be set.

9.5 Frame Check Sequence (FCS) field

(MII_RX_EOS=1) calculates FCS under the EOS pattern, and in ending place of every frame the FCS byte checked.This option is by register MII_RX_EOS_FCS_INH control, and FCS is effective during value MII_RX_EOS_FCS_INH=0; FCS is invalid during value MII_RX_EOS_FCS_INH=1.Only adopt 32 verification sequence (CRC-32).It is the FCS-32 pattern that MII_RX_EOS_FCS_MODE=0 makes equipment operation.

EOS device 1 provides CRC-32 function, adopts generator polynomial to be: 1+x+x ²+ x ⁴+ x ⁵+ x ⁷+ x ⁸+ x ¹⁰+ x ¹¹+ x ¹²+ x ¹⁶+ x ²²+ x ²³+ x ²⁶+ x ³²The FCS field is calculated in all frame sign indicating number positions except that flag sequence and FCS field oneself itself.

If MII_RX_EOS_FCS_BIT_ORDR=0 (default value) adopts high significance bit (being MSB earlier) order that the signal that receives is read into shift register; If MII_RX_EOS_FCS_BIT_ORDR=1 adopts low order (at first being LSB) order that the signal that receives is read into shift register.No matter be the sort of situation, after FCS calculated, data all were to adopt high significance bit to store, so that handle.

The FCS end value that obtains compares with the FCS field value that receives, if the mistake of detecting is just informed the management control interface, corresponding counter adds 1, and last 1 sign of wrapping among the FIFO is designated as mistake.EOS device 1 comprises one 20 fcs error counter, each FCS CRC is broken rules count.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), the value of this counter is by register MII_RX_EOS_FCS_ERRCNT[19:0] latch, and remove the fcs error counter.

If begin to cause at least 1 fcs error, the fcs error second event bit MII_RX_EOS_FCS_ERR_SECE is set then from the last rising edge of LATCH_EVENT.

After the FCS verification, stop FCS byte (they do not store FIFO into).If forbid the FCS verification by management interface, last 2 or 4 bytes just send to FIFO.Suppose to detect a fcs error that when sending to link layer device, the mark bag is wrong (RX_ERR).

9.6LAPS frame stops

Under EOS pattern (MII_RX_EOS=1), FCS monitors following LAPS byte after calculating, and optionally stops.

9.6.1 flag sequence

The frame that is useful on is described to fill purpose with interior frame and the flag sequence that occurs is all deleted.The starting and ending sign of frame information is still kept by EOS device 1, sends to link layer by RX_SOP and RX_EOP signal.

9.6.2 address and control byte

Address and control byte (following preceding two bytes in the LAPS frame of flag sequence) are by 1 monitoring of EOS device, and monitoring comprises checks effective address field and control field (0xFF03 or 0x0403).Do not match if detect, just think that this field compresses, do not send.If detect invalid value, these two bytes are not separated, are delivered to link layer by the MII interface.By being set, MII_RX_EOS_ADRCTL_INVALID=1 informs that the management control interface detects invalid address and control field.Corresponding delta position by MII_RX_EOS_ADRCTL_INVALID_D is set is 1, and the state of expression MII_RX_EOS_ADRCTL_INVALID changes.

If the effective address of detecting and control field, EOS device 1 just stop this two bytes, be not delivered to RX FIFO.By MII_RX_EOS_ADRCTL_DROP_INH=1 is set, can forbid deleting effective address and control byte.The default value of this register was 0 (separating effectively automatically).

9.6.3FCS byte

As mentioning in FCS one joint, EOS device 1 also can stop 4 FCS bytes.If forbid the FCS verification by management control interface (MII_RX_EOS_FCS_INH=1), expiry feature also is under an embargo, and last 4 bytes of LAPS frame just send to link layer.

10 receive fifo interface

10.1 system end bag loopback

The packet function that EOS device 1 provides loopback to accept by system interface for the user.

Work as SYS_T_TO_R_LOOP=1, the bag that receives from link layer device is routed directly to reception FIFO from sending FIFO, exports back the link layer device of the cell data that starts again.When SYS_T_TO_R_LOOP was set to 0, the bag that receives in the SONET/SDH link signal sent to and receives FIFO, outputs to system interface then.

10.2FIFO processing procedure

EOS device 1 is write FIFO with bag, prepares to output to link layer device by the receiving system interface.The FIFO minimum value is 512 eight hytes.Together with bag, following applicable identifier must be followed each word of FIFO: whether the beginning of bag, the end of bag, bag finish, and whether (1 or 2) have several eight hytes and bag to make mistakes in the word.In case detect mistake in bag the signal, bag no longer includes more byte and packs among the FIFO.

Fifo status is by 1 monitoring of EOS device.By MII_RX_FIFOOVER_E=1 is set, to management control interface report FIFO overflow incident, the generation of FIFO underflow also can make corresponding performance monitoring counter increase simultaneously.

EOS device 1 comprises the counter of one 8 FIFO underflow mistakes, and each bag that influenced by the FIFO underflow event is counted.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), the value of this counter is just by register MII_RX_FIFOOVER_ERRCNT[7:0] latch, and remove FIFO underflow error counter.

If begin to cause at least 1 FIFO underflow event, FIFO underflow error event position MII_RX_FIFOOVER_ERR_SECE just is set from the last rising edge of LATCH_EVENT.

In case detect the underflow mistake, send into FIFO with regard to the byte that no longer includes bag.Under EOS pattern (MII_RX_EOS=1), last 1 sign of bag is designated as mistake (RX_ERR).

FIFO just before the receiving system compatibility interface, its objective is the rate-matched function of finishing between SONET clock zone and the link layer clock zone.

10.3 erroneous packets is handled

RX processing unit 12 provides decision unit (determining unit) (not shown), and it is used for determining to receive type of data packet, generates corresponding predetermined SAPI, and verification occurs in the mistake in the frame.

Under EOS pattern (MII_RX_EOS=1), for the bag that is destroyed by FIFO overflow incident, EOS device 1 usefulness RX_ERR is labeled as erroneous packets with it.

Invalid frame is:

A) not having correct is the boundary with two flag sequences; Or

B) eight hytes between the flag of frame sequence are less than 8; Or

C) include a Frame Check Sequence mistake; Or

D) comprise that a receiver does not match or unsupported service access point identifier (seeing that ITU-T X.85 A.3.3); Or

E) comprise a unrecognizable control word segment value; Or

F) end mark is for surpassing the sequence of six " 1 " position.

Invalid frame will be dropped, and not notify originating party, also not produce any action.

10.4. reception data parity check

As the regulation of MAC-PHY, EOS device 1 provides 1 parity bit, follows the word (MII_RX_SYS_DAT[15:0]) of each eight hyte that sends to link layer or two eight hytes.Provide this parity check bit at the RX_PRTY pin.As default (MII_RX_PRTY_MODE=0), this position provides odd parity; When MII_RX_PRTY_MODE=1, provide even parity.

Carry out the rate adapted from LAPS to MII among the RX_FIFO 13.From the periodicity LAPS frame (as 155M) of RX_LAPS processing unit 12 outputs, convert the MII frame (as 100M) of burst to.Carry out opposite rate adapted process at TX FIFO.After treatment, the SDH/SONET frame that receives converts the MII frame to, is sent to ethernet layer by transducer 19.

The MII interface requirement

The requirement of 1 pair of MII interface of EOS device is based on the definition of 802.3 pairs of reconciliation sublayer of IEEE and medium independent interface.

Figure 13 is the detailed functions module map of the transducer 19 among Fig. 9.Used being defined as follows among the figure:

TX_ER: send code error; TXD: send data; TX_EN: send permission; TX_CLK: tranmitting data register; GTX_CLK: kilomegabit tranmitting data register; COL: collision detection; RXD: receive data; RX_EN: reception enables; RX_CLK: receive clock; CRS: carrier sense; RX_DV: it is effective to receive data; MDC: management data clock; MDIO: management data I/O; TSOF: frame sends beginning; TEOF: frame sends and finishes; TCLK: tranmitting data register; TENA: send and write permission; TFA: transmit frame can be used; TxDATA: send data; RSOF: frame receives beginning; REOF: frame receives and finishes; RCLK: receive clock; RV: it is effective to receive data; RFA: received frame can be used; RxDATA: receive data.

It should be noted, the signal terms of mark bracket changes, two kinds of systems of selection are arranged here: for Ethernet/Fast (fast) Ethernet over SDH/SONET situation, use be TxDATA＜7:0 (8 * 19.44MHZ), RxDATA＜7:0 (8 * 19.44MHZ), TXD＜3:0 (4 * 25MHZ), RXD＜3:0 (4 * 25MHZ) and TX_CLK (25MHZ).For what Gigabit (kilomegabit) Ethernetover SDH/SONET comprised the use of GTX_CLK direction be: TxDATA＜31:0〉(32 * 78.76MHZ)/＜63:0 (64 * 38.88MHZ), RxDATA＜31:0 (32 * 78.76MHZ)/＜63:0 (64 * 38.88MHZ), TXD＜7:O (8 * 125MHZ), RXD＜7:0 (8 * 125MHZ) and GTX_CLK (125MHZ).

As shown in figure 13, the translation function between transducer 19 execution MII/GMII interfaces and WRI interface.

Between input and output modular converter synchronously

MII and GMII and IEEE 802.3 operating suchs.TX_CLK (tranmitting data register) or GTX_CLK (kilomegabit tranmitting data register) are continuous clocks that timing reference is provided for TX_EN, TXD and TX_ER transfer.RX_CLK (tranmitting data register or kilomegabit tranmitting data register) is a continuous clock that timing reference is provided for TX_DV, RXD and RX_ER transfer.When handling selection full duplex mode of operation automatically through consultation, the operating state of COL (collision detection) signal and CRS (carrier sense) does not describe in detail.

At the sending direction of EOS device, MII/GMII and WRI interface are respectively the input and output interface, and at receive direction, MII/GMII and WRI interface are respectively output and input interface.The WRI interface provides following two kinds of parallel branch modes that transmit and receive data, and this dual mode all adopts the clock rate that is independent of linear speed: be 8bits (position) * 19.44MHz when STM-1/OC-3c speed; In STM-16/OC-48c speed is 32bits * 78.76MHz/64bits * 38.88MHz.The EOS chip is supported by the FIFO achieve frame speed decoupling between transducer and LAPS processor.

In order to simplify interface between MII/GMII layer and EOS, to support multiple physical layer (PHY) interface, transducer 19 and FIFO have been used.Provide control signal to support MII/GMII layer and EOS layer equipment, so that allow EOS to carry out current control at the WRI interface.Connect because bus interface is based on point-to-point, therefore, the receiving interface of EOS device pushes MII/GMII layer equipment by FIFO and transducer 19 with data.Be based on eight hytes in transmission and receiving interface available frame state particle (granularity).At receive direction, when EOS layer equipment has been stored the end (a little LAPS frame or a big LAPS frame end) of a frame or has been scheduled to several bytes in its reception FIFO, by transducer 19 address (in-band address) in MII/GMII layer equipment sends band, heel data fifo.On the data post of WRI interface bus, receive the sign of useful signal (RV).

When the multiport EOS device with a plurality of FIFO had enough data in its FIFO, each port (round-bin) mode that can circulate was worked.The WRI interface allows signal (RENB) can suspend data flow with relevant transducer 19 by not keeping according to IEEE 802.3x.At sending direction, when being scheduled to several bytes in EOS layer equipment has living space to transmission FIFO, (transmitframe available is TFA) through transducer 19 notice MII/GMII layer equipment by stating a transmit frame arrival.MII/GMII layer equipment can the WRI interface allow with one signal (TENB) with the band of heel frame data in the address write EOS layer equipment.Transducer 19 monitoring TFA transformations from high to low, this transformations expression send FIFO near full (remaining byte number can be selected by the user among the FIFO, but must predefine), hang the data transfer to avoid underflow.Transducer 19 allows signal (TENB) can suspend data flow by not keeping.

At sending direction, WRI-PHY definition frame level shifts control.Because frame sign is variable, do not provide any available word joint number to guarantee, sending and receiving the both direction signal, on STFA, provide the available EOS transmit frame of selection, it is effective to receive data on signal RV.STFA and RV reflect that always data just are being transferred to the state of back from the EOS of its selection of producing.Whether RV indication valid data are receiving on the data/address bus availablely, and are defined as data and shift and can align with frame boundaries.Select physical layer port with addressing in the band.At sending direction, MII/GMII equipment is by at TxDATA＜7:0〉or TxDATA＜31:0/TxDATA＜63:0〉send the address on the bus and select the EOS port, there is the TSX signal to be in activated state on the bus, the TENB signal is in non-activated state sign.All have indicated that TENB is in the follow-up TxDATA＜7:0 of activated state〉or TxDATA＜31:0/TxDATA＜63:0〉bus operation is the frame data that are used to specify port.At receive direction, MII/GMII equipment is by at RxDATA＜7:0〉or RxDATA＜31:0/RxDATA＜63:0〉send the address on the bus and specify the selection port, bus has the RSX signal to be in activated state, the RV signal is in non-activated state sign.All have indicated that RV is in the follow-up RxDATA＜7:0 of activated state〉or RxDATA＜31:0/RxDATA＜63:0〉bus operation is the frame data that are used to specify port.

In order to support existing a spot of multiport EOS layer equipment and high-density multi-port equipment in the future, when the port number of EOS layer equipment has in limited time, adopt the byte level transfer of DFTA signal that a kind of simpler implementation method is provided, reduce required addressing pin simultaneously.In this case, along with the increase of port number, directly visit just becomes and has no reason.When port number for a long time, adopt the TADR bus to make the frame level shift required number of pin much less.Addressing guarantees that the agreement of two kinds of methods keeps unanimity in the band.Yet system designer and physical layer equipment manufacturer specifically select for use the sort of method to depend on that the sort of method is more suitable for its conceivable application.

2. the data structure of transducer 19

Should adopt the data structure of a definition that frame is write transmission FIFO and read frame from received FIFO.The same sequence read-write of eight hytes in the SDH/SONET circuit, to send or to receive.Highest significant position in one eight hyte (position 7) at first sends (referring to Fig. 7/ITU-T draft proplsal X.86).The EOS device can be used to shift the frame of 1 byte.In this case, state the beginning and the end of frame signal simultaneously.For the frame of frame length above EOS device FIFO, frame must shift by the WRI interface.Byte number at each frame data of each section can immobilize, and also can change, and this depends on concrete application.MII/GMII can perhaps use the TFA signal to determine when FIFO is full on the WRI interface by the frame section of transducer 19 in MII/GMII interface transmission fixed size.Use for many MII/GMII port, effective with the band inner port address choice on TPAS (transmit port address choice, Transmit Port Address Selection) the indication TxDATA bus.When TPAS is in a high position, TENB and also is a high position, TxDATA[7:0] or TxDATA＜31:0/TxDATA＜63:0 value be the address of the transmission FIFO that will select.Subsequent data on the TxDATA bus shifts among the FIFO that is filled into address appointment in this band.For the EOS device of single-port, the TPAS signal is an option, because when TENB is in a high position, the EOS device will be ignored address in the band.Only when not stating TENB, TPAS is just effective.

In 32/64 bus interface and 8 bus interface, the band inner port address of multiport EOS device is not shown.Transducer 19 should send the MII/GMII port address on the bus identical with data, this total line index TPAS signal is in activated state, and the TENB signal is in non-activated state.Subsequently data shift to be used the transmission FIFO of address choice in the band on the WRI interface.At receiving interface, EOS device RPAS (receiving port address choice before shifting frame data, Receive Port Address Selection) signal is in activated state, and the RV signal is in and receives fifo address (the receive FIFO addressin-band) in the non-activated state report tape.For both of these case, the big frame that exceeds the FIFO size shifts through the WRI interface by add address prefix in the suitable band in each section.

Address regulation in the band with the single clock cycle operation of TPAS/RPAS marker.Port address is by TxDATA[7:0] and RxDATA[7:0] signal or TxDATA[31:0]/TxDATA[63:0] and RxDATA[31:0]/RxDATA[63:0] signal determines.Under the numeric coding mode, the address is TxDATA[7:0] and RxDATA[7:0] signal or TxDATA[31:0]/TxDATA[63:0] and RxDATA[31:0]/RxDATA[63:0] numerical value of signal, at this moment, position 0 is a least significant bit, position 7 is highest significant positions.Like this, a single interface can be supported nearly 256 port.To 32 interfaces, neglect top 24, to 64 interfaces, neglect top 56.

According to the ITU-T draft proplsal, must processed frame verification sequence (FCS) in the LAPS processor.If the EOS device does not insert the FCS byte in the option mode before transmission, then should comprise these bytes at the inclusion tail.If the EOS device is not peeled off the FCS field at receive direction, then should keep these bytes at the inclusion tail.

The management control interface

Management control interface corresponding to the EOS device is described below, and definition can be for all register addresss of external microprocessor read-write.Here used a table, this has shown to comprise common configuration and overall status mapping (Summary Status Map), and the latter has public control of entire equipment and monitoring parameter.At transmitting terminal, this table is for management control interface register mappings, and at receiving terminal, each piece is a management control interface register mappings.The highest significant position ADDR[8:0 of microprocessor bus address] whether indicate mapping relevant with transmission or receive direction.ADDR[7:0] indicate special mapping, each mapping that these values employings are described in detail is later discerned.Common configuration and overall map are ADDR[8]=0.

1. interrupt or poll (polled) operation

The management control interface is with drives interrupts or the work of poll pattern dual mode.In these two kinds of patterns, the EOS apparatus registers position SUM_INT among common configuration and the overall status mapping address 0x002 is used for determining whether the control register state of EOS device variation has taken place.

1.1 interrupt source

1.1.1 transmitting terminal

Transmitting terminal register mappings (Transmit Side register map) almost is whole regulation parameters (provisioning parameters) of determining that the SONET/SDH signal is formed and LAPS, SONET/SDH POH and SONET/SDH TOH/SOH value are provided.Except that these regulation parameters, the transmitting terminal register mappings comprises system interface and general purpose I/O watch-dog.If any one in these indications is in activated state, then the SUM_INT position among the register 0x002 is high-order (logical one).If SUM_INT_MASK=0, Microprocessor Interface is interrupted output (INTB) and is in activated state (logical zero).

1.1.2 receiving terminal

This table also comprises the overall status position of receiving terminal among the register 0x005.These provide the SUM_INT among the register 0x002 position.If any one in the overall status position is " 1 ", and shelter the position accordingly for " 0 ", the SUM_INT position then is set is " 1 ".If one or more corresponding hytes are " 1 " in the table (TBD), then the middle overall status position of register 0x005 (TBD) is " 1 " in the table.Can shelter single TOH/SOH delta and event bit (the Second event bit) second time (table (TBD), for example the address is 0x204-0x206).

1.2 drives interrupts

In the drives interrupts pattern, should remove the SUM_INT_MASK position (being set to 0) of the register 0x006 of common configuration and overall status mapping.This allows INTB output becoming activating position (logical zero). (! SUM_INT_MASK﹠amp; ﹠amp; SUM_INT).In addition, should empty the MII_RX_APS_INT_MASK position (being set to logical zero) of receiving terminal. (! MII_RX_APS_INT_MASK﹠amp; ﹠amp; MII_RX_APS_INT).If interruption has taken place, microprocessor at first reads the interrupt source class of overall status register 0x004-0x005 to determine to activate, and reads the specified register in such then, with the accurate reason of determining to interrupt.

1.3 poll pattern

In poll pattern, SUM_INT_MASK and MII_RX_APS_INT_MASK position (for logical one) should be set, to suppress all hardware interruption and to operate in the poll pattern.In this pattern, EOS device 1 output INTB, APS_INTB remains on unactivated state (logical one).

Be to be noted that SUM_INT_MASK and MII_RX_APS_INT_MASK position do not influence the state of register-bit SUM_INT and MII_RX_APS_INT.Can further inquire register to determine whether needs in these positions of poll.

Microprocessor Interface

The Microprocessor Interface 18 that connects the EOS device makes system can insert all registers in the OS device.Microprocessor Interface may operate in drives interrupts or poll pattern.In interrupt mode, the EOS device is supported multiple interrupt source.No matter in the sort of pattern, the EOS device all can be sheltered any interruption.

Because other sections in the EOS device of the present invention are well-known, in this slightly description of decorrelation.

Described EOS device of the present invention with reference to SDH/SONET above, EOS device of the present invention also can be used on to be simplified among the SDH/SONET.Simplify the SDH/SONET that SDH/SONET is meant simplification, wherein stop POH, to reduce the load of processor.

Figure 14 shows that according to the embodiment of the invention exemplary plot that the SDH private network is connected with 2 layer switch (called after S24-2OC-48) of the 10base-T with EOS device, 100BASE-T and 1000BASE-x.

Used being defined as follows: GMAC among the figure, the access control of kilomegabit medium; GMII, the kilomegabit medium independent interface; MAC, the medium access control; Exchange control internal memory (Switch control Memory): be used for exchange process read and write data; The I2C interface is used to provide the E2PROM interface; Cpu i/f unit: be used to provide interface function to outside microcomputer main frame; Frame buffer: be used for the storing high-speed data; Frame memory is used for storing in a usual manner data; Gigabit Ethernet over STM-16c/OC-48C, the EOS unit that provides two gigabit Ethernets to shine upon.

Show single GMII channel according to the single OC-48c/STM-16c shown in the block diagram of Fig. 9.24 port one 0/100MAC are used to provide 24 MAC port to handle.(MACFrame Engine MFE) is main mac frame buffering and forwarding engine among the S24-2GEOC48 to the mac frame engine.The MAC search engine (MSE) be used to provide the destination-address function of search.

The essential characteristic of S24-2GEOC48 is as follows:

● 2 gigabit ethernet ports on the STM-16c/OC-48c;

● 24 10/100Mbps of band MII interface intercept automatically, fast ethernet port;

● support IEEE 802.1d spanning tree algorithm;

● 2 layers of exchange.

--the support of inner exchanging databases reach 2k MAC Address, up to 64k be used for SNMP network management CPU memory, based on the network management consloe interface of Web or local console interface of RS-232 or parallel interface.

---in 24+2 (EOS) system supports the nearly MAC Address of 16k.

● try to find out the support ip multicast by IGMP;

● the high speed mac frame is transmitted, and forwarding rate is greater than per second 3,000,000 mac frames (3Mpps), and full line speed filters;

● adopt real non-modularization architecture, support to surpass the system of 6Mpps (per second 6,000,000 bags) throughput.

● in storage of entry port list and forwarding, in the straight-through exchange of destination port

● by single storage and forwarding switching technology, it is very low to delay time;

● FDX Ethernet IEEE 802.3x current control minimizes traffic congestion;

● half-duplex port is adopted back pressure (backpressure) current control (IEEE802.3x);

● port and ID are provided the Virtual Local Area Network 802.1Q of sign;

● VLAN ID indicates insertion/extraction;

● support IEEE 802.1p/Q service quality, it has 4 preferential transmit queues, Weighted Fair Queuing and users and shines upon priority and weight

● support Ethernet-Tree and broadcasting;

● source, purpose and protocol filtering are provided;

● strict electricallyerasable ROM (EEROM) is carried (EEPROM) the configuration data protection is provided.

S24-2GEOC48 is the non-modularization Ethernet switching chip that the 10/100/1000Mbps Gigabit Ethernet overover STM-16c/OC-48c of one 26 port has address memory space in the sheet.The addressed memory support reaches the MAC Address of 2K and reaches 256 IEEE 802.1Q Virtual Local Area Network in the sheet.Support port relaying (port trunking)/load Sharing at 10/100Mbps port S24-2GEOC48.In can be used for, port relaying/load Sharing connects the port grouping of inter-exchange, to increase network bandwidth efficient.The frame buffer memory interface adopt performance and price worthwhile, high-performance continuous-flow type synchronization burst SRAM, to support full line speed at all outside ports simultaneously.At semiduplex mode, all of the port is supported back-pressure flow control, and the threat that activates the loss of data of burst is for a long time dropped to minimum.At full-duplex mode, provide IEEE 802.3x current control.Under the full duplex situation, port 0-11 supports 200Mbps to assemble the bandwidth connection, and port one 2 supports 2Gbps to desktop computer, server or other high-performance switches.Each port in 26 ports is independently collected the statistical information of Ethernet SNMP and remote interface management information bank (RMONMIB).Provide access by cpu i/f to these statistical counter/registers.Receive and transmission snmp management frame by cpu i/f, form a whole network Managed Solution.S24-2GEOC48 makes with 0.18 μ m technology.The input voltage of allowing is 3.3V, and output directly is connected with the LVTTL level.

As shown in the figure, when between switch and transmission equipment (as ADM), communicating by letter, EOS device of the present invention can in be contained in 10M/100M/1000M local area network (LAN) 2 layer switch.

24 10/100 medium access controllers (MAC) provide the protocol interface that enters S24-2GEOC48.These MAC finish the requirement of mac frame verification, meet all IEEE 802.3 standards to guarantee each mac frame that offers the mac frame engine.Abandon those length greater than 1518 bytes (band VLAN be masked as 1522 bytes) and less than the data M AC frame of 64 bytes, VHS108 has been designed to support to import the minimum interframe gap between mac frame.

Mac frame engine (MFE) is main mac frame buffer and the forwarding engine among the S24-2GEOC48.Therefore, the storage of the mac frame of MFE control turnover external frame storage buffer is careful the availability of frame buffer, and is arranged the output mac frame to send.When the mac frame data were cushioned, MFE extracted necessary information from each mac frame head, send it in the search engine and handle.Search Results is sent MFE back to, thereby arranges mac frame to send and priority.When a selected mac frame sent, MFE read mac frame from external buffer memory, and it is placed among the output FIFO of output port.

MFE can manage the output transmit queue of S24-2GEOC48 all of the port.In case finish the destination-address search in MSE, the exchange of making decision sends back to MFE, and mac frame is inserted into suitable output queue.Frame enters high priority or enters Low Priority Queuing and controlled by type of service/different business (TOS/DS) field in VLAN Priority flag information or the IP head.What configuration register can determine that QoS mapping adopted is VLAN priority tag or TOS/DS field.In case employing VLAN priority tag carries out the QoS mapping, the user also can send priority by the mapping of register VLAN priority mapping method, and abandons the precedence that the mapping register appointment abandons by register VLAN.When system adopts TOS/DS encoded point field to shine upon QoS, can select for use position [3:5] (with reference to other RFC documents on RFC 2460 and the IETF website) of TOS byte (with reference to RFC 791) or TOS byte to shine upon the priority of transmit queue and the precedence that frame abandons.The user can control selected TOS map field.The TOS field mappings abandons the mapping processing to high-priority queue or Low Priority Queuing by register TOS priority mapping and TOS.S24-2GEOC48 with weighting circulation (Weighted Round Robin, WRR) and the Weighted random earlier detection/abandon that (WeightedRandom Early Detection/Drop WRED) arranges frame to send.For making S24-2GEOC48 that the QoS ability be arranged, need an EEPROM (4k byte) to change the default register configuration, open QoS.

After the power-on, S24-2GEOC48 start address study immediately and mac frame are transmitted.MAC search engine (MSE) is checked its inner exchanging database storage content for each the effective mac frame that receives on the S24-2GEOC48 input port.When MSE does not find coupling in its database, detect unknown source and destination MAC Address.By in the swap data storehouse memorizer, generating new projects, in the resolution information of this location storage necessity, learn these unknown source MAC Address simultaneously.After searching a destination MAC Address of learning, will return this MAC Address control table (MACAddress Control Table, MACT) fresh content of project.After each source address search, MACT project change flag (aging flag) is upgraded.Those will be removed in the user MACT project that (from 5 to 7200 seconds) are not access in the configurable time cycle.Transformation period cycle storage availability is in the low and high 16 place values configuration of register MAC Address transformation period.In each time cycle, all MACT projects change to be checked 1 time.If the mac entry order does not use before next time cycle finishes, then with its deletion.

S24-2GEOC48 supports isolation mode, and this moment, each port of port 0～23 only allowed uplink side port communications direct and based on OC-48.Therefore, this pattern guarantees can directly do not seen by other ports from the data of a port in the port 0～23.This specific character is linked at dwelling house normally that ISP (Internet service provider) wishes in using to obtain, thereby provides the user to transmit the confidentiality of data.

S24-2GEOC48 adopts the strict port interface of standard to make external host insert internal register, management bus as shown in figure 14.This interface is made up of 3 pins: TRANSMIT DATA, RECEIVEDATA and GROUNG.TRANSMIT DATA and RECEIVE DATA pin provide to the address of S24-2GEOC48 and the input of data content.Simple 2 line serial line interfaces are provided, allow from EEPROM configuration S24-2GEOC48.VHS108 adopts the 4K bit EEPROM with an I2C interface.

The another one example of supporting EOS to use is that systems provider provides the Ethernet interface that connects the 10/100/1000M Ethernet switch in its equipment, and the OC-3/STM-1 or the OC-48/STM-16 interface that connect the SDH/SONET transmission system.At an other end, adopt opposite variation.

Figure 15 shows that the schematic diagram of the 10base-T of SDH private network connecting band EOS device according to an embodiment of the invention and 100BASE-T 2 layer switch, 1000BASE-x switch.As shown in the figure, when communicating between Ethernet switch and transmission equipment (as ADM), EOS device of the present invention is arranged in 10M/100M/1000M local area network (LAN) 2 layer switch.

Figure 16 shows that the exemplary plot of SDH public network connection IEEE 802.3 Ethernets 3 layer switch according to another embodiment of the present invention.As shown in the figure, when between Ethernet switch and transmission equipment (as ADM) during with the full line speed high-speed communication, the EOS device is arranged in 10M/100M/1000M local area network (LAN) 3 layer switch.

In the example shown in Figure 15 and 16, can be arranged on (as ADM) in the transmission equipment in addition according to EOS device of the present invention.By adopting this network architecture, benefit of the present invention is Ethernet interface can be provided in transmission equipment.This network configuration can be expanded the Ethernet transmitting range, widens the range of application of transmission equipment, inserts and transmits, and simplifying under the SDH/SONET situation, can be used for DWDM, and Ethernet and SDH/SONET are combined, and need not atm device.

In addition, EOS device according to the present invention is connected between transmission equipment and the LAN switch,, becomes a kind of practical approach on the wide area network thereby Ethernet is operated in so that point-to-point full duplex way traffic simultaneously to be provided.

In addition, the cascade of the VC by SDH/SONET, ethernet frame can mpeg frame and audio frame etc. encapsulate and transmit.Equally, by regulating the pointer among the VC, isolate far transmitting terminal and receiving terminal mutually and be easy to reach synchronous.

Compared with prior art, EOS device of the present invention shows following advantage:

(1) deviation is little the stand-by period

By calculating as can be known, Ethernet-15 μ s, rate adapted buffer-15 μ s, LAPS shine upon buffer-15 μ s, LAPS CRC buffer-15 μ s, and therefore, total stand-by period deviation is 60 μ s.This is than little many of 1 microsecond, thereby EOS device of the present invention can satisfy real-time service transmission requirements.

(2) frame internal clearance (IFP)/IEEE 802.3 frames and LAPS frame mate fully

The complete matching relationship of frame internal clearance (IFP)/IEEE 802.3 frames and LAPS frame as shown in figure 17.The eight hyte sums of the IFG of IEEE 802.3, lead code and SFD (Start Frame Delimiter) are 20 eight hytes all the time.The minimum frame of IEEE 802.3 frames is of a size of 64 eight hytes.In this EOS scheme (Ethernet over SDH/SONET), when IFG (12 eight hytes) occurring, it will be abandoned stealthily, and time filling (totally 12 eight hytes) will substitute IFG.Compare with the prior art PCT/CN00/00211 that has wherein adopted 2 eight hytes (control field of the SAPI of one eight hyte and one eight hyte), the present invention adopted 4 eight hytes (comprise the address field of one eight hyte, eight hytes control field, and the SAPI field of two eight hytes), eight total hyte numbers equal 84.Fortune just means that LAPS frame and IEEE 802.3 frames mate fully.

(3) when operator provided dedicated ethernet or Gigabit (kilomegabit) Ethernet service (for example the Ethernet service provides) for its client, EOS device of the present invention showed following performance:

A. adopt the B1/B2/B3 byte to carry out the remote tracing performance monitoring

B. remote failure indication

Effective current control under the c.IEEE802.3x-burst service state

D. adopt based on SDH/SONET base 1+1 redundancy reliability services is provided

E. low latency and low latency change

F. because various " public " data transfer rate (Ethernet/gigabit Ethernet) is incompatible with the SONET/SDH transmission rate, therefore adopt virtual concatenation and byte-interleaved

(4) disclosed EOS device is complimentary to one another and consistent among EOS device of the present invention and the prior art PCT/CN00/00211.Being expected LAPS adopts 4 bytes of beginning rather than 2 bytes of beginning to identify more high-rise packet.The advantage that LAPS is reused the ppp protocol identifier and therefore mates PPP online (on-the-wire) packet format is, if LAPS defines the L2 signaling afterwards, then LAPS will adopt the PPP signal needn't discard as a reference or change LAPS itself by any way.For example, use LAPS, and adopt PPP for other items for some items.Compared with prior art, LAPS frame format of the present invention embodies performance more flexibly.Require to adopt simultaneously the manufacturer of LAPS and PPP to check 4 bytes that begin, preferably allow LAPS also do like this, come the recognition data grouping just enough with 2 bytes of head beginning to avoid manufacturer to think.

(5) as for the LAPS frame format, information field is based on 32 Ipv4 or Ipv6 datagram.If total expense, comprise that address field (one eight hyte), control field (one eight hyte), SAPI field (2 eight hytes) and FCS field (4 eight hytes) also are based on 32, this is more favourable for implementing, and especially handles for high-speed data.Therefore, compared with prior art, EOS technical scheme of the present invention is more suitable for high-speed data and handles.

(6), change into 4 byte sequences from 2 byte sequences according to embodiments of the invention.Therefore,＜040,300 21〉and＜04 03 00 57 respectively expression encapsulated Ipv4 and Ipv6.Between the use of PPP or LAPS and LAPSSAPI, can not cause and obscure, because in ITU-T SG15, PPP or LAPS have been stipulated SDH VC-4 signal label, thereby distinguished.

(7), according to embodiments of the invention, can avoid any and obscure, that is minimum effective FCS byte (the highest coefficient) is the FCS byte that is right after information field byte insertion afterwards in the end/transmission as for the FCS field.For each byte, import to the CRC calculator with the minimum order that effectively (transmits) position at last.The order gap scrambling that the position of being transmitted is transmitted by them.

(8) according to the type of transmission data, SAPI value of the present invention can adopt other value.Meanwhile, the packaging information field of LAPS frame of the present invention can also can be a byte-oriented towards the position both.

From top with reference to accompanying drawing explanation as can be seen, the present invention has disclosed a kind of brand-new interface arrangement and method that directly Ethernet is fitted to physical channel.The present invention provides Ethernet interface on telecommunications SDH/SONET transmission equipment, or realize long-range access data communications equipment, as core and edge router, switch device, IP-based network access device, ply-yarn drill, high-speed interface unit, as direct adaptive mac frame to SDH/SONET.By simplifying SDH/SONET, as adopting the SDH/SONET that simplifies, Ethernet can be used for DWDM.In addition, technical scheme disclosed in this invention can be compatible mutually with existing various used equipments.The present invention has more flexibility, can satisfy the little real-time Transmission demand of stand-by period and stand-by period deviation, and, can be applicable to real-time Transmission service better based on 32.

More than describe various aspects of the present invention in detail, what however, it should be understood that is that the one of ordinary skilled in the art can openly carry out various modifications to these exemplary embodiments according to of the present invention.These that done are revised and modification all falls in the scope of the invention and aim that is defined by the following claims.

Claims (81)

1. one kind from the data transmission device of upper layer device to lower floor's equipment transmission data bag, comprising:

First receiving device is used for receiving packet from upper layer device, converts described packet to first kind frame;

First processing unit, be used for described first kind frame is packaged into the frame format of the SAPI field that comprises beginning flag, address field, control field, contains the SAPI identifier, the information field that comprises described packet, FCS field and end mark, form the second class frame;

Second processing unit is used for the described second class frame is encapsulated into payload part, and inserts the suitable expense in response to described packet, forms the 3rd class frame; With

First dispensing device is used for described the 3rd class frame is outputed to lower floor's equipment.

2. data transmission device as claimed in claim 1, wherein, described address field is one eight hyte, and described control field is one eight hyte, and described SAPI field is two eight hytes.

3. data transmission device as claimed in claim 2, wherein, described first receiving device is to be used for receiving and buffering input packet, and a FIFO of the speed of the speed of adaptive upper layer device and lower floor's equipment.

4. data transmission device as claimed in claim 3 also comprises scrambling device, is used for the described second class frame is used from multinomial g (x)=x ⁷+ 1 frame synchronization scrambler sequence that generates is carried out the scrambler operation.

5. data transmission device as claimed in claim 4 also comprises pointer processing apparatus, is used for inserting at described the 3rd class frame the pointer of indication payload original position.

6. data transmission device as claimed in claim 5 also comprises the framing device, is used for the second class frame behind the scrambler is encapsulated into described the 3rd class frame.

7. data transmission device as claimed in claim 6, wherein, the beginning flag and the end mark of the described second class frame is " 0x7E ", and described 0x7E sends during the time between frame and the frame fills.

8. data transmission device as claimed in claim 7, wherein, the described first framing device is realized the transparency processing that eight hytes are filled.

9. data transmission device as claimed in claim 8, wherein, described first processing unit utilizes generator polynomial 1+x+x ²+ x ⁴+ x ⁵+ x ⁷+ x ⁸+ x ¹⁰+ x ¹¹+ x ¹²+ x ¹⁶+ x ²²+ x ²³+ x ²⁶+ x ³²All eight hytes to frame except that beginning flag, end mark and FCS field itself are calculated 32 Frame Check Sequence fields.

10. data transmission device as claimed in claim 4, wherein, described payload part comprises one or more payload subdivisions that are used to carry described first kind frame.

11. data transmission device as claimed in claim 1, wherein, described first processing unit obtains SAPI from described first receiving device.

12. data transmission device as claimed in claim 1, wherein, the end mark of the previous second class frame is the beginning flag of the second class frame subsequently.

13. data transmission device as claimed in claim 1, the inside also comprise line scan pickup coil side bag loopback apparatus, are used for the first kind frame from the extraction of the second class frame is looped back to first processing unit, are used for test.

14. data transmission device as claimed in claim 10, wherein, described payload part is cascade adjacency or virtual of virtual container or virtual container, and virtual container is the payload subdivision.

15. according to any one described data transmission device in the aforementioned claim, wherein, described expense comprises channels track byte (J1), channel B IP-8 byte (B3), signal label byte (C2), the channel status byte (G1) with single virtual container or cascade system.

16. as any one described data transmission device in the claim 1 to 14, wherein, described physical layer is SDH/SONET or simplifies SDH/SONET.

17. as any one described data transmission device in the claim 1 to 14, wherein, described upper strata is the ethernet mac layer, described first kind frame is a mac frame, and the described second class frame is the LAPS frame, and described the 3rd class frame is the SDH/SONET frame.

18. as any one described data transmission device in the claim 1 to 14, wherein, described data transmission device is built in the SDH/SONET transmission equipment.

19. as any one described data transmission device in the claim 1 to 14, wherein, described data transmission device is built in the ethernet switching device.

20. as any one described data transmission device in the claim 1 to 14, wherein, described data transmission device is ethernet switching device or Ethernet/Fast Ethernet/gigabit Ethernet 2 layers/3 layer switch or relevant router.

21. data transmission device as claimed in claim 19, wherein, described ethernet switching device is Ethernet/Fast Ethernet/gigabit Ethernet 2 layers/3 layer switch or relevant router.

22. data transmission device as claimed in claim 16, wherein, described data transmission device by transducer make the MAC/GMAC frame that receives from the MII/GMII synchronization map to the SDH/SONET module.

23. data transmission device as claimed in claim 16, wherein, for rate adapted, described data transmission device adds rate adapted able to programme gap byte of padding " 0xdd " with the form of " 0x7d, 0xdd " in the described second class frame.

24. one kind from the data transmission method of upper layer device to lower floor's equipment transmission data bag, comprises the following steps:

Receive and buffered data packet from described upper layer device, the speed of the speed of adaptive upper layer device and lower floor's equipment converts this packet to first kind frame;

Described first kind frame is packaged into the frame format of the SAPI field that comprises beginning flag, address field, control field, contains the SAPI identifier, the information field that comprises described packet, FCS field and end mark, forms the second class frame;

The described second class frame is encapsulated into payload part, and inserts the suitable expense of described packet, form the 3rd class frame; With

Described the 3rd class frame is outputed to lower floor's equipment.

25. data transmission method as claimed in claim 24,, wherein, described address field is one eight hyte, and described control field is one eight hyte, and described SAPI field is two eight hytes.

26. data transmission method as claimed in claim 25 also comprises the scrambler step, is used for the second class frame in order to multinomial g (x)=x ⁷+ 1 frame synchronization scrambler sequence that generates is carried out the scrambler operation.

27. data transmission method as claimed in claim 26 also comprises the step that is used for inserting at described the 3rd class frame the pointer of indication payload part original position.

28. data transmission method as claimed in claim 27 also comprises the second class frame behind the scrambler is encapsulated into step in the 3rd class frame.

29. data transmission method as claimed in claim 28, wherein, described beginning flag and end mark are " 0x7E ", and described data transmission method also comprises the step of the transparency processing that eight hytes are filled.

30. data transmission method as claimed in claim 29 also comprises calculation procedure, is used to utilize generator polynomial 1+x+x ²+ x ⁴+ x ⁵+ x ⁷+ x ⁸+ x ¹⁰+ x ¹¹+ x ¹²+ x ¹⁶+ x ²²+ x ²³+ x ²⁶+ x ³², all eight hytes of frame except that beginning flag, end mark and FCS field itself are calculated 32 Frame Check Sequences.

31. data transmission method as claimed in claim 30, wherein, described payload part comprises a plurality of payload subdivisions that are used to carry described first kind frame.

32. data transmission method as claimed in claim 24, wherein, the end mark of former frame is the beginning flag of frame subsequently.

33. data transmission method as claimed in claim 24, wherein, described payload part is adjacency and the virtual cascade of virtual container or virtual container, and virtual container is the payload subdivision.

34. as any one described data transmission method in the claim 24 to 33, wherein, described expense comprises channels track byte (J1), channel B IP-8 byte (B3), signal label byte (C2), the channel status byte (G1) with single virtual container or cascade system.

35. as any one described data transmission method in the claim 24 to 33, wherein, described physical layer is SDH/SONET or simplifies SDH/SONET.

36. as any one described data transmission method in the claim 24 to 33, wherein, described upper strata is ethernet mac/GMAC layer, described first kind frame is the MAC/GMA frame, and the described second class frame is the LAPS frame, and described the 3rd class frame is the SDH/SONET frame.

37. data transmission method as claimed in claim 36, wherein, described ethernet layer is the ethernet layer of IEEE802.3/802.3u/802.3z.

38. data transmission method as claimed in claim 35 also comprises by transducer making the MAC/GMAC frame that receives be synchronized to the step of SDH/SONET module from MII/GMII.

39. data transmission method as claimed in claim 35 for rate adapted, also comprises the step that adds rate adapted able to programme gap byte of padding " 0xdd " with the form of " 0x7d, 0xdd " in the described second class frame.

40. one kind sends the data transmission device of the packet that is formed by first kind frame from lower floor's equipment to upper layer device, comprising:

Second receiving system is used for the equipment receiving data bag from described lower floor;

The frame resolver is used for removing expense from described first kind frame;

The 3rd processing unit, be used for extracting SAPI field and the data that are included in information field from the payload part of described first kind frame, form the second class frame, each described second class frame comprises: beginning flag, address field, control field, SAPI field, information field, FCS field and end mark;

Determine device, be used for the value and the preset value of comparison SAPI field, and when value that SAPI field data value equals to set, determine the data of output actual extracting;

Manages device everywhere, is used for the described second class frame is converted to and corresponding the 3rd class frame of packet; With

Second dispensing device, the packet that is used for extracting sends to described upper layer device.

41. data transmission device as claimed in claim 40, wherein, described address field is one eight hyte, and described control field is one eight hyte, and described SAPI field is two eight hytes.

42. data transmission device as claimed in claim 41, wherein, described second dispensing device is to be used for receiving and buffering input packet, and the 2nd FIFO of the speed of the speed of adaptive lower floor equipment and upper layer device.

43. data transmission device as claimed in claim 42 also comprises descrambler, being used for the described second class frame is g (x)=x in order to multinomial ⁷+ 1 frame synchronization scrambler sequence that generates is carried out descrambling operation.

44. data transmission device as claimed in claim 43 also comprises pointer processing apparatus, is used for adopting pointer to being encapsulated in the payload part original position location of described first kind frame.

45. data transmission device as claimed in claim 44, wherein, described beginning flag and end mark are " 0x7E ".

46. data transmission device as claimed in claim 45, wherein, described frame resolver is removed interframe and is filled, and described frame resolver is carried out the transparency and handled.

47. data transmission device as claimed in claim 46, wherein, by utilizing generator polynomial 1+x+x ²+ x ⁴+ x ⁵+ x ⁷+ x ⁸+ x ¹⁰+ x ¹¹+ x ¹²+ x ¹⁶+ x ²²+ x ²³+ x ²⁶+ x ³²All eight hytes between beginning flag and end mark are calculated FCS, come the FCS field of the described reception of verification.

48. data transmission device as claimed in claim 47 also comprises the expense supervising device, is used for the status error of expense in the described first kind frame of DRP data reception process monitoring.

49. data transmission device as claimed in claim 48, wherein, described payload part comprises a plurality of payload subdivisions.

50. data transmission device as claimed in claim 49, wherein, the end mark of former frame is the beginning flag of the frame subsequently after the former frame.

51. data transmission device as claimed in claim 50, wherein, described payload part is adjacency and the virtual cascade of virtual container or virtual container, and virtual container is the payload subdivision.

52. as any one described data transmission device in the claim 40 to 51, wherein, described expense comprises channels track byte (J1), channel B IP-8 byte (B3), signal label byte (C2), channel status byte (G1).

53. as any one described data transmission device in the claim 40 to 51, wherein, described physical layer is SDH/SONET or simplifies SDH/SONET.

54. as any one described data transmission device in the claim 40 to 51, wherein, described upper strata is ethernet mac/GMAC layer, described first kind frame is the SDH/SONET frame, and the described second class frame is the LAPS frame, and described the 3rd class frame is the MAC/GMAC frame.

55. as any one described data transmission device in the claim 40 to 51, wherein, described data transmission device is built in the SDH/SONET transmission equipment.

56. as any one described data transmission device in the claim 40 to 51, wherein, described data transmission device is built in the ethernet switching device.

57. as any one described data transmission device in the claim 40 to 51, wherein, described data transmission device is ethernet switching device or Ethernet/Fast Ethernet/gigabit Ethernet 2 layers/3 layer switch or relevant router.

58. data transmission device as claimed in claim 56, wherein, described ethernet switching device is Ethernet/Fast Ethernet/gigabit Ethernet 2 layers/3 layer switch or relevant router.

59. data transmission device as claimed in claim 53, wherein, for rate adapted, described data transmission device removes the rate adapted able to programme gap byte of padding that the form with " 0x7d, 0xdd " exists in the described second class frame.

60. data transmission device as claimed in claim 53, wherein, described data transmission device makes the LAPS information field for the MAC/GMAC frame be synchronized to RX_CLK from the SDH/SONET module at the MII/GMII interface by transducer.

61. one kind sends the data transmission method of the packet that is formed by first kind frame from lower floor's equipment to upper layer device, comprises the following steps:

From described lower floor equipment receiving data bag;

From described first kind frame, remove expense;

Extract SAPI field and the data that are included in the information field from the payload part of described first kind frame, form the second class frame, each described second class frame comprises: beginning flag, address field, control field, SAPI field, information field, FCS field and end mark;

The value and the preset value of SAPI field are compared, when value that SAPI field data value equals to set, determine the data of output actual extracting;

The described second class frame is converted to and corresponding the 3rd class frame of described packet; With

The packet that extracts is sent to described upper layer device.

62. data transmission method as claimed in claim 61, wherein, described address field is one eight hyte, and described control field is one eight hyte, and described SAPI field is two eight hytes.

63. data transmission method as claimed in claim 62 also comprises receiving and buffering input packet the step of the speed of adaptive lower floor equipment and the speed of upper layer device.

64. as the described data transmission method of claim 63, also comprise the scrambler step, being used for the described second class frame is that the frame synchronization scrambler sequence that g (x)=x7+1 generates is carried out descrambling operation in order to multinomial.

65., also comprise being used for adopting the original position localization step of pointer to the payload that is encapsulated in described first kind frame as the described data transmission method of claim 64.

66. as the described data transmission method of claim 65, wherein, described beginning flag and end mark are " 0x7E ", and described data transmission method also comprises the step of removing the interframe filling.

67. as the described data transmission method of claim 66, wherein, by utilizing generator polynomial 1+x+x ²+ x ⁴+ x ⁵+ x ⁷+ x ⁸+ x ¹⁰+ x ¹¹+ x ¹²+ x ¹⁶+ x ²²+ x ²³+ x ²⁶+ x ³²All eight hytes between beginning flag and end mark are calculated FCS, come the FCS field of the described reception of verification.

68., also comprise the step that is used at the status error of the described first kind frame overhead of receiving course monitoring as the described data transmission method of claim 67.

69. as the described data transmission method of claim 68, wherein, described payload part comprises a plurality of payload subdivisions.

70. as the described data transmission method of claim 69, wherein, the end mark of former frame is the beginning flag of frame subsequently.

71. as the described data transmission method of claim 70, wherein, described payload part is adjacency and the virtual cascade of virtual container or virtual container, virtual container is the payload subdivision.

72. as any one described data transmission method in the claim 61 to 71, wherein, described expense comprises channels track byte (J1), channel B IP-8 byte (B3), signal label byte (C2), the channel status byte (G1) with single virtual container or cascade system.

73. as any one described data transmission method in the claim 61 to 71, wherein, described physical layer is SDH/SONET or simplifies SDH/SONET.

74. as any one described data transmission method in the claim 61 to 71, wherein, described upper strata is ethernet mac/GMAC layer, described first kind frame is the SDH/SONET frame, and the described second class frame is the LAPS frame, and described the 3rd class frame is the MAC/GMAC frame.

75. as the described data transmission method of claim 74, wherein, described ethernet layer is the IEEE802.3/802.3u/802.3z ethernet layer.

76.,, also comprise a step that the rate adapted byte of padding able to programme that exists with the form of " 0x7d, 0xdd " removes in the described second class frame for rate adapted as the described data transmission method of claim 73.

77., also be included in the MII/GMII interface and make for the LAPS information field of the MAC/GMAC frame step synchronous from the SDH/SONET module to RX_CLK by transducer as the described data transmission method of claim 73.

78. a packet interface arrangement that sends packet between upper layer device and lower floor's equipment comprises according to any one described data transmission device among the claim 1-23 with according to any one described data transmission device among the claim 40-60.

79. as the described DIU data interface unit of claim 78, also comprise line scan pickup coil side interface device, be used for equipment transmission/reception packet from lower floor.

80., also comprise converting means as the described DIU data interface unit of claim 79, be used at sending direction, make the packet of upper layer device synchronous with the packet that is input to described first receiving device process; At receive direction, make the packet of the packet that extracts from second dispensing device and described upper layer device synchronous.

81. as the described DIU data interface unit of claim 80, also comprise: the Microprocessor Interface device is used to make described DIU data interface unit can insert its all interior registers; The jtag port that is used to test; Be used for temporarily cushioning the GPIO register of I/O configuration data.

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