CN1255878C - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN1255878C CN1255878C CNB028026772A CN02802677A CN1255878C CN 1255878 C CN1255878 C CN 1255878C CN B028026772 A CNB028026772 A CN B028026772A CN 02802677 A CN02802677 A CN 02802677A CN 1255878 C CN1255878 C CN 1255878C
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- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
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- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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Abstract
The region between a source region (19) and a drain region (20) in an Si layer (15) is an Si body region (21) containing high-concentration N-type impurities. An Si layer (16) and an SiGe layer (17) are undoped layer not doped with N-type impurities in an as-grown state. The regions between the source and drain regions (19, 20) of the Si layer (16) and the SiGe layer (17) are respectively a low-concentration N-type impurity-containing Si buffer region (22) and a low-concentration N-type impurity-containing SiGe channel region (23). The region right under a gate insulating film (12), of the Si film (18), is an Si cap region (24) where P-type impurities (5 X 10<17> atoms cm<-3>) are introduced. Thus a semiconductor device in which an increase of the threshold voltage is suppressed is realized.
Description
Technical field
The present invention relates to a kind of heterojunction is used for the field-effect transistor of channel region, especially relate to a kind of change countermeasure of threshold voltage.
Background technology
In recent years, be that the mobile information terminal apparatus of representative is widely used with the portable phone.This portable unit is generally battery-operated, and for extending battery life, strong expectation is not sacrificed responsiveness and carry out low consumpting powerization.For being reduced, responsiveness realizes low consumpting powerization, reduces threshold voltage and reduce supply voltage that increase drain saturation current simultaneously, it is effective keeping current driving capability.In order to satisfy above-mentioned requirements, the heterojunction MOS transistor (below abbreviate heterojunction type MOS as) of the high material of the mobility of charge carrier is used in research in vogue in channel region.
In existing MOS transistor, charge carrier is along the Interface Moving of grid oxidation film and silicon substrate.As in the grid oxidation film of noncrystalline layer and the interface as the silicon substrate of crystallizing layer, the fluctuating of energy energy level is big.Therefore, in existing MOS transistor, charge carrier is subject to interface influence at random, produces bad phenomenon such as carrier mobility decline, noise increase.
On the other hand, so-called heterojunction type MOS is the MOS transistor that heterojunction semiconductor is made as raceway groove.In heterojunction type MOS, form the heterogeneous semiconductor junction interface in the degree of depth of leaving the semiconductor substrate gate insulating film slightly.Form raceway groove in this heterogeneous semiconductor junction interface, charge carrier moves along this raceway groove.Because the heterogeneous semiconductor junction interface is crystallizing layer interface connected to one another, so the fluctuating of energy energy level is little.Therefore, interface influence at random is little.So, have the feature that current driving capability is big, noise reduces.And, compare with existing MOS transistor, also have the feature that can reduce threshold voltage.
Deal with problems
But in the above-mentioned heterojunction type MOS that heterojunction is used for raceway groove, channel region becomes baried type.Therefore, threshold voltage depends on the thickness in Si lid zone to a great extent.
Figure 15 represents the structure of existing heterojunction type MOS.
As shown in figure 15, existing heterojunction type MOS 100 is made of Si substrate 101, the polysilicon that is formed at the gate insulating film 102 on the Si substrate 101 and comprises the high concentration p type impurity, possess the gate electrode 103 that is formed on the gate insulating film 102 and be formed on the gate insulating film 102, the sidewall spacer 104 of cover gate electrode 103 sides.Si substrate 101 has the P type source region 105 and the drain region 106 that are arranged on the grid both sides, be set in place between source region 105 and drain region 106 lid of the N type Si in zone zone 107, be arranged on N type SiGe channel region 108 that Si covers regional 107 belows, be arranged on the N type Si buffer area 109 of SiGe channel region 108 belows and be arranged on the N type Si matrix region 110 of 109 belows, Si buffer area.
Figure 16 represents to simulate threshold voltage among the existing heterojunction type MOS100 covers regional 107 thickness dependences to Si result.
As shown in figure 16, the thickness in Si lid zone 107 becomes big, and then the absolute value of threshold voltage obviously becomes big.That is, threshold voltage obviously uprises.This is that to leave grid dark more because form the position (being Si lid zone 107 and the interface of SiGe channel region 108) of raceway groove, and then the relative grid voltage of the current potential of raceway groove can fully not change more.
But, if consider, then because Si covers zone 107 at SiO from the processing aspect
2Heat oxide film forms film minimizing in operation, the clean operation etc., so be very difficult to control thickness.Therefore, in the thickness in Si lid zone 107, easily produce difference.Therefore, easily produce difference in the threshold voltage, threshold of appearance threshold voltage height, can not realize expecting the bad result that moves.
Especially, in having a plurality of identical transistorized integrated circuits,, then in change-over time, produce difference between each transistor if between each transistor, produce difference in the threshold voltage.As a result, between each transistor of integrated circuit, regularly produce dislocation, integrated circuit can not regular event.In addition, the difference of considering threshold voltage must be to be the slowest change-over time benchmark, so be difficult to the action of high speed integrated circuit with under the situation of guaranteeing operation margin.
Summary of the invention
Above-mentionedly not to be inconsistent in order solving, to the object of the present invention is to provide a kind of semiconductor device that threshold voltage increases that suppresses.
Semiconductor device of the present invention possesses: substrate; Be arranged on the semiconductor layer on aforesaid substrate top; Be arranged on the gate insulating film on above-mentioned semiconductor layer top; Be arranged on the gate electrode on the above-mentioned gate insulating film; Be arranged on the 1st conductivity type the 1st source-drain electrodes zone of above-mentioned gate electrode both sides in the above-mentioned semiconductor layer; Be arranged on the 1st lid zone that is arranged in the 1st conductivity type interregional zone of above-mentioned the 1st source-drain electrodes, that constitute by the 1st semiconductor in the above-mentioned semiconductor layer; Be arranged on above-mentioned the 1st lid zone below in the above-mentioned semiconductor layer, by move for charge carrier can band edge the 1st channel region that constitutes of charge carrier current potential 2nd semiconductor also littler than above-mentioned the 1st semiconductor; With the 1st matrix region that is arranged on the 2nd conductivity type above-mentioned the 1st channel region below in the above-mentioned semiconductor layer, that constitute by the 3rd semiconductor.
By constituting the 1st lid zone that possesses the 1st conductivity type that constitutes by the 1st semiconductor; Be arranged on lid zone below, by move for charge carrier can band edge the 1st channel region that constitutes of charge carrier current potential 2nd semiconductor also littler than above-mentioned the 1st semiconductor; With the 1st matrix region that is arranged on the 2nd conductivity type channel region below, that constitute by the 3rd semiconductor, can obtain relative the 1st lid area thickness and increase and suppress the semiconductor device that threshold voltage increases.
Also can be electrically connected above-mentioned gate electrode and above-mentioned the 1st matrix region.
Thus, if apply grid bias, then apply forward bias voltage drop with the identical size of grid bias to the 1st channel region through the 1st matrix region to gate electrode.Thereby, when semiconductor device of the present invention ends in grid bias, become the state identical with common MOS transistor, in addition, when the grid bias conducting, owing to the increase along with grid bias, the 1st matrix region deflection is along direction, so threshold voltage reduces.That is, obtain the semiconductor device that can under low threshold voltage, move.In addition, be electrically connected grid electrode and the 1st matrix region, can further reduce the variable quantity of relative the 1st lid area thickness change of threshold voltage by constituting.
Above-mentioned lid zone constitutes when applying grid bias depleted.
The 1st conductive-type impurity concentration that comprises in above-mentioned the 1st lid zone is preferably 1 * 10
17Atomscm
-3More than.
Preferred the 1st conductive-type impurity that mixes in above-mentioned the 1st lid zone, so that with respect to the varied in thickness in above-mentioned the 1st lid zone, the current potential that is formed at the raceway groove in the regional interface of above-mentioned the 1st channel region and above-mentioned the 1st lid when zero-bias is in ± 0.05eV scope.
Therefore, even can obtain the semiconductor device that the lid area thickness changes, also can suppress the threshold voltage change.
The 2nd conductive-type impurity concentration that comprises in above-mentioned the 1st matrix region is preferably 5 * 10
18Atomscm
-3More than.
Thus, can suppress the matrix electric current that occurs in the horizontal parasitic bipolar transistor low.And,, can suppress depletion layer and widen from source region and drain region when to source-drain electrodes is interregional when applying voltage.Therefore, even matrix concentration height also can guarantee low threshold voltage, can be suppressed at the short-channel effect that takes place under the short situation of grid length.
The thickness in above-mentioned the 1st lid zone is preferably below 10nm.
Above-mentioned the 1st semiconductor also can be a silicon.
Above-mentioned the 2nd semiconductor also can be by any constitutes at least in silicon, germanium and the carbon.
Also can also possess: second half conductor layer that is arranged on aforesaid substrate top; Be arranged on another gate insulating film on above-mentioned second half conductor layer; Be arranged on another gate electrode on above-mentioned another gate insulating film; Be arranged on another the 1st source-drain electrodes zone of the 1st conductivity type of above-mentioned another gate electrode both sides in above-mentioned second half conductor layer; Be arranged on another the 1st lid zone that is arranged in the 1st conductivity type interregional zone of above-mentioned another the 1st source-drain electrodes, that constitute by above-mentioned the 1st semiconductor in above-mentioned second half conductor layer; Another the 1st channel region that is arranged on above-mentioned another the 1st lid zone below in above-mentioned second half conductor layer, constitutes by above-mentioned the 2nd semiconductor; With another the 1st matrix region that is arranged on the 2nd conductivity type above-mentioned another the 1st channel region below in above-mentioned second half conductor layer, that constitute by above-mentioned the 3rd semiconductor.
Thereby, even produce under the situation of difference the semiconductor device of each transistor threshold difference that still can be reduced in the 1st lid area thickness that causes because of processing differences.
Also can constitute also and possess: second half conductor layer that is arranged on aforesaid substrate top; Be arranged on another gate insulating film on above-mentioned second half conductor layer; Be arranged on another gate electrode on above-mentioned another gate insulating film; Be arranged on the 2nd source-drain electrodes zone of the 2nd conductivity type of above-mentioned another gate electrode both sides in above-mentioned second half conductor layer; Be arranged on and be arranged in the 2nd channel region interregional zone of above-mentioned the 2nd source-drain electrodes, that constitute by the 4th semiconductor in above-mentioned second half conductor layer; With the 2nd matrix region that is arranged on the 1st conductivity type above-mentioned the 2nd channel region below in above-mentioned second half conductor layer, that constitute by the 5th semiconductor, as complementary type device performance function.
Above-mentioned the 2nd channel region is the 2nd conductivity type preferably.
Thus, the transistorized threshold voltage that can suppress to be formed in second half conductor layer changes.
Also can be electrically connected above-mentioned gate electrode and above-mentioned the 1st matrix region, be electrically connected above-mentioned another gate electrode and above-mentioned the 2nd matrix region.
The manufacture method of semiconductor device of the present invention comprises: operation (a), form the 1st semiconductor layer on the top of semiconductor substrate, this semiconductor layer has the 1st semiconductor regions that has imported the 1st conductive-type impurity and has imported the 2nd semiconductor regions of the 2nd conductive-type impurity; Operation (b), the 3rd semiconductor layer that on above-mentioned the 1st semiconductor layer, forms the 2nd semiconductor layer successively and constitute than the big semiconductor of above-mentioned the 2nd semiconductor layer by band gap; Operation (c) is positioned in above-mentioned the 3rd semiconductor layer on the part of above-mentioned the 1st semiconductor regions and forms mask, uses aforementioned mask, the 1st conductive-type impurity is imported the part that is arranged in above-mentioned the 2nd semiconductor regions in above-mentioned the 3rd semiconductor layer at least; Operation (d) after removing aforementioned mask, is positioned at the part of above-mentioned the 1st semiconductor regions and is positioned on the part of above-mentioned the 2nd semiconductor regions in above-mentioned the 3rd semiconductor layer, form gate insulating film and gate electrode respectively; And operation (e), with above-mentioned each gate electrode as mask, by implanting impurity ion in above-mentioned the 1st semiconductor layer, above-mentioned the 2nd semiconductor layer and above-mentioned the 3rd semiconductor layer, in above-mentioned the 1st semiconductor regions, form the 2nd conductive type source-drain region, in above-mentioned the 2nd semiconductor regions, form the 1st conductive type source-drain region.
According to the present invention, can obtain semiconductor device as the complementary type device, suppress to be formed at the heterojunction type MIS threshold voltage in the 2nd semiconductor regions covers the 3rd semiconductor layer thickness variation in zone along with formation change.And, according to the present invention, the part that in the 3rd semiconductor layer, is arranged in the 1st semiconductor regions the 1st conductive-type impurity that undopes.Therefore, being used as in the semiconductor device of complementary type device of obtaining by the inventive method, can not damage the characteristic of the heterojunction type MIS that is formed in the 1st semiconductor regions.
In above-mentioned operation (c), preferred implanting impurity ion makes the maximum of the 1st conductive-type impurity CONCENTRATION DISTRIBUTION be present in above-mentioned the 2nd semiconductor layer or in above-mentioned the 3rd semiconductor layer.
The transistorized threshold voltage change that thus, can suppress to form in the 1st semiconductor regions.
Description of drawings
Fig. 1 is the figure of expression heterojunction type MOS cross-sectional configuration of the present invention.
Fig. 2 represents for existing heterojunction type MOS and heterojunction type MOS of the present invention, the figure of the dependency relation of threshold voltage and Si lid area thickness.
Fig. 3 (A)～(C) represents for 3 kinds of heterojunction type MOS with the Impurity Distribution that is used for Fig. 2 simulation the figure that can be with distribution during zero-bias.
Fig. 4 is the figure of the Vg-Id characteristic of 3 kinds of different heterojunction type MOS of expression Si lid zone.
Fig. 5 is for heterojunction type MOS, and grid voltage is drawn the figure of the peak concentration that accumulates in the hole in raceway groove and the parasitic channel relatively.
Fig. 6 is the figure of expression heterojunction type DTMOS cross-sectional configuration of the present invention.
Fig. 7 is the vertical view of heterojunction type DTMOS of the present invention.
Fig. 8 represents for existing heterojunction type DTMOS and heterojunction type DTMOS of the present invention, the figure of the dependency relation of threshold voltage and Si lid area thickness.
Fig. 9 represents to simulate the result's of Vg-Id characteristic figure separately for existing heterojunction type DTMOS and heterojunction type DTMOS of the present invention.
Figure 10 be expression for existing heterojunction type DTMOS and heterojunction type DTMOS of the present invention, the figure of Vg-Id characteristic separately.
Figure 11 be expression with the SiGe layer as channel region, utilize the figure of the complementary type MOS cross-sectional configuration of the present invention of Si/SiGe heterojunction.
Figure 12 is the operation sectional view of expression complementary type MOS manufacture method of the present invention.
Figure 13 (a) is that the P-heterojunction type MOS that possesses of expression complementary type heterojunction type MOS of the present invention can be with distribution map when applying grid bias, and Figure 13 (b) is that the N-heterojunction type MOS that possesses of expression complementary type heterojunction type MOS of the present invention can be with distribution map when applying grid bias.
Figure 14 is that the Ge of the P-heterojunction type MOS that has of expression complementary type heterojunction type MOS of the present invention in Si matrix region, Si buffer area, SiGe channel region and Si lid zone forms and the figure of Impurity Distribution.
Figure 15 is the figure of the existing heterojunction type MOS structure of expression.
Figure 16 is the figure that threshold voltage covers the dependent result of area thickness among the existing heterojunction type MOS of expression simulation to Si.
Embodiment
Below, with reference to accompanying drawing embodiments of the present invention are described.For simply, the common inscape of each execution mode is represented by identical reference marks.
(execution mode 1)
The formation of the heterojunction type MOS of present embodiment at first, is described.Fig. 1 represent with the SiGe layer as channel region, utilize the cross-sectional configuration of P raceway groove heterojunction type MOS10 of the present embodiment of Si/SiGe heterojunction.
As shown in Figure 1, the P raceway groove heterojunction type MOS10 of present embodiment possesses: P type Si substrate 11, be arranged on the Si substrate 11 by SiO
2The gate insulating film 12 that film (about 6nm) constitutes, by the polysilicon that comprises the high concentration p type impurity constitute and be arranged on the gate electrode 13 on the gate insulating film 12 and be formed on the gate insulating film 12, the sidewall spacer 14 of cover gate electrode 13 sides.
The P raceway groove heterojunction type MOS10 of present embodiment shown in Figure 1 before crystalline growth, injects the N type impurity (2 * 10 that imports high concentration to Si substrate 11 tops by ion in advance with regard to its manufacturing process
18Atomscm
-3), form Si layer 15.On Si layer 15, form epitaxially grown Si layer 16, SiGe layer 17 and Si layer 18 successively by the UHV-CVD method.
In addition, for the P raceway groove heterojunction type MOS10 of present embodiment,, be provided with the source region 19 and the drain region 20 that comprise the high concentration p type impurity in the zone that is arranged in gate electrode 13 both sides of Si layer 15, Si layer 16, SiGe layer 17 and Si layer 18.
In addition, source region 19 among the Si layer 15 and the zone between the drain region 20 constitute the Si matrix region 21 that comprises high concentration N type impurity.Si layer 16 and SiGe layer 17 arbitrary non-doped layer that all constitutes the N type impurity that undopes under growth (as-grown) state, source region 19 among Si layer 16 and the SiGe layer 17 and the zone between the drain region 20 constitute Si buffer area 22 that comprises low concentration N type impurity and the SiGe channel region 23 that comprises low concentration N type impurity respectively.Being positioned at zone under the gate insulating film 12 in the Si film 18 constitutes and imports p type impurity (5 * 10
17Atomscm
-3) Si lid zone 24.In addition, gate insulating film 12 forms by thermal oxidation Si layer 18.When the P of present embodiment raceway groove heterojunction type MOS10 moves, by the grid bias that is applied on the grid 13, exhaust SiGe channel region 23 and Si lid zone 24, move in SiGe channel region 23 in the hole.
The thickness of Si layer 16 is 10nm, SiGe layer 17, is that the thickness of SiGe channel region 23 is 15nm.In addition, the Ge containing ratio in the SiGe channel region 23 is 30%.
Fig. 2 represents for the heterojunction type MOS10 of above-mentioned existing heterojunction type MOS100 and present embodiment, the dependency relation of threshold voltage and Si lid area thickness.
In existing heterojunction type MOS 100, doped N-type impurity in Si lid zone 107 is with the dependency relation of chain-dotted line shown in Figure 2 (A) expression threshold voltage and Si lid area thickness.
On the other hand, has doping 5 * 10
17Atomscm
-3Among the heterojunction type MOS10 of the present embodiment in the Si lid zone 24 of left and right sides p type impurity, with the dependency relation of solid line shown in Figure 2 (B) expression threshold voltage and Si lid area thickness.As can be seen from Figure 2, in the heterojunction type MOS10 of present embodiment, compare with existing heterojunction type MOS100, threshold variation diminishes.And (p type impurity concentration is 1 * 10 under the many situations of the p type impurity concentration in Si lid zone 24
18Atomscm
-3), opposite with existing heterojunction type MOS100, dotted line (C) expression as shown in Figure 2, the thickness in Si lid zone 24 becomes big, and the absolute value of threshold voltage diminishes.That is threshold voltage step-down.This is because Si covers the high regional thickening of doping content in the zone 24, the current potential step-down of SiGe channel region 23.
Therefore, by the p type impurity that in Si lid zone 24, mixes, even can also can suppress threshold voltage and increase because processing differences increases the thickness in Si lid zone 24.
In existing heterojunction type MOS100, because Si lid zone 107 is adding man-hour because SiO
2Heat oxide film forms film attenuates such as operation, clean operation, so be very difficult to control thickness.Therefore, the thickness in Si lid zone 107 easily produces difference.Therefore, in same wafer and between each wafer, constitute the reason that produces threshold voltage difference, become the big problem among the existing heterojunction type MOS.
But, according to present embodiment, by suitable doping p type impurity in Si lid zone 24, even the thickness in Si lid zone 24 also can suppress the change of threshold voltage little owing to processing differences changes.Come further to be explained in detail with reference to Fig. 3.
Fig. 3 (A)～(C) represents for 3 kinds of heterojunction type MOS with the impurity profile that is used for above-mentioned Fig. 2 simulation the figure that can be with distribution during zero-bias.In Fig. 3 (A)～(C), the thickness in expression Si lid zone be 1,2,5 and 10nm down each 4 kinds can be with distribution map.
Shown in Fig. 3 (A), in existing heterojunction type MOS100, the absolute value of the valence band current potential of SiGe channel region 23 (male member among the figure) covers the thickness increase in zone 24 along with Si and uprises.This rises relevant with threshold voltage.
On the other hand, shown in Fig. 3 (B), in Si lid zone 24, mixing 5 * 10
17Atomscm
-3Among the heterojunction type MOS10 of the present embodiment of left and right sides p type impurity, even the thickness variation in Si lid zone 24, the valence band current potential of SiGe channel region 23 (male member among the figure) is also certain substantially, and the current potential of the valence electron band edge in the interface is positioned at ± the 0.05eV scope.That is, suppressed the change of threshold voltage.
And, cover under the situation of doped P-type impurity concentration in the zone 24 at raising Si, shown in Fig. 3 (C), along with the increase that Si covers regional 24 thickness, the absolute value step-down of the valence band current potential of SiGe channel region 23 (male member among the figure).This with Fig. 2 in the threshold voltage that dots reduce corresponding.
As mentioned above, cover regional 24 varied in thickness for Si as can be known,, set doping content, make the current potential of SiGe channel region 23 equal substantially in order to reduce the change of threshold voltage.
Then, above-mentioned Si shown in Fig. 4 covers the Vg-Id characteristic of 3 kinds of different heterojunction type MOS of zone.Fig. 4 is the analog result of the Vg-Id characteristic among Fig. 2 and the 3 kinds of heterojunction type MOS shown in Figure 3.Wherein, the thickness in Si lid zone 24 and Si lid zone 107 is 5nm.
As shown in Figure 4, compare, mix 5 * 10 with covering in the zone 24 of solid line (B) expression to Si with the existing heterojunction type MOS100 that represents with chain-dotted line (A)
17Atomscm
-3The heterojunction type MOS10 of the present embodiment of left and right sides p type impurity can flow through the drain current of regulation under low grid voltage.And, when improving the concentration of doped P-type impurity in Si lid zone 24, shown in dotted line (C), can under lower grid voltage, flow through the regulation drain current.
This shows, compare that the heterojunction type MOS10 of the present embodiment of doping p type impurity has the effect that can reduce threshold voltage in Si lid zone 24 with existing heterojunction type MOS100.In addition, change for the threshold voltage that suppresses heterojunction type MOS follows the thickness variation in Si lid zone 24, as long as the p type impurity concentration that comprises in the Si lid zone 24 is 1 * 10
17Atomscm
-3More than get final product.And the p type impurity concentration that comprises in the Si lid zone 24 is preferably 1 * 10
18Atomscm
-3Below.This is because as shown in Figures 2 and 3, and in above-mentioned p type impurity concentration range, the threshold voltage that suppresses heterojunction type MOS is followed the thickness variation in Si lid zone 24 and the effect height that changes.
Fig. 5 is for heterojunction type MOS, and grid voltage is drawn and accumulated in gate insulating film 12 (SiO by applying grid voltage relatively
2The figure of the peak concentration in the hole in the interface (raceway groove) that the interface (parasitic channel) in)/Si lid zone 24 and Si cover regional 24/SiGe channel region 23.
As shown in Figure 5, (concentration is 1 * 10 having doped N-type impurity
17Atomscm
-3) the existing heterojunction type MOS 100 (chain-dotted line (A)) in Si lid zone 107 in, the number of cavities scope bigger than the number of cavities of parasitic channel in the interface that Si covers regional 24/SiGe channel region 23 of accumulating in is the voltage range A among the figure.On the other hand, in the heterojunction type MOS10 of the present embodiment in the Si lid zone 24 that possesses doping p type impurity in Si lid zone 24, accumulate in number of cavities in the interface that Si covers regional 24/SiGe channel region 23 than the big scope of the number of cavities of parasitic channel along with p type impurity concentration increases to 5 * 10
17Atomscm
-3(solid line (B)), 1 * 10
18Atomscm
-3(dotted line (C)) expands voltage range B, C among the figure successively to.This expression can suppress to become among the existing heterojunction type MOS100 parasitic channel of problem, obtains high actuating force.
Said, by suitably import p type impurity in Si lid zone 24, the threshold voltage that can suppress heterojunction type MOS is followed the change of the thickness variation in Si lid zone 24.Therefore, even in the thickness in Si that processing differences causes lid zone 24, produce under the situation of difference, also can reduce in the same wafer, the threshold value difference between each wafer, between one group.Especially, constitute at the heterojunction type MOS10 that uses a plurality of present embodiments under the situation of integrated circuit, in order further to reduce the threshold voltage difference between each heterojunction type MOS10, preferably to cover regional 24 varied in thickness little for the Si among each heterojunction type MOS10, particularly, preferably less than 10nm.
In addition, also can reduce the threshold voltage of heterojunction type MOS.And can suppress becomes the parasitic channel that has problem among the heterojunction type MOS now, realizes high actuating force.
In addition, in the present embodiment,, the invention is not restricted to this, even also can obtain same effect as the N type raceway groove heterojunction type MOS that oppositely replaces all conductivity types though the P raceway groove heterojunction type MOS that uses SiGe channel region 23 is shown.Promptly, the structure of heterojunction type MOS is so long as to the structure that is present between channel region and the gate insulating film and forms in the semiconductor layer (corresponding to the Si lid zone 24 of present embodiment) of channel region and heterojunction the identical impurity of charge carrier mobile in the suitable conductive doped property and raceway groove, and the threshold voltage that can suppress heterojunction type MOS changes.For example, also available Si
1-XC
XThe channel region that constitutes replaces SiGe channel region 23, uses the Si lid zone of doped N-type impurity, as N raceway groove heterojunction type MOS.In addition, also SiGeC can be used for raceway groove, be doped with the N raceway groove heterojunction type MOS in the Si lid zone of N type impurity, or be doped with the P raceway groove heterojunction type MOS in the Si lid zone of p type impurity as use as use.In addition, also can be used as integrated their CMOS.
(execution mode 2)
Below, the formation of the heterojunction type DTMOS of present embodiment is described.Fig. 6 represents the SiGe layer as channel region, utilizes the cross-sectional configuration of P raceway groove heterojunction type DTMOS60 of the present embodiment of Si/SiGe heterojunction.Fig. 7 is the vertical view of the P raceway groove heterojunction type DTMOS60 of present embodiment.
As shown in Figure 6, the P raceway groove heterojunction type DTMOS60 of present embodiment possesses: P type Si substrate 11, be arranged on the Si substrate 11 by SiO
2The gate insulating film 12 that film (about 6nm) constitutes, by the polysilicon that comprises the high concentration p type impurity constitute, be arranged on the gate electrode 13 on the gate insulating film 12 and be formed on the gate insulating film 12, the sidewall spacer 14 of cover gate electrode 13 sides.
The P raceway groove heterojunction type DTMOS60 of present embodiment shown in Figure 6 before crystalline growth, injects the N type impurity (2 * 10 that imports high concentration to Si substrate 11 tops by ion in advance with regard to its manufacturing process
18Atomscm
-3), form Si layer 15.On this Si layer 15, form epitaxially grown Si layer 16, SiGe layer 17 and Si layer 18 successively by the UHV-CVD method.
In addition, for the P raceway groove heterojunction type DTMOS60 of present embodiment, in Si layer 15, Si layer 16, SiGe layer 17 and Si layer 18, be arranged in the zone of gate electrode 13 both sides, the source region 19 and the drain region 20 that comprise the high concentration p type impurity are set.
In addition, the zone between source region 19 and the drain region 20 constitutes the Si matrix region 21 that comprises high concentration N type impurity in the Si layer 15.With wiring 25 electric short circuit Si matrix regions 21 and gate electrode 13.Particularly, as shown in Figure 7, outside forming the zone of raceway groove, directly connect gate electrode 13 and Si matrix region 21.
The thickness of Si layer 16 is 10nm, SiGe layer 17, is that the thickness of SiGe channel region 23 is 15nm.In addition, the Ge containing ratio in the SiGe channel region 23 is 30%.
From foregoing as can be known, identical based on the structure of heterojunction type MOS shown in the last and above-mentioned execution mode 1, but difference is electric short circuit Si matrix region 21 and gate electrode 13.
In the heterojunction type DTMOS60 of present embodiment, as shown in Figure 6, electric short circuit gate electrode 13 and Si matrix region 21.Therefore, if apply grid bias, then become by Si matrix region 21 and apply the forward bias voltage drop identical with the grid bias size to Si channel region 23 to gate electrode 13.Thereby, when grid bias is ended, become the state identical with common MOS transistor, in addition, when the grid bias conducting, owing to increase, to the Si matrix region 21 of forward setovering, so threshold voltage reduces along with grid bias.Therefore, compare, can under low threshold voltage, move with the DTMOS of existing use Si substrate.
In addition, in the heterojunction type DTMOS60 of present embodiment because can increase the substrate bias coefficient gamma, thus can be bigger threshold value during the reduction action, increase the grid blasting amount of actual effect.As a result, can obtain high conducting electric current.That is, according to heterojunction type DTMOS60, even under low-voltage, also can realize high current driving capability and fast conversion speed.
Fig. 8 represent at the heterojunction type DTMOS of electric short circuit gate electrode 13 among the existing heterojunction type MOS100 and Si matrix region 21 (below be called existing type heterojunction type DTMOS) with for the heterojunction type DTMOS60 of the present embodiment that imports p type impurity in the Si lid zone 24, threshold voltage and Si cover the figure of the dependency relation of area thickness.
Be illustrated among the existing type heterojunction type DTMOS doped N-type impurity in Si lid zone 107, the dependency relation of threshold voltage and Si lid area thickness with chain-dotted line shown in Figure 8 (a).
On the other hand, be illustrated in to have with solid line shown in Figure 8 (b) and mix 5 * 10
17Atomscm
-3Among the present embodiment heterojunction type DTMOS60 in the Si lid zone 24 of left and right sides p type impurity, the dependency relation of the thickness in threshold voltage and Si lid zone 24.As can be seen from Figure 8, in the heterojunction type DTMOS60 of present embodiment, compare with existing type heterojunction type DTMOS, threshold variation diminishes.And (p type impurity concentration is 1 * 10 under the many situations of the p type impurity concentration in Si lid zone 24
18Atomscm
-3: dotted line among Fig. 8 (c)) opposite with the situation (chain-dotted line (a)) of existing heterojunction type DTMOS, the thickness in Si lid zone 24 becomes big, and the absolute value of threshold voltage diminishes.That is threshold voltage step-down.This is because Si covers the high regional thickening of doping content in the zone 24, the current potential step-down of SiGe channel region 23.
In addition, compare with the change of threshold voltage among the heterojunction type MOS10 shown in the above-mentioned execution mode 1, its variable quantity diminishes.Thereby, comparing with the heterojunction type MOS10 of above-mentioned execution mode 1 as can be known, the heterojunction type DTMOS60 of present embodiment is effective to the stabilisation of threshold voltage.In addition, change for the threshold voltage that suppresses heterojunction type DTMOS follows the thickness variation in Si lid zone 24, as long as the p type impurity concentration that comprises in the Si lid zone 24 is 1 * 10
17Atomscm
-3More than get final product.In addition, the p type impurity concentration that comprises in the Si lid zone 24 is preferably 1 * 10
18Atomscm
-3Below.This is because as shown in Figure 8, and in above-mentioned p type impurity concentration range, the threshold voltage that suppresses heterojunction type MOS is followed the thickness variation in Si lid zone 24 and the effect height that changes.
Fig. 9 represents for existing type heterojunction type DTMOS with for the heterojunction type DTMOS60 of the present embodiment that imports p type impurity in the Si lid zone 24, the result of simulation Vg-Id characteristic.Wherein, the thickness in the Si lid zone 24 of the heterojunction type DTMOS60 of the Si of existing type heterojunction type DTMOS lid zone 107 and present embodiment all is 5nm.
Among Fig. 9,, then can reduce threshold voltage as can be known if relatively use the existing type heterojunction type DTMOS of chain-dotted line (a) expression and the heterojunction type DTMOS60 of the present embodiment represented with solid line (b).
Usually, in DTMOS, horizontal parasitic bipolar transistor takes place between P type grid-N mold base (base stage)-drain region, P type source region 19 (emitter) 20 (collector electrodes), after this transistor turns, the matrix electric current that flows through becomes problem in practicality.
But, as shown in Figure 9, between the heterojunction type DTMOS60 of existing type heterojunction type DTMOS and present embodiment, matrix electric current no change.That is, in the heterojunction type DTMOS60 of present embodiment, enlarged the poor of matrix electric current and drain current, can realize expansion by the operation voltage scope of matrix electric current restriction.
Figure 10 is that expression is in order to make existing type heterojunction type DTMOS (the N type impurity concentration of matrix region 21: 2 * 10
18Atomscm
-3) equate with the threshold value of the heterojunction type DTMOS60 of present embodiment, set the N type impurity concentration of the Si matrix region 21 of the heterojunction type DTMOS60 of present embodiment high by (2 * 10
19Atomscm
-3), the figure of the Vg-Id characteristic of each heterojunction type DTMOS.
According to present embodiment,,, can set the impurity concentration of matrix region 21 high in order to reduce threshold value by the p type impurity that in Si lid zone 24, mixes.If the impurity concentration of matrix region 21 uprises, then the inherent potential between source electrode-matrix increases.Therefore, can suppress the matrix electric current that betides in the lateral parasitic bipolar transistor low.That is, realize the expansion of operation voltage scope.And,, then when between source electrode-drain electrode, applying voltage, can suppress to broaden from the depletion layer of source region 19 and drain region 20 if the impurity concentration of matrix region 21 uprises.Therefore, even matrix concentration height also can keep low threshold voltage, the abundant short-channel effect that produces under the short situation of suppressor grid length.In addition, in the present embodiment, though the impurity concentration of Si matrix region 21 is set at 2 * 10
19Atomscm
-3, but if greater than 5 * 10
18Atomscm
-3, also can obtain same effect.
Said, by suitable doping p type impurity in Si lid zone 24, can suppress threshold voltage and follow the thickness variation in Si lid zone and change.Therefore, even produce under the situation of difference, also can reduce in the same wafer at the thickness in Si that processing differences causes lid zone 24, the threshold value difference between each wafer, between one group.Especially, constitute at the heterojunction type DTMOS20 that uses a plurality of present embodiments under the situation of integrated circuit, in order further to reduce the threshold voltage difference between each heterojunction type DTMOS60, it is little that Si among preferred each heterojunction type DTMOS60 covers regional 24 varied in thickness, particularly, preferably less than 10nm.
In addition, by suitable doping p type impurity in Si lid zone 24, also can reduce threshold voltage.
And, can suppress to become in the heterojunction type DTMOS structure matrix electric current of problem, realize wide operation voltage scope, fully suppress short-channel effect.
In addition, in the present embodiment,, the invention is not restricted to this, even also can obtain same effect as the N type raceway groove heterojunction type MOS that oppositely replaces all conductivity types though the P raceway groove heterojunction type DTMOS that uses SiGe channel region 23 is shown.Promptly, the structure of heterojunction type DTMOS is so long as to the structure that is present between channel region and the gate insulating film and forms in the semiconductor layer (corresponding to the Si lid zone 24 of present embodiment) of channel region and heterojunction the identical impurity of charge carrier mobile in the suitable conductive doped property and raceway groove, the heterojunction type DTMOS that the threshold voltage that can be inhibited changes.For example, also available by Si
1-XC
XThe channel region that constitutes replaces SiGe channel region 23, uses the Si lid zone of doped N-type impurity, as N raceway groove heterojunction type DTMOS.In addition, also SiGeC can be used for raceway groove, be doped with the N raceway groove heterojunction type DTMOS in the Si lid zone of N type impurity, or be doped with the P raceway groove heterojunction type DTMOS in the Si lid zone of p type impurity as use as use.In addition, also can be used as integrated their DTMOS of complementary type.
(execution mode 3)
The formation of complementary type heterojunction type MOS is described in the present embodiment.Figure 11 represent with the SiGe layer as channel region, utilize the cross-sectional configuration of complementary type heterojunction type MOS70 of the present embodiment of Si/SiGe heterojunction.
As shown in figure 11, the complementary type heterojunction type MOS70 of present embodiment has: Si layer 15a, by in Si layer 15a, inject embedding oxide-film 15b that methods such as oxonium ion form, be arranged on P raceway groove heterojunction type MOS on the embedding oxide-film 15b (below be called P-heterojunction type MOS) with semiconductor layer 30, be arranged on N raceway groove heterojunction type MOS (hereinafter referred to as N-heterojunction type MOS) the usefulness semiconductor layer 90 on the embedding oxide-film 15b.On semiconductor layer 30, be provided with: by SiO
2The gate insulating film 12 that film (about 6nm) constitutes, by the polysilicon that comprises the high concentration p type impurity constitute, be arranged on the gate electrode 13 on the gate insulating film 12 and be formed on the gate insulating film 12, the sidewall spacer 14 of cover gate electrode 13 sides.In addition, on semiconductor layer 90, be provided with: by SiO
2The gate insulating film 72 that film (about 6nm) constitutes, by the polysilicon that comprises high concentration N type impurity constitute, be arranged on the gate electrode 73 on the gate insulating film 72 and be formed on the gate insulating film 72, the sidewall spacer 74 of cover gate electrode 73 sides.
In the manufacturing process of the complementary type heterojunction type MOS70 of present embodiment, before crystalline growth, inject the N type impurity (2 * 10 that imports high concentrations to P-heterojunction type MOS with semiconductor layer 30 by ion in advance
18Atomscm
-3), form Si layer 15.On Si layer 15, form epitaxially grown Si layer 16, SiGe layer 17 and Si layer 18 successively by the UHV-CVD method.And, in Si layer 15, Si layer 16, SiGe layer 17 and Si layer 18, be arranged in the zone of gate electrode 13 both sides, the source region 19 and the drain region 20 that comprise the high concentration p type impurity are set.
Zone in the Si layer 15 between source region 19 and the drain region 20 constitutes the Si matrix region 21 that comprises high concentration N type impurity.Si layer 16 and SiGe layer 17 arbitrary non-doped layer that all constitutes the N type impurity that undopes under growth (as-grown) state, the zone in Si layer 16 and the SiGe layer 17 between source region 19 and the drain region 20 constitutes Si buffer area 22 that comprises low concentration N type impurity and the SiGe channel region 23 that comprises low concentration N type impurity respectively.Being positioned at zone under the gate insulating film 12 in the Si film 18 constitutes and imports p type impurity (5 * 10
17Atomscm
-3) Si lid zone 24.In addition, gate insulating film 12 forms by thermal oxidation Si layer 18.
In addition, before crystalline growth, also inject the p type impurity (2 * 10 that imports high concentration to N-heterojunction type MOS with semiconductor layer 90 by ion in advance
18Atomscm
-3), form Si layer 75.On this Si layer 75, form epitaxially grown Si layer 76, SiGe layer 77 and Si layer 78 successively by the UHV-CVD method.And, in Si layer 75, Si layer 76, SiGe layer 77 and Si layer 78, be arranged in the zone of gate electrode 73 both sides, the source region 79 and the drain region 80 that comprise high concentration N type impurity are set.
Zone in the Si layer 75 between source region 79 and the drain region 80 constitutes the Si matrix region 81 that comprises the high concentration p type impurity.Si layer 76 and SiGe layer 77 arbitrary non-doped layer that all constitutes the p type impurity that undopes under growth (as-grown) state, the zone in Si layer 76 and the SiGe layer 77 between source region 79 and the drain region 80 constitutes Si buffer area 82 that comprises the low concentration p type impurity and the SiGe zone 83 that comprises the low concentration p type impurity respectively.The zone that is positioned in the Si film 78 under the gate insulating film 72 constitutes Si channel region 84.Especially, the Si channel region 84 of the N-heterojunction type MOS of present embodiment constitutes the non-doped layer of the impurity that undopes under growth (as-grown) state.
As seen from the above description, the complementary type heterojunction type MOS70 of present embodiment possesses: be formed on the SOI substrate, construct essentially identical P-heterojunction type MOS with the heterojunction type MOS10 of above-mentioned execution mode 1; Though be with the essentially identical structure of heterojunction type MOS10 of above-mentioned execution mode 1 but difference is all opposite conductivity type of each one of heterojunction type MOS10 and the N-heterojunction type MOS of doping p type impurity in Si channel region 84 not of replacing.
Below, the manufacture method of the complementary type heterojunction type MOS of present embodiment is described with reference to Figure 12.Figure 12 is the operation sectional view of the complementary type heterojunction type MOS70 manufacture method of expression present embodiment.
At first, in operation shown in Figure 12 (a), prepare the SOI substrate 71 that constitutes by Si layer 15a, embedding oxide-film 15b and Si layer 15c.Then, inject by ion, formation imports concentration to Si layer 15c and is about 2 * 10
18Atomscm
-3The n of impurity
+Si zone (P-heterojunction type MOS zone) and p
+Si zone (N-heterojunction type MOS zone).Then, on Si layer 15c,, form Si layer 16a, SiGe layer 17a and Si layer 18a successively by using the epitaxial growth of UHV-CVD method.At this moment, form each layer, making above-mentioned each layer is non-doped layer, and the thickness of Si layer 16a is 10nm, and the thickness of SiGe layer 17a is 15nm, and the thickness of Si layer 18a is 5nm, and the Ge containing ratio among the SiGe layer 17a is 30%.
Then, in operation shown in Figure 12 (b), on N-heterojunction type MOS zone, pile up Etching mask.Afterwards, as mask, the Si layer 18a importing concentration of injecting to P-heterojunction type MOS zone by ion is about 5 * 10 with Etching mask
17Atomscm
-3P type impurity.
Then, in operation shown in Figure 12 (c), behind the removal Etching mask, on the Si layer 18a in P-heterojunction type MOS zone and N-heterojunction type MOS zone, form gate insulating film 12 and 72 respectively, and form the n that constitutes by the polysilicon that is doped with high concentration N type impurity thereon respectively
+ Type gate electrode 13 and the p that constitutes by the polysilicon of doped with high concentration p type impurity
+Type gate electrode 73.Afterwards, form the sidewall spacer 14 and 74 of cover gate electrode 73 sides.
Then, in operation shown in Figure 12 (d), each gate electrode and each sidewall spacer as mask, by injecting the foreign ion of high concentration, are formed n
+ Type source region 19 and drain region 20 and p
+ Type source region 79 and drain region 80.
Then, by forming groove 86, separate P-heterojunction type MOS zone and N-heterojunction type MOS zone.Thereby, in P-heterojunction type MOS zone, form Si layer 15, Si layer 16, SiGe layer 17 and Si layer 18, in N-heterojunction type MOS zone, form Si layer 75, Si layer 76, SiGe layer 77 and Si layer 78.
At this moment, form in the zone between source region 19 and drain region 20 Si matrix region 21, Si buffer area 22,, SiGe channel region 23 and Si lid zone 24.In addition, form Si matrix region 81, Si buffer area 82, SiGe channel region 83 and Si channel region 84 in the zone between source region 79 and drain region 80.
By the manufacture method of forming by above operation, obtain complementary type heterojunction type MOS70.
By using above-mentioned manufacture method, can simple manufacturing method make the CMOS device that has used high-performance heterojunction type MOS.In addition, for each P-heterojunction type MOS, N-heterojunction type MOS, also can be by connecting gate electrode and Si matrix region, as complementary type heterojunction type DTMOS by the contact.
According to present embodiment, by suitably import p type impurity in the Si of P-heterojunction type MOS lid zone 24, the threshold voltage that can suppress heterojunction type MOS is followed the thickness variation in Si lid zone 24 and is changed.Therefore, even in the thickness in Si that processing differences causes lid zone 24, produce under the situation of difference, can reduce in the same wafer, the threshold value difference between each wafer, between one group.In addition, also can reduce the threshold voltage of P-heterojunction type MOS.And, can suppress to have the parasitic channel that becomes problem among the heterojunction type MOS now, realize high actuating force.
And in the complementary type heterojunction type MOS70 of present embodiment, p type impurity does not mix in the Si channel region 84 of N-heterojunction type MOS.Therefore, can not damage the characteristic of N-heterojunction type MOS.Further be described with Figure 13 (a) with (b).Figure 13 (a) is the figure that can be with distribution of P-heterojunction type MOS when applying grid bias that the complementary type heterojunction type MOS70 of expression present embodiment possesses, and Figure 13 (b) is the figure that can be with distribution of N-heterojunction type MOS when applying grid bias that the complementary type heterojunction type MOS70 of expression present embodiment possesses.
Shown in Figure 13 (a), in P-heterojunction type MOS, in SiGe channel region 23, form raceway groove, move in the hole.
Shown in Figure 13 (b), in N-heterojunction type MOS, in Si channel region 84, form raceway groove, electronics moves.With regard to the manufacture method of above-mentioned complementary type heterojunction type MOS70, in operation shown in Figure 12 (a), import under the situation of p type impurity limit formation the final Si layer 78 that is doped with p type impurity that forms to Si layer 18a limit at mix by the original place (イ Application サ イ チ コ De one ピ Application ダ).Therefore, the valence band of Si channel region 84 becomes the current potential shown in dotted line in (b) that has Figure 13, and threshold voltage rises.
But, in the present embodiment, in operation shown in Figure 12 (a), do not carry out the original place of p type impurity and mix, inject only to the Si layer 18a importing p type impurity that is arranged in P-heterojunction type MOS zone by ion.Therefore, finally do not import p type impurity substantially to Si layer 78.So the valence band of Si channel region 84 becomes the current potential shown in solid line in (b) that has Figure 13.Thereby, owing to the threshold voltage that has suppressed among the N-heterojunction type MOS rises, so do not damage the characteristic of N-heterojunction type MOS basically.
Figure 14 represents that the Ge that Si matrix region 21, Si buffer area 22, SiGe channel region 23 and the Si of the P-heterojunction type MOS that the complementary type heterojunction type MOS of present embodiment has cover in the zone 24 forms and Impurity Distribution.
As shown in figure 14, the concentration of p type impurity is the highest by (5 * 10 in the surface concentration in Si lid zone 24
17Atomscm
-3), along with the degree of depth apart from the surface increases, concentration reduces.
Thus, in the manufacture method of the complementary type heterojunction type MOS of present embodiment,,, p type impurity is positioned at the zone that Si covers regional 24 belows so can arriving because import p type impurity and form Si lid zone 24 by injecting by ion.In case p type impurity arrival is positioned at the zone that Si covers regional 24 belows, then beyond Si covers the interface of regional 24/SiGe channel region 23, cover the zone that move in meeting formation hole in the dark zone (for example the Si buffer area 22), 24 surfaces, zone at distance Si.Therefore, the conducting that is difficult to control by the grid bias that applies to gate electrode 13 drain current ends.That is, the characteristic of P-heterojunction type MOS descends.
Therefore, preferably regulate ion implanting conditions, make p type impurity not arrive Si buffer area 22 as far as possible, in addition, preferably in Si lid zone 24 or SiGe channel region 23, p type impurity concentration become the highest (promptly, in Si lid zone 24 or SiGe channel region 23, the peak value that exists p type impurity to distribute).Especially, preferably in Si lid zone 24, p type impurity concentration becomes the highest, and more preferably as present embodiment, on the surface in Si lid zone 24, concentration becomes the highest.
Thus, according to present embodiment, can not damaged N-heterojunction type MOS characteristic, have the complementary type heterojunction type MOS of high-performance P-heterojunction type MOS.
Utilizability on the industry
The present invention can be used for heterojunction type MOS transistor, heterojunction type DTMOS transistor etc. Hetero-junctions is used in the field-effect transistor of channel region.
Claims (14)
1, a kind of semiconductor device possesses:
Substrate;
Be arranged on the semiconductor layer on described substrate top;
Be arranged on the gate insulating film on described semiconductor layer top;
Be arranged on the gate electrode on the described gate insulating film;
Be arranged on the 1st conductivity type the 1st source-drain electrodes zone of gate electrode both sides described in the described semiconductor layer;
Be arranged on the 1st lid zone that is arranged in the 1st conductivity type interregional zone of described the 1st source-drain electrodes, that constitute by the 1st semiconductor in the described semiconductor layer;
The 1st channel region that is arranged on described in the described semiconductor layer below, the 1st lid zone, constitutes by current potential the 2nd semiconductor also littler that moves charge carrier that can band edge for charge carrier than described the 1st semiconductor; With
Be arranged on the 1st matrix region of the 2nd conductivity type the 1st channel region described in described semiconductor layer below, that constitute by the 3rd semiconductor,
The 1st conductive-type impurity concentration that comprises in described the 1st lid zone is 1 * 10
17Atomscm
-3More than.
2, semiconductor device according to claim 1 is characterized in that:
Described gate electrode is electrically connected with described the 1st matrix region.
3, semiconductor device according to claim 1 is characterized in that:
Described lid zone forms structure depleted when applying grid bias.
4, semiconductor device according to claim 1 is characterized in that:
The 1st conductive-type impurity that mixes in described the 1st lid zone so that with respect to the varied in thickness in described the 1st lid zone, is formed at described the 1st channel region and the described the 1st and covers channel potential in the regional interface in ± 0.05eV scope when zero-bias.
5, semiconductor device according to claim 1 is characterized in that:
The 2nd conductive-type impurity concentration that comprises in described the 1st matrix region is 5 * 10
18Atomscm
-3More than.
6, semiconductor device according to claim 1 is characterized in that:
The thickness in described the 1st lid zone is below 10nm.
7, semiconductor device according to claim 1 is characterized in that:
Described the 1st semiconductor is a silicon.
8, semiconductor device according to claim 7 is characterized in that:
Described the 2nd semiconductor by in silicon and germanium and the carbon any constitutes at least.
9, semiconductor device according to claim 1 is characterized in that: possess:
Be arranged on second half conductor layer on described substrate top;
Be arranged on another gate insulating film on described second half conductor layer;
Be arranged on another gate electrode on described another gate insulating film;
Be arranged on another the 1st source-drain electrodes zone of the 1st conductivity type of another gate electrode both sides described in described second half conductor layer;
Be arranged on another the 1st lid zone that is arranged in the 1st conductivity type interregional zone of described another the 1st source-drain electrodes, that constitute by described the 1st semiconductor in described second half conductor layer;
Another the 1st channel region that is arranged on described in described second half conductor layer another below, the 1st lid zone, constitutes by described the 2nd semiconductor; With
Be arranged on described in described second half conductor layer another the 1st matrix region of the 2nd conductivity type another the 1st channel region below, that constitute by described the 3rd semiconductor.
10, semiconductor device according to claim 1 is characterized in that: also possess:
Be arranged on second half conductor layer on described substrate top;
Be arranged on another gate insulating film on described second half conductor layer;
Be arranged on another gate electrode on described another gate insulating film;
Be arranged on the 2nd source-drain electrodes zone of the 2nd conductivity type of another gate electrode both sides described in described second half conductor layer;
Be arranged on and be arranged in the 2nd channel region interregional zone of described the 2nd source-drain electrodes, that constitute by the 4th semiconductor in described second half conductor layer; With
Be arranged on the 2nd matrix region of the 1st conductivity type the 2nd channel region described in described second half conductor layer below, that constitute by the 5th semiconductor,
As complementary type device performance function.
11, semiconductor device according to claim 10 is characterized in that:
Described the 2nd channel region is the 2nd conductivity type.
12, semiconductor device according to claim 10 is characterized in that:
Described gate electrode and described the 1st matrix region are electrically connected,
Described another gate electrode is electrically connected with described the 2nd matrix region.
13, a kind of manufacture method of semiconductor device comprises:
Operation (a) forms the 1st semiconductor layer on the top of semiconductor substrate, and the 1st semiconductor layer has the 1st semiconductor regions that has imported the 1st conductive-type impurity and imported the 2nd semiconductor regions of the 2nd conductive-type impurity;
Operation (b), the 3rd semiconductor layer that on described the 1st semiconductor layer, forms the 2nd semiconductor layer successively and constitute than the big semiconductor of described the 2nd semiconductor layer by band gap;
Operation (c) is positioned in described the 3rd semiconductor layer on the part of described the 1st semiconductor regions and forms mask, uses described mask, with 1 * 10
17Atomscm
-3The 1st above conductive-type impurity imports the part that is arranged in described the 2nd semiconductor regions in described the 3rd semiconductor layer at least;
Operation (d) after removing described mask, is positioned at the part of described the 1st semiconductor regions and is positioned on the part of described the 2nd semiconductor regions in described the 3rd semiconductor layer, form gate insulating film and gate electrode respectively; With
Operation (e), with described each gate electrode as mask, by implanting impurity ion in described the 1st semiconductor layer, described the 2nd semiconductor layer and described the 3rd semiconductor layer, in described the 1st semiconductor regions, form the 2nd conductive type source-drain region, in described the 2nd semiconductor regions, form the 1st conductive type source-drain region.
14, the manufacture method of semiconductor device according to claim 13 is characterized in that:
In described operation (c), implanting impurity ion makes the maximum of the 1st conductive-type impurity CONCENTRATION DISTRIBUTION be present in described the 2nd semiconductor layer or in described the 3rd semiconductor layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP113437/01 | 2001-04-12 | ||
| JP113437/2001 | 2001-04-12 | ||
| JP2001113437 | 2001-04-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466779A CN1466779A (en) | 2004-01-07 |
| CN1255878C true CN1255878C (en) | 2006-05-10 |
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ID=18964656
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028026772A Expired - Fee Related CN1255878C (en) | 2001-04-12 | 2002-03-27 | Semiconductor device and its manufacturing method |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US6781163B2 (en) |
| EP (1) | EP1378943A4 (en) |
| CN (1) | CN1255878C (en) |
| TW (1) | TW554531B (en) |
| WO (1) | WO2002084744A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7078723B2 (en) * | 2004-04-06 | 2006-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Microelectronic device with depth adjustable sill |
| TWI431771B (en) * | 2004-10-07 | 2014-03-21 | Fairchild Semiconductor | Bandgap engineered mos-gated power transistors |
| JP2006186261A (en) * | 2004-12-28 | 2006-07-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US8659054B2 (en) * | 2010-10-15 | 2014-02-25 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
| US8962417B2 (en) | 2010-10-15 | 2015-02-24 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
| JP6359401B2 (en) * | 2014-09-24 | 2018-07-18 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| KR102307457B1 (en) | 2015-08-05 | 2021-09-29 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| CN106060742A (en) * | 2016-06-08 | 2016-10-26 | 钰太芯微电子科技（上海）有限公司 | Microphone circuit and MOS tube therein |
| CN116344590B (en) * | 2023-05-23 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03187269A (en) * | 1989-12-18 | 1991-08-15 | Hitachi Ltd | Semiconductor device |
| JPH03280437A (en) | 1990-03-29 | 1991-12-11 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH08293557A (en) * | 1995-04-25 | 1996-11-05 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JP2778553B2 (en) | 1995-09-29 | 1998-07-23 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| US6399970B2 (en) * | 1996-09-17 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | FET having a Si/SiGeC heterojunction channel |
| JPH10163342A (en) | 1996-12-04 | 1998-06-19 | Sharp Corp | Semiconductor device |
| JP3443343B2 (en) * | 1997-12-03 | 2003-09-02 | 松下電器産業株式会社 | Semiconductor device |
| WO2000016391A1 (en) * | 1998-09-14 | 2000-03-23 | Matsushita Electric Industrial Co., Ltd. | Method for producing semiconductor device |
| EP1102327B1 (en) * | 1999-11-15 | 2007-10-03 | Matsushita Electric Industrial Co., Ltd. | Field effect semiconductor device |
| US6319799B1 (en) * | 2000-05-09 | 2001-11-20 | Board Of Regents, The University Of Texas System | High mobility heterojunction transistor and method |
-
2002
- 2002-03-27 CN CNB028026772A patent/CN1255878C/en not_active Expired - Fee Related
- 2002-03-27 EP EP02707195A patent/EP1378943A4/en not_active Withdrawn
- 2002-03-27 WO PCT/JP2002/003025 patent/WO2002084744A1/en not_active Application Discontinuation
- 2002-03-27 US US10/311,293 patent/US6781163B2/en not_active Expired - Lifetime
- 2002-04-11 TW TW091107325A patent/TW554531B/en not_active IP Right Cessation
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2004
- 2004-08-09 US US10/913,383 patent/US7084026B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1378943A4 (en) | 2008-04-02 |
| WO2002084744A1 (en) | 2002-10-24 |
| US7084026B2 (en) | 2006-08-01 |
| EP1378943A1 (en) | 2004-01-07 |
| TW554531B (en) | 2003-09-21 |
| US20030190788A1 (en) | 2003-10-09 |
| US6781163B2 (en) | 2004-08-24 |
| CN1466779A (en) | 2004-01-07 |
| US20050017265A1 (en) | 2005-01-27 |
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