CN1242108A - Surface connectable semiconductor bridge elements, devices and methods - Google Patents
Surface connectable semiconductor bridge elements, devices and methods Download PDFInfo
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- CN1242108A CN1242108A CN 97180963 CN97180963A CN1242108A CN 1242108 A CN1242108 A CN 1242108A CN 97180963 CN97180963 CN 97180963 CN 97180963 A CN97180963 A CN 97180963A CN 1242108 A CN1242108 A CN 1242108A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
A semiconductor element, e.g., a semiconductor bridge element (30), is surface mountable as it has thereon a metal layer comprised of metal lands (44) and electrical connectors (45a, 45b and 45c) which terminate in flat electrical contacts (47) on the back surface (35) of the element. Optionally, the element may also contain back-to-back zener diodes (46a, 46b) to provide unbiased protection against electrostatic discharge. When configured as a semiconductor bridge element (30), the element, among other uses, finds use as an igniter (13) for an explosive element. The elements may be made by a method including a cross-cut technique in which grooves (60) cut in the front surface (58) of a silicon wafer substrate (56) intersect grooves (64) cut in the back surface (62) of the wafer. The intersecting grooves (60,64) form a plurality of apertures in the wafer (56), the apertures and grooves helping to define a plurality of dies having side surfaces. A dielectric layer (48) is deposited on the wafer (56) and a polysilicon film (52) is deposited over the dielectric layer (48). A metal layer (44, 45a-45c, and 47) is then deposited on the wafer while it is still intact to provide an electrical connection from the top surface (34) of element (30) along the side surfaces (66a, 66b and 66c, and 68a, 68b and 66c) to the bottom surface (35) to constitute the dies as the semiconductor elements (30). The elements (30) are separated and the electrical contacts (47) of a given element can be mounted directly to a header (36) or the like by soldering, without need for connector wires (14).
Description
Background of invention
Invention field
The device that the present invention relates to semiconductor element and comprise this semiconductor element; described semiconductor element is semiconductor bridge joint element for example; these elements can connect on the surface; and can optionally have and the irrelevant electrostatic discharge (ESD) protection of polarity, the invention still further relates to the method for making this element and device.More particularly, the present invention relates to have from its top surface to basal surface the semiconductor element that extends with conductive coating, realize that by back-to-back Zener diode semiconductor element, the method for making these elements and the manufacturing of electrostatic discharge (ESD) protection comprise the method for the device of these elements.
Correlation technique
Semiconductor bridge joint (" SCB ") element (being sometimes referred to as " chip " here) and the means that are electrically connected these elements for electricity starting purposes are well known in the art.At present, the tungsten bridge SCB element of the SCB element of United States Patent (USP) 4708060 and United States Patent (USP) 4976200 all prepares big metallization solder joint, these solder joints are used to electrically contact the active region of bridging element, here the United States Patent (USP) of quoting 4708060 is to authorize Bickes on November 24th, 1987, Jr. wait the people, United States Patent (USP) 4976200 is to authorize people such as Benson December 11 nineteen ninety.The SCB chip is connected to (base or other element) installation surface with adopting the adhering with epoxy resin material mechanical usually.Then, by wire bonds, promptly be connected to the suitable electric contact of base (leader) from the metallization solder joint of chip by going between, formation is connected with the standard electric at chip top.The proper function of SCB element requires closely to contact with high energy material in detonator, and these high energy materials are such as blast or pyrotechnic material, and this requires chip uprightly to place; That is, chip can not make its active region lean against base location assembling, but its active region must in the face of and contact high energy material so that active region freely interacts with high energy material.
The international monopoly WO94/19661 that authorizes Willis that announced on September 1st, 1994 discloses a kind of conductive layer of coiling, and this conductive layer is by cutting out a groove in wafer, wafer being carried out the bottom of metal-plated, etched wafer and subsequently the metal-plated manufacturing carried out at the back side.The United States Patent (USP) 5080016 that on January 14th, 1992 was authorized Osher discloses a kind of conductor, and this conductor is wound on the electrolyte blocks and occupies its whole rear surface.
Prior art has also proposed to be used to protect the SCB chip to prevent the means of static discharge.The SCB component fabrication of authorizing people's such as Hartman United States Patent (USP) 5179248 on January 12nd, 1993 and authorizing people's such as Hartman United States Patent (USP) 5309841 on May 10th, 1994 has big metallization solder joint, and these solder joints are used to the active region that excites bridging element and provide and electrically contact.These patents also show the application of single Zener diode (with discrete or be integrated in form on the chip), and this diode and SCB element are connected in parallel, to prevent undesirable static discharge (" ESD ") and EMI voltage.
The United States Patent (USP) 5327832 of authorizing Atkeson on July 12nd, 1994 shows inclined to one side (unbiased) discharge prevention of the nothing of three conductor field-effect transistors.The United States Patent (USP) 5500546 that on March 19th, 1996 was authorized Marum discloses a plurality of diodes that are used for electrostatic discharge (ESD) protection.But, these elements are arranged in the discrete control circuit of function circuit.
Therefore, be desirable to provide a kind of SCB element that can the surface connects, this element can easily be made has inherent no inclined to one side esd protection.
Summary of the invention
Generally speaking, the invention provides a kind of semiconductor element, it has the smooth electric contact that is positioned at its rear surface.For example, smooth electric contact can be arranged on the rear surface of SCB element (chip), and it often is used to realize requiring the function of chip vertical orientation.For example, the front surface of some SCB application requirements semiconductor chip closely contacts with the high energy material of volatile or other type, these materials are compacted to be loaded in the holder, and this holder comprises the SCB chip, and this chip is installed and wire bonds to a chip carrier, shell or base.(term " base " is used in the claims represent that element can be electrically connected to any suitable surface or the structure on it.) the present invention contains semiconductor element, these semiconductor elements can comprise simple two lead-in wire or three lead elements and production method thereof, such as semiconductor bridge joint element, diode, capacitor, rectifier and like.
Another total aspect of the present invention is to provide and irrelevant (no inclined to one side) electrostatic discharge (ESD) protection of polarity for semiconductor element by forming the Zener diode that is electrically connected by back-to-back topology.When using with semiconductor bridge joint combination of elements, Zener diode and semiconductive bridge connection circuit are connected in parallel.Semiconductor bridge joint element and Zener diode can prepare on same chip, Zener diode is to be formed on by means of a side metal level on the sidewall of semiconductor chip, this side metal level contacts the type opposite that alloy that this diffusion layer comprises and Semiconductor substrate are comprised with a diffusion layer.
More particularly, according to the present invention, provide a kind of and made the method for a plurality of semiconductor elements by a substrate wafer, described wafer has a front surface and a rear surface.This method may further comprise the steps.On at least one surface of a silicon substrate wafer, apply a dielectric layer, and on dielectric layer deposit one deck polysilicon membrane.In substrate wafer, form a plurality of openings, each opening passes wafer from the front surface of wafer and extends to its rear surface, thereby defined the side surface that extends to the rear surface from the front surface of wafer, the setting of these openings is suitable for cutting out a plurality of matrixs (die) from substrate wafer, and each matrix has a pair of opposed side surface.On the wafer and, so that between front surface and rear surface, forming continuous conductive path on the matrix by side surface by opening metal level of deposit on front surface, rear surface and side surface.Polysilicon membrane and metal level are carried out mask process and etching,, thereby constitute semiconductor element by matrix so that on matrix, form required circuit.Subsequently semiconductor element is separated from each other from the substrate wafer separation and with them.
According to an aspect of the present invention, semiconductor element can comprise semiconductor bridge joint element, and this method also can comprise carries out mask process and etched step to polysilicon membrane and metal level, so that forming the electric contact of at least two separation on the rear surface and form semiconductive bridge connection circuit geometric figure on front surface.
Another aspect of the present invention provides such technical scheme, that is, silicon substrate wafer is to select from be made of p type substrate and n type substrate one group, and further may further comprise the steps.Before the aforesaid metal level of deposit, adopt the selected a kind of alloy that goes out from the group that p type alloy and n type alloy constitute, the side surface of polysilicon membrane and silicon substrate wafer is mixed by following condition.When substrate was p type substrate, polysilicon membrane and side surface mixed with n type alloy; When substrate was n type substrate, polysilicon membrane and side surface mixed with p type alloy.In such a way, being entrained in of polysilicon membrane and side surface formed the back to back diode device between the opposite side surfaces, thereby provides no inclined to one side electrostatic discharge protection for each final semiconductor element.
In another aspect of this invention, form a plurality of openings in the following manner in substrate wafer: the front surface that passes substrate wafer cuts a plurality of first grooves, and the rear surface of passing substrate wafer is along laterally for example along cutting a plurality of second grooves perpendicular to the direction of a plurality of first grooves.A plurality of first and second grooves are cut enough deeply, so that a plurality of first groove and a plurality of second groove intersect mutually, thereby form a plurality of holes at infall, and these holes and associated channels thereof are in conjunction with having defined a plurality of side surfaces.A plurality of first grooves can be parallel to each other and equidistantly cut, and a plurality of second groove can be parallel to each other and equidistantly cut.
One side more of the present invention provides a kind of method, is used for by the metal level on the rear surface being soldered to an electric contact on the base, and semiconductor bridge joint element directly is mounted to base thereby incite somebody to action independently.
According to the present invention, a kind of semiconductor element that can the surface connects also is provided, and it comprises following assembly: a substrate, and it is made by silicon semiconductor material, and have a top surface, basal surface and side surface, at least one surface of this substrate is provided with a dielectric layer; One deck polysilicon membrane, it is arranged on the dielectric layer; With a metal level, it is installed on the polysilicon layer and from top surface and extends to basal surface along side surface, the configuration of polysilicon membrane and metal level is suitable for forming the contact on basal surface, the configuration of these contacts is suitable for direct surface mounted on a base, and promptly they are smooth substantially.
Others of the present invention provide following feature alone or in combination.Aforesaid element can comprise semiconductor bridge joint element, and wherein the configuration of polysilicon membrane and metal level is suitable at least two electric contacts that separate being provided on the rear surface and semiconductive bridge connection circuit geometric figure being provided on front surface; Substrate is to select from be made of p type substrate and n type substrate one group, and the side surface of polysilicon membrane and substrate adopts, and the selected a kind of alloy that goes out mixes one group that constitutes from p type alloy and n type alloy, when substrate comprised p type alloy, polysilicon membrane and side surface mixed with n type alloy; When substrate comprised n type alloy, polysilicon membrane and side surface mixed with p type alloy, formed the back to back diode device thus between opposite side surfaces, thereby provided no inclined to one side electrostatic discharge protection for semiconductor element.
Others of the present invention provide following feature: the resistivity of substrate is about 0.01-10 Ω-cm, and dielectric layer thickness is about 0.2-1 micron, and the thickness of polysilicon membrane is about 1-3 micron.
Other aspect of the present invention provides following feature: aforesaid semiconductor element combines with a base with electric contact, wherein, by the contact on the basal surface of this element being soldered to the contact of base, makes this element direct surface mounted on base.
In one aspect of the invention, semiconductor element can form the part of an explosive element, and its bridgt circuit geometric figure is configured to contact with a kind of explosive material.
The present invention also provides the semiconductor element of making according to said method.
Others of the present invention are disclosed in the following description.
The accompanying drawing summary
Fig. 1 is the profile of the blast igniter of prior art, and this igniter comprises the semiconductor bridge joint element igniter of prior art;
Fig. 2 is the electrical structure schematic diagram of amplification of the semiconductor bridge joint element igniter of prior art shown in Figure 1;
Fig. 3 is the profile of blast igniter according to an embodiment of the invention, and this igniter comprises a semiconductor bridge joint element that can the surface connects with as igniter, and this element has the diode that no inclined to one side electrostatic discharge (ESD) protection is provided;
Fig. 4 is the electrical structure schematic diagram of the semiconductor bridge joint element that can the surface connects shown in Figure 3;
Fig. 4 A is the circuit diagram of the diode of element shown in Figure 4;
Fig. 5 is the top view of the silicon wafer of cross-cut according to an aspect of the present invention, and state shown in this figure is the primary stage of being made semiconductor element by wafer;
Fig. 5 A is the bottom view of the wafer of Fig. 5;
Fig. 5 B is the end view of the wafer of Fig. 5;
Fig. 5 C is the partial sectional view with respect to Fig. 5 B amplification along the line C-C intercepting of Fig. 5 B;
Fig. 6 is the top plan view of the semiconductor bridge joint element that according to an embodiment of the invention can the surface connects;
Fig. 6 A, 6B and 6C are respectively the cutaway views along line A-A, the B-B of Fig. 6 and C-C intercepting;
Fig. 6 D is the stereogram of top surface of the semiconductor bridge joint element of Fig. 6; And
Fig. 6 E is the stereogram of basal surface of the semiconductor bridge joint element of Fig. 6.
The detailed description of the present invention and specific embodiments thereof
The semiconductor chip structure that the present invention has exempted prior art is the wire bonds and the matrix solder technology of semiconductor device or element, with regard to its character, these Technology Needs use specialized apparatus, instrument, binding agent and epoxide resin material so that semiconductor chip is mounted to shell, shell subsequently must be processed on the wire bonds platform, so that form being electrically connected of lead and chip and shell.For the element that can the surface connects, SCB element for example of the present invention is mounted to required adhesive special of shell and epoxide resin material and their corresponding cure cycles with chip and is exempted.Replace, be used than wire bonds and simpler, the easier and more cheap standard circumfluence solder technology of matrix welding, thereby high-intensity and more economical electrical connection is provided.The present invention can be applied to multiple semiconductor element, comprises two-terminal and three terminal components, such as SCB element, diode, capacitor, rectifier and like.The method of the semiconductor element SCB element for example of the present invention that manufacturing can the surface connects comprises makes element have electric contact, and these electric contacts can connect from the rear surface of semiconductor element.Method of the present invention has guaranteed to make this electric contact to produce (wafer) level in enormous quantities, has reduced cost thus, saved the time and has reduced the manufacturing of semiconductor element and the complexity of finally assembling.In addition, just as understood by the skilled person in the art, the technology integrated (by wafer-level) of the element that can the surface connects can more easily realize.
The present invention also provides semiconductor element, for example SCB chip that does not have the protection of inclined to one side static discharge Zener diode, and it has the electric contact that is connected to its dorsal part, and increases chip area for holding electric contact not needing to resemble in the structure of prior art.
For the range of application of broad, comprise that the application that is not easy to adapt to wire bonds, the present invention also provide the superiority that is electrically connected the semiconductor element aspect.For example, the SCB chip that can the surface connects according to the present invention can directly be assemblied in any flat hard or even softer surface on, have on the base of dark and narrow cavity, on the flexible circuit, on the down-lead bracket and on many more complicated shells; Since physics, mechanically and restriction hot property, these supporting structures be unsuitable for chips welding to it on or the employing prior art can only be extremely difficultly with chips welding on it.
The semiconductor element that can the surface connects of the present invention also on very big area, is generally 1 square millimeter of (mm
2) or bigger area on, between the uppermost metal level of the active region of semiconductor element and element, provide very little maximum height or thickness (good flatness), its value is approximately the 1-3 micron.This use of having exempted welding lead realizes, the thickness of welding lead is generally equal to or greater than 0.005 inch (about 125 microns).Above the active region of bridging element, lead presents usually and is at least the curved around height of conductor thickness twice.
One of design structure of semiconductor element of the present invention is as the SCB element, and it is mainly used is a part that is used as the igniter of explosive element.As known in those skilled in the art, the SCB element can be used as the igniter of explosive element, and demonstrates fail safe and the reliability more superior than the hot wire fuse lighter of routine.By making electric current the flow through lead-in wire 12 of the element of prior art shown in Fig. 1 or the lead-in wire 32 of the embodiment of the invention shown in Fig. 3 of flowing through, active region is (in the element of the prior art of Fig. 1 with 22 expressions, represent with 42a in the embodiments of figure 3) will produce plasma discharge, this discharge is enough to correspondingly make the blast load 20 of the prior art element shown in Fig. 1 or the embodiment shown in Fig. 3 load 40 igniting of exploding. Blast load 20 and 40 can be any suitable high energy material, for example, and blast material, perhaps other suitable explosive material such as lead azide.
Because it is evenness that structure of the present invention provides good flatness, do not insert and put under the situation of any structure such as the connection wire loop between SCB element and blast load, the high energy material of forms such as powder, thin slice, bead can closely contact with the active region of SCB element.This is very important, because blast load 20 (Fig. 1) or 40 (Fig. 3) normally compress active region 22 (Fig. 1) or 42a (Fig. 3) with high pressure, described pressure is several kips per square inch.The present invention eliminated in any standard SCB element igniter one of fault cause that all exists, has been lead itself (representing with 14 in prior art structure shown in Figure 1), in this high-pressure powder pressing process, and the possibility that this lead has fluffing or ruptures.The semiconductor bridge joint element of the prior art of a this part that is used as demolition point firearm A is shown among Fig. 1, and wherein SCB element 10 is connected to lead-in wire 12 by lead 14.SCB element 10 is fixed to base 16 by epoxide resin material 18.Base 16 contains blast load 20, and blast load 20 contacts with the active region 22 of SCB element 10.Fig. 2 shows the SCB element 10 of prior art, and it has metal bond district (land) 24.The circuit that schematically draws among Fig. 2 demonstrates the electric effect that the substrate of SCB element 10 suitably mixes, and this doping is in order to form a diode that is connected between each bonding land 24, and this diode is with in parallel by the resistance of active region 22 generations of SCB element 10.This known structure only 12 just can provide electrostatic discharge (ESD) protection when suitable polarity is connected at SCB element 10 by going between.
Fig. 3 demonstrates the SCB element 30 that can the surface connects according to an embodiment of the invention.SCB element 30 also is provided with no inclined to one side electrostatic discharge protection according to a particular aspect of the invention, and illustrated be a part used as demolition point firearm B, wherein by pad 38, SCB element 30 is mounted to the lead-in wire 32 that i.e. surface is connected to base 36.A blast load 40 contacts with active region 42a, and the latter forms in the gap between each bonding land 44.As appreciable from Fig. 4, SCB element 30 comprises a silicon dioxide layer 48, and this layer is arranged on the silicon substrate 50 of a p type.One deck polysilicon membrane 52 is arranged on the subregion of silicon dioxide layer 48.On each side of SCB element 30, impurity 54 is introduced in the silicon substrate 50 of p type.(in the embodiment of a conversion, substrate 50 can be the silicon substrate of n type, and impurity 54 can be the impurity of p type.) metal bond district 44 extends along the outer top surface of substrate 50, and be connected to the contact zone 47 that is positioned on substrate 50 rear surfaces by electric connector 45a.Impurity 54 near bonding land 44 has formed back to back diode 46a and 46b, and they provide no inclined to one side electrostatic discharge (ESD) protection for SCB element 30.In other words, regardless of the polarity that is connected to lead-in wire 32, SCB element 30 includes electrostatic discharge (ESD) protection.The electrostatic discharge (ESD) protection that is provided by back to back diode is not all to need in each case, but to little semiconductor element provide the protection and be in the application such as the ignition of explosive material, this additional protection is necessary.
Fig. 4 A demonstrates the circuit diagram with Fig. 4 of the structurally associated of SCB element 30, and wherein back to back diode 46a and 46b are connected in parallel to the resistance that is formed by active region 42a.When by lead-in wire 32 during to SCB element 30 service voltages, the major part of electric current will flow through the active region 42a of SCB element 30 during beginning, reach its intrinsic puncture voltage up to diode, and electric current will flow through Zener diode 46a, 46b this moment.The very high voltage peak that is run into for as static discharge the time, Zener diode 46a, 46b will puncture and shunt the electric current of flowing through, and reduce the magnitude of current through the active region 42a of SCB element 30 thus.
The circuit that is used for semiconductor bridge joint element of the present invention is to adopt standard techniques to be made by the silicon substrate of standard, and the silicon substrate of described standard is referred to as wafer or wafer substrates.Although silicon substrate does not have preferred crystal orientation, base substrate concentration is preferably in 10
14-10
18Cm
3Scope in, and select suitable doping impurity for use, with the resistance of separate substrate, as described below.
Then, this manufacturing process is: form active element or circuit as follows on silicon substrate, that is, electrically contact solder joint or layer and extend continuously from a side to the opposite side of chip.Although surface mounting technology of the present invention is applicable to many circuit or component structure, such as diode, triode, resistor, capacitor and any other discrete semiconductor component with two or three terminals, but for ease of describing, following discussion is carried out with reference to the SCB element.The SCB technology depends on the utilization of film (monocrystalline and polysilicon), and these films are by dielectric layer or non-conductive layer and its substrate electric insulation.
According to the present invention, the manufacturing of the SCB element that can the surface connects can be for example from the high resistivity of the p type (silicon substrate of 0.01-10 Ω-cm), the front surface of this substrate and rear surface coating dielectric layer, dielectric layer thickness is generally the 0.2-1.0 micron, by well known to a person skilled in the art deposition techniques one deck polysilicon membrane, the thickness of this deposition film is generally the 1.0-3.0 micron on it.For example, the polysilicon membrane deposit can realize by the low pressure chemical vapor deposition of polysilicon on silica membrane, and silica membrane is heat growth on silicon substrate in controlled oxygen-vapour atmosphere at high temperature.
After this, silicon substrate will stand hole, groove or raceway groove and form technology, and is as described below.In one approach, can on the select location of substrate, carry out laser drill, bore pair of holes at least for each element on the wafer.In another approach, can also adopt at least one groove to separate two adjacent elements in the chemical etching of carrying out groove on the silicon substrate on the select location of wafer.In another approach, can increase groove and tape in the following manner: saw chip, only form otch in one direction, and all cutting routes all be connect but not all cutting route all intersect, thereby define a parallel tape array that supports by the peripheral part of wafer.
In a kind of method for optimizing according to one aspect of the invention, saw technology is used for cutting out opening in wafer substrates, defined the area that is used to form matrix between these openings, these matrixs are cut from wafer after forming required circuit thereon, so that form a plurality of semiconductor elements by the single wafer substrate.Formed square through hole (these through holes pass the entire depth and any coating on it of wafer) according to cutting technique of the present invention from the front surface of wafer to the rear surface.Through hole forms by cut wafer on front surface and top, rear surface, the front surface otch along laterally, for example perpendicular to the rear surface incision extension.Two kinds of otch are all enough dark, and for example each otch can extend beyond a half thickness of wafer, so that form square opening at their infall, and provide a plurality of front surfaces from wafer to extend to the passage of rear surface thus.The otch of rear surface and front surface or groove are all done enough widely, so that after this can adopt thin cast-cutting saw that semiconductor element cutting and separating from the wafer is got off, this will make the sidewall that is formed by initial front surface and rear surface otch be kept perfectly harmless.
Referring now to Fig. 5,5A, 5B and 5C, wherein demonstrate a wafer substrates 56 in schematic form, and for describing convenience, thickness amplifies greatly.Fig. 5 demonstrates front surface 58 with plane graph, wherein is cut with one group of parallel equally spaced front surface groove 60.As seeing among Fig. 5 B, front surface groove 60 extends half just over the depth d of wafer substrates 56.Fig. 5 A demonstrates the rear surface 62 of wafer substrates 56, wherein is formed with one group of parallel equally spaced rear surface groove 64.As being clear that among Fig. 5 C, the degree of depth of rear surface groove 64 is substantially equal to front surface groove 60, and extends just over the depth d of wafer substrates 56 half.
The intersection of front surface groove 60 and rear surface groove 64 causes forming a plurality of square aperture (unnumbered) by the crosspoint of each groove, and provides path defining the wall 60a of front surface groove 60 (only showing one of them in Fig. 5 C) and define between the wall 64a of rear surface groove 64.The each several part of wall 60a, 64a comprises the side surface (being respectively 66a-66c and 68a-68b among Fig. 6 D and 6E) of the element that plan cuts down from wafer substrates 56.Therefore, for gaseous reactant provides a flow path, shown in unnumbered curved arrow among Fig. 5 C, described gaseous reactant is used in the gaseous state thermal diffusion process being mixed in the wall of front surface 58, front surface groove 60, the wall and the rear surface 62 of rear surface groove 64.
When thermal diffusion process and required other processing step finished, the whole thickness that the sawing mouth passes wafer substrates 56 extended, thereby forms a plurality of matrixs, has formed suitable SCB circuit on these matrixs, so that a plurality of SCB elements are provided.By adopting illustrated technology, wafer substrates 56 has been kept its physical integrity, and processing step can be implemented on entire wafer.
When requiring to form back-to-back Zener diode on matrix, preferably by after the formation of the cross-cut technology shown in Fig. 5-5C opening, the silicon substrate that p mixes will stand n type gaseous state thermal diffusion process, for example uses phosphorus oxychloride therein.During at high temperature with oxygen of supplying with in suitable ratio and nitrogen reaction, phosphorus oxychloride provides the source of the gas of phosphorus impurities.The flow path of phosphorus oxychloride is shown in unnumbered curved arrow among Fig. 5 C, as mentioned above.Thus, the final side surface of the front of each matrix on the wafer and back side polysilicon layer and silicon substrate is mixed by the gaseous state diffusion technology.The use of gaseous state diffusion technology is that to set up continuous conductive path from front surface to rear surface needed, and the formation of this conductive path is to realize by means of the side surface that passes the hole that forms, raceway groove or groove in the wafer.It will also be appreciated that, by mixing with the side surface of n type impurity to the silicon matrix, electricity between two opposing sidewalls of each matrix is isolated and is able to realize by defining back to back diode that (when adopting the silicon substrate of p type as mentioned above), back to back diode can be used as prevents that the SCB element that can the surface connects from producing the electric device of static discharge effect.
In another aspect of this invention, the electricity that can also adopt n type silicon substrate and p type gaseous state thermal diffusion process to form between two opposing sidewalls of each matrix is isolated.This is to realize by the back-to-back Zener diode that intrinsic is provided, to prevent and can produce the static discharge effect by the surperficial SCB element that connects.
According to another embodiment of the present invention, silicon substrate and doping source of the gas can be chosen as same type, i.e. p type or n type are to provide front surface and the rear surface required continuous conductive path that connects matrix.But, electricity between two opposite flanks of each matrix is isolated then not realization (back to back diode does not form in such a way), because only obtained a simple resistive path, under suitable condition, according to the doped level of original silicon substrate, this resistive path can intend being designed to very high resistance.Those skilled in the art is that this latter event can not provide the element of anti-electrostatic-discharge with accessible.
In either case, removing the unnecessary alloy (being phosphorosilicate glass or PSG) left in the diffusion technology with buffered oxide etching solution afterwards, by any suitable standard deposition technology, technology such as thermal evaporation, sputter for example, the first metal layer that deposit is made of aluminium, tungsten or any other suitable metal on the front surface of polycrystalline silicon wafer and rear surface.In the metal deposition process, wafer rotates in a planet-shaped system, so that metals deposited is wanted in big as far as possible being exposed to of the surf zone of wafer.This rotation effect helps to overcome by " shade " of near the structure projection influence to the metal deposit, and helps lend some impetus to form thick and even metal coating on the sidewall of substrate.The width of groove and raceway groove and the diameter in hole can influence the quality of side metal level.
With accessible,, adopt tungsten, aluminium, copper or metalloid to make wafer metallization as those skilled in the art, so just can exempt the needs of rotation wafer, because realized more consistent deposit if use the chemical vapor deposition technology.
Well known to a person skilled in the art that photoetching technique and custom-designed photocopy are used to image transfer to the selection area of silicon substrate, to form a mask, this mask protects those selected zones not to be subjected to the corrosion of chemical etchant.Implement etching and cleaning technique subsequently, so that on silicon substrate, define particular geometric shapes.More particularly, implement the etching and the cleaning of aluminium and polysilicon, so that on the front surface of wafer, define the geometric figure of SCB element and separating metal contact on the rear surface.In the aluminium on front surface and the etching process of polysilicon, the rear surface of wafer protected (for example adopting photoresist) avoids the influence of chemical etchant, and vice versa.
When metal level comprised aluminium, the heat treatment of wafer was carried out in blanket of nitrogen 30 minutes at 450 ℃, so that to aluminum metal-interface annealing, thereby guaranteed low contact resistance and metal-semiconductor suitably bonding.
Implement the 3rd lithography step, to adopt photoresist to shelter the aluminium on the wafer rear surface and polysilicon is etched and those zones of cleaning.When photoresist mask is in place, by thermal evaporation, sputter, plating, brushing or any other appropriate technology, on the rear surface of wafer, lay second metal level of adequate thickness, it is the material that is fit to welding, for example silver, nickel, tin, gold, copper etc., thickness is generally the 1-10 micron.More particularly, titanium of deposit-Jin layer on the SCB element that can the surface connects of one embodiment of the invention, wherein the thickness of Ti is about 300 dusts, and the thickness of gold is 1.0 microns.Titanium plays the effect of the adhesive linkage between aluminium and the gold layer, strengthens the adhesion properties of golden film and the heat transfer efficiency in the raising welding procedure thus.In the process that this second metal level is deposited on the rear surface, the front surface of wafer (wherein having defined the active region of SCB element) for example adopts photoresist protection, is deposited on bridge areas as there to avoid metal.
The removal of photoresist mask is adopted and is peeled off (lift-off) technology and carry out, and this technology is removed the metal on it.In such a way, titanium-Jin layer is only stayed on previously described aluminium/polysilicon solder joint.
Wafer is received on the electrical testing platform subsequently, checks the resistance of each SCB element at this.The face shaping of matrix also will be observed at microscopically.Electrical testing and the bad matrix of observation discovery are labeled and go out of use subsequently.
At last, use the cast-cutting saw cut crystal, this cast-cutting saw is thinner than the saw of cutting front surface groove 60 and 64 uses of rear surface groove, so that separate each SCB element and these SCB elements are separated from each other from wafer.When this time cutting, cut will pass completely through wafer, so that separate each row and column matrix that the position by the hole is as previously described defined.
Fig. 6-6E depicts the SCB element 30 shown in Fig. 4 in more detailed mode.As shown in Fig. 6-6E, SCB element 30 is above-mentionedly to make a typical products of the technology of a plurality of silicon semiconductor elements by a wafer shown in Fig. 5-5C.The assembly of the SCB element 30 shown in Fig. 4 uses same numeral in Fig. 6-6E, and no longer repeat specification.
Fig. 6 is the plane graph of the top surface 34 of SCB element 30, and Fig. 6 D is the stereogram of the top surface 34 of SCB element 30; Fig. 6 E demonstrates the basal surface 35 of SCB element 30.SCB element 30 comprises a non-conductive substrate 50, and as known in the field, substrate 50 can comprise any suitable non-conducting material, and can comprise monocrystalline substrate.Just as the R.W.Bickes that for example mentions in front, described in people's such as Jr. the United States Patent (USP) 4708060, the metallization bonding land 44 that forms in the structure shown in Fig. 6 and the 6D is covered with a kind of semi-conducting material, for example heavily doped Si semiconductor 42.The latter is arranged on the substrate 50 with " arc " structure, the solder joint (being covered by metal bond district 44) that this " arc " structure comprises two large surface areas and bridge that is connected these two big solder joints or active layer 42a.The sequence number that similar structure is shown in people such as Bernardo Martinez-Tovar is that the name of this application is called " semiconductor bridge joint element and manufacture method thereof " (" Semiconductor Bridge Element and Method of Making the same ") in 08/644008 the common pending application application.
When a current potential is applied on the bonding land 44, active region 42a on the semiconductor layer 42 becomes conduction, and when the electric current of sufficient intensity applies sufficiently long time, active region 42a breaks out with the formation of plasma, this will play the effect that a thermal source is provided, and this thermal source is used for for example igniting and contacts the explosive material of filling with active region 42a.As what can be clear that from Fig. 6 A, 6B, 6D and 6E, SCB element 30 is ladder-type structure in the side.This ladder-type structure is due to the fact that and causes: SCB element 30 is by the preparation of the method shown in Fig. 5-5C, wherein front surface groove 60 and rear surface groove 64 adopt the cast-cutting saw cutting, and this cast-cutting saw is than wide for separating the employed cast-cutting saw of each SCB element subsequently.Thus, in Fig. 5 B, thin cast-cutting saw is placed in along the centre position of the width of front surface groove 60, for example along the C-C line among Fig. 5 B, to cut wafer and to isolate each semiconductor element from it.Along the corresponding thin blade otch of each formation in front surface groove 60 and the rear surface groove 64, thereby isolate each semiconductor element and they are separated from each other from wafer substrates 56.As mentioned above, because front surface groove 60 and rear surface groove 64 intersect mutually, in wafer substrates 56, formed through hole or hole (unnumbered), and they provide the path that is used for depositing metal and alloy.Therefore, when deposit (such as chemical vapor deposition) was used to form the metal in metal bond district 44, metal also is deposited on side surface 66a, 66b and 66c goes up (Fig. 6 E).Can see that side surface 66b is faying surface or the projection between side surface 66a and the 66c.Side surface 66b is the longitudinal component of the bottom of a front surface groove or rear surface groove, and side surface 66c is formed by thin cast-cutting saw cutting.
A similar technological process causes forming the ladder-type structure of side surface 68a, 68b and 68c, and these side surfaces extend perpendicular to side surface 66a, 66b and 66c.(in Fig. 6 D and 6E, for ease of showing, the fraction that covers the metal level of side surface is cut open)
Through hole that in wafer substrates 56, forms or hole (Fig. 5-5C) provide by for example path of chemical vapor deposition process depositing metal, as shown in Fig. 5 C, so forming the metal level of bonding land 44 extends continuously, thereby formed electric connector 45a, 45b and 45c, they play the effect (Fig. 6 E) that connects metal bond district 44 and contact zone 47.In Fig. 6 D and 6E, connector 45a and 45b are with shown in the mode of partly cut-away, so that demonstrate the part of sidewall 68a and 68b.Contact zone 47 is covered by one deck weld metal 49, so that effective welding of 30 pairs of bases 36 of SCB element to be provided, as shown in Figure 3.
Can see, a continuous metal level provides bonding land 44, connector 45a, 45b and 45c and contact zone 47, a continuous conductive path is provided on SCB element 30 thus, this path from front surface 34 along side surface 66a, 66b and 66c and 68a, 68b and 68c extend to rear surface 35.Optionally the final structure of the flat surface contact zone 47 that is covered by a thin weld metal layers 49 provides electric contact, the size of electric contact and configuration be suitable for by be directly installed in the mode shown in Fig. 3 on the base, welding or otherwise be connected to electric contact and be electrically connected, wherein pad 38 is connected to electrical lead 32 with the rear surface of SCB element 30.
Although with reference to specific embodiment the present invention is described in detail, be that many versions still will fall into the scope of claims with accessible.
Claims (19)
1. make the method for a plurality of semiconductor elements by a substrate wafer for one kind, described wafer has a front surface and a rear surface, and this method may further comprise the steps:
(a) at least one surface of a silicon substrate wafer, apply a dielectric layer;
(b) deposit one deck polysilicon membrane on dielectric layer;
(c) in substrate wafer, form a plurality of openings, these openings pass wafer from the front surface of wafer and extend to its rear surface, thereby defined the side surface that extends to the rear surface from the front surface of wafer, the setting of these openings is suitable for cutting out a plurality of matrixs from substrate wafer, and each matrix has a pair of opposed side surface;
(d) on the wafer and, so that between front surface and rear surface, forming continuous conductive path on the matrix by side surface by opening metal level of deposit on front surface, rear surface and side surface;
(e) polysilicon membrane and metal level are carried out mask and etching,, thereby constitute semiconductor element by matrix so that on matrix, form required circuit; With
(f) semiconductor element is separated from each other from the substrate wafer separation and with each semiconductor element.
2. according to the method for claim 1, it is characterized in that, semiconductor element comprises semiconductor bridge joint element, and step (e) comprises carries out mask and etching to polysilicon membrane and metal level, so that forming the electric contact of at least two separation on the rear surface and form a semiconductive bridge connection circuit geometric figure on front surface.
3. according to the method for claim 1 or 2, it is characterized in that silicon substrate wafer is to select, and may further comprise the steps from be made of p type substrate and n type substrate one group:
(g) before the deposited metal of step (d), adopt the selected a kind of alloy that goes out a group that constitutes from p type alloy and n type alloy that the side surface of polysilicon membrane and silicon substrate wafer is mixed; When substrate comprises p type substrate; polysilicon membrane and side surface mix with n type alloy; when substrate comprises n type substrate; polysilicon membrane and side surface mix with p type alloy; being entrained between the opposite side surfaces of polysilicon membrane and side surface forms the back to back diode device thus, thereby provides no inclined to one side electrostatic discharge protection for each semiconductor element.
4. according to the method for claim 1 or 2, comprise and form a plurality of openings in the following manner in substrate wafer: the front surface that passes substrate wafer cuts a plurality of first grooves, and a plurality of second grooves are cut in the rear surface of passing substrate wafer, the direction of this second groove is perpendicular to a plurality of first grooves, a plurality of first and second grooves are cut enough deeply, so that a plurality of first grooves and a plurality of second groove intersect mutually, the place forms a plurality of holes in the crosspoint, and these holes and associated channels thereof combine and defined a plurality of side surfaces.
5. according to the method for claim 4, comprise a plurality of first grooves of (i) cutting, these first grooves are parallel to each other and equidistantly; (ii) cut a plurality of second grooves, these second grooves are parallel to each other and equidistantly; (iii) cut a plurality of first grooves perpendicular to a plurality of second grooves.
6. make the method for a plurality of semiconductor bridge joint elements by a silicon substrate wafer for one kind, described substrate wafer be select one group that constitutes from p type substrate and n type substrate and have a front surface and a rear surface, this method may further comprise the steps:
(a) at least one surface of silicon substrate wafer, apply a dielectric layer;
(b) deposit one deck polysilicon membrane on dielectric layer;
(c) in substrate wafer, form a plurality of openings, these openings pass wafer from the front surface of wafer and extend to its rear surface, thereby defined the side surface that extends to the rear surface from the front surface of wafer, the setting of these openings is suitable for cutting out a plurality of matrixs from substrate wafer, and each matrix has a pair of opposed side surface;
(d) employing comes the side surface of polysilicon membrane and silicon substrate is mixed with the opposite polarity alloy of wafer, so that between opposite side surfaces, form the back to back diode device, provide no inclined to one side electrostatic discharge protection for each final semiconductor bridge joint element thus;
(e) metal level of deposit on front surface, rear surface and side surface so that forming continuous conductive path on the matrix by side surface between front surface and rear surface, thereby makes matrix constitute semiconductor bridge joint element; With
(f) semiconductor bridge joint element is separated and each semiconductive bridge is connect element from substrate wafer be separated from each other.
7. according to the method for claim 2 or 6, may further comprise the steps: by the metal level on the rear surface being soldered to an electric contact on the base, thereby each semiconductive bridge is connect the element direct surface mounted to base.
8. according to claim 1,2 or 6 method, it is characterized in that silicon substrate comprises p type substrate, and polysilicon membrane and side surface mix with n type alloy.
9. according to claim 1,2 or 6 method, it is characterized in that silicon substrate comprises n type substrate, and polysilicon membrane and side surface mix with p type alloy.
10. semiconductor element that can the surface connects comprises:
(a) substrate, it is made by silicon semiconductor material, and it has a top surface, basal surface and side surface;
(b) dielectric layer, it is arranged at least one surface of substrate;
(c) one deck polysilicon membrane, it is arranged on the dielectric layer; With
(d) metal level, it is installed on the polysilicon layer and from top surface and extends to basal surface along side surface, and the configuration of metal level is suitable for forming the contact on basal surface, and the configuration of these contacts is suitable for direct surface mounted on a base.
11. according to the element of claim 10, comprise a semiconductor bridge joint element, wherein the configuration of polysilicon membrane and metal level is suitable at least two electric contacts that separate being provided on the rear surface and a semiconductive bridge connection circuit geometric figure being provided on front surface.
12. element according to claim 10 or 11, it is characterized in that, substrate is to select from be made of p type substrate and n type substrate one group, and the side surface of polysilicon membrane and substrate adopts a kind of alloy of selecting one group that is constituted from p type alloy and n type alloy to mix; When substrate comprises p type alloy; polysilicon membrane and side surface mix with n type alloy; when substrate comprises n type alloy; polysilicon membrane and side surface mix with p type alloy; between different side surfaces, form the back to back diode device thus, thereby provide no inclined to one side electrostatic discharge protection for semiconductor element.
13. the element according to claim 12 is characterized in that, silicon substrate comprises p type silicon substrate, and polysilicon membrane and side surface n type alloy doping.
14. the element according to claim 12 is characterized in that, silicon substrate comprises n type silicon substrate, and polysilicon membrane and side surface p type alloy doping.
15. the element according to claim 10 or 11 is characterized in that, the resistivity of substrate is about 0.01-10 Ω-cm, and dielectric layer thickness is about 0.2-1 micron, and the thickness of polysilicon membrane is about 1-3 micron.
16. according to the element of claim 10 or 11, it is used in combination with a base with electric contact, wherein, by the contact on the basal surface of this element being soldered to the electric contact of base, makes this element direct surface mounted on base.
17. the element according to claim 11 is characterized in that, it forms the part of an explosive element, and its bridgt circuit geometric figure is configured to contact with a kind of explosive material.
18. element according to claim 10 or 11, it is to be made by the part of a plurality of this semiconductor elements of a substrate wafer manufacturing by conduct, substrate wafer has a front surface and a rear surface, and these elements are to be made by a kind of method that may further comprise the steps:
(a) at least one surface of a silicon substrate wafer, apply a dielectric layer;
(b) deposit one deck polysilicon membrane on dielectric layer;
(c) in substrate wafer, form a plurality of openings, these openings pass wafer from the front surface of wafer and extend to its rear surface, thereby defined the side surface that extends to the rear surface from the front surface of wafer, the setting of these openings is suitable for cutting out a plurality of matrixs from substrate wafer, and each matrix has a pair of opposed side surface;
(d),, thereby constitute semiconductor element by matrix so that between front surface and rear surface, forming continuous conductive path on the matrix by side surface on the wafer and by opening metal level of deposit on front surface, rear surface and side surface;
(e) polysilicon membrane and metal level are carried out mask and etching, so that on basal surface, form the contact; With
(f) semiconductor element is separated from each other from the substrate wafer separation and with each semiconductor element.
19. element according to claim 18, comprise a semiconductor bridge joint element, it is made by described method, wherein step (e) comprises polysilicon membrane and metal level is carried out mask and etching, so that forming the electric contact of at least two separation on the rear surface and form a semiconductor bridge joint element geometric figure on front surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97180963 CN1242108A (en) | 1996-12-23 | 1997-12-03 | Surface connectable semiconductor bridge elements, devices and methods |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/771,536 | 1996-12-23 | ||
| CN 97180963 CN1242108A (en) | 1996-12-23 | 1997-12-03 | Surface connectable semiconductor bridge elements, devices and methods |
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| Publication Number | Publication Date |
|---|---|
| CN1242108A true CN1242108A (en) | 2000-01-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 97180963 Pending CN1242108A (en) | 1996-12-23 | 1997-12-03 | Surface connectable semiconductor bridge elements, devices and methods |
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| Country | Link |
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| CN (1) | CN1242108A (en) |
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| CN1333494C (en) * | 2002-07-05 | 2007-08-22 | 日本压着端子制造株式会社 | Connector, method for manufacturing the same, and wiring board structure employing it |
| CN100461402C (en) * | 2003-09-30 | 2009-02-11 | 三洋电机株式会社 | Circuit device and method for manufacturing same |
| CN101258378B (en) * | 2005-09-07 | 2010-06-02 | 日本化药株式会社 | Semiconductor bridge, igniter, and gas generator |
| CN102853724A (en) * | 2012-10-08 | 2013-01-02 | 南京理工大学 | Transduction component with surface-mounted semi-conductive bridge for electric initiating explosive device |
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- 1997-12-03 CN CN 97180963 patent/CN1242108A/en active Pending
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| CN1333494C (en) * | 2002-07-05 | 2007-08-22 | 日本压着端子制造株式会社 | Connector, method for manufacturing the same, and wiring board structure employing it |
| CN100461402C (en) * | 2003-09-30 | 2009-02-11 | 三洋电机株式会社 | Circuit device and method for manufacturing same |
| CN101258378B (en) * | 2005-09-07 | 2010-06-02 | 日本化药株式会社 | Semiconductor bridge, igniter, and gas generator |
| CN101711340B (en) * | 2007-03-12 | 2013-06-12 | 戴诺·诺贝尔公司 | Detonator ignition protection circuit |
| CN103673792B (en) * | 2012-09-06 | 2016-03-02 | 北京理工大学 | One sends out semiconductor bridge ignition module in high wink |
| CN103673792A (en) * | 2012-09-06 | 2014-03-26 | 北京理工大学 | High-voltage instant semiconductor bridge ignition module |
| CN102853724B (en) * | 2012-10-08 | 2014-06-25 | 南京理工大学 | Transduction component with surface-mounted semi-conductive bridge for electric initiating explosive device |
| CN102853724A (en) * | 2012-10-08 | 2013-01-02 | 南京理工大学 | Transduction component with surface-mounted semi-conductive bridge for electric initiating explosive device |
| CN103344150A (en) * | 2013-07-12 | 2013-10-09 | 南京理工大学 | Schottky junction explosive-electric transducer component and manufacturing method thereof |
| CN103344150B (en) * | 2013-07-12 | 2015-02-18 | 南京理工大学 | Schottky junction explosive-electric transducer component and manufacturing method thereof |
| CN103344151B (en) * | 2013-07-12 | 2015-02-25 | 南京理工大学 | Schottky junction plane explosion switch used for exploding foil initiator and preparation method thereof |
| CN103344151A (en) * | 2013-07-12 | 2013-10-09 | 南京理工大学 | Schottky junction plane explosion switch used for exploding foil initiator and preparation method thereof |
| CN104776759A (en) * | 2015-04-01 | 2015-07-15 | 南京理工大学 | Electro-explosive energy conversion element of energetic nanocomposite film integrated with SCB (Semiconductor Bridge) and Al/MxOy |
| CN104776759B (en) * | 2015-04-01 | 2017-01-18 | 南京理工大学 | Electro-explosive energy conversion element of energetic nanocomposite film integrated with SCB (Semiconductor Bridge) and Al/MxOy |
| CN110278682A (en) * | 2018-03-15 | 2019-09-24 | 英研智能移动股份有限公司 | The radiating module of variable bridge joint and its electronic device of application |
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