CN1222992A - Time-interleaved bit-plane, pulse-width-modulation digital display system - Google Patents
Time-interleaved bit-plane, pulse-width-modulation digital display system Download PDFInfo
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- CN1222992A CN1222992A CN 97195719 CN97195719A CN1222992A CN 1222992 A CN1222992 A CN 1222992A CN 97195719 CN97195719 CN 97195719 CN 97195719 A CN97195719 A CN 97195719A CN 1222992 A CN1222992 A CN 1222992A
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Abstract
A time interleaved bit addressed weighted pulse width modulation (PWM) method and apparatus reduces the bandwidth requirement necessary for providing a plurality of data entries regarding multiple points of information. As is well known, a weighted PWM scheme modulates an output by utilizing a frame time that is divided into events of varying durations; most conventional schemes have each bit in the frame being half the duration of its predecessor. The modulated signal is activated during all, some or none of the events in the frame to develop a signal representing a particular parameter. This method and apparatus can be used in a display for selecting among varying levels of gray scale or from among multiple colors on a palette. In one application for a display, a register containing the same number of data pits as pixels in a row of the display is provided. The register is loaded with one bit per frame for each pixel in the entire row. The bandwidth is reduced because the bit for each of the pixels are not all for the same weight event. This allows a bit for a long duration event to be displayed in one pixel, while more than one bit for shorter duration events to be displayed in another pixel. This obviates the need to load one bit for each pixel in the row during the shortest event duration. The organization of the sequence of the events amongst the various rows can be pseudo-random to achieve reduced bandwidth. If the organization is pseudo-random the order can be pre-selected for an optimized bandwidth or organized into a predetermined format to achieve a pseudo-random effect.
Description
Invention field
The present invention relates to width modulation (PWM) technical field.More specifically, the present invention relates on digital indicator, provide gray scale or colored method and apparatus, in this method and apparatus, time interleaving is carried out in the different position of weight, so that the peak value minimum of data bandwidth.
Background of invention
It is well-known using PWM to form gray scale in display technique.The technology that produces gray scale with PWM can directly apply to the technology that produces colour in display technique with PWM.For fear of making the present invention be difficult to be understood aspect the inessential details, only prior art and the present invention are described in the formation that shows with respect to the black and white gray scale.For those of ordinary skills, it is conspicuous that these technology can directly be used for forming colored the demonstration.Be readily appreciated that this grayscale technology can be applicable to color system to produce the colour signal of Strength Changes.Will be appreciated that colored also within the scope of technology of the present invention.
On digital indicator during displayed image, pixel is not that to be switched " on " be exactly to be " closed ".In order to form more changeful image, need to produce selectable gray scale.This changeability that has increased can be used to provide more information or more real image.For example, consider that " connections " pixel is white and " closing " pixel is the demonstration of deceiving under the situation.In order to obtain intermediateness, for example the ash, can make pixel between " connection " and " closing " equably repeatedly.If it is enough short that pixel shows the duration, eyes/brain system of beholder is just automatically synthesized this pixel repeatedly, thereby feels that it is an ash image rather than black or white visual.In order to obtain more shallow or darker ash, can adjust the longer or weak point of time that pixel duty factor is repeatedly connected pixel.
The described technology of the preceding paragraph is commonly referred to width modulation (PWM).As everyone knows, the PWM scheme can be unweighted or weighting.Fig. 1 represents common 3 weighting PWM schemes not.In weighting PWM scheme not, the visual display cycle of pixel (being commonly referred to a frame) is divided into 7 equal time slots.Each pixel is that connection or the selection of closing can realize by writing corresponding data values in the duration of time slot.Drive pixel in can be during the time slot of any number of from 0 to 7.As long as frame rate is enough high, then any ordering for the position all will obtain identical intensity.Therefore, in the system of Fig. 1,8 different intensity levels are arranged, its scope is connected pixel from closing pixel in during all time slots in during all time slots.
Fig. 2 represents 8 PWM schemes of ordinary binary weighting.In this PWM scheme, the duration of each incident is inequality, and the duration of back one incident is half of duration of last incident.So just can utilize ordinary binary to encode and select the intensity of pixel.Under the situation of general weighting, the frame period is divided into N incident, selects the duration of each incident by the contraposition weighting.In the system of N position, the frame period is divided into 1/2n-1 the time interval, n={0 here, and N}, All Time interval sum is 1/2+1/4+ ... + 1/2N.The shortest incident (corresponding to least significant bit (LSB)) of duration be the frame period/(2
N-1).Therefore, PWM scheme shown in Figure 2 is having 256 (0 to 255) kind gray level available from black to white scope.
The present invention is designed to can be applicable to comprise display system by many pixels of the arrayed of row and column.This system comprises 1024 row pixels, and each row has 1280 pixels arranging by row.Video data 1280 registers of packing into, then these data are write display.Data with shift register sequence ground storing one row pixel.Is pack into operational time of these shift registers of data line Λ/(line number #), and Λ is that pixel shows the duration here, and line number # is 1024 in the present example.Therefore, the required data bus peak bandwidth of electronic circuit that data are offered these shift registers is (line number #)/Λ * 1280.Be readily appreciated that the cost of system enlarges markedly along with the increase of peak bandwidth demand.
According to the conventional way of PWM mode, at first pack into and show the incident Λ that the duration is the longest
1Data, pack into then and show duration time the longest incident Λ
2Data, the rest may be inferred, up to packing into and showing the incident Λ that the duration is the shortest
NData till.Because must be at the shortest incident Λ of duration
NTime in pack into and then show whole 1024 data bit, so the limiting factor of Here it is system bandwidth.
Fig. 3 A, 3B and 3C utilize 4 weighting gray scales to pack into and show the diagrammatic representation of the timing that delegation's pixel of a display system is required.In this example of Fig. 3 A, 3B and 3C, gradation data is 4, so 16 kinds of different gray levels are arranged.In the diagrammatic representation of Fig. 3 A, the transverse axis express time, and Z-axis represents to be used for to show the line of a row of display.Will be appreciated that the time shaft that will repeat Fig. 3 A to each row of display, so that form the complete image of a frame.In case shown a frame, the process that forms a frame just ad infinitum repeats down, so that form each subsequent frame in the display sequence.
According to conventional way, sequentially the data of the position 3 (duration the longest position) of all row display of packing into.Video data in the duration of the incident shown in concise and to the point as Fig. 3 A.In case the duration of position 3 finishes, and just the data of position 2 is write display.In case the duration of position 2 finishes, and just the data of position 1 is write display.In case the duration of position 1 finishes, and just the data of position 0 is write display.At last, in case the duration of position 0 finishes, just the data of the position 3 of next frame are write display.Finish in the duration of the incident of this process essential on the throne 0 of the data of demonstration position 3.
In many systems, in one-period, can only write delegation, so the data of 1024 row can not be by the display of packing into simultaneously.Oblique line 100 (Fig. 3 A) is illustrated in demonstration time interior timing of the data load register of position 3 of incident 0 briefly.Those of ordinary skills be it is evident that: the required bandwidth of 1280 bit data of the position 3 of the next line of packing in the 0 demonstration time of position of current line is very big.Consider that for example the frame rate of display is 60Hz, promptly the entire frame per second is drawn 60 times, so at frame of about 16.667 milliseconds of inside-paints.Suppose that display has 1024 row, then each row must be shown in about 16.28 microseconds.If adopt 8 weighting gray scales, then the shortest incident was about for 64 nanoseconds the duration.Must be in about 64 nanoseconds or pack into 16 at every turn and just write whole 1280 of next line if this means in the mode of about 800 psecs of every word.This just is converted into the bandwidth of about 1.25GHz.Certainly these numerals are just for for the purpose of illustrating.For example, the frame rate of 60Hz is derived from the standard television display technique.Other frame rate for example will be applicable to the digital video signal that the high resolution computer graphical application by common employing 1280 * 1024 displays is produced.
Fig. 3 B is the timing of events figure of presentation graphs 3A accurately.Not the imaginary figure that all incidents in each row of order that occurs simultaneously are shown, but the incident of each row of order of actual appearance of cycle in order is shown.Fig. 3 C packs data according to bandwidth demand of each row of the timing designed system of Fig. 3 B into diagrammatic representation.As shown in the figure, bandwidth demand is very high in data are transmitted to time of display.Therefore, will have as mentioned above bandwidth demand according to the timing diagram designed system of Fig. 3 B by the shortest position weighting defined of the duration of binary coding mode.So for any long summation of weighted bits, bandwidth demand reduces to zero in during the major part in frame period, causes undesirable " rest time " (dead times).In other words, the bandwidth demand degree of this system is not that maximum is exactly zero.
Known, can not reduce bandwidth by the duration of all incidents that extend simply.For example need to consider intermediate grey scales.If the duration of frame and appropriate incident are long, the pixel that is shown will glimmer, rather than presents intermediate grey scales.Therefore, it is very important making demonstration time of all incidents not too long.
A kind of solution of this problem is seen U.S. Patent application " removing of display system is in the back matrix addressing " (the Clear-behind matrixaddressing for display system that submits to June 7 nineteen ninety-five, application number is 08/482192), this application is as list of references of the present invention.According to this invention, in each pixel display frame, a dead band is set.Providing long incident duration prevent that the bandwidth demand of locking system becomes for the shortest one or more incidents is difficult to bear.Regrettably, in this system, losing of a part of available demonstration intensity caused in the dead band, and bandwidth is not best.
Need a kind of like this display system of utilizing weighting PWM scheme that gray scale is provided, this display system not have flicker and the bandwidth demand that has alleviated is provided for the control circuit of being correlated with and data bus.
Brief summary of the invention
A kind of algorithm time-interleaved bit-plane, width modulation (PWM) numeric displaying method and equipment have alleviated the required bandwidth demand of a plurality of data item that expression multiple spot information is provided.For coming appropriate designed system according to the present invention, bandwidth demand is constant and is best at least a metering system.As everyone knows, weighting PWM mode was modulated output by the frame period that employing is divided into the incident of duration variation.In most conventional PWM design proposal, the duration of each is half of its duration of last in the frame.In frame during all incidents, during some incidents or do not have the drive modulated signals of incident in the frame, so that produce the signal of representing special parameter.This method and equipment can be used in display to elect from gray level that changes or the multiple colour from palette.In a kind of application of display, provide the register of the data bit of a pixel similar number in the delegation that comprises with display.The position that each delegation packs every row of each pixel in the full line into on ground this register.Preferably make the duration of order display line inequality, alleviate bandwidth demand thus.This position of just having realized the long duration incident is shown in a row, and those positions of shorter duration incident are shown in other row.This does not just need the data of minimum length in time position all row of sequentially packing into.Can arrange the order of the incident in each row, so that reduce bandwidth.If arrange, just can or make this have predetermined form in proper order and obtain improved visual effect for optimized bandwidth chosen in advance order in pseudorandom mode.
Summary of drawings
Fig. 1 represents the sequential chart of the not weighting PWM mode of prior art.
Fig. 2 represents the sequential chart of the weighting PWM mode of prior art.
Fig. 3 A represents the sequential chart of the weighting PWM mode of conventional way.
Fig. 3 B represents to be counted as the sequential chart of the actual Fig. 3 A that occurs in time.
Fig. 3 C is the diagram by the bandwidth demand of the sequential chart designed system of Fig. 3 B.
Fig. 4 represents to be used for realizing the block scheme of equipment of the present invention.
Fig. 5 represents the sequential chart of the pseudo-random binary weighting PWM mode of one embodiment of the invention.
Fig. 6 A represents the sequential chart of the weighting PWM mode of most preferred embodiment of the present invention.
Fig. 6 B is the diagram by the bandwidth demand of the sequential chart designed system of Fig. 6 A.
Fig. 6 C represents the another kind of sequential chart of weighting PWM mode of the present invention.
Fig. 7 A represents the conventional sequential chart of weighting PWM mode.
Fig. 7 B represents to adopt the conventional sequential chart of the weighting PWM mode of the ordering opposite with the timing shown in Fig. 7 A.
Fig. 8 represents the sequential chart of nonbinary weighting embodiment of the present invention.
Fig. 9 represents the sequential chart of the relative zero hour in a period of time of most preferred embodiment of the present invention.
Figure 10 represents the sequential chart that has comprised the timing that is used for clearing data of the present invention.
Figure 11 represents the sequential chart of most preferred embodiment of the present invention.
The detailed description of most preferred embodiment
Developing time-interleaved bit-plane, PWM technology of the present invention is in order to provide gray scale to display.In most preferred embodiment, display is to license to being made of the defraction grating device array described in people's such as Bloom the United States Patent (USP) 5311360 as on May 10th, 1994, and this patent is as list of references of the present invention.According to most preferred embodiment of the present invention, the array of defraction grating device is pressed row and column and is arranged, and forms the pixel of display.1024 row and 1280 row pixels are arranged in the array of most preferred embodiment.This array can be formed or be made up of the multiplexed pixel of sequential that supplies colored demonstration usefulness by the monochromatic light grid pixel of using for white and black displays.Similarly, these pixels can constitute color monitor with the many optical grating elements that use for every pixel.
By using diffraction grating, the display optics that can make the light of irradiation source enter display selectively.When the light from a pixel enters display optics, this pixel is just lighted seemingly.By lighting pixel by different percentage of times, promptly just having formed various gray levels by modulating pulse width.Using weighting PWM mode to produce gray scale in most preferred embodiment selects.
Conventional display is described (irradiation) pixel at every turn when making beam flying cross its whole surface.Different with conventional display, in most preferred embodiment, can upgrade all pixels in delegation's diffraction grating light valve simultaneously.Therefore the following description of the present invention will be referred to show delegation at every turn.Yet those of ordinary skill in the art be it is evident that: technology of the present invention can be applied to use the PWM mode to produce the equipment of other type of gray scale equally.
To most preferred embodiment be described with respect to single width image, the i.e. demonstration of a frame.Every frame comprises 1280 * 1024 pixels, has 1,310,720 pixels.Suppose to need 8 weighting gray scales, promptly 10,485,760 data bit are determined a frame.According to the present invention, each delegation ground forms each row of image.Because show at every turn,, line number just equals the number of every frame update incident or the write cycle time of every frame delegation so multiply by the figure place of intensity-weighted.Therefore describe a frame and need 1024 * 8 incidents.Notice that an incident is the pixel data in the register of a line width to be transferred in the row go.Being readily appreciated that needs certain operations (for example memory cycle) to come to fill this register with the pixel data of this row.
Row image was shown in a frame period, so that 8 of each pixel eyes that the beholder is suitably presented in the position in this row.Eyes/brain system of beholder synthesizes delegation's pixel to 8 summation of weighted bits of each pixel then, and each pixel has suitable gray scale.Similarly, eyes/brain system of beholder synthesizes the single width image to the demonstration of every row.
Display device of the present invention comprises a video memory 400 as shown in Figure 4.Video memory 400 can be any suitable type of memory, comprise such as the such semiconductor memory of RAM (can be but be not limited to DRAM, SRAM or VRAM) or such as the such non-semiconductor storer of hard disk, floppy disk or CD having or not have intermediate treatment (for example mpeg decompression contracts).Fig. 4 illustrates video memory 400 and has a plurality of.This metaphor is used for illustrating on principle: each pixel has comprised each a plurality of data bit for weighting PWM mode; Those of ordinary skills be it is evident that: in video memory 400, can adopt any suitable arrangement of pictorial data.
Under the control of control circuit 402, data move into register 404 from video memory 400.In case register is filled, under the correct timing of the clock signal that control circuit 402 produces, the data in the register 404 just are used to shine the pixel in the suitable delegation of display 406.Display keeps being written into the data of each pixel state of going, till they are updated in subsequent cycle.In most preferred embodiment, register 404 comprises 1280 latchs and drive circuit, and these circuit buffer buses are connected with the row of display.Such as in the background parts of this patent file discussion, if must give whole 1280 latchs data of packing in the shortest incident duration, then for the solution of economy, it is too strict that the bandwidth demand of electronic circuit just becomes.
In order to alleviate the bandwidth demand of this system, compared with the prior art, the present invention to show various weightings the position the moment rearrange.Because the frame period is enough short, so that eyes/brain system of beholder can synthesize correct gray scale being shown image, and these DISPLAY ORDER does not influence image quality.Fig. 5 represents the example of 8 binary weighting PWM modes of 4 line data of one embodiment of the invention.Fig. 5 is shown clearly between arbitrary departure date of 4 row and does not repeat the shortest incident in same time slot.Those of ordinary skills are easy to after having read this instructions recognize that the order that can select summation of weighted bits comes the different characteristic of optimization, for example bandwidth or visual effect.
Fig. 6 A represents not need to carry out the another kind of scheme that complicated optimization just can select to be encased in the data of going in the register.The data line of preceding 8 row only is shown among the figure.Just constantly before 0, the position of the data load register of the 0th summation of weighted bits corresponding to row 0, the data of the 3rd summation of weighted bits are packed into for the register-bit of row 1 usefulness, the data of the 2nd summation of weighted bits are packed into for the register-bit of row 2 usefulness, the register-bit that the data of the 1st summation of weighted bits are packed into and used for row 3-6, the data of the 0th summation of weighted bits are packed into for the register-bit of row 7 usefulness.During the next clock period, so change the data in row 1 and 2, promptly pack into row 1 and of the data of the 0th summation of weighted bits the data of the 3rd the summation of weighted bits row 2 of packing into.Constantly 1, under the driving of clock signal this new data input display.During the ensuing clock period, only change the data in row 2 and 3, and the like.So just reduced the number of times that per clock period data shift significantly, can from storer, extract data according to the mode of rule.
Fig. 6 B is the bandwidth demand diagram according to the sequential chart designed system of Fig. 6 A.As mentioned above, the bandwidth demand by the embodiment designed system of Fig. 6 A is alleviated.Shown in Fig. 6 B, bandwidth demand becomes constant; There is not " rest time " as shown in the prior art of Fig. 3 C.
According to the difference of clock rate, if only show the position of maximum length in time, then the display that moves by the mode of Fig. 6 A can produce flicker in image.At the display that moves under this condition this is being switched on basically in half time.Under this condition, the cycle of connecting-close can be long, and human eye can be awared, and makes the beholder produce the psycho-visual problem.This situation produces undesirable image.In addition, this image can cause the adverse effect of headache etc. to the user.The replacement scheme of Fig. 6 C presentation graphs 6A.According to the scheme of Fig. 6 C, the position 602 of maximum length in time is divided into the display cycle of two (or more a plurality of) time-divisions.In the example shown in Fig. 6 C, between the two halves of maximum length in time position 602, show the shortest position 604 that is right after in the back.The 3rd maximum length in time position 606 and minimum length in time position 608 are followed at second of maximum length in time position 602 after half.So, even only show the maximum length in time position, its duty factor is identical, but each connects-close reduced enough weak points that arrives of duration in cycle, has avoided producing flicker.
Referring again to Fig. 3, obviously, adopt common gray scale implementation, to conventional display bandwidth constraints can appear then, so just have to carry out simultaneously all the shortest event actions.For example consider long 15 row, display with 4 intensity-weighted.Fig. 7 A and 7B represent that the PWM mode according to prior art is that each luggage of this miniscope is gone into the timing that data are used.As mentioned above, the time of display frame is divided into (2
n-1) section.In Fig. 7 A, whole 15 provisional capitals show the data of long incident in the time period 0.Whole 15 provisional capitals show time the longest incident in the time period 8.Whole 15 provisional capitals show the 3rd data of long incident in the time period 12.Whole 15 provisional capitals show the data of short incident in the time period 14.The PWM of the prior art that Fig. 7 B represents is regularly except that at first showing the shortest incident identical with Fig. 7 A.In Fig. 7 B, whole 15 provisional capitals show the data of short incident in time period 0.Whole 15 provisional capitals show time the data of short incident in the time period 1, whole 15 provisional capitals show the 3rd data of short incident in the time period 3, and whole 15 provisional capitals show the data of long incident in the time period 7.
Fig. 8 represents to go into the required timing of data according to a nonbinary embodiment of the present invention for each luggage of this miniscope.The sequential chart of Fig. 8 shows: by not showing that at synchronization whole minimum length in time incidents are alleviated the bandwidth demand of display system significantly.During each time period of 15 time periods, have only 4 presented event.In the time period 0, there are 4 to be shown incident: row 0 (the shortest incident gray scale), row 8 (the longest incident gray scale), row 12 (the 3rd the shortest incident) and row 14 (the shortest inferior incident).In the time period 1, there are 4 incidents to be shown: row 0 (the shortest inferior incident), row 1 (the shortest incident), row 9 (the longest incident) and row 13 (the 3rd the shortest incident).In the time period 2, have only 4 incidents to be shown: row 1 (inferior the shortest), row 2 (the shortest), row 10 (the longest) and row 14 (the 3rd is the shortest).The timing of the remainder of display frame is shown in remainder among this figure.
Those of ordinary skills should find out easily: compare with the bandwidth of Fig. 7 A or 7B, the bandwidth of this system is significantly reduced.Do not need in a period of time 15 incidents to occur, but 4 incidents only need occur.Should find out that also 4 incidents in the time period can not occur at synchronization exactly.For 4 incidents are occurred simultaneously, these time periods are divided into 4 moieties again in each time period.Each part is used for one of 4 positions of gray scale.The video data of being about in first of each incident is during 1/4th, receive oneself with incident of being used for showing the shortest incident.Have be used for showing time the incident of short incident row during second 1/4th of each incident in the video data of reception oneself, and the like.Fig. 9 represents the sequential chart according to the delegation of Fig. 8 display.
The line number that can be described according to the present invention equals the number of time period.Because the character of conventional PWM weighting has only 2
n-1 time period can be used, and n is the figure place of gray scale here.For example, in Fig. 8, because adopt 4 gray scale, so 15 row in display, can only occur.In order to show more multirow, 30 row for example, must interlock the timing of the two halves of describing array.The graininess of gray scale is the function of the line number of the line number of display or video format.
According to most preferred embodiment of the present invention, before each new presented event at first the every row of blanking the position.Figure 10 has represented to comprise the modification sequential chart of delegation of the display of these blanking times.The total blanking time that shows the gray scale of delegation preferably equals a time period.Because each of gray scale all has one period blanking time of duration 1/n, so just increased by a whole time period.Therefore, as shown in figure 10, this most preferred embodiment comprises 2
nIndividual time period rather than as prior art, comprise 2
n-1 time period.So, this embodiment just can easily support 16 capable describing rather than describing as Fig. 7 A, Fig. 7 B and 15 row shown in Figure 8 as shown in figure 11.Referring now to Figure 10,, it shows the timing that makes the delegation that its shortest incident occurs at first.Position 0 (the shortest incident) was shown in first time period.Being provided then for position 1 duration is the blanking time of 1/4 time period.In the T.T. of 2 time periods, show position 1 then.This sequence is continued in all the other positions to gray-scale Control.
Each row of expressing whole frame image at Fig. 7 A, Fig. 7 B, Fig. 8 and Figure 11 is shown simultaneously.In most preferred embodiment, the data of each frame are received in order.Fig. 6 represents that the time line sheet of the timing of the data presentation of each row in the display shows.The dash area 600 expression data acquisitions of Fig. 6 and the timing of their each self-forming single frame images.When first row of a new frame image was transfused to display, the remaining part of past frame image still was shown.
The another kind of mode of timing that prior art is described is shown in the following table I.The table I represents that the mode according to Fig. 7 B shows the timing of least significant bit (LSB).According to the table I, each data bit is as each row of also sequentially being packed into as shown in Fig. 3.In order to show a frame,, need 240 clock period for 4 gray scales according to a kind of scheme of prior art.
| Time | OK | The position |
| ????t1 | ????r1 | ????b0 |
| ????t2 | ????r2 | ????b0 |
| ????t3 | ????r3 | ????b0 |
| ????t4 | ????r4 | ????b0 |
| ????t5 | ????r5 | ????b0 |
| ????t6 | ????r6 | ????b0 |
| ????t7 | ????r7 | ????b0 |
| ????t8 | ????r8 | ????b0 |
| ????t9 | ????r9 | ????b0 |
| ????t10 | ????r10 | ????b0 |
| ????t11 | ????r11 | ????b0 |
| ????t12 | ????r12 | ????b0 |
| ????t13 | ????r13 | ????b0 |
| ????t14 | ????r14 | ????b0 |
| ????t15 | ????r15 | ????b0 |
| ????t16 | ????r16 | ????b0 |
| ????t17 | ????r1 | ????b1 |
| ????-- | ????-- | ????-- |
The table I
The table II is represented timing of the present invention.The timing of packing into and clearing data is shown in the figure of Figure 10.At this, for example in the moment 1, the data of pack into position 0, row 0, the data of removing row 15.In the moment 2, the data of pack into position 1, row 15, the data of removing row 13.The remaining part of his-and-hers watches II can continue to do this analysis.In order to show a frame,, need 64 clock period for 4 gray scales according to most preferred embodiment of the present invention.
| Time | OK | The position | Remove |
| ????t1 | ????r0 | ????b0 | ????r15 |
| ????t2 | ????r15 | ????b1 | ????r13 |
| ????t3 | ????r13 | ????b2 | ????r9 |
| ????t4 | ????r9 | ????b3 | ????r1 |
| ????t5 | ????r1 | ????b0 | ????r0 |
| ????t6 | ????r0 | ????b1 | ????r14 |
| ????t7 | ????r14 | ????b2 | ????r10 |
| ????t8 | ????r10 | ????b3 | ????r2 |
| ????t9 | ????r2 | ????b0 | ????r1 |
| ????t10 | ????r1 | ????b1 | ????r15 |
| ????t11 | ????r15 | ????b2 | ????r11 |
| ????t12 | ????r11 | ????b3 | ????r3 |
| ????t13 | ????r3 | ????b0 | ????r2 |
| ????t14 | ????r2 | ????b1 | ????r0 |
| ????t15 | ????r0 | ????b2 | ????r12 |
| ????t16 | ????r12 | ????b3 | ????r4 |
The table II
More than the system shown in two tables aspect bandwidth, be best.The meaning of bandwidth the best has been meant 2
nOK, n is the figure place of gray level resolution.Do not need idling cycle, otherwise can reduce bandwidth.The blanking cycle that does not also have unnecessary reduction display efficiency.Those of ordinary skills be it is evident that: according to the present invention, 2
nThe row of integral multiple can be included in the display, make the increase of bandwidth demand be directly proportional with this integral multiple.Another relevant problem is that gray scale demand and line number mismatch for example not enough 2
nRow or the gray scale that is not 2 power is arranged.All these system design problems are called the gray scale display system that do not match.
There are some kinds of methods can handle the gray scale display system that do not match.Can increase dummy row to display sequence and mate the gray level resolution demand.Will be appreciated that these dummy row not to be shown and just be added to and go in the sequence of events so that form displayed image.For example, if only 480 row are formed frames, and represent every frame 512 row by adjusting the clock period, then bandwidth has just increased 6%.In this case, 6% of possible update cycle be not used for writing data to display.
The solution graininess that the second method of gray scale display system problem is to use total line number to provide that do not match.For this reason, can reduce gray level resolution and/or can adopt bigger bandwidth.For example, 480 row displays will be realized gray level resolution (512 grades) near 9, but some binary code can lose, and other binary code will produce equal output brightness simultaneously.Therefore, if only need 8 bit resolutions, but, then can make bandwidth increase 12% with 9 gray scales, 480 the different values of encoding.
Do not match the third method of gray scale display system problem of solution is to adopt removing of describing in the U.S. Patent application of for example submitting in June 7 nineteen ninety-five " removing of display system is in the back matrix addressing " (application number is 08/482,192) in duration that the back technology increases least significant bit (LSB).It is not the bandwidth optimizer system of 2 power that this system can provide line number, but has reduced optical efficiency.
With respect to most preferred embodiment the present invention has been described.After reading this instructions conspicuous improvement of those of ordinary skills or modification all are considered within the application's spirit and scope.
Claims (27)
1. a generation is used for sending to the method for a plurality of pulse-width signals of the digital indicator with a plurality of row and a plurality of row, and wherein the each delegation of this display pixel ground receives these pulse-width signals, and this method may further comprise the steps:
A. receive the position of the predetermined number of each signal, these positions are enough to define this signal, thus make these each represent the incident of a various durations;
B. store these positions;
C. each delegation ground writes all row to data, and this write step comprises some set of each pixel of selecting delegation, so that the signal of formation predetermined lasting time;
D. forming a plurality of its duration represents the signal of these set, in corresponding these signals of each of these set one, and these signals are sent to the predetermined row of display; And
E. be that any incident that will finish when next time clock is selected an alternative position set, wherein at least 3 position set in succession showed with the different duration.
2. one kind is used for providing equipment of n position weighting width modulation to each row of m signal rows, wherein each signal rows receives n signal, so that show some positions that its duration changes between minimum length in time and maximum length in time, these representatives have been carried out the data bit of m * n width modulation, this equipment comprises a control circuit, this control circuit is selected first set of some data bit, wherein the duration of each data bit is variable, this control circuit also forms corresponding first signal set so that show the position of predetermined row with predetermined lasting time, this control circuit shows the position set that each is follow-up then in the row of remainder, wherein at least 3 position set in succession are the position set for the position of various durations.
3. the equipment of claim 2 is characterized in that, if the position of all minimum length in time shown in proper order, show that then the bandwidth demand of subsequent bit set just can be alleviated.
4. the equipment of claim 3 is characterized in that, bandwidth demand wherein is constant.
5. the equipment of claim 2 is characterized in that, only is chosen in the position of the incident that finishes during the next clock period.
6. the equipment of claim 5 is characterized in that, comes a plurality of pixels of modulation display so that form a gray scale image with this signal.
7. the equipment of claim 6 is characterized in that, wherein pixel is lined up a plurality of row and columns, and this equipment also comprises a register with a plurality of storage unit, the corresponding storage unit of each pixel in the one row.
8. the equipment of claim 5 is characterized in that, forms predetermined colored with a plurality of pixels of signal modulation display.
9. the equipment of claim 8 is characterized in that, wherein pixel is lined up a plurality of row and columns, and this equipment also comprises the register with a plurality of storage unit, the corresponding storage unit of each pixel in row.
10. the equipment of claim 2 is characterized in that, control circuit is wherein selected the set of selected position according to pre-defined algorithm.
11. the equipment of claim 10 is characterized in that, only is chosen in the position of the incident that finishes during the back to back clock period.
12. the equipment of claim 11 is characterized in that, forms gray scale image with a plurality of pixels of signal modulation display.
13. the equipment of claim 12 is characterized in that, wherein pixel is lined up a plurality of row and columns, and this equipment also comprises a register with a plurality of storage unit, the corresponding storage unit of each pixel in the one row.
14. the equipment of claim 11 is characterized in that, forms predetermined colored with a plurality of pixels of signal modulation display.
15. the equipment of claim 14 is characterized in that, wherein pixel is lined up a plurality of row and columns, and this equipment also comprises the register with a plurality of storage unit, the corresponding storage unit of each pixel in row.
16. each of a plurality of signals that is used in a frame period provides the equipment of weighting width modulation, comprising:
A. store each the storer of set of data bits in these a plurality of signals of a plurality of representatives, each set is made up of the position of similar number, thereby makes one of different event duration that each bit representation in the set is scheduled to;
B. be used for selecting to form from this first subclass of a plurality of of each position of set the first selection circuit of gathering of selected location, each selected location has the foregone conclusion spare duration;
C. be used to produce circuit corresponding to a plurality of transferred signals of these selected location; And
D. control circuit, be used for controlling and select circuit so that select to form second set of selected location from this second subclass of a plurality of of a position of every set, thereby make that those ability of having only different incident durations to finish are replaced in the next clock period when next time clock, and have only a position set when any one time clock, to finish.
17. the equipment of claim 16 is characterized in that, if the position of all minimum length in time by select progressively, then selects the bandwidth demand of second set of selected location just can be alleviated.
18. the equipment of claim 17 is characterized in that, bandwidth demand wherein is constant.
19. the equipment of claim 16 is characterized in that, comes a plurality of pixels of modulation display so that form gray scale image with this signal.
20. the equipment of claim 19 is characterized in that, wherein pixel is lined up a plurality of row and columns, and this equipment also comprises a register with a plurality of storage unit, the corresponding storage unit of each pixel in row.
21. the equipment of claim 16 is characterized in that, control circuit is wherein selected the set of selected position according to pre-defined algorithm.
22. the equipment of claim 21 is characterized in that, comes a plurality of pixels of modulation display so that form gray scale image with this signal.
23. the equipment of claim 22 is characterized in that, wherein pixel is lined up a plurality of row and columns, and this equipment also comprises a register with a plurality of storage unit, the corresponding storage unit of each pixel in row.
24. a display comprises:
A. line up the cell array of a plurality of row and a plurality of row;
B. have and be used for the register of a plurality of storage unit of temporal data, the number of the pixel in the number of the storage unit that this register has and the row is identical;
C. the control circuit that is connected with register with storer is used for the transmission of control data to predetermined row;
D. be used to store the storer of the position set of each pixel, each set comprises the position of similar number, thereby makes one of different event duration that each representative in the set is scheduled to; With
E. select circuit, being used for ground of every row selects so that form the selected position set with scheduled event duration, and then different row are selected a new selected position set, thereby make have only that the different event duration finished those are replaced.
25. the equipment of claim 24 is characterized in that, if the position of all minimum length in time shown in proper order, show that then the bandwidth demand of subsequent bit set just can be alleviated.
26. the equipment of claim 25 is characterized in that, bandwidth demand wherein is constant.
27. a method that is used to produce a plurality of pulse-width signals may further comprise the steps:
A. store the position of the predetermined number of each signal, these positions are enough to define this signal, thus make these each represent the incident of various durations;
B. select a position set for each signal, thereby can select the position of at least two various durations incidents; And
C. select one of any incident that when next time clock, to finish to substitute the position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97195719 CN1222992A (en) | 1996-04-22 | 1997-04-21 | Time-interleaved bit-plane, pulse-width-modulation digital display system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/635,479 | 1996-04-22 | ||
| CN 97195719 CN1222992A (en) | 1996-04-22 | 1997-04-21 | Time-interleaved bit-plane, pulse-width-modulation digital display system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1222992A true CN1222992A (en) | 1999-07-14 |
Family
ID=5179342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 97195719 Pending CN1222992A (en) | 1996-04-22 | 1997-04-21 | Time-interleaved bit-plane, pulse-width-modulation digital display system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1222992A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374727A (en) * | 2016-10-08 | 2017-02-01 | 北京精密机电控制设备研究所 | High-reliability IGBT (Insulated Gate Bipolar Transistor) parallel control device |
-
1997
- 1997-04-21 CN CN 97195719 patent/CN1222992A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374727A (en) * | 2016-10-08 | 2017-02-01 | 北京精密机电控制设备研究所 | High-reliability IGBT (Insulated Gate Bipolar Transistor) parallel control device |
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