CN1222885C - FLASH data protecting method and its FLASH curcuit - Google Patents
FLASH data protecting method and its FLASH curcuit Download PDFInfo
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- CN1222885C CN1222885C CN 02124199 CN02124199A CN1222885C CN 1222885 C CN1222885 C CN 1222885C CN 02124199 CN02124199 CN 02124199 CN 02124199 A CN02124199 A CN 02124199A CN 1222885 C CN1222885 C CN 1222885C
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Abstract
The present invention relates to a FLASH data protecting method and a FLASH circuit thereof. The FLASH data protecting method comprises the following steps: a. an address signal to be protected is output to a first logical calculation unit for logical calculation; b. an output result of the first logical calculation unit and a control signal of a CPU are input to a second logical calculation unit for the calculation, and a calculation result is input to the signal writing end of FLASH. The FLASH circuit of the FLASH data protecting method comprises a FLASH chip and an address line, wherein the address line is used for inputting the signal to the FLASH chip. The FLASH circuit of the FLASH data protecting method is characterized in that the end of the address line is provided with the first logical calculation unit, the input of the first logical calculation unit is the address line needing protection, the output of the first logical calculation unit and the writing signal of the CPU are used as the input of the second logical calculation unit together, and the output of the second logical calculation unit is introduced into the signal writing input end of FLASH. The FLASH data protecting method and the FLASH circuit thereof have the advantages of high reliability, low cost, wide application range and flexible control.
Description
Technical field
The present invention relates to communication and microelectronic, relate in particular to a kind of FLASH data guard method and FLASH circuit thereof.
Technical background
FLASH is the abbreviation of Flash Memory, but is a kind of non-volatile flash memory that can wipe field programming fast.Because it is non-volatile that the FLASH device has, it is widely used in BOOTROM, online erasable and occasions such as power down protection data and partition protecting data, uses very extensive at modern communications and microelectronic.
Because the critical role of FLASH in system also had higher requirement to its safety of data, such as, in a lot of occasions,, will cause system to power on and then paralyse because of starting if the start-up code among the FLASH is lost.
The programming operation of FLASH device is realized by a series of instruction sequence.Can avoid the data among the FLASH unexpectedly to be rewritten by this method.According to these characteristics of FLASH device, can realize the data protection of FLASH usually with the method for software.When the data among the FLASH were supported online programming, the measure of its data protection may lose its effect because of the fault of software.
Now, having only to design on the increasing circuit board has a slice FLASH, has wherein both deposited start-up code, also deposited application code, and application code generally all requires online programming.Start-up code among the FLASH is probably write when upgrade applications by mistake, perhaps causes loss of data when software breaks down.To cause veneer not restart after start-up code is destroyed.FLASH data guard method commonly used at present has two kinds:
1, realize protection by the mode that program voltage pin Vpp voltage is set:
The FLASH of some low capacities makes in this way usually.This class device need provide specific program voltage (as 12V) at the Vpp pin when programming; the program voltage of this class FLASH generally is to be provided by special-purpose programmable device when loading; and on product single board, do not provide this program voltage; so just guaranteed on hardware that the FLASH device can not be written into, this is a kind of hardware protection method.
The high capacity FLASH device, as the 28F160C3 of Intel Company, its Vpp end also can be used for realizing the write-protect of FLASH.If the input voltage of the Vpp pin of this class device is greater than a certain threshold values, then device allows to be written into; If this voltage is lower than this threshold values, then will forbid writing.Utilize this characteristic, can on veneer the Vpp signal be drawn or control separately, only its program voltage of ability is set to be higher than threshold voltage (but magnitude of voltage parametric device handbook) when FLASH is programmed.
When the input voltage that passes through control Vpp pin in veneer was realized data protection, this control operation was generally controlled by software, so this is a kind of data protection that realizes by software.
2, utilize the protection mode of operation of FLASH device itself
Utilize the protection mode of operation of FLASH device itself, when soon certain BLOCK of FLASH is set to lock-out state, forbid programming operation; When needs were programmed to this BLOCK, with its release, this was a kind of data guard method of realizing by software by a series of instruction sequence in needs elder generation.
Fig. 1 is a typical write operation schematic flow sheet to BLOCK, has wherein just comprised the unlocking operation to BLOCK.
3, utilize the programming instruction sequence of FLASH, prevent that FLASH from being write by mistake, this also is a kind of method that is realized by software.
Utilize the characteristic of Vpp pin, it is a kind of reliable data guard method that the protection of the method realization of program voltage is not provided on veneer, and this method is widely used in the FLASH of low capacity, plug-in mounting type.The shortcoming of this method also is clearly, that is:
1, this method can not be applied to high capacity FLASH.Because high capacity FLASH generally requires to support online programming, promptly require CPU on the veneer can realize programming, and program voltage is not provided on the veneer, so software can't be realized programming to FLASH;
2, this method can not be applied to the FLASH of paster encapsulation.Because veneer itself is for the FLASH device provides program voltage, so FLASH must programme at the programmable device of special use, and for the device of paster encapsulated type, be fixed to when programming obviously is unpractical on the special-purpose programming tool at every turn.
By software control Vpp voltage, perhaps utilize FLASH programming instruction sequence to prevent to write by mistake, perhaps utilize the protected mode of FLASH device itself to realize data protection, all be a kind of method that realizes by software in essence, promptly, under protected mode, whole address spaces of FLASH device or part address space are set to and can not write; Before each programming, be set to programmable pattern again.
The data protection that utilizes this mode to realize faces following problem:
1, when software breaks down, the data among the FLASH will be rewritten.Because software itself can be programmed to FLASH, when software breaks down, can't guarantee that the data among the FLASH can not write by mistake;
2, obliterated data in the process of upgrading.Application program among the FLASH generally all requires to support online programming, and online programming is realized by software.In escalation process, just when software is programmed to FLASH, data might be write in the wrong address, that is to say, the data corruption that should keep;
3, when only using a slice FLASH on the veneer, be a pair of conflicting operation to the protection of start-up code and the online programming of application programs.Owing to supporting that software itself can be programmed to FLASH under the situation of online programming, so how guaranteeing that partial data among the FLASH is not write becomes a problem that urgency is to be solved by mistake.
Summary of the invention
The present invention is exactly at present compromise FLASH data protection present situation, proposes a kind of method and FLASH circuit thereof of new FLASH data protection.
A kind of FLASH data guard method is characterized in that comprising:
A, protect address signal to export first arithmetic logic unit to desire to carry out logical operation;
B, the control signal of the output result of first arithmetic logic unit and CPU is imported second arithmetic logic unit carry out logical operation, the write signal input end of operation result input FLASH.
Described first arithmetic logic unit is carried out logical operation, is to carry out the NOR-logic computing.
Described second arithmetic logic unit is carried out logical operation, is to carry out or logical operation.
Described FLSAH data guard method; also comprise one to second arithmetic logic unit output result; import the step that the 3rd arithmetic logic unit is carried out logical operation with another write signal, described the 3rd arithmetic logic unit is carried out logical operation, is and logical operation.
Described FLASH data guard method, the input end that also is included in first arithmetic logic unit adds the step of a control signal, and the address that described control signal is used to control there not being protection loads.
A kind of FLASH circuit; comprise FLASH chip and address wire; described address wire is used for input signal to the FLASH chip; it is characterized in that; at the address line end, one first arithmetic logic unit also is set, it is input as the address wire that needs protection; as the input of one second arithmetic logic unit, FLASH write signal input end is introduced in the output of second arithmetic logic unit to the write signal of its output and CPU jointly.
Described first arithmetic logic unit is the NOR-logic door, and described second arithmetic logic unit is or logic gate.
Described FLASH circuit, also comprise one the 3rd arithmetic logic unit, the 3rd arithmetic logic unit receives the output of second arithmetic logic unit and the input signal of loading tool carries out logical operation, operation result inputs to the write signal input end of FLASH, and described the 3rd arithmetic logic unit is and logic gate.
Described FLASH circuit at the input end of first arithmetic logic unit, is provided with a signal input end, and the address that described control signal is used to control there not being protection loads.
FLASH circuit and FLASH data guard method that the present invention proposes; reliability height, cost are low, applied widely, control flexibly; utilize simple logical circuit can realize data protection; owing to be by the data protection of hardware circuit realization to FLASH; even software breaks down; also can not influence the safety of FLASH internal data; design by logical circuit; can specify neatly needs protected address space; and; even protected address space also can be implemented in the line programming.
Description of drawings
Fig. 1 is in the prior art, by the process flow diagram of software protection FLASH data;
Fig. 2 is in the prior art, the circuit diagram of a FLASH;
Fig. 3 is a circuit block diagram of the present invention;
Fig. 4 is a FLASH logical circuitry of the embodiment of the invention;
Fig. 5 is another FLASH circuit diagram of the embodiment of the invention.
Embodiment
Below in conjunction with Figure of description the specific embodiment of the present invention is described.
Core concept of the present invention is provided with arithmetic logic unit on former FLASH circuit, by the logical operation to desire protection address and CPU control signal, finish data protection.
As shown in Figure 2, be a traditional FLASH circuit.
As shown in Figure 3 and Figure 4; it is the improved FLASH circuit that the present invention is directed to Fig. 2; comprise address wire and CPU write signal end; this address wire is used for input signal to the FLASH chip; at the address line end; one first arithmetic logic unit is set; this first arithmetic logic unit is the NOR-logic door; it is input as the address wire that needs protection; its output and the write signal of CPU are jointly as the input of one second arithmetic logic unit; this second arithmetic logic unit is or logic gate that FLASH write signal input end is introduced in the output of second arithmetic logic unit.
On FLASH circuit of the present invention, one the 3rd arithmetic logic unit also is set, the 3rd arithmetic logic unit receives the output of second arithmetic logic unit and the input signal of loading tool carries out logical operation, operation result inputs to the write signal input end of FLASH, and the 3rd arithmetic logic unit is and logic gate.
The present invention is provided with a signal input end also at the input end of first arithmetic logic unit, and the address that this control signal is used to control there not being protection loads.
FLASH data guard method of the present invention is characterized in that comprising:
A, protect address signal to export first arithmetic logic unit to desire to carry out logical operation, the arithmetic logic of this first arithmetic logic unit is the NOR-logic computing;
B, the control signal of the output result of first arithmetic logic unit and CPU is imported second arithmetic logic unit carry out computing, the write signal input end of operation result input FLASH.The arithmetic logic of this second arithmetic logic unit is or logical operation.
The present invention also comprises one to second arithmetic logic unit output result, and with the step that another write signal carries out the 3rd logical operation, the 3rd logical operation is and logical operation.
Method of the present invention also is included in the step of a control signal of input end adding of first arithmetic logic unit, and the address that described control signal is used to control there not being protection loads.
Seeing a concrete example below, as shown in Figure 4, is that the present invention designs a kind of novel FLASH circuit, and this circuit comprises the CPU signal input end of 21 bit address lines and a CPU_WE.This circuit is changed the address wire of this circuit on traditional FLASH circuit base, and this FLASH address wire has 21, and wherein A18-A21 is a high address, now designs a logical circuit, and this high address is protected.
At the high address line end, with A18, A19, A20, A21 four bit address lines input signal as the rejection gate logical circuit, a rejection gate logical circuit is set, the output of this rejection gate logical circuit, import a NOT gate logic circuit with CPU_WE, this NOT gate logic circuit outputs signal to the write signal end FLASH_WE of FLASH.
The selection of the Input Address of this rejection gate logical circuit; be next fixed according to the requirement of FLASH desire protection address wire; which address needs protection; just which address wire is got final product as the input end of this rejection gate logical circuit jointly; it can be whole address wires; also can selection portion sub address line, just selected the address wire of high address part in the present embodiment.
In the FLASH circuit of the present invention's design, a write signal input end TOOL_WE also is set, this writes AND of the common input of output terminal of input end TOOL_WE and NOT gate logic circuit, and the write signal input end FLASH_WE of FLASH is introduced in this AND output.
In Fig. 4, being one is the principle schematic of its minimum 51 2K bytes realization protection of FLASH of 2M byte to capacity, and wherein CPU_/WE is the write signal from CPU; TOOL_/WR is the write signal input end that is designed to keep for loading tool, remains high level (logic ' 1 ') during normal working of single board.
The start address of FLASH is 0x0, and the address realm of then minimum 512K byte is 0x0-0x7FFFF.
When CPU operates low address space, be complete 0 the time promptly as [A21..A18], the write signal input end (FLASH_/WE) of FLASH remains high level, and just, the FLASH of this moment can not write.When [A21..A18] is complete ' 0 ', A[17..0] when carrying out write operation for the address location of arbitrary value, the write signal of FLASH will remain high level, and this unit, address is in protected state; When [A21..A18] is not complete ' 0 ', A[17..0] when carrying out write operation for the address location of arbitrary value, the write signal of FLASH can be controlled by the CPU_/WE among the last figure, and data can be written into.
When to the space, high address (more than or equal to 0 * 80000) of FLASH when writing data, have at least one to be logic ' 1 ' in these four signal wires of A21-A18, rejection gate output ' 0 ', like this, when CPU_/WE is low level, the write signal of FLASH (FLASH_/WE) will be logic ' 0 '.By such design, CPU can carry out normal programming operation to the space, high address of FLASH, realizes the demand of online programming.[A21..A18] carries out or logical operation for CPU_/WE among Fig. 3 and high address; then in the address of all data cells [A21..A0]; [A21..A18] be complete ' 0 ' data cell with protected, and [A21..A18] can not carry out normal load operation for complete ' 0 ' data cell.
The circuit design of introducing above, CPU can't carry out programming operation to low address space.As shown in Figure 5, if realize the online programming of low address space, can do following improvement:
Input end at the NOR-logic gate circuit adds a signal input end, and the address that this control signal LOCK is used to control there not being protection loads.
This LOCK signal is equivalent to the lock of protected location, can realize with simple logic.Behind the Board Power up, the LOCK signal is in (logical zero) state that locks.This moment, the low address space of FLASH forbade writing.In the time will programming to low address space, can make LOCK signal release (logic ' 1 ') by the key of outside input (or online download), remove protection, thereby realize the upgrading of FLASH low address space the FLASH low address space.
What will propose especially is: for protected data reliably, the information that is used for release can only be imported (or the outside is imported into) from the outside.After release, remove the information that these are used for release, and close the LOCK signal, and can not leave in the software of system.Could protect the FLASH district that needs protection veritably like this.
After using the present invention, can reach following effect:
1, reliability height.Owing to be,, also can not influence the safety of FLASH internal data even software breaks down by the data protection of hardware circuit realization to FLASH;
2, cost is low, utilizes simple logical circuit can realize data protection;
3, applied widely, both can be used for having on the veneer situation of multi-disc FLASH, also can be used for having only on the veneer situation of a slice FLASH;
4, control is flexible, and by the design of logical circuit, can specify neatly needs protected address space, and, even protected address space also can be implemented in the line programming.
The present invention is respond well in breadboard test, acts on very obvious.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, the protection domain of this aspect should be as the criterion with the protection domain of claims.
Claims (6)
1, a kind of FLASH data guard method is applied to the FLASH circuit, and the address wire of this circuit connects the FLASH chip, and described address wire input signal is given the FLASH chip, it is characterized in that this method comprises the steps:
A, protect address signal to export first arithmetic logic unit to desire to carry out the NOR-logic computing;
B, the control signal of the output result of first arithmetic logic unit and CPU is imported second arithmetic logic unit carry out or logical operation the write signal end of operation result input FLASH.
2, FLASH data guard method as claimed in claim 1; it is characterized in that also comprising one to second arithmetic logic unit output result; be input to the step that the 3rd arithmetic logic unit is carried out logical operation with another write signal; described the 3rd arithmetic logic unit is carried out logical operation, is and logical operation.
3, FLASH data guard method as claimed in claim 2, the input end that it is characterized in that also being included in first arithmetic logic unit adds the step of a control signal, and the address that described control signal is used to control not have to protect loads.
4, a kind of FLASH circuit of realizing the described FLASH data guard method of claim 1, comprise FLASH chip and address wire, described address wire is used for input signal to the FLASH chip, it is characterized in that, at the address line end, one first arithmetic logic unit also is set, it is input as the address wire that needs protection, as the input of one second arithmetic logic unit, FLASH write signal input end is introduced in the output of second arithmetic logic unit to the write signal of its output and CPU jointly;
Wherein, described first arithmetic logic unit is the NOR-logic door, and described second arithmetic logic unit is or logic gate.
5, FLASH circuit as claimed in claim 4, it is characterized in that also comprising one the 3rd arithmetic logic unit, the 3rd arithmetic logic unit receives the output of second arithmetic logic unit and the input signal of loading tool carries out logical operation, operation result inputs to the write signal input end of FLASH, and described the 3rd arithmetic logic unit is and logic gate.
6, FLASH circuit as claimed in claim 5 is characterized in that the input end in first arithmetic logic unit, and a signal input end is set, and the address that described control signal is used to control there not being protection loads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02124199 CN1222885C (en) | 2002-08-05 | 2002-08-05 | FLASH data protecting method and its FLASH curcuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02124199 CN1222885C (en) | 2002-08-05 | 2002-08-05 | FLASH data protecting method and its FLASH curcuit |
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| Publication Number | Publication Date |
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| CN1474277A CN1474277A (en) | 2004-02-11 |
| CN1222885C true CN1222885C (en) | 2005-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02124199 Expired - Fee Related CN1222885C (en) | 2002-08-05 | 2002-08-05 | FLASH data protecting method and its FLASH curcuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100594481C (en) * | 2005-10-20 | 2010-03-17 | 国际商业机器公司 | Method and system for allowing program operated on logical partitions to access resources |
| CN109522241A (en) * | 2018-11-15 | 2019-03-26 | 锐捷网络股份有限公司 | A kind of Write-protection method based on Flash, device and circuit |
-
2002
- 2002-08-05 CN CN 02124199 patent/CN1222885C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100594481C (en) * | 2005-10-20 | 2010-03-17 | 国际商业机器公司 | Method and system for allowing program operated on logical partitions to access resources |
| CN109522241A (en) * | 2018-11-15 | 2019-03-26 | 锐捷网络股份有限公司 | A kind of Write-protection method based on Flash, device and circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1474277A (en) | 2004-02-11 |
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Granted publication date: 20051012 Termination date: 20180805 |