CN1218400C - EFT with neck shape channel and mfg. method thereof - Google Patents
EFT with neck shape channel and mfg. method thereof Download PDFInfo
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- CN1218400C CN1218400C CN 02122346 CN02122346A CN1218400C CN 1218400 C CN1218400 C CN 1218400C CN 02122346 CN02122346 CN 02122346 CN 02122346 A CN02122346 A CN 02122346A CN 1218400 C CN1218400 C CN 1218400C
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- neck shape
- channel
- shape channel
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Abstract
The present invention relates to a field effect transistor with a neck-shaped channel and a manufacturing method thereof. The field effect transistor with a neck-shaped channel of the present invention is a double grid electrode metal oxygen half field effect transistor. The field effect transistor of the present invention at least comprises a channel between a source electrode and a drain electrode and a gap wrapping wall, wherein the channel is in a neck-shaped structure; the middle part of the channel is thin; both ends of the channel are broad; in such a way, the channel avoids occurrence of short channel effect, and simultaneously is capable of reducing resistance of series-wound channel; the gap wrapping wall is covered on the channel and the active region of the source electrode and the drain electrode; in such a way, the gap wrapping wall avoids metallic siliconization of the region. The manufacturing method of the present invention at least comprises: the present invention carries out photetching or etch process to form the neck-shaped channel, the source electrode and the drain electrode by OD mask on an SOI basal plate or the similar structure; after the neck-shaped channel, the source electrode and the drain electrode deposit on a gate material layer, the gap wrapping wall is formed.
Description
Technical field
The present invention relates to a kind of field-effect transistor (Field Effect Transistor with neck shape channel (necking channel); FET) and its manufacture method.Particularly relate to a kind of vertical double gate utmost point (vertical double gate) metal-oxide half field effect transistor (MOSFET) and its manufacture method with neck shape channel.
Background technology
In recent years, semiconductor industry is flourish, and nowadays integrated circuit has developed into very lagre scale integrated circuit (VLSIC) (Ultra Large Scale Integrated Circuit, field ULSI).In order to pursue the integrated circuit of high density more, high-speed and low power consumption, metal oxide semiconductor device must constantly dwindle.Increase along with the semiconductor element integrated level, short channel effect is also more serious, so various metal-oxide half field effect transistor is suggested the problem that solves short channel effect (short channel effect), wherein the bigrid metal-oxide half field effect transistor is an element of quite being noted.The FINFET of Chu Xianing a kind ofly suppresses the vertical double gate utmost point metal-oxide half field effect transistor of short channel effect (short channeleffect) with super narrow cuboid (be called " FIN ") channel (channel) in recent years.
Please refer to Fig. 1, Fig. 1 is the elevational schematic view that illustrates the channel architecture of existing FINFET.The source electrode 20 that wherein is fabricated from a silicon, channel 80 and draining 30 is formed on the obstacle oxide layer (barrier oxide) 15, and obstacle oxide layer 15 is formed on the base material (not illustrating).Channel 80 is a cuboid, and promptly the width from an end to the other end is all identical.Width as channel 80 is narrower, then grid voltage (V
g) to drain current (I
d) control ability sensitiveer, also can prevent more that short channel effect from taking place, and can improve subcritical swing (subthreshold swing).Yet, for reaching aforesaid effect, often need to use quite narrow channel, as tens of nanometers, and so narrow channel 80 can bring the too big problem of cascaded channel resistance value (series channelresistance), all causes great difficulty in design and use.In addition, in the process of making FINFET, when when carrying out the step of metal silication (silicidation), the position that narrow channel particularly connects source electrode (source) and drain electrode (drain) is very easy to be damaged.
Therefore, press for very much and develop a kind of channel architecture, not only can suppress the generation of short channel effect effectively, increase the control sensitivity of grid voltage to drain current, improve subcritical swing, and less cascaded channel resistance value is arranged, to reduce the degree of difficulty in the design and use.In addition, more can when carrying out the step of metal silication, avoid making the particularly narrow channel of structure of FINFET to be damaged.
Summary of the invention
In above-mentioned background of invention, existing FINFET increases the control sensitivity of grid voltage to drain current with the channel that is rather narrow, and prevent that short channel effect from taking place, and so narrow channel can produce the too big problem of cascaded channel resistance value, all causes great difficulty in design and use.In addition, existing FINFET is when carrying out the step of metal silication, and the particularly narrow channel of the structure of FINFET is very easy to be damaged.
Therefore, a purpose of the present invention is used reaching the control sensitivity of increase grid voltage to drain current for a kind of field-effect transistor with neck shape channel is provided, and prevents the short channel effect generation, and when improving the target of subcritical swing, can reduce the cascaded channel resistance value simultaneously.
A further object of the present invention is for providing a kind of field-effect transistor with neck shape channel, wherein before the step of carrying out metal silication, form parcel clearance wall (wrap up spacer), use when carrying out the step of metal silication, avoid making the particularly narrow channel of structure of FINFET to be damaged.
Another purpose of the present invention is for providing a kind of manufacture method with field-effect transistor of neck shape channel, in order to forming source electrode, drain electrode and neck shape channel effectively, and follow-up grid and parcel clearance wall etc.
According to above-mentioned purpose of the present invention, therefore the invention provides a kind of field-effect transistor and manufacture method thereof with neck shape channel.Field-effect transistor with neck shape channel of the present invention comprises at least: SOI (Silicon On Insulator) substrate or similar board structure, wherein this substrate comprises silicon substrate, is formed at the obstacle oxide layer (barrier oxide) on the silicon substrate and is formed at silicon material layer on the obstacle oxide layer; By the made source electrode of silicon material layer, drain electrode and the neck shape channel that is connected source electrode and drain electrode, wherein the Breadth Maximum of this neck shape channel is positioned at the two ends of channel, and minimum widith is positioned at the centre position of channel; Be formed at the grid in the centre position of neck shape channel; And the parcel clearance wall, wherein wrap up the active area that clearance wall covers channel and source electrode and drain electrode.
In other words, the field-effect transistor with neck shape channel of the present invention comprises at least: a substrate, and wherein this substrate comprises: a base material; One obstacle oxide layer is formed on this base material; And one silicon material layer be formed on this obstacle oxide layer; One source pole; One drain electrode; One neck shape channel, wherein this neck shape channel is connected between this source electrode and this drain electrode, and this source electrode, this drain electrode and this neck shape channel are made by this silicon material layer, and this neck shape channel has one first width and less than one second width of this first width, this first width is positioned at an end and the other end of this neck shape channel approximately, this second width is positioned at a centre position of this neck shape channel approximately, being shaped as by this end of this neck shape channel is contracted to this centre position gradually, is expanded to this other end gradually by this centre position again; And a grid layer, wherein this grid layer is formed at this centre position of this neck shape channel, and this grid layer comprises at least: a grid oxic horizon is formed at the peripheral side in this centre position of this neck shape channel; And one gate material layers be deposited on this grid oxic horizon.
In addition, the manufacture method with field-effect transistor of neck shape channel of the present invention comprises at least: a substrate is provided, and SOI substrate for example, wherein this substrate comprises that silicon substrate, obstacle oxide layer are formed on the silicon substrate and silicon material layer is formed on the obstacle oxide layer; Silicon material layer is carried out photoetching and etch process forms neck shape channel, source electrode and drain electrode with active area mask (ODmask); And form grid oxic horizon around the centre position of neck shape channel, wherein also can form hard mask layer (for example oxide or nitride) behind the top in the centre position of channel, again deposition of gate material, for example polysilicon or metal material; Deposit with etch process and form the parcel clearance wall, for example oxide or nitride are to cover the active area of channel and source electrode and drain electrode.
Major advantage of the present invention is for providing a kind of field-effect transistor with neck shape channel, reaching of the control sensitivity of increase grid voltage to drain current, prevent that short channel effect from taking place, and when improving the target of subcritical swing, can reduce cascaded channel resistance simultaneously.And the two ends broad of channel of the present invention, so be difficult for being damaged by the metal silication step.
An advantage more of the present invention is for providing a kind of field-effect transistor with neck shape channel, the present invention formed the parcel clearance wall before carrying out the metal silication step, so when carrying out the step of metal silication, can avoid making the particularly narrow channel of structure of FINFET to be damaged.
Another advantage of the present invention can form source electrode, drain electrode and neck shape channel effectively for a kind of manufacture method with field-effect transistor of neck shape channel is provided, and follow-up grid and parcel clearance wall etc.
Description of drawings
Preferred embodiment of the present invention will be aided with following accompanying drawing and do more detailed elaboration in comment backward, wherein:
Fig. 1 is the elevational schematic view that illustrates the channel architecture of existing FINFET;
Fig. 2 is the elevational schematic view that illustrates the channel architecture of the field-effect transistor with neck shape channel of the present invention;
Fig. 3 illustrates the elevational schematic view with field-effect transistor of neck shape channel of the present invention, and wherein clearance wall does not form as yet;
Fig. 4 illustrates the generalized section with field-effect transistor of neck shape channel of the present invention (direction by the A-A of Fig. 3 is seen);
Fig. 5 illustrates the elevational schematic view with field-effect transistor of neck shape channel of the present invention, and wherein clearance wall forms; And
Fig. 6 A to Fig. 6 D is the generalized section (direction by the B-B of Fig. 3 is seen) of flow process that illustrates the manufacture method of the field-effect transistor with neck shape channel of the present invention.
Symbol description among the figure:
12 base materials
15 obstacle oxide layers
18 silicon material layers
20 source electrodes
30 drain electrodes
80,100 channels
102 minimum widiths
104 Breadth Maximums
200 grid layers
220 grid oxic horizons
230 hard mask layers
240 gate material layers
320,330,340,350 parcel clearance walls
Embodiment
The present invention discloses a kind of field-effect transistor and manufacture method thereof with neck shape channel.So-called neck shape channel is meant that the channel between source electrode and drain electrode is the thin structure in wide centre, two ends, but not the elongated square channel 80 of existing FINFET as shown in Figure 1.
Please refer to Fig. 2, Fig. 2 is the elevational schematic view that illustrates the channel architecture of the field-effect transistor with neck shape channel of the present invention.One of principal character of the present invention is to provide a neck shape channel 100, and the centre position of this neck shape channel 100 is about minimum widith 102, and two ends then are about Breadth Maximum 104 respectively.Being shaped as by the end with Breadth Maximum 104 of neck shape channel 100 is contracted to the centre position with minimum widith 102 gradually, and the centre position that has minimum widith 102 more thus is expanded to the other end with Breadth Maximum 104 gradually.Minimum widith 102 for example can be: about 10 nanometers are to about 50 nanometers, and using fully to reach increases the control sensitivity of grid voltage to drain current, improves subcritical swing, and prevents the target that short channel effect takes place.Simultaneously, because there is Breadth Maximum 104 at two ends, its width is much larger than minimum widith 102, so compare with the elongated square channel 80 of as shown in Figure 1 existing FINFET, the channel 100 with field-effect transistor of neck shape channel of the present invention can reduce the cascaded channel resistance value significantly.In addition, when the step of carrying out metal silication when reducing the resistance value of metal-oxide half field effect transistor, because the two ends of channel 100 of the present invention are brought in widely more than two of existing channel 80, so the also more existing channel of the ability of channel 100 anti-infringements 80 is high.
Please refer to Fig. 3 and Fig. 4, Fig. 3 illustrates the elevational schematic view with field-effect transistor of neck shape channel of the present invention, and wherein clearance wall does not form as yet; And Fig. 4 illustrates the generalized section with field-effect transistor of neck shape channel of the present invention (direction by the A-A of Fig. 3 is seen).Field-effect transistor with neck shape channel of the present invention comprises at least: a substrate, this substrate can be the substrate of SOI substrate or other similar structures, wherein this substrate include base material 12 as silicon substrate, be formed at the obstacle oxide layer 15 on the base material 12 and be formed at silicon material layer 18 on the obstacle oxide layer 15.The present invention also comprises at least: made source electrode 20, drain electrode 30 and be connected source electrode 20 and 30 the neck shape channel 100 of draining on silicon material layer 18, wherein about Breadth Maximum of this neck shape channel 100 is positioned at the two ends of neck shape channel 100, and its about minimum widith is positioned at the centre position of neck shape channel 100.Being shaped as by the end with about Breadth Maximum of neck shape channel 100 is contracted to the centre position with about minimum widith gradually, and the centre position that has about minimum widith more thus is expanded to the other end with about Breadth Maximum gradually.The present invention comprises again at least: grid layer 200 is formed at the centre position of neck shape channel 100, wherein this grid layer 200 comprises at least: grid oxic horizon 220 is formed at the peripheral side in the centre position of neck shape channel 100, wherein also can have hard mask layer 230 (for example oxide or nitride) to be formed at the top in the centre position of neck shape channel 100; To be deposited on grid oxic horizon 220 and the hard mask layer 230 (nonessential) with gate material layers 240 (for example polysilicon or metal material).
Please refer to Fig. 5, Fig. 5 illustrates the elevational schematic view with field-effect transistor of neck shape channel of the present invention, and wherein clearance wall forms.Field-effect transistor with neck shape channel of the present invention also comprises at least: parcel clearance wall 320,330,340 and 350, wherein wrap up clearance wall 340 and 350 and cover neck shape channel 100, parcel clearance wall 320 and 330 covers the active area of source electrode 20 and drain electrode 30, and parcel clearance wall 320,330,340 and 350 for example can be silica or silicon nitride is made.When the step of carrying out metal silication when reducing the resistance value of metal-oxide half field effect transistor; parcel clearance wall 340 and 350 can be protected channel 100; parcel clearance wall 320 and 330 can be protected the active area of source electrode 20 and drain electrode 30; use and avoid the active area of channel 100 and source electrode 20 and drain electrode 30 to suffer damage.
In addition, please refer to Fig. 6 A to Fig. 6 D, Fig. 6 A to Fig. 6 D is the generalized section (direction by the B-B of Fig. 3 is seen) of flow process that illustrates the manufacture method of the field-effect transistor with neck shape channel of the present invention.Manufacture method with field-effect transistor of neck shape channel of the present invention comprises the following steps at least.At first, as shown in Figure 6A, provide a substrate, SOI substrate for example, wherein the formation method of this substrate comprises provides a base material 12 as silicon substrate; Form obstacle oxide layer 15 on base material 12; And form silicon material layer 18 on obstacle oxide layer 15.Then, as Fig. 6 B
Shown in, silicon material layer is carried out photoetching and etch process forms neck shape channel 100, source electrode 20 and drains 30 with OD mask (mask).Then, shown in Fig. 6 C, form grid oxic horizon 220, wherein also can form hard mask layer 230 (for example: oxide or nitride) behind the top in the centre position of channel in the peripheral side in the centre position of neck shape channel.Then, shown in Fig. 6 D, deposition of gate material layer 240 (for example: polysilicon or metal material) is on grid oxic horizon 220 and hard mask layer 230 (nonessential) again, then deposit and etch process, form parcel clearance wall 340 and 350 and cover channel 100, cover the active area of source electrode 20 and drain electrode 30 with parcel clearance wall 320 and 330, parcel clearance wall 320,330,340 and 350 can be for example oxide or nitride.
As understood by those skilled in the art, the above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the scope of claims.
Claims (10)
1. field-effect transistor with neck shape channel comprises at least:
One substrate, wherein this substrate comprises:
One base material;
One obstacle oxide layer is formed on this base material; And
One silicon material layer is formed on this obstacle oxide layer;
One source pole;
One drain electrode;
One neck shape channel, wherein this neck shape channel is connected between this source electrode and this drain electrode, and this source electrode, this drain electrode and this neck shape channel are made by this silicon material layer, and this neck shape channel has one first width and less than one second width of this first width, this first width is positioned at an end and the other end of this neck shape channel, this second width is positioned at a centre position of this neck shape channel, being shaped as by this end of this neck shape channel is contracted to this centre position gradually, is expanded to this other end gradually by this centre position again; And
One grid layer, wherein this grid layer is formed at this centre position of this neck shape channel, and this grid layer comprises at least:
One grid oxic horizon is formed at the peripheral side in this centre position of this neck shape channel; And
One gate material layers is deposited on this grid oxic horizon.
2. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: this field-effect transistor with neck shape channel also comprises at least:
A plurality of parcel clearance walls, wherein these parcel clearance walls cover the active area of this neck shape channel and this source electrode and this drain electrode.
3. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: this base material is a silicon substrate.
4. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: this substrate is the SOI substrate.
5. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: the material of this gate material layers is a polysilicon.
6. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: the material of this gate material layers is a metal material.
7. the field-effect transistor with neck shape channel as claimed in claim 2 is characterized in that: the material of these parcel clearance walls is a silica.
8. the field-effect transistor with neck shape channel as claimed in claim 2 is characterized in that: the material of these parcel clearance walls is a silicon nitride.
9. the manufacture method with field-effect transistor of neck shape channel is characterized in that, comprises at least:
One substrate is provided, and wherein the formation method of this substrate comprises:
One base material is provided;
Form an obstacle oxide layer on this base material; And
Form a silicon material layer on this obstacle oxide layer;
This silicon material layer is carried out photoetching and etch process forms a neck shape channel, one source pole and a drain electrode with the active area mask;
Form the peripheral side of a grid oxic horizon in a centre position of this neck shape channel; And
Deposit a gate material layers on this grid oxic horizon.
10. the manufacture method with field-effect transistor of neck shape channel as claimed in claim 9 is characterized in that: this manufacture method with field-effect transistor of neck shape channel also comprises at least:
Deposit with etch process to form the active area that a plurality of parcel clearance walls cover this neck shape channel and this source electrode and this drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02122346 CN1218400C (en) | 2002-06-14 | 2002-06-14 | EFT with neck shape channel and mfg. method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02122346 CN1218400C (en) | 2002-06-14 | 2002-06-14 | EFT with neck shape channel and mfg. method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466226A CN1466226A (en) | 2004-01-07 |
| CN1218400C true CN1218400C (en) | 2005-09-07 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02122346 Expired - Lifetime CN1218400C (en) | 2002-06-14 | 2002-06-14 | EFT with neck shape channel and mfg. method thereof |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI292933B (en) * | 2004-03-17 | 2008-01-21 | Imec Inter Uni Micro Electr | Method of manufacturing a semiconductor device having damascene structures with air gaps |
| US6951784B1 (en) * | 2004-08-05 | 2005-10-04 | International Business Machines Corporation | Three-mask method of constructing the final hard mask used for etching the silicon fins for FinFETs |
| CN107039281B (en) | 2011-12-22 | 2021-06-18 | 英特尔公司 | Semiconductor device having a neck-shaped semiconductor body and method of forming semiconductor bodies of different widths |
| CN111665669A (en) * | 2015-01-08 | 2020-09-15 | 群创光电股份有限公司 | Display panel |
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2002
- 2002-06-14 CN CN 02122346 patent/CN1218400C/en not_active Expired - Lifetime
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| CN1466226A (en) | 2004-01-07 |
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