CN117955513A - Electronic device with high linearity receiver and low linearity receiver - Google Patents

Abstract

The present disclosure relates to electronic devices having a high linearity receiver and a low linearity receiver. An electronic device may be provided with a wireless circuit having an antenna, a primary receiver, and a secondary receiver. The main receiver may be coupled to the antenna through a first signal path having a low noise amplifier. An input of the primary receiver may be coupled to the first signal path and an input of the secondary receiver may be coupled to a node on the first signal path through a second signal path. The primary receiver may consume more power and exhibit greater linearity than the secondary receiver. The secondary receiver may wake up when the primary receiver sleeps and may wake up when a paging signal is received. The wireless circuitry may switch between a single receiver mode and a receiver diversity mode based on wireless performance metric data collected by the primary receiver and/or the secondary receiver, if desired.

Description

Electronic device with high linearity receiver and low linearity receiver

The present application claims priority from U.S. patent application Ser. No. 18/474,921, filed on month 26 of 2023, and U.S. provisional patent application Ser. No. 63/420,067, filed on month 27 of 2022, which are hereby incorporated by reference in their entireties.

Technical Field

The present disclosure relates generally to wireless communications, including wireless communications performed by electronic devices.

Background

The communication system may include an electronic device having wireless communication capabilities. Electronic devices with wireless communication capabilities use antennas to transmit and receive radio frequency signals. An electronic device with wireless communication capability may have a limited amount of power, such as power provided by a battery.

If careless, receiving the radio frequency signal may consume excessive power, thereby minimizing battery life of the electronic device. On the other hand, increasing power consumption may help ensure that the electronic device receives the radio frequency signal correctly.

Disclosure of Invention

The electronic device may be provided with a wireless circuit. The wireless circuit may include an antenna, a primary receiver, and a secondary receiver. The primary receiver may be coupled to the antenna through a first signal path. A first Low Noise Amplifier (LNA) may be disposed on the first signal path. The primary receiver may have a second LNA having an input coupled to the first signal path. The primary receiver may have a first Digital Signal Processor (DSP) coupled to an output of the second LNA. The secondary receiver may have a third LNA having an input coupled to a node on the first signal path through the second signal path. A node may be disposed on the first signal path between an output of the first LNA and an input of the second LNA. The secondary receiver may have a second DSP coupled to the output of the third LNA.

The primary receiver may include circuitry with higher complexity that consumes more power, operates at a higher sampling rate, and exhibits more linearity than circuitry in the secondary receiver. The antenna may receive radio frequency energy. The first LNA may transfer radio frequency energy to both the primary receiver and the secondary receiver simultaneously. While the primary receiver is sleeping, the secondary receiver may periodically wake up to listen for Physical Downlink Control Channel (PDCCH) signals, such as paging signals. When the secondary receiver successfully decodes the PDCCH signal indicating the data allocation of the device requiring higher linearity than supported by the secondary receiver, the secondary receiver may wake up the primary receiver for a subsequent data reception cycle. The primary receiver may then decode the signal from the radio frequency energy using a higher degree of linearity.

If desired, the radio circuit may switch between a single receiver mode (such as a high linearity mode in which the primary receiver wakes up and the secondary receiver sleeps, or a low linearity mode in which the primary receiver sleeps and the secondary receiver wakes up) and a receiver diversity mode in which both the primary and secondary receivers wake up. One or both receivers may collect wireless performance metric data from the received radio frequency energy. The one or more processors may compare the wireless performance metric data to one or more thresholds to select an operating mode to be used during a subsequent data reception cycle. For example, a single receiver mode may be used when the radio performance metric data exceeds a threshold, and a receiver diversity mode may be used when the radio performance metric data falls below the threshold.

One aspect of the present disclosure provides an electronic device. The electronic device may include an antenna. The electronic device may include a first receiver having a first Low Noise Amplifier (LNA). The electronic device may include a second receiver having a second LNA. The electronic device may include a first signal path coupling the antenna to an input of the first LNA. The electronic device may include a third LNA disposed on the first signal path. The electronic device may include a second signal path coupling a node on the first signal path to an input of the second LNA, the node being disposed between an output of the third LNA and an input of the first LNA on the first signal path.

An aspect of the present disclosure provides a method of operating an electronic device. The method may include receiving radio frequency energy using an antenna. The method may include transferring the radio frequency energy to a second LNA in a first receiver using a Low Noise Amplifier (LNA) and simultaneously to a third LNA in a second receiver, wherein the second receiver consumes less power than the first receiver. The method may include attempting to use the second receiver to decode a Physical Downlink Control Channel (PDCCH) signal from the radio frequency energy while the first receiver is asleep. The method may include waking up the first receiver for a subsequent data reception cycle using the second receiver in response to the second receiver decoding the PDDCH signal.

An aspect of the present disclosure provides a method of operating an electronic device. The method may include receiving radio frequency energy using an antenna. The method may include delivering the radio frequency energy to a first receiver using a Low Noise Amplifier (LNA) and a second receiver operating at a lower sampling rate than the first receiver. The method may include generating wireless performance metric data from the radio frequency energy using the second receiver during a first period of time. The method may include attempting to decode a signal from the radio frequency energy using the first receiver and the second receiver during a second period subsequent to the first period in response to the wireless performance metric data collected during the first period being less than a threshold.

Drawings

Fig. 1 is a schematic block diagram of an exemplary electronic device with wireless circuitry according to some embodiments.

Fig. 2 is a circuit diagram of an exemplary radio circuit having a high linearity receiver and a low linearity receiver that receive radio frequency energy from an antenna simultaneously, according to some embodiments.

Fig. 3 is a flowchart of exemplary operations involved in using a high linearity receiver and a low linearity receiver to receive radio frequency signals using an antenna, according to some embodiments.

Fig. 4 is a timing diagram illustrating how a low linearity receiver and a high linearity receiver may be activated to receive a radio frequency signal according to some embodiments.

Fig. 5 is a state diagram illustrating how high linearity and low linearity receivers may be switched between low linearity, high linearity, and receiver diversity operation modes according to some embodiments.

Fig. 6 is a circuit diagram showing how a supplemental low noise amplifier may be switched for a low linearity receiver according to some embodiments.

Fig. 7 is a flowchart of exemplary operations involved in switching a low linearity receiver and a high linearity receiver between a single receiver and a receiver diversity mode of operation based on collected wireless performance metric data, according to some embodiments.

Fig. 8 is a graph showing how exemplary wireless performance metric data may be compared to different thresholds for switching a low linearity receiver and a high linearity receiver between a single receiver and a receiver diversity mode of operation, according to some embodiments.

Detailed Description

Fig. 1 is a block diagram of an exemplary electronic device 10. The device 10 may be: computing devices such as laptop computers, desktop computers, computer monitors including embedded computers, tablet computers, cellular telephones (mobile telephones), media players, or other handheld or portable electronic devices; smaller devices such as wristwatch devices, hanging devices, earphone or earpiece devices, devices embedded in eyeglasses; or other equipment worn on the user's head; or other wearable or miniature devices, televisions, computer displays that do not contain embedded computers, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with displays is installed in kiosks or automobiles), voice-controlled speakers connected to the wireless internet, home entertainment devices, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that implements the functionality of two or more of these devices; or other electronic equipment.

As shown in fig. 1, device 10 may include components located on or within an electronic device housing, such as housing 12. The housing 12 (which may sometimes be referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or a combination of these materials. In some cases, some or all of the housing 12 may be formed of a dielectric or other low conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, the housing 12 or at least some of the structures making up the housing 12 may be formed from metal elements.

The device 10 may include a control circuit 14. The control circuit 14 may include a memory device, such as the memory circuit 18. The storage circuitry 18 may include hard drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid state drive), volatile memory (e.g., static random access memory or dynamic random access memory), and the like. The storage circuitry 18 may include storage and/or removable storage media integrated within the device 10.

The control circuit 14 may include processing circuitry, such as processing circuitry 16. The processing circuitry 16 may be used to control the operation of the device 10. The processing circuitry 16 may include one or more processors, such as microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application specific integrated circuits, central Processing Units (CPUs), graphics Processing Units (GPUs), and the like. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and/or software. The software code for performing operations in the device 10 may be stored on the storage circuitry 18 (e.g., the storage circuitry 18 may comprise a non-transitory (tangible) computer-readable storage medium storing the software code). The software code may sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on the memory circuit 18 may be executed by the processing circuit 16.

Control circuitry 14 may be used to run software, such as one or more software applications (applications), on device 10. The applications may include satellite navigation applications, internet browsing applications, voice Over Internet Protocol (VOIP) telephone call applications, email applications, media playback applications, operating system functions, gaming applications, productivity applications, workplace applications, augmented Reality (AR) applications, augmented reality (XR) applications, virtual Reality (VR) applications, scheduling applications, consumer applications, social media applications, educational applications, banking applications, spatial ranging applications, sensing applications, security applications, media applications, streaming applications, automotive applications, video editing applications, image editing applications, rendering applications, simulation applications, camera-based applications, imaging applications, news applications, and/or any other desired software applications.

To support interaction with external communication equipment, the control circuit 14 may be used to implement a communication protocol. Communication protocols that may be implemented using control circuitry 14 include Internet protocol, wireless Local Area Network (WLAN) protocol (e.g., IEEE 802.11 protocol-sometimes referred to as) Such as/> Protocols or other Wireless Personal Area Network (WPAN) protocols, etc. for other short-range wireless communication links, IEEE 802.11ad protocols (e.g., ultra wideband protocols), cellular telephone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP fifth generation (5G) New Radio (NR) protocols, 6G protocols, cellular sideband protocols, etc.), device-to-device (D2D) protocols, antenna diversity protocols, satellite navigation system protocols (e.g., global Positioning System (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols, or any other desired communication protocol. Each communication protocol may be associated with a corresponding Radio Access Technology (RAT) that specifies the physical connection method used to implement the protocol. Radio frequency signals transmitted using a cellular telephone protocol may sometimes be referred to herein as cellular telephone signals.

The device 10 may include an input-output device 20. An input-output (I/O) device 20 may be used to allow data to be supplied to the device 10 and to allow data to be provided from the device 10 to an external device. The input-output device 20 may include user interface devices, data port devices, and other input-output components. For example, the input-output device 20 may include a touch sensor, a display (e.g., a touch-sensitive display and/or a force-sensitive display), a light-emitting component such as a display without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touch pads, keypads, keyboards, microphones, cameras, image sensors, light sensors, radar sensors, lidar sensors, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and/or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to the display to detect pressure applied to the display), temperature sensors, and the like. In some configurations, keyboards, headphones, displays, pointing devices such as touch pads, mice, and joysticks, and other input-output devices may be coupled to device 10 using wired or wireless connections (e.g., some of input-output devices 20 may be peripheral devices coupled to a main processing unit or other portion of device 10 via wired or wireless links).

The electronic device 10 may include a wireless circuit 24. The wireless circuitry 24 may support wireless communications. The wireless circuitry 24 (sometimes referred to herein as wireless communications circuitry 24) may include one or more antennas 34. The antenna 34 may transmit radio frequency signals to and/or may receive radio frequency signals from external communication equipment. The external communication equipment may include one or more other electronic devices, such as device 10, a wireless base station, or a wireless access point (as examples).

The wireless circuitry 24 may also include one or more radios 30. The radio 30 may include circuitry (e.g., baseband circuitry) and radio frequency transceiver circuitry that operate on signals at baseband frequencies, such as one or more radio frequency Transmitters (TX) 31 and two or more radio frequency Receivers (RX) 36. Each transmitter 31 may include signal generator circuitry, modulation circuitry, mixer circuitry for up-converting signals from baseband frequencies to intermediate and/or radio frequencies, amplifier circuitry such as one or more power amplifiers, digital-to-analog converter (DAC) circuitry, control paths, power paths, switching circuitry, filter circuitry, and/or any other circuitry for transmitting radio frequency signals using antenna 34. Each receiver 36 may include demodulation circuitry, mixer circuitry for down-converting signals from intermediate and/or radio frequencies to baseband frequencies, amplifier circuitry (e.g., one or more Low Noise Amplifiers (LNAs)), analog-to-digital converter (ADC) circuitry, control paths, power paths, signal paths, switching circuitry, filter circuitry, and/or any other circuitry for receiving radio frequency signals using the antenna 34. The components of the radio component 30 may be mounted on a single substrate or integrated into a single integrated circuit, chip, package, or system on a chip (SOC) or may be distributed among multiple substrates, integrated circuits, chips, packages, or SOCs.

The radio 30 (e.g., transmitter 31 and/or receiver 36) may be coupled to one or more antennas 34 through one or more signal paths 32. Each signal path 32 may include one or more radio frequency transmission lines, switching circuits, filter circuits, coupler circuits, and the like. The radio frequency transmission lines in the signal path 32 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from combinations of these types of transmission lines, and the like. The radio frequency transmission lines in the signal path 32 may be integrated into rigid and/or flexible printed circuit boards, if desired. One or more signal paths 32 (e.g., one or more radio frequency transmission lines in one or more signal paths 32) may be shared between multiple transmitters 31 and/or multiple receivers 36 in a radio 30 and/or between multiple radios 31. If desired, one or more Radio Frequency Front End (RFFE) modules may be interposed on one or more signal paths 32 (e.g., external to radio 30).

In performing wireless transmission, baseband circuitry in radio 30 may provide baseband signals (e.g., digital signals containing wireless data for transmission to one or more other devices) to transmitter 31. For example, the baseband circuitry may process the incoming digital data by encoding, modulation/demodulation, time and frequency conversion, pulse shaping, etc., to generate processed baseband data that is transmitted by the baseband signal. The transmitter 31 may modulate the processed baseband data onto a radio frequency signal for transmission by the antenna 34. For example, the transmitter 31 may include a mixer circuit and a local oscillator circuit for up-converting the baseband signal to radio frequency prior to transmission through the antenna 34. The transmitter may also include digital-to-analog converter (DAC) circuitry for converting signals between the digital and analog domains, amplification circuitry (e.g., power amplification circuitry) for amplifying radio frequency signals, filter circuitry, switching circuitry, and the like. The transmitter may transmit radio frequency signals via signal path 32 through antenna 34. The antenna 34 may transmit the radio frequency signal to external wireless equipment by radiating the radio frequency signal into free space.

The antenna 34 may be formed using any desired antenna structure for transmitting radio frequency signals. For example, the antenna 34 may include an antenna having a resonating element formed from a loop antenna structure, a patch antenna structure, an inverted-F antenna structure, a slot antenna structure, a planar inverted-F antenna structure, a helical antenna structure, a monopole antenna, a dipole, a hybrid of these designs, or the like. Filter circuitry, switching circuitry, impedance matching circuitry, and/or other antenna tuning components may be adjusted to adjust the frequency response and wireless performance of the antenna 34 over time. If desired, two or more of the antennas 34 may be integrated into a phased antenna array (sometimes referred to herein as a phased array antenna) in which each antenna transmits radio frequency signals having respective phases and magnitudes that are adjusted over time so that the radio frequency signals constructively and destructively interfere to produce a signal beam in a given/selected beam pointing direction (e.g., toward external communication equipment).

As used herein, the term "transmit radio frequency signal" means transmission and/or reception of a radio frequency signal (e.g., for performing unidirectional and/or bidirectional wireless communications with external wireless communication equipment). Similarly, the term "transmitting wireless data" as used herein means transmitting and/or receiving wireless data using radio frequency signals. The antenna 34 may transmit radio frequency signals by radiating radio frequency signals into free space (or through intervening device structures such as dielectric cover layers). Additionally or alternatively, antenna 34 may receive radio frequency signals from free space (e.g., through an intervening device structure such as a dielectric cover layer). The transmission and reception of radio frequency signals by the antenna 34 each involves the current excitation or resonance of the antenna on an antenna resonating element in the antenna by radio frequency signals within the operating band of the antenna.

In performing wireless reception, the antenna 34 may receive radio frequency signals from one or more other devices (external communication equipment). The antenna 34 may communicate received radio frequency signals through a signal path 32 to one or more receivers 36 in the radio 30. Each receiver 36 may include demodulation circuitry (e.g., a corresponding Digital Signal Processor (DSP)), mixer circuitry for down-converting signals from intermediate and/or radio frequencies to baseband frequencies, amplifier circuitry (e.g., one or more Low Noise Amplifiers (LNAs)), analog-to-digital converter (ADC) circuitry, control paths, power paths, signal paths, switching circuitry, filter circuitry, and/or any other circuitry for receiving radio frequency signals using the antenna 34. The receiver may convert the received radio frequency signal to a baseband signal (e.g., digital data samples). The receiver may transmit baseband signals to baseband circuitry (e.g., DSP) through a digital interface. The baseband circuitry may process incoming digital data from the received baseband signal by decoding, demodulation, time and frequency conversion, pulse shaping, etc., to extract wireless data from the baseband signal. The extracted wireless data may be passed up the protocol stack or to an application processor for further processing.

The radio 30 may transmit and/or receive radio frequency signals within a corresponding frequency band of radio frequencies (sometimes referred to herein as a communication band or simply "band"). The frequency bands processed by transceiver circuitry 30 may include Wireless Local Area Network (WLAN) frequency bands (e.g.,(IEEE 802.11) or other WLAN communication bands) such as the 2.4GHz WLAN band (e.g., 2400MHz to 2480 MHz), the 5GHz WLAN band (e.g., 5180MHz to 5825 MHz),/>6E band (e.g., 5925MHz to 7125 MHz) and/or other/>A band (e.g., 1875MHz to 5160 MHz); wireless Personal Area Network (WPAN) bands such as 2.4GHz/>A band or other WPAN communication band; cellular telephone bands (e.g., about 600MHz to about 5GHz band, 3G band, 4G LTE band, 5G new radio frequency range 1 (FR 1) band below 10GHz, 5G new radio frequency range 2 (FR 2) band between 20GHz and 60GHz, 6G band in sub-THz or THz about 100GHz to 1000GHz, cellular sidebands, etc.); other centimeter or millimeter wave bands between 10GHz and 100 GHz; near field communication band (e.g., 13.56 MHz); satellite navigation frequency bands (e.g., GPS band 1565MHz to 1610MHz, global navigation satellite System (GLONASS) band, beidou satellite navigation System (BDS) band, etc.); an Ultra Wideband (UWB) band operating under the IEEE 802.15.4 protocol and/or other ultra wideband communication protocols; a communication band under the 3GPP family of wireless communication standards; a communications band under the IEEE 802.Xx family of standards; industrial, scientific, and medical (ISM) bands, such as ISM bands between about 900MHz and 950MHz or other ISM bands below or above 1 GHz; one or more unauthorized bands; one or more bands reserved for emergency services and/or public services; and/or any other desired band of interest. The wireless circuitry 24 may also be used to perform spatial ranging (e.g., radar) operations, if desired.

The example of fig. 1 is illustrative and not limiting. Although, for clarity, in the example of fig. 1, control circuit 14 is shown separate from wireless circuit 24, wireless circuit 24 may include processing circuitry (e.g., one or more processors) that forms part of processing circuit 16 and/or storage circuitry that forms part of storage circuit 18 of control circuit 14 (e.g., portions of control circuit 14 may be implemented on wireless circuit 24). As one example, the control circuitry 14 may include baseband circuitry (e.g., one or more baseband processors), digital control circuits, analog control circuits, and/or other control circuits forming part of the radio 30. The baseband circuitry may, for example, access a communication protocol stack on the control circuitry 14 (e.g., the storage circuitry 18) to: executing user plane functions in a PHY layer, a MAC layer, an RLC layer, a PDCP layer, an SDAP layer and/or a PDU layer; and/or performing control plane functions at a PHY layer, a MAC layer, an RLC layer, a PDCP layer, an RRC layer, and/or a non-access stratum (NAS).

During wireless communications, external equipment (e.g., base stations of a cellular telephone network, schedulers associated with or managed by the network, etc.) may allocate time and/or frequency resources to the device 10 for transmitting data (e.g., in an uplink direction from the device 10 to the base stations and/or in a downlink direction from the base stations to the device 10). The device 10 may have a battery to power the components of the device 10. Thus, the device 10 typically has a limited amount of power (e.g., when the device is not connected to an external power source such as a charger or an electrical outlet).

Depending on the received signal quality and data allocation, the receiver may adapt its performance in order to minimize power and save battery. For example, a receiver may adapt its linearity and power consumption depending on different metrics, such as signal-to-noise ratio (SNR) of the received signal, presence of interference, and signal monitoring. The receiver may consume less power to operate with less linearity and may consume more power to operate with greater linearity. The receiver may operate with less linearity (lower power) when the received signal to be decoded is robust (e.g., modulated using a low order modulation scheme) and there is no interference that stresses the dynamic range of the receiver. On the other hand, the receiver may operate with greater linearity (higher power) when interference is present and/or when a high modulation order is used to modulate the received signal to be decoded.

However, in practice, changing the configuration of a single receiver to operate with low or high linearity can be challenging. For example, it may be difficult to synchronize receiver timing and DSP optimization for the receiver over time because the received signal must first be processed by the entire receive chain even if there is no data allocation (e.g., physical Downlink Shared Channel (PDSCH) allocation) after the corresponding Physical Downlink Control Channel (PDCCH) signal has been received.

To alleviate these problems and at the same time allow the device 10 to reduce its overall power consumption, the wireless circuit 24 may include at least a first receiver 36 having a relatively high linearity and a second receiver 36 having a relatively low linearity for receiving radio frequency signals using the corresponding antenna 34. Fig. 2 is a circuit diagram illustrating an example of how the wireless circuit 24 may include at least a first receiver 36 having a relatively high linearity and a second receiver 36 having a relatively low linearity for receiving radio frequency signals using the corresponding antenna 34.

As shown in fig. 2, the wireless circuit 24 may include a first receiver 36, such as receiver 36A, and a second receiver 36, such as receiver 36B. Receiver 36A may sometimes be referred to herein as primary receiver 36A. Receiver 36B may sometimes be referred to herein as secondary receiver 36B. A given antenna 34 may be coupled to an input of a primary receiver 36A through a first signal path, such as signal path 32-1 (e.g., a first radio frequency transmission line). A first amplifier, such as a Low Noise Amplifier (LNA) 38, may be disposed on signal path 32-1. An input of LNA 38 may be coupled to antenna 34. An output of LNA 38 may be coupled to an input of main receiver 36A.

The wireless circuit 24 may also include a second signal path, such as signal path 32-2 (e.g., a second radio frequency transmission line), coupled to an input of the secondary receiver 36B. Signal path 32-2 may be coupled to signal path 32-1 at a radio frequency node, such as node 60. Node 60 may be disposed on signal path 32-1 between the output of LNA 38 and the input of main receiver 36A. Node 60 may include a radio frequency signal splitter or splitter, a radio frequency coupler, or other passive circuit that passes the radio frequency signal output by LNA 38 to both primary receiver 36A and secondary receiver 36B. Node 60 may have no switch.

The main receiver 36A may include front-end circuitry 40A and baseband circuitry such as DSP 52. The input of front-end circuit 40A and thus primary receiver 36A may be coupled to signal path 32-1. An output of front-end circuit 40A may be coupled to an input of DSP 52. In other words, signal path 32-1, LNA 38, and front-end circuit 40A may form a receive chain or receive path for main receiver 36A.

Similarly, secondary receiver 36B may include front-end circuitry 40B and baseband circuitry such as DSP 54. The input of front-end circuit 40B and thus secondary receiver 36B may be coupled to signal path 32-2. An output of front-end circuit 40B may be coupled to an input of DSP 54. In other words, signal path 32-1, LNA 38, node 60, signal path 32-2, and front-end circuit 40B may form a receive chain or receive path for secondary receiver 36B. DSP 54 in secondary receiver 36B may be coupled to DSP 52 in primary receiver 36A by control path 56 (e.g., an inter-receiver or inter-processor digital control path).

Front-end circuits 40A and 40B may each include a respective input amplifier (such as LNA 42), a mixer circuit (such as mixer 44 coupled to the output of LNA 42) (e.g., in an in-phase and quadrature-phase (I/Q) mixer in implementations in which front-end 40A includes an I/Q path between LNA 42 and a corresponding DSP), a filter circuit (such as a Low Pass Filter (LPF) 46 coupled to the output of mixer 44), an additional amplifier (such as a Variable Gain Amplifier (VGA) 48 coupled to the output of LPF 46), and a converter circuit (such as an analog-to-digital converter (ADC) coupled to the output of VGA 48).

An input of LNA 42 in front-end circuit 40A may be coupled to signal path 32-1. The output of the ADC 50 in the front-end circuit 40A may be coupled to the DSP 52. An input of LNA 42 in front-end circuit 40B may be coupled to signal path 32-2. The output of the ADC 50 in the front-end circuit 40B may be coupled to the DSP 54. If desired, both the primary receiver 36A and the secondary receiver 36B may be disposed on a common substrate such as a system on a chip (SOC) 58 (e.g., a radio frequency SOC or an integrated circuit package). Receivers 36A and 36B may be provided on or integrated into different respective Integrated Circuits (ICs), if desired. LNA 38 external to SOC 58 may sometimes be referred to herein as external LNA (eLNA) 38, while LNA 42 internal to SOC 58 may sometimes be referred to herein as Internal LNA (iLNA) 42 (e.g., an LNA implemented using CMOS technology on SOC 58).

The control circuit 14 (fig. 1) may control the receivers 36A and 36B to operate in a full power mode or state (sometimes referred to herein as an active or awake state) or in a reduced power mode or state (sometimes referred to herein as an inactive, sleep, or sleep state/mode). In the awake state (sometimes referred to herein as awake or active), a receiver may actively receive and process radio frequency signals (e.g., may demodulate/decode these radio frequency signals to recover wireless data from the received signals). In the awake state, components of the receiver may be fully powered or may otherwise receive a relatively high amount of power (e.g., a relatively high supply voltage).

In a sleep state (sometimes referred to herein as sleep or inactive), the receiver does not actively receive or process the radio frequency signal (e.g., does not demodulate/decode the radio frequency signal to recover wireless data from the received signal) even though the radio frequency signal may still be incident on the antenna 34. In the sleep state, one or more of the components of the receiver may be powered down or may receive a relatively low amount of power (e.g., a relatively low supply voltage).

If desired, one or more components of the receiver may continue to draw power while the receiver is in a sleep state, thereby allowing the components of the receiver to continue to meet radio frequency operating requirements (e.g., start-up time requirements, settling time requirements, etc.). The receiver may also operate in a fully powered off or off state, where no component in the receiver draws power. For example, the receiver may be in a powered-down state when the device 10 is powered down or turned off. Transitioning a receiver from a sleep state or a powered-down state to an awake state may sometimes be referred to herein as waking up or activating the receiver.

The control circuit 14 may provide control signals that switch the receiver between powered down, sleep and awake states over time as needed for communication and/or conserve battery power when not needed. As one example, the wireless circuit 24 may include one or more switches (e.g., transistors such as Field Effect Transistors (FETs), etc.) disposed on a power supply line (not shown) coupled to one or more of the components of the receiver. The switch may have a control terminal (e.g., gate terminal) that receives a control signal from control circuit 14 (fig. 1).

The control circuit 14 may use the control signals to selectively power down (disable) one or more of the components of the receiver to place the receiver in a sleep or powered down state, and to selectively power up (enable) the components of the receiver to place the receiver in an awake state. For example, when the receiver is in a sleep or power down state, the control signal may control the switches on one or more of the power supply lines to form an open circuit, to form a very high impedance (e.g., an impedance exceeding a threshold impedance value), or to form a very low transconductance g _m across the switches (e.g., a transconductance less than a threshold transconductance value) to power down one or more components of the receiver.

On the other hand, when the receiver is in the awake state, the control signal may control the switch on the power supply line to form a closed circuit, a low impedance (e.g., an impedance less than a threshold impedance value), or a high transconductance across the switch (e.g., a transconductance greater than a threshold transconductance value) to energize components of the receiver. Thus, the receiver may consume (draw) less power in the sleep state than in the active state and, if desired, may consume less power in the powered-off state than in the sleep state. In this way, power consumption in the device 10 may be reduced by placing the receiver in a sleep state when not needed, thereby maximizing battery life.

The components of the primary receiver 36A may have greater processing complexity and may consume more processing resources on the wireless circuit 24 than the components of the secondary receiver 36B. When in the awake state, the primary receiver 36A may consume more power than the secondary receiver 36B. For example, one or more of the components in the front-end circuit 40A of the primary receiver 36A may have higher complexity and/or may consume more power and thus exhibit higher linearity (e.g., higher peak/maximum linearity) and higher dynamic range (e.g., higher peak/maximum dynamic range) than corresponding components in the front-end circuit 40B of the secondary receiver 36B (e.g., the LNA 42, VGA 48, and/or ADC 50 in the front-end circuit 40A may have higher complexity and/or may consume more power than the LNA 42, VGA 48, and/or ADC 50 in the front-end circuit 40B).

Furthermore, DSP 54 in secondary receiver 36B may be implemented using circuitry that has less complexity and consumes less power than the circuitry used to implement DSP 52 of primary receiver 36A. Thus, DSP 52 is sometimes referred to herein as an all-DSP 52, while DSP 54 is sometimes referred to herein as a simplified DSP 54. The simplified DSP 54 may include dedicated processing circuitry (e.g., dedicated processing cores) that operate on a smaller set of samples (e.g., at a lower sampling rate) than the full DSP 52.

For example, the reduced DSP 54 may perform demodulation/decoding operations necessary to recover PDCCH data in the radio frequency signals received by the antenna 34, but the demodulation/decoding operations are insufficient to fully decode PDSCH data in the radio frequency signals received by the antenna 34 (e.g., the reduced DSP 54 may be optimized only for recovering received control channels, synchronization, and paging signals). On the other hand, the full DSP 52 may perform demodulation/decoding operations necessary to recover both PDSCH data and PDCCH data in the radio frequency signals received by the antenna 34. For example, the full DSP 52 may successfully decode radio frequency signals that have been modulated using a higher order modulation scheme than the simplified DSP 54.

The secondary receiver 36B may thus operate as a dedicated low power and low linearity receiver. The secondary receiver 36B may be periodically active (having relatively low linearity) such as during a DRX cycle and/or CDRX cycle (e.g., paging cycle) of the device 10 (e.g., as given by network scheduling and/or by a communication protocol that manages the receivers 36A and 36B). The secondary receiver 36B may listen (e.g., attempt to decode) for paging signals received by the antenna 34 when active. The paging signal has a low modulation order and is simple enough to be properly processed and decoded by the simplified DSP 54 despite the low linearity of the front-end circuit 40B and the low power consumption of the secondary receiver 36B. The primary receiver 36A may remain asleep while the secondary receiver 36B is active to conserve power. The secondary receiver 36B may also be sometimes referred to herein as a wake-up receiver 36B, a reduced receiver 36B, or a low linearity receiver 36B, while the primary receiver 36A is sometimes referred to herein as a high linearity receiver 36A or a full receiver 36A.

When the secondary receiver 36B receives and decodes a paging signal indicating that the network has allocated data for receipt by the device 10 (e.g., data having a higher modulation order than supported by the receiver 36B or otherwise requiring a higher linearity than supported by the receiver), the reduced DSP 54 may transmit a control signal CTRL to the primary receiver 36A over the control path 56 that wakes up the primary receiver 36A (e.g., during a next or subsequent DRX cycle). The primary receiver 36A may then enter an awake state and may receive and process (e.g., attempt to decode) data in the radio frequency signal received by the antenna 34. By activating the primary receiver 36A only when data requiring high linearity has been allocated to the device 10, power consumption in the device 10 can be minimized. Using the secondary receiver 36B to monitor the paging signal and wake-up the primary receiver 36A may alleviate timing and DSP optimization challenges associated with switching a single receiver between a low linearity state and a high linearity state.

For example, radio frequency energy may be incident on the antenna 34. Antenna 34 may transfer radio frequency energy to LNA 38 via signal path 32-1. When the external equipment transmits radio frequency signals to the device 10, the radio frequency energy may include radio frequency signals SIGRX (e.g., PDCCH signals such as paging signals or PDSCH signals carrying PDSCH data). LNA 38 may amplify the radio frequency energy (e.g., radio frequency signal SIGRX) and may simultaneously transfer the radio frequency energy to front-end circuit 40A of primary receiver 36A via signal path 32-1 and to front-end circuit 40B of secondary receiver 36B via signal path 32-2 (via node 60).

While the primary receiver 36A is asleep, the primary receiver 36A does not process or attempt to decode the received radio frequency energy. During periods in which the secondary receiver 36B wakes up, the LNA 42 in the front-end circuit 40B may further amplify the received radio frequency energy. The mixer 44 in the front-end circuit 40B may then down-convert the received radio frequency energy using a Local Oscillator (LO). LPF 46 in front-end circuit 40B may then filter the down-converted signal, which is then further amplified by VGA 48 and converted from the analog domain to the digital domain (e.g., as a digital baseband signal) using ADC 50 in front-end circuit 40B. The reduced DSP 54 may then attempt to demodulate/decode the digital baseband signal. When the reduced DSP 54 successfully resumes the paging signal for the device 10 indicating that data has been allocated by the network for receipt at the device 10, the reduced DSP 54 may wake up the primary receiver 36A.

When the primary receiver 36A wakes up, the secondary receiver 36B may sleep to save power (if needed). The secondary receiver 36B may remain asleep until the next DRX cycle, if desired. LNA 42 in front-end circuit 40A may further amplify the received radio frequency energy. The mixer 44 in the front-end circuit 40A may then down-convert the received radio frequency energy using a Local Oscillator (LO). LPF 46 in front-end circuit 40A may then filter the down-converted signal, which is then further amplified by VGA 48 and converted from the analog domain to the digital domain (e.g., as a digital baseband signal) using ADC 50 in front-end circuit 40A. The full DSP 52 may then attempt to demodulate/decode the digital baseband signal (e.g., recover PDSCH data from the received radio frequency energy). When no more data is allocated to device 10, primary receiver 36A may go back to sleep and secondary receiver 36B may continue to wake up periodically to listen for paging signals.

Fig. 3 is a flowchart of exemplary operations that may be performed by the primary receiver 36A and the secondary receiver 36B to receive radio frequency signals from external communication equipment. At operation 80, the antenna 34 may begin receiving radio frequency energy. LNA 38 may amplify the received radio frequency energy. Signal path 32-1 may pass a first portion of the radio frequency energy to primary receiver 36A. Node 60 and signal path 32-2 may simultaneously pass a second portion of the radio frequency energy to secondary receiver 36B.

At operation 82, while the primary receiver 36A is asleep, the secondary receiver 36B may begin to periodically wake up to listen for received signals with low linearity (e.g., during periodic DRX cycles, paging cycles, sync block cycles, etc.). For example, when secondary receiver 36B wakes up, reduced DSP 54 may attempt to perform PDCCH modulation on the received signal. When the secondary receiver 36B receives the appropriate paging signal (e.g., when the reduced DSP 54 successfully performs PDCCH modulation to recover the paging signal indicating that the device 10 is assigned data requiring a relatively high degree of linearity), processing may proceed to operation 84.

At operation 84, the secondary receiver 36B may transmit a control signal CTRL to the primary receiver 36A over the control path 56 to wake up the primary receiver 36A. The primary receiver 36A may then enter an awake state for the next DRX cycle.

At operation 86, the primary receiver 36A may begin receiving a radio frequency signal having a high linearity. For example, when the primary receiver 36A wakes up, the full DSP 52 may perform PDSCH demodulation on the received signal. The secondary receiver 36B may sleep to save power if desired. The primary receiver 36A may continue to receive radio frequency signals until data is no longer allocated to the device 10. At this point, the primary receiver 36A may go back to sleep and processing may loop back to operation 82 to listen for subsequent paging signals.

Fig. 4 includes a timing diagram that illustrates how receivers 36A and 36B may be activated to receive radio frequency signals. Timing diagram 90 of fig. 4 depicts operation of secondary receiver 36B, while timing diagram 92 depicts operation of primary receiver 36A. The secondary receiver 36B may wake up during the blocks 94 and may sleep between the blocks 94. As an example, block 94 may be a periodic/cyclic block corresponding to a DRX cycle, a CDRX cycle, a synchronization burst cycle (e.g., a period in which a base station transmits a synchronization signal block), a paging opportunity reception cycle (e.g., a period in which a base station transmits a paging signal), an SSB-based RRM measurement timing configuration (SMTC) window cycle (e.g., a period in which frequency scanning is performed for determining whether to perform a handoff), or other period. The block 94 need not be periodic or cyclical.

During block 94, the secondary receiver 36B may listen for paging signals or other signals indicating that the device 10 needs to transition to high linearity reception (e.g., when processing operation 82 of fig. 3). In the example of fig. 4, the secondary receiver 36B may receive the paging signal during a block 94 beginning at time TA. The secondary receiver 36B may then control the primary receiver 36A to wake up during the next DRX cycle (e.g., beginning at time TB). At this point, the secondary receiver 36B may go to sleep to save power. The master receiver 36A may wake up at time TB and may remain awake for the duration of block 96. The primary receiver 36A may sleep outside of block 96. During block 96, the primary receiver 36A may listen and may receive (attempt to decode) PDSCH data in the received radio frequency energy with high linearity (e.g., when processing operation 86 of fig. 3). Once PDSCH data is no longer allocated to the device 10 (e.g., at time TC), the primary receiver 36A may go to sleep and the secondary receiver 36B may continue to wake up during block 94 to listen for signals having low linearity.

In the example of fig. 4, only secondary receiver 36B wakes up when device 10 requires only a low level of linearity to properly decode signals (e.g., PDCCH signals) incident on antenna 34, and only primary receiver 36A wakes up when device 10 requires a high level of linearity to properly decode signals (e.g., PDSCH signals) incident on antenna 34. The wireless circuit 24 (SOC 58 of fig. 2 or radio 30 of fig. 1) may sometimes be referred to herein as operating in a low linearity mode when the secondary receiver 36B wakes up (active) and the primary receiver 36A sleeps (inactive), and may sometimes be referred to herein as operating in a high linearity mode when the primary receiver 36A wakes up and the secondary receiver 36B sleeps.

Both the high linearity mode and the low linearity mode represent a single receiver mode in which only a single one of the receivers 36A and 36B wakes up at a given time. If desired, wireless circuit 24 (SOC 58 of FIG. 2 or radio 30 of FIG. 1) may also operate in a Receiver (RX) diversity mode, wherein both receivers 36A and 36B wake up simultaneously. Fig. 5 is a state diagram showing these exemplary modes of operation for wireless circuitry 24.

As shown in fig. 5, the wireless circuit 24 may operate in an RX diversity mode (state) 104 or in a single receiver mode, such as a high linearity mode (state) 100 or a low linearity mode (state) 102. In the low linearity mode 102, the secondary receiver 36B may wake up periodically to listen for signals while the primary receiver 36A sleeps. When in the low linearity mode 102, the wireless circuit 24 may receive radio frequency signals having low linearity and low level of overall receiver performance. On the other hand, wireless circuit 24 may consume a minimum amount of power in low linearity mode 102.

In the high linearity mode 104, the primary receiver 36A may wake up and may receive and demodulate data (e.g., PDSCH data). The secondary receiver 36B may sleep to save power. When in the high linearity mode 100, the wireless circuit 24 may receive radio frequency signals having high linearity and a high level of overall receiver performance. On the other hand, the wireless circuit 24 may consume a relatively large amount of power in the high linearity mode 100.

In the RX diversity mode 104, both the primary receiver 36A and the secondary receiver 36B may wake up simultaneously, may receive radio frequency signals simultaneously, and may demodulate/decode data (e.g., PDSCH data, PDCCH data, etc.) from the received radio frequency signals simultaneously. The use of primary receiver 36A and secondary receiver 36B to simultaneously receive signals may be used to increase the receive sensitivity of wireless circuitry 24. This may help ensure that when the device 10 exhibits relatively poor radio frequency channel conditions (e.g., relatively low SNR), the wireless circuitry 24 is able to properly decode data from the received signal. Radio circuit 24 may consume a relatively high amount of power in RX diversity mode 104.

If desired, when operating in the RX diversity mode 104, an additional LNA may be switched for the secondary receiver 36B to help compensate for the low linearity of the secondary receiver 36B in receiving the signal. Fig. 6 is a circuit diagram illustrating one example of how an additional LNA may be switched for the secondary receiver 36B in the RX diversity mode.

As shown in FIG. 6, an additional LNA 118 may be disposed on signal path 32-2 between node 60 and the input of LNA 42 in secondary receiver 36B. LNA 118 may be external to SOC 58 (FIG. 2) or may be formed on SOC 58 (e.g., LNA 118 may be iLNA or eLNA). A switching circuit, such as switch 110, may be disposed between node 60 and LNA 118 on signal path 32-2. Signal path 32-2 may also include a bypass path 119 coupled around LNA 118. Switch 110 may have a first state in which switch 110 couples node 60 to the input of LNA 118, thereby switching LNA 118 into use along signal path 32-2. Switch 110 may also have a second state in which switch 110 couples node 60 to bypass path 119, thereby switching LNA 118 out of use along signal path 32-2 (e.g., bypassing LNA 118).

Switch 110 may be switched to switch LNA 118 into use as necessary over time. If desired, switch 110 may switch LNA 118 into use when wireless circuit 24 is in RX diversity mode 104 (FIG. 5). LNA 118 may provide further gain to the received signal to help mitigate the low linearity of secondary receiver 36B, thereby helping secondary receiver 36B to properly receive/decode data (e.g., PDSCH data) when operating in RX diversity mode 104. The example of fig. 6 is illustrative and not limiting. LNA 118 may be coupled to the input of LNA 42 using any desired architecture. LNA 118 and switch 110 may be omitted if desired.

In one or more of the modes 100-104 of fig. 5, the wireless circuitry 24 may collect wireless performance metric data from the received radio frequency signals. For example, in the low linearity mode 102, the secondary receiver 36B may collect (e.g., generate, calculate, compute, sense, etc.) wireless performance metric data from the received radio frequency signal. In the high linearity mode 100, the primary receiver 36A may collect wireless performance metric data from the received radio frequency signal. In the RX diversity mode 104, the primary receiver 36A and/or the secondary receiver 36B may collect wireless performance metric data from the received radio frequency signals. The wireless performance metric data may include received power level values, SNR values, noise floor values, error rate values, receive sensitivity values, information identifying the modulation order of the received signal, or any other desired wireless performance metric data value that characterizes the performance of wireless circuitry 24 in receiving radio frequency signals and/or data. Wireless circuitry 24 may transition between modes 100-104 based on the collected wireless performance metric data and, if desired, based on the current mode of wireless circuitry 24.

Fig. 7 is a flowchart of exemplary operations that may be performed by wireless circuitry 24 to transition a switch between modes 100-104 of fig. 5 based on collected wireless performance metric data. The operations of fig. 7 may be performed, for example, after operation 80 of fig. 3.

At operation 120, when the secondary receiver 36B wakes up, the secondary receiver 36B may collect wireless performance metric data from the radio frequency energy (e.g., radio frequency signals) received by the antenna 34. Additionally or alternatively, the primary receiver 36A may wake up and may collect wireless performance metric data from the radio frequency energy received by the antenna 34.

For example, when the wireless circuit 24 is in the low linearity mode 102, the secondary receiver 36B may collect wireless performance metric data (e.g., during one of the blocks 94 of fig. 4). When the wireless circuit 24 is in the high linearity mode 100, the primary receiver 36A may collect wireless performance metric data (e.g., during block 96 of fig. 4, during DRX periods, etc.). When wireless circuitry 24 is in RX diversity mode 104, primary receiver 36A and/or secondary receiver 36B may collect wireless performance metric data.

At operation 122, the secondary receiver 36B and/or the primary receiver 36A may place the wireless circuit 24 in a selected one of the modes 100-104 or may perform a out-of-service (OOS) procedure (e.g., the operating mode of the wireless circuit 24 may be updated or changed) based on the collected wireless performance metric data for the next DRX cycle. The OOS process may help reestablish the connection between the device and the base station when the wireless performance (e.g., radio frequency channel conditions) of the device 10 is sufficiently low.

At operation 124, the primary receiver 36A and/or the secondary receiver 36B may receive a radio frequency signal in a selected mode of operation (e.g., beginning at a next DRX cycle) (e.g., the receiver may receive a signal in one of the modes of operation 100-104 or may perform an OOS procedure).

For example, when the wireless performance metric data (e.g., SNR values) collected by the secondary receiver 36B and/or the primary receiver 36A exceeds the first threshold TH1, the wireless circuit 24 may be placed (e.g., by one or both of the receivers and/or the control circuit 14 of fig. 1) in a single receiver mode of operation, such as the low linearity mode 102 or the high linearity mode 100 of fig. 5. When the received radio frequency energy associated with the wireless performance metric data does not include a paging signal indicating a subsequent data allocation of the device 10 that would require high linearity, the wireless circuit 24 may be placed in the low linearity mode 102. When the received radio frequency energy includes a paging signal indicating a subsequent data allocation of the device 10 that would require high linearity, the wireless circuit 24 may be placed in the high linearity mode 100.

When the wireless performance metric data (e.g., SNR values) collected by the secondary receiver 36B and/or the primary receiver 36A is less than the first threshold TH1 but exceeds the second threshold TH2, the wireless circuitry 24 may be placed (e.g., by one or both of the receivers and/or the control circuitry 14 of fig. 1) in the RX diversity mode 104 of fig. 5. This may be used to increase the receiver sensitivity of the wireless circuit 24 by configuring both the primary receiver 36A and the secondary receiver 36B to receive radio frequency signals. The increased sensitivity may help compensate for relatively low radio performance levels (e.g., relatively poor channel conditions) exhibited by the radio circuit 24, thereby allowing the radio circuit 24 to properly receive wireless data (e.g., PDCCH or PDSCH data) from the received radio frequency energy.

When the wireless performance metric data (e.g., SNR value) collected by the secondary receiver 36B and/or the primary receiver 36A is less than the second threshold TH2, this may indicate a dropped connection between the device 10 and the base station, and the wireless circuitry 24 may perform an OOS procedure to reestablish the connection. In this manner, wireless circuitry 24 may be dynamically monitored and adjusted to receive signals over time using one or both of receivers 36A and 36B as desired, while minimizing power consumption of the system and without introducing timing or DSP optimization difficulties associated with receiving signals using a single receiver.

Fig. 8 is a graph of wireless performance metric data measurements 126 (e.g., SNR values) collected by primary receiver 36A and/or secondary receiver 36B over time (e.g., in processing operation 120 of fig. 7). As shown by measurement 126, the wireless performance metric data may be compared to a first threshold (level) TH1 and a second threshold (level) TH 2. When the measurement 126 exceeds the first threshold TH1 (e.g., between times T0 and T1), the wireless circuit 24 may be placed in the high linearity mode 100 (e.g., when data has been allocated to the device 10) or the low linearity mode 102 (e.g., to monitor for receipt of paging signals). The relatively high SNR associated with the measurement 126 exceeding the first threshold TH1 may mean that a single receiver is sufficient to properly receive the corresponding radio frequency signal.

When the measurement 126 exceeds the second threshold TH2 but does not exceed the first threshold TH1 (e.g., between times T1 and T2 or after time T3), the wireless circuit 24 may be placed in the RX diversity mode 104 (e.g., the wireless circuit 24 may switch from the high linearity mode 100 or the low linearity mode 102 to the RX diversity mode 104 at time T1). The relatively low SNR associated with the measurement 126 exceeding the second threshold TH2 but not exceeding the first threshold TH1 may mean that two receivers may be required to provide sufficient receiver sensitivity to properly receive the corresponding radio frequency signal.

When the measurement 126 falls below the second threshold TH2 (e.g., between times T2 and T3), the wireless circuit 24 may perform an OOS procedure to reestablish the connection to the network (e.g., the wireless circuit 24 may return to the RX diversity mode 104 at time T3). If the radio performance metric data then exceeds the first threshold TH1, the radio circuit 24 may switch from the RX diversity mode 104 to either the high linearity mode 100 or the low linearity mode 102. For example, the first threshold TH1 may be a minimum SNR (e.g., 5dB, 4dB, 6dB, or other value) at which a single receiver (e.g., the primary receiver 36A or the secondary receiver 36B) can successfully decode wireless data in the received radio frequency energy. For example, the second threshold TH2 may be a minimum SNR (e.g., 2dB or other value less than the first threshold TH 1) at which both receivers 36A and 36B are jointly able to successfully decode wireless data in the received radio frequency energy. The example of fig. 8 is illustrative and not limiting.

As used herein, the term "simultaneously" means overlapping at least partially in time. In other words, a first event and a second event are referred to herein as being "simultaneous" with each other if at least some of the first event occurs concurrently with at least some of the second event (e.g., if at least some of the first event occurs during at least some of the second event, occurs concurrently with at least some of the second event, or occurs when at least some of the second event occurs). The first event and the second event may be simultaneous if the first event and the second event are synchronized (e.g., if the entire duration of the first event overlaps in time with the entire duration of the second event), but the first event and the second event may also be simultaneous if the first event and the second event are not synchronized (e.g., if the first event begins before or after the second event begins, if the first event ends before or after the second event ends, or if the first event and the second event do not overlap in part in time). As used herein, the term "while" is synonymous with "simultaneous (concurrent)".

The device 10 may collect and/or use personally identifiable information. It is well known that the use of personally identifiable information should follow privacy policies and practices that are recognized as meeting or exceeding industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of inadvertent or unauthorized access or use, and the nature of authorized use should be specified to the user.

The methods and operations described above in connection with fig. 1-5 may be performed by components of device 10 using software, firmware, and/or hardware (e.g., dedicated circuitry or hardware). The software code for performing these operations may be stored on a non-transitory computer readable storage medium (e.g., a tangible computer readable storage medium) that is stored on one or more of the components of the device 10. The software code may sometimes be referred to as software, data, instructions, program instructions, or code. The non-transitory computer readable storage medium may include a drive, non-volatile memory such as non-volatile random access memory (NVRAM), a removable flash drive or other removable medium, other types of random access memory, and the like. Software stored on the non-transitory computer readable storage medium may be executed by processing circuitry on one or more of the components of device 10. The processing circuitry may include a microprocessor, a Central Processing Unit (CPU), an application-specific integrated circuit with processing circuitry, or other processing circuitry.

According to one embodiment, there is provided an electronic device including: an antenna; a first receiver having a first Low Noise Amplifier (LNA); a second receiver having a second LNA; a first signal path coupling the antenna to an input of the first LNA; a third LNA disposed on the first signal path; and a second signal path coupling a node on the first signal path to an input of the second LNA, the node being disposed on the first signal path between an output of the third LNA and an input of the first LNA.

According to another embodiment, the second LNA has a lower linearity than the first LNA.

According to another embodiment, the second receiver comprises a wake-up receiver.

According to another embodiment, the node comprises a radio frequency signal separator.

According to another embodiment, the node comprises a radio frequency coupler.

According to another embodiment, the node is devoid of a switch.

According to another embodiment, the first receiver has a first Digital Signal Processor (DSP) coupled to an output of the first LNA, the second receiver has a second DSP coupled to an output of the second LNA, and the second DSP has a lower sampling rate than the first DSP.

According to another embodiment, the electronic device includes a control path coupling the second DSP to the first DSP.

According to another embodiment, the second DSP is configured to wake up the first receiver by transmitting control signals on the control path.

According to another embodiment, the first DSP and the second DSP are configured to attempt to decode wireless data in the radio frequency signal received by the antenna simultaneously.

According to another embodiment, the electronic device includes: a fourth LNA disposed on the second signal path, the second signal path including a bypass path around the fourth LNA; and a switch disposed on the second signal path and configured to couple the node to a selected one of the fourth LNA and the bypass path.

According to another embodiment, the first receiver and the second receiver are integrated into a System On Chip (SOC) and the third LNA is external to the SOC.

According to one embodiment, there is provided a method of operating an electronic device, the method comprising: receiving radio frequency energy using an antenna; using a Low Noise Amplifier (LNA) to pass the radio frequency energy to a second LNA in a first receiver and simultaneously to a third LNA in a second receiver that consumes less power than the first receiver; attempting to decode a Physical Downlink Control Channel (PDCCH) signal from the radio frequency energy using the second receiver while the first receiver is asleep; and in response to the second receiver decoding the PDDCH signal, waking up the first receiver for a subsequent data reception cycle using the second receiver.

According to another embodiment, the method includes attempting to decode a Physical Downlink Shared Channel (PDSCH) signal from the radio frequency energy using the first receiver during the subsequent data reception cycle.

According to another embodiment, the method includes attempting to decode data from the radio frequency energy using the second receiver during the subsequent data reception cycle and while the first receiver is attempting to decode the PDSCH signal from the radio frequency energy.

According to another embodiment, the second receiver sleeps during the subsequent data reception cycle.

According to another embodiment, the method comprises: generating wireless performance metric data from the radio frequency energy using the second receiver prior to the subsequent data reception cycle; and during the subsequent data reception cycle, activating one or both of the first receiver and the second receiver using one or more processors based on the wireless performance metric data.

According to one embodiment, there is provided a method of operating an electronic device, the method comprising: receiving radio frequency energy using an antenna; delivering the radio frequency energy to a first receiver and a second receiver operating at a lower sampling rate than the first receiver using a Low Noise Amplifier (LNA); generating wireless performance metric data from the radio frequency energy using the second receiver during a first period of time; and responsive to the wireless performance metric data collected during the first period being less than a threshold, attempting to decode a signal from the radio frequency energy using the first receiver and the second receiver during a second period subsequent to the first period.

According to another embodiment, the method includes attempting to decode the signal from the radio frequency energy using the first receiver without using the second receiver during the second period and in response to the wireless performance metric data collected during the first period exceeding the threshold.

According to another embodiment, the method includes waking up the first receiver using the second receiver in response to the second receiver decoding a paging signal in the radio frequency energy.

The foregoing is merely illustrative and various modifications may be made to the embodiments. The foregoing embodiments may be implemented independently or may be implemented in any combination.

Claims (20)

1. An electronic device, comprising:

An antenna;

A first receiver having a first Low Noise Amplifier (LNA);

a second receiver having a second LNA;

a first signal path coupling the antenna to an input of the first LNA;

a third LNA disposed on the first signal path; and

A second signal path coupling a node on the first signal path to an input of the second LNA, the node being disposed on the first signal path between an output of the third LNA and an input of the first LNA.

2. The electronic device of claim 1, wherein the second LNA has a lower linearity than the first LNA.

3. The electronic device of claim 2, wherein the second receiver comprises a wake-up receiver.

4. The electronic device of claim 1, wherein the node comprises a radio frequency signal splitter.

5. The electronic device of claim 1, wherein the node comprises a radio frequency coupler.

6. The electronic device of claim 1, wherein the node is devoid of a switch.

7. The electronic device of claim 1, wherein the first receiver has a first Digital Signal Processor (DSP) coupled to an output of the first LNA, the second receiver has a second DSP coupled to an output of the second LNA, and the second DSP has a lower sampling rate than the first DSP.

8. The electronic device of claim 7, further comprising a control path coupling the second DSP to the first DSP.

9. The electronic device of claim 8, wherein the second DSP is configured to wake up the first receiver by transmitting control signals on the control path.

10. The electronic device of claim 7, wherein the first DSP and the second DSP are configured to attempt to decode wireless data in a radio frequency signal received by the antenna simultaneously.

11. The electronic device of claim 1, further comprising:

A fourth LNA disposed on the second signal path, the second signal path including a bypass path around the fourth LNA; and

A switch disposed on the second signal path and configured to couple the node to a selected one of the fourth LNA and the bypass path.

12. The electronic device of claim 1, wherein the first receiver and the second receiver are integrated into a System On Chip (SOC) and the third LNA is external to the SOC.

13. A method of operating an electronic device, the method comprising:

Receiving radio frequency energy using an antenna;

Transferring the radio frequency energy using a Low Noise Amplifier (LNA) to a second LNA in a first receiver and simultaneously to a third LNA in a second receiver, wherein the second receiver consumes less power than the first receiver;

attempting to decode a Physical Downlink Control Channel (PDCCH) signal from the radio frequency energy using the second receiver while the first receiver is asleep; and

In response to the second receiver decoding the PDDCH signal, the first receiver is awakened using the second receiver for a subsequent data reception cycle.

14. The method of claim 13, further comprising:

During the subsequent data reception cycle, an attempt is made to decode a Physical Downlink Shared Channel (PDSCH) signal from the radio frequency energy using the first receiver.

15. The method of claim 14, further comprising:

During the subsequent data reception cycle and while the first receiver attempts to decode the PDSCH signal from the radio frequency energy, attempting to decode data from the radio frequency energy using the second receiver.

16. The method of claim 14, wherein the second receiver sleeps during the subsequent data reception cycle.

17. The method of claim 13, further comprising:

Generating wireless performance metric data from the radio frequency energy using the second receiver prior to the subsequent data reception cycle; and

One or more processors are used to activate one or both of the first receiver and the second receiver during the subsequent data reception cycle based on the wireless performance metric data.

18. A method of operating an electronic device, the method comprising:

Receiving radio frequency energy using an antenna;

Delivering the radio frequency energy to a first receiver and a second receiver operating at a lower sampling rate than the first receiver using a Low Noise Amplifier (LNA);

generating wireless performance metric data from the radio frequency energy using the second receiver during a first period of time; and

Responsive to the wireless performance metric data collected during the first period being less than a threshold, attempting to decode a signal from the radio frequency energy using the first receiver and the second receiver during a second period subsequent to the first period.

19. The method of claim 18, further comprising:

During the second period of time and in response to the radio performance metric data collected during the first period of time exceeding the threshold, attempting to decode the signal from the radio frequency energy using the first receiver and not using the second receiver.

20. The method of claim 18, further comprising:

the second receiver is used to wake up the first receiver in response to the second receiver decoding a paging signal in the radio frequency energy.