CN117950618A

CN117950618A - Display method, system, device, display controller, equipment and storage medium

Info

Publication number: CN117950618A
Application number: CN202410354970.5A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2024-03-26
Filing date: 2024-03-26
Publication date: 2024-04-30

Abstract

The embodiment of the disclosure provides a display method, a system, a device, a display controller, equipment and a storage medium, wherein the method comprises the following steps: acquiring clock frequencies respectively corresponding to a plurality of display controllers; the display controllers are in one-to-one correspondence with the first buffer subareas; for each display controller, adjusting a clock signal corresponding to the display controller based on a clock frequency corresponding to the display controller, wherein the clock signal is used for driving the display controller to acquire a corresponding image content sub-block from a frame of image content currently rendered, generating an image frame sub-block based on the image content sub-block, and storing the image frame sub-block into a corresponding first buffer subarea; and in response to each display controller completing the storage of the image frame sub-blocks, obtaining the target image frame by utilizing the image frame sub-blocks stored in each first buffer subarea. According to the embodiment of the disclosure, the display refresh rate can be improved, and the power consumption can be saved.

Description

Display method, system, device, display controller, equipment and storage medium

Technical Field

The present disclosure relates to, but not limited to, the field of electronic technology, and in particular, to a display method, system, apparatus, display controller, device, and storage medium.

Background

The display refresh rate refers to the number of times a display panel is refreshed per second of pictures. In a dynamic picture display scene, such as a video playing scene, a game picture display scene, and the like, the higher the display refresh rate is, the better the continuity and dynamic effect of the display picture are. However, in the related art display system, the display refresh rate is not yet high enough, and adjustment of the display refresh rate lacks flexibility.

Disclosure of Invention

In view of this, embodiments of the present disclosure at least provide a display method, a system, an apparatus, a display controller, a device, and a storage medium.

The technical scheme of the embodiment of the disclosure is realized as follows:

The embodiment of the disclosure provides a display method, which comprises the following steps:

acquiring clock frequencies respectively corresponding to a plurality of display controllers; wherein the plurality of display controllers are in one-to-one correspondence with the plurality of first buffer subareas;

For each display controller, adjusting a clock signal corresponding to the display controller based on a clock frequency corresponding to the display controller, wherein the clock signal is used for driving the display controller to acquire a corresponding image content sub-block from a currently rendered image content frame, generating an image frame sub-block based on the image content sub-block, and storing the image frame sub-block into a corresponding first buffer subarea;

and responding to the completion of the storage of the image frame sub-blocks by each display controller, and obtaining a target image frame by utilizing the image frame sub-blocks stored in each first buffer subarea.

The embodiment of the disclosure provides a display system, which comprises a main processor, a plurality of display controllers, a memory and a display panel, wherein the memory comprises a plurality of first buffer subareas, the plurality of display controllers are in one-to-one correspondence with the plurality of first buffer subareas, and the display system comprises:

the display controller is used for: responding to the received clock signal, and acquiring a corresponding image content sub-block from the currently rendered image content of one frame; generating an image frame sub-block based on the image content sub-block, and storing the image frame sub-block into a corresponding first buffer sub-region;

The main processor is configured to: acquiring clock frequencies respectively corresponding to a plurality of display controllers; adjusting a clock signal corresponding to each display controller based on a clock frequency corresponding to the display controller; and responding to the completion of the storage of the image frame sub-blocks by each display controller, obtaining a target image frame by using the image frame sub-blocks stored in each first buffer subarea, and sending the target image frame to the display panel for display by the display panel.

Embodiments of the present disclosure provide a display device including:

the first acquisition module is used for acquiring clock frequencies respectively corresponding to the display controllers; wherein the plurality of display controllers are in one-to-one correspondence with the plurality of first buffer subareas;

The first adjusting module is used for adjusting clock signals corresponding to the display controllers based on the clock frequencies corresponding to the display controllers, wherein the clock signals are used for driving the display controllers to acquire corresponding image content sub-blocks from currently rendered image content of one frame, generating image frame sub-blocks based on the image content sub-blocks, and storing the image frame sub-blocks into corresponding first buffer sub-regions;

And the obtaining module is used for obtaining the target image frame by utilizing the image frame sub-blocks stored in each first buffer subarea in response to the fact that each display controller completes the storage of the image frame sub-blocks.

The embodiment of the disclosure provides a display controller, comprising:

The second acquisition module is used for responding to the received clock signal and acquiring a corresponding image content sub-block from the currently rendered image content of one frame; wherein the clock signal is adjusted based on a clock frequency corresponding to the display controller;

A generation module for generating image frame sub-blocks based on the image content sub-blocks;

A storage module for storing the image frame sub-blocks into a first target buffer sub-area; the first target buffer subarea is a first buffer subarea corresponding to the display controller in a plurality of first buffer subareas; the plurality of first buffer subareas are in one-to-one correspondence with the plurality of display controllers, and the plurality of image frame subblocks stored in the plurality of first buffer subareas are used for determining target image frames.

The disclosed embodiments provide a computer device comprising a memory storing a computer program executable on the processor and a processor implementing some or all of the steps of the above method when the processor executes the program.

The disclosed embodiments provide a computer readable storage medium having stored thereon a computer program which when executed by a processor performs some or all of the steps of the above method.

Embodiments of the present disclosure provide a computer program product comprising a computer program or instructions which, when executed by a processor, implement some or all of the steps of the above-described method.

In the embodiment of the disclosure, clock frequencies respectively corresponding to a plurality of display controllers are obtained; wherein, the plurality of display controllers are in one-to-one correspondence with the plurality of first buffer subareas; for each display controller, adjusting a clock signal corresponding to the display controller based on a clock frequency corresponding to the display controller, wherein the clock signal is used for driving the display controller to acquire a corresponding image content sub-block from a frame of image content currently rendered, generating an image frame sub-block based on the image content sub-block, and storing the image frame sub-block into a corresponding first buffer subarea; and in response to each display controller completing the storage of the image frame sub-blocks, obtaining the target image frame by utilizing the image frame sub-blocks stored in each first buffer subarea. Thus, on the one hand, the refresh rate of the display can be increased by sharing the refresh task of a single image frame to multiple display controllers for processing; on the other hand, since the plurality of display controllers respectively have corresponding clock frequencies, the display refresh rate can be flexibly adjusted in fine granularity by adjusting the clock frequencies respectively corresponding to the display controllers so as to more accurately match the graphics rendering frame rate in the display system; on the other hand, since the clock frequency can be set for each display controller, respectively, the power consumption in the image display process can be better controlled to reduce unnecessary power consumption while meeting the display refresh rate requirement, thereby achieving power consumption saving.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the aspects of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.

Fig. 1A is a schematic implementation flow diagram of a display method according to an embodiment of the disclosure;

Fig. 1B is a schematic diagram illustrating an implementation of region division of a first buffer in a display method according to an embodiment of the disclosure;

Fig. 1C is a second schematic implementation diagram of region division of a first buffer region in a display method according to an embodiment of the present disclosure;

fig. 1D is a schematic diagram III for implementing region division of a first buffer region in a display method according to an embodiment of the present disclosure;

Fig. 1E is a schematic diagram for implementing region division of a first buffer region in a display method according to an embodiment of the present disclosure;

Fig. 1F is a schematic diagram fifth implementation diagram of region division of a first buffer region in a display method according to an embodiment of the present disclosure;

fig. 1G is a schematic diagram sixth implementation diagram of region division of a first buffer region in a display method according to an embodiment of the present disclosure;

fig. 1H is a schematic diagram seventh for implementing region division of a first buffer area in a display method according to an embodiment of the present disclosure;

fig. 1I is a schematic diagram eighth implementation diagram of region division of a first buffer in a display method according to an embodiment of the present disclosure;

Fig. 2 is a second schematic implementation flow chart of a display method according to an embodiment of the disclosure;

Fig. 3A is a schematic diagram of a composition structure of a display system according to an embodiment of the disclosure;

fig. 3B is a schematic diagram of a second component structure of a display system according to an embodiment of the disclosure;

Fig. 3C is a schematic diagram of a composition structure of a display system according to an embodiment of the disclosure;

fig. 3D is a schematic diagram of a composition structure of a display system according to an embodiment of the disclosure;

fig. 3E is a schematic diagram of a composition structure of a display system according to an embodiment of the disclosure;

fig. 4 is a schematic diagram of a composition structure of a display controller according to an embodiment of the disclosure;

Fig. 5 is a schematic diagram of a composition structure of a display device according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a hardware entity of a computer device according to an embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

The term "first/second/third" is merely to distinguish similar objects and does not represent a particular ordering of objects, it being understood that the "first/second/third" may be interchanged with a particular order or precedence where allowed, to enable embodiments of the disclosure described herein to be implemented in other than those illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing the present disclosure only and is not intended to be limiting of the present disclosure.

In view of this, the embodiments of the present disclosure provide a display method. The method may be performed by a main processor of a computer device. Wherein the computer device may include, but is not limited to, at least one of a server, a notebook computer, a tablet computer, a desktop computer, a smart television, a set-top box, a mobile device (e.g., a mobile phone, a portable video player, a personal digital assistant, a dedicated messaging device, a portable gaming device), and the like. The main Processor of the computer device may include, but is not limited to, at least one of a central processing unit (Central Processing Unit, CPU), a graphics Processor (Graphics Processing Unit, GPU), a microprocessor (Microprocessor Unit, MPU), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), or a field programmable gate array (Field Programmable GATE ARRAY, FPGA), etc. Fig. 1A is a schematic implementation flow diagram of a display method according to an embodiment of the disclosure, as shown in fig. 1A, the method may include the following steps S101 to S103: step S101, clock frequencies respectively corresponding to a plurality of display controllers are obtained; wherein, a plurality of display controllers correspond with a plurality of first buffer subareas one by one.

Here, the first buffer sub-area may be a buffer area or a buffer sub-area in a memory for storing the target image frame to be displayed, which is not limited by the embodiment of the present disclosure. The storage may include, but is not limited to, at least one of a video memory, a memory, and the like. Each first buffer sub-region may be used to store one image frame sub-block in a target image frame to be displayed. The plurality of first buffer sub-areas may belong to the same buffer area or may belong to different buffer areas.

In some embodiments, the plurality of first buffer sub-regions is obtained by zoning the first buffer region. The first buffer may be any suitable buffer in memory for storing the target image frames to be displayed, as the embodiments of the present disclosure are not limited in this respect. For example, the first buffer may be a buffer in a video memory or a buffer in a memory.

In some embodiments, the first buffer may be a display frame buffer in a display memory, and the size of the first buffer may be the same as a resolution of a display panel for displaying the image frames.

The first buffer area may be divided into a plurality of first buffer sub-areas, and each display controller may correspond to one of the first buffer sub-areas. In practice, a person skilled in the art may divide the first buffer area into a plurality of first buffer sub-areas by using any suitable manner according to practical situations, which is not limited herein.

In some embodiments, the first buffer region may be uniformly divided into a plurality of first buffer sub-regions having the same size. For example, referring to fig. 1B, the first buffer area D1 may be divided into 2×2 first buffer sub-areas D11, D12, D13, and D14 of the same size, and the first buffer sub-areas D11, D12, D13, and D14 are used to store image frame sub-blocks R11, R12, R13, and R14, respectively, in the target image frame R1 to be displayed. As another example, referring to fig. 1C, the first buffer area D2 may be divided into 3×3 first buffer sub-areas D21, D22, D23, D24, D25, D26, D27, D28, and D29 of the same size, and the first buffer sub-areas D21, D22, D23, D24, D25, D26, D27, D28, and D29 are used to store image frame sub-blocks R21, R22, R23, R24, R25, R26, R27, R28, and R29, respectively, in the target image frame R2 to be displayed.

In some embodiments, the first buffer area may be divided into a plurality of first buffer sub-areas according to a distribution state of an image Layer (Layer) in a frame of image content currently rendered. The number and/or the size of the image layers to be displayed in the image frame sub-blocks to be stored in the plurality of first buffer sub-areas may be the same or different. It will be appreciated that at least one image layer to be displayed in the target image frame to be displayed may be included in the current rendered image content of one frame. The distribution state of image layers in the currently rendered image content of one frame may include, but is not limited to, at least one of the number of image layers, the size of each image layer, the distribution position of each image layer, and the like.

The display controller may be any suitable control unit for processing the rendered image content to obtain at least one pixel value to be displayed on the display panel. In some implementations, the display controller may be configured to perform two-dimensional operations on the rendered image content, where the two-dimensional operations may include, but are not limited to, at least one of scaling, rotation, blending, compositing, and the like. For example, the display controller may be configured to layer at least one image of the rendered image content into one image frame to be displayed or a partial region in the image frame to be displayed.

The clock signal of each display controller can be controlled by the main processor, and each display controller corresponds to one clock frequency respectively. In implementation, the clock frequencies respectively corresponding to the different display controllers may be the same or different, which is not limited by the embodiments of the present disclosure.

In some embodiments, the clock frequencies respectively corresponding to the plurality of display controllers may be default values, may be set by a user according to actual situations, or may be determined according to a current graphics rendering frame rate.

Step S102, for each display controller, adjusting a clock signal corresponding to the display controller based on a clock frequency corresponding to the display controller, where the clock signal is used to drive the display controller to obtain a corresponding image content sub-block from a currently rendered image content frame, generate an image frame sub-block based on the image content sub-block, and store the image frame sub-block into a corresponding first buffer sub-area.

Here, the currently rendered one-frame image content refers to image content corresponding to a currently rendered target image frame to be displayed.

In some embodiments, the currently rendered frame of image content may be rendered by a graphics renderer and/or video encoder at a particular image rendering frame rate.

In some embodiments, the host processor may directly provide the clock signal to the display controller and directly adjust the clock signal provided to the display controller based on the corresponding clock frequency of the display controller.

In some embodiments, the host processor may provide a clock signal to the display controller by controlling the other module and sending an adjustment instruction to the other module based on the clock frequency corresponding to the display controller, such that the other module adjusts the clock signal provided to the display controller in response to the adjustment instruction. Here, other modules may include, but are not limited to, a clock signal generator, and the like.

The display controller may acquire an image content sub-block corresponding to the display controller from a currently rendered image content of one frame in response to driving of the clock signal, and generate and store one image frame sub-block into the corresponding first buffer sub-region based on the image content sub-block. The image content sub-block corresponding to the display controller refers to image content required for generating the image frame sub-block to be stored in the first buffer sub-region corresponding to the display controller.

In some embodiments, according to the location area of the image frame sub-block in the target image frame, determining the partial image content in the current rendered image content in the location area as the image content sub-block corresponding to the image frame sub-block.

In some embodiments, the number of main processors is single, and the clock signal corresponding to each display controller can be adjusted by the single main processor. In this way, hardware costs may be reduced.

In some embodiments, the number of the main processors is plural, the plural main processors are in one-to-one correspondence with the plural display controllers, and each main processor can adjust the clock signal of the corresponding display controller. In this way, the clock signal of each display controller can be controlled more flexibly.

And step S103, responding to the fact that each display controller completes storage of the image frame sub-blocks, and obtaining a target image frame by utilizing the image frame sub-blocks stored in each first buffer subarea.

Here, in the case where each display controller completes storage of the image frame sub-blocks, the main processor may process the image frame sub-blocks stored in each first buffer sub-area in any suitable manner to obtain the target image frame to be displayed, which is not limited by the embodiment of the present disclosure.

In some embodiments, the main processor may combine the image frame sub-blocks stored in the respective first buffer sub-areas to obtain the target image frame.

In some embodiments, after obtaining the target image frame to be displayed, the main processor may send the target image frame to the display panel for display. The display panel may include, but is not limited to, at least one of a liquid crystal display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a plasma display panel, and the like.

In some embodiments, in the event that it is determined that each display controller completes the storage of an image frame sub-block, the main processor may directly read each image frame sub-block from each first buffer sub-region and compose each read image frame sub-block into a target image frame.

In some embodiments, in the case where it is determined that each display controller completes the storage of the image frame sub-blocks, the main processor may send a driving instruction to any one of the plurality of display controllers to drive the display controller to read each image frame sub-block from each first buffer sub-region, and to compose each read image frame sub-block into the target image frame.

In some embodiments, a direct memory access (Direct Memory Access, DMA) channel may be used to compose the target image frame from the image frame sub-blocks stored in each first buffer sub-area and then send the target image frame to the display panel.

In some embodiments, the method may further include the following step S111:

Step S111, when a first display controller of the plurality of display controllers has completed storing the image frame sub-blocks and at least one second display controller of the plurality of display controllers has not completed storing the image frame sub-blocks, reducing the frequency of the clock signal of the first display controller.

Here, the first display controller is a display controller of which storage of the image frame sub-blocks has been completed among the plurality of display controllers. The second display controller is a display controller of the plurality of display controllers that does not have storage of the sub-blocks of the image frames.

In implementation, the clock signal of the first display controller may be reduced to any suitable frequency according to practical situations, which is not limited by the embodiments of the present disclosure. For example, the frequency of the clock signal of the first display controller may be reduced to 0, i.e. the clock signal of the first display controller is turned off. For another example, the clock signal of the first display controller may be reduced to a preset frequency greater than 0, such as controlling the first display controller to enter a sleep state at a low clock frequency.

In some embodiments, the master controller may directly stop sending the clock signal to the first display controller to turn off the clock signal of the first display controller.

In some embodiments, the master controller may send a preset clock gating signal to the first display controller to turn off the clock signal of the first display controller.

In the above embodiment, in the case where the first display controller has completed the storage of the image frame sub-blocks and the second display controller has not completed the storage of the image frame sub-blocks, the frequency of the clock signal of the first display controller is reduced, so that power consumption can be saved.

In some embodiments, the plurality of first buffer sub-regions is obtained by partitioning the first buffer region; the method further comprises step S121 or step S122:

step S121, dividing the first buffer into the plurality of first buffer sub-areas with the same size based on the number of the plurality of display controllers.

Here, the first buffer area may be equally divided into a plurality of first buffer sub-areas having the same size according to the number of display controllers. For example, in the case where the number of display controllers is 4, the first buffer area may be divided into 2×2 first buffer sub-areas having the same size, or may be divided into 4×1 first buffer sub-areas having the same size. In another example, in the case where the number of display controllers is 8, the first buffer area may be divided into 2×4 first buffer sub-areas having the same size, or may be divided into 4×2 first buffer sub-areas having the same size. For another example, in the case where the number of display controllers is 9, the first buffer area may be divided into 3×3 first buffer sub-areas having the same size.

In some embodiments, the size of each first buffer sub-region is the same, and the number of image layers to be displayed in the image frame sub-block to be stored in each first buffer sub-region is the same.

For example, referring to fig. 1D, in the case of dividing the first buffer into 2×2 first buffer sub-areas of the same size, each first buffer sub-area is used to store one image frame sub-block 110 in the target image frame 100 to be displayed, and each image frame sub-block 110 may contain the same number of image layers 111 to be displayed.

As another example, referring to fig. 1E, in the case that the first buffer area is divided into 3×3 first buffer sub-areas with the same size, each first buffer sub-area is used to store one image frame sub-block 110 in the target image frame 100 to be displayed, and each image frame sub-block 110 may include the same number of image layers 111 to be displayed.

In some embodiments, the size of each first buffer sub-region is the same, and the number of image layers to be displayed in the image frame sub-block to be stored in each first buffer sub-region is different.

Referring to fig. 1F, in the case of dividing the first buffer into 2×2 first buffer sub-areas of the same size, each first buffer sub-area is used to store one image frame sub-block 110 in the target image frame 100 to be displayed, and each image frame sub-block 110 may contain a different number of image layers 111 to be displayed.

Referring to fig. 1G, in the case of dividing the first buffer into 3×3 first buffer sub-areas of the same size, each first buffer sub-area is used to store one image frame sub-block 110 in the target image frame 100 to be displayed, and each image frame sub-block 110 may contain a different number of image layers 111 to be displayed.

In this way, the sizes of the first buffer subareas are the same, so that the processing loads of the display controllers are balanced, the stability of the display refresh rate can be improved, and the smoothness and quality of the display of dynamic pictures such as games and/or videos can be improved.

Step S122, dividing the first buffer into the plurality of first buffer sub-areas based on the number of the plurality of display controllers and the distribution state of the image layers in the currently rendered image content.

Here, the distribution state of the image layers in the currently rendered one frame of image content may include, but is not limited to, at least one of the number of image layers, the size of each image layer, the distribution position of each image layer, and the like.

In implementation, the number/size of the image layers to be displayed in the image frame sub-block to be stored in each first buffer sub-area may be the same or different, which is not limited by the embodiment of the disclosure.

In this way, in the process of dividing the first buffer area, the number of display controllers and the distribution state of the image layers in the currently rendered image content of one frame are comprehensively considered, so that the first buffer area can be more reasonably divided.

In some embodiments, the number and/or size of image layers to be displayed in the image frame sub-block to be stored in each of the first buffer sub-areas are the same.

In some embodiments, the size of each first buffer sub-region may be different, and the number of image layers to be displayed in the image frame sub-block to be stored in each first buffer sub-region is the same. I.e. the sizes of the at least two first buffer sub-areas are different.

Referring to fig. 1H, in case that the first buffer area is divided into 2×2 first buffer sub-areas, each of the first buffer sub-areas is used to store one image frame sub-block 110 in the target image frame 100 to be displayed, the size of each of the first buffer sub-areas may be different, and the same number of image layers 111 to be displayed may be included in each of the image frame sub-blocks 110.

Referring to fig. 1I, in case that the first buffer area is divided into 3×3 first buffer sub-areas, each of the first buffer sub-areas is used to store one image frame sub-block 110 in the target image frame 100 to be displayed, the size of each of the first buffer sub-areas may be different, and the same number of image layers 111 to be displayed may be included in each of the image frame sub-blocks 110.

In the above embodiment, the number and/or the size of the image layers to be displayed in the image frame sub-block to be stored in each first buffer sub-region are the same, so that the processing load of each display controller is balanced, and therefore, the stability of the display refresh rate can be improved, and further, the smoothness and quality of the display of dynamic pictures such as games and/or videos can be improved.

In some embodiments, the currently rendered frame of image content is stored in a second buffer, the plurality of display controllers being in one-to-one correspondence with a plurality of second buffer sub-regions in the second buffer; the clock signal corresponding to the display controller is further used for driving the display controller to read the corresponding image content sub-block from the corresponding second buffer sub-area.

Here, the second buffer may be any suitable buffer in memory for storing rendered image content, which the embodiments of the present disclosure are not limited to. For example, the second buffer may be a buffer in a video memory or a buffer in a memory.

In some embodiments, the second buffer may be a display input buffer in a display memory.

The second buffer may be divided into a plurality of second buffer sub-areas, each of which may correspond to one of the second buffer sub-areas, respectively, each of which may be used to store one of the image content sub-blocks in the currently rendered one frame of image content. In practice, a person skilled in the art may divide the second buffer area into a plurality of second buffer areas by using any suitable manner according to practical situations, which is not limited herein.

In the above embodiment, the clock signal corresponding to the display controller is further used to drive the display controller to read the image content sub-block corresponding to the display controller from the second buffer sub-area corresponding to the display controller. In this way, the image content sub-blocks respectively corresponding to the display controllers can be rapidly acquired, so that the efficiency of generating and storing the corresponding image frame sub-blocks by the display controllers can be improved, and the display refresh rate is further improved.

Embodiments of the present disclosure provide a display method that may be performed by a main processor of a computer device. Fig. 2 is a second implementation flow chart of a display method according to an embodiment of the present disclosure, as shown in fig. 2, the method may include the following steps S201 to S205:

Step S201, a current graphics rendering frame rate is obtained.

Here, the graphics rendering Frame rate indicates how many frames of image content of a still image are rendered Per Second by a video encoder and/or a graphics renderer or the like, in units of frames Per Second (fps). For example, when playing a game, the graphics rendering frame rate is 60fps, representing the image content of a graphics renderer rendering 60 frames of still images per second.

It will be appreciated that the computational pressure at which the graphics renderer processes the images may vary due to the varying complexity of each image frame, thereby affecting the variation in the graphics rendering frame rate.

In some implementations, the current graphics rendering frame rate may be predicted or obtained, for example, via a video encoder and/or graphics renderer, etc., or an internal or external module of the GPU or other dedicated hardware.

Step S202, determining a target display refresh rate based on the graphics rendering frame rate.

Here, the target display refresh rate refers to a target number of times the display panel is refreshed per second of the screen.

In practice, one skilled in the art may determine the target display refresh rate that matches the current graphics rendering frame rate in any suitable manner, as the case may be, and the embodiments of the present disclosure are not limited in this regard.

In some implementations, the target display refresh rate may be greater than or equal to the graphics rendering frame rate. Thus, the situation that the display panel displays the frame can be reduced, and the fluency and quality of the game and/or video playing can be improved.

For example, at the current graphics rendering frame rate ofIn the case of fps, it may be determined that the target display refresh rate is equal to the graphics rendering frame rate, i.e., the target display refresh rate isHertz (Hz).

In some embodiments, the target display refresh rate may be dynamically adjusted according to the change of the image rendering frame rate, so as to implement a Variable refresh rate (Variable REFRESH RATE, VRR), so as to reduce the problems of screen tearing, image delay, and the like, and further improve the smoothness and quality of the game and/or video playing.

Step S203, determining clock frequencies respectively corresponding to a plurality of display controllers based on the target display refresh rate; the display controllers are in one-to-one correspondence with a plurality of first buffer subareas, and the plurality of first buffer subareas are obtained by dividing the first buffer areas into areas.

It can be understood that, under the condition that each display controller completes the storage of the image frame sub-blocks, the image frame sub-blocks stored in each first buffer sub-area are formed into target image frames and then sent to the display panel for display, so that the number of times that the display panel is refreshed every second of the picture is related to the clock frequency corresponding to each display controller, that is, the display refresh rate of the display panel is related to the clock frequency corresponding to each display controller.

In practice, one skilled in the art may determine the clock frequencies respectively corresponding to the display controllers based on the target display refresh rate in any suitable manner according to the actual situation, and the embodiments of the present disclosure are not limited in this regard.

In some embodiments, it may be determined that the respective clock frequency of each display controller is greater than or equal to the target display refresh rate.

Step S204, for each display controller, adjusting a clock signal corresponding to the display controller based on a clock frequency corresponding to the display controller, where the clock signal is used to drive the display controller to obtain a corresponding image content sub-block from a currently rendered image content frame, generate an image frame sub-block based on the image content sub-block, and store the image frame sub-block into a corresponding first buffer sub-area.

In step S205, in response to each of the display controllers completing storage of the image frame sub-blocks, a target image frame is obtained using the image frame sub-blocks stored in each of the first buffer sub-areas.

Here, steps S204 to S205 correspond to steps S102 to S103 in the foregoing examples, respectively, and reference may be made to the implementation of the foregoing steps S102 to S103 when implemented.

In the embodiment of the disclosure, the target display refresh rate is determined based on the current image rendering frame rate, and the clock frequencies respectively corresponding to the plurality of display controllers are determined based on the target display refresh rate, so that the clock frequencies respectively corresponding to the plurality of display controllers can be better adapted to the current image rendering frame rate, and the display refresh rate of the display panel can be better adapted to the current image rendering frame rate, so that the smoothness and quality of game and/or video playing are improved.

In some embodiments, the step S203 may include the following steps S211 to S213:

Step S211, determining a reference duration threshold based on the target display refresh rate; and the reference time length threshold value does not exceed the single frame refresh time length corresponding to the target display refresh rate.

Here, the reference duration threshold characterizes an upper duration limit spent by each display controller generating a corresponding image frame sub-block and storing the image frame sub-block to a corresponding first buffer sub-region if the target display refresh rate is met.

It will be appreciated that assume the firstThe processing time spent by each display controller for generating the corresponding image frame sub-block and storing the image frame sub-block into the corresponding first buffer sub-region isProcessing time length corresponding to each display controllerRefresh rate with target displayThe following formula 1-1 is satisfied therebetween:

（1-1）；

That is, the processing time length corresponding to each display controller Maximum value of (2)No greater than a target display refresh rateCorresponding single frame refresh durationWherein, the method comprises the steps of, wherein,Is a positive integer. Thus, the reference duration threshold does not exceed the target display refresh rateCorresponding single frame refresh duration。

In implementation, a person skilled in the art may determine an appropriate reference duration threshold according to an actual situation, so that the reference duration threshold does not exceed a single frame refresh duration corresponding to the target display refresh rate, which is not limited by the embodiments of the present disclosure.

Step S212, determining a reference clock frequency based on the reference time period threshold.

Here, the reference clock frequency characterizes the clock frequency required for the display controller to complete the generation and storage of the corresponding image frame sub-blocks below the reference time duration threshold.

In some embodiments, for a reference duration thresholdThe reference clock frequency may be。

Step S213, determining clock frequencies corresponding to the plurality of display controllers respectively based on the reference clock frequency.

Here, since the reference clock frequency characterizes the clock frequency required for the display controller to complete the generation and storage of the corresponding image frame sub-block under the reference time period threshold, the reference time period threshold characterizes the time period upper limit consumed by each display controller to generate the corresponding image frame sub-block and store the image frame sub-block to the corresponding first buffer sub-zone if the target display refresh rate is satisfied. Therefore, according to the reference clock frequency, the clock frequency corresponding to each display controller can be determined, so that the processing time required by each display controller to complete the generation and storage of the image frame sub-blocks does not exceed the reference time threshold.

In practice, a person skilled in the art may determine, according to the actual situation, the clock frequency corresponding to each display controller based on the reference clock frequency in any suitable manner.

In the above embodiment, based on the target display refresh rate, a reference time length threshold is determined, where the reference time length threshold does not exceed a single frame refresh time length corresponding to the target display refresh rate; determining a reference clock frequency based on a reference duration threshold; based on the reference clock frequency, a clock frequency respectively corresponding to the plurality of display controllers is determined. In this way, the processing time consumed by each display controller to generate and store the corresponding image frame sub-block can better meet the target display refresh rate, so that the display performance can be improved, and the smoothness and quality of the game and/or video playing can be improved.

In some embodiments, the step S213 may include the following step S221 or step S222:

step S221, determining clock frequencies corresponding to the plurality of display controllers as the reference clock frequency.

Thus, the clock frequency corresponding to each display controller can be simply and quickly determined while the target display refresh rate is satisfied.

Step S222, determining, for each display controller, a load parameter of the display controller, and determining, based on the load parameter and the reference clock frequency, a clock frequency corresponding to the display controller; the load parameters of the display controllers represent the workload required by generating and storing the image frame sub-blocks corresponding to the display controllers, and the clock frequency corresponding to each display controller is in a proportional relation with the load parameters.

Here, the load parameters of the display controller may include any suitable parameters capable of characterizing the workload required to generate and store the image frame sub-blocks corresponding to the display controller, which the disclosed embodiments are not limited to.

In some embodiments, the load parameter corresponding to the display controller includes at least one of: the method comprises the steps of displaying the number of image layers to be displayed in image frame sub-blocks corresponding to the display controller, displaying the size of the image layers to be displayed in the image frame sub-blocks corresponding to the display controller and displaying the size of the image frame sub-blocks corresponding to the display controller.

In some embodiments, the number of image layers to be displayed in the image frame sub-block corresponding to each display controller, the size of the image layers to be displayed, and the like may be determined based on the distribution state of the image layers in the currently rendered image content of one frame. For example, the number of image layers to be displayed in the image frame sub-block corresponding to each display controller may be determined according to the distribution position of each image layer in the currently rendered image content of one frame. For another example, the number of image layers to be displayed in the image frame sub-block corresponding to each display controller, the size of the image layers to be displayed, and the like may be determined according to the distribution position and the size of each image layer in the currently rendered image content of one frame.

In some embodiments, the size of the image frame sub-block corresponding to each display controller may be determined based on the size of the first buffer sub-region corresponding to the display controller.

In practice, a person skilled in the art may determine, according to the actual situation, the clock frequency corresponding to the display controller based on the load parameter of the display controller and the reference clock frequency in any suitable manner, which is not limited herein. The clock frequency of each display controller is in a proportional relation with the load parameter, that is, the larger the load parameter of the display controller represents the work load required by the display controller to generate and store the corresponding image frame sub-block, the higher the clock frequency of the display controller is, and the smaller the load parameter of the display controller represents the work load required by the display controller to generate and store the corresponding image frame sub-block is, the lower the clock frequency of the display controller is.

It will be appreciated that the greater the number of image layers to be displayed in the corresponding image frame sub-block of the display controller, the greater the workload required for the display controller to generate and store the corresponding image frame sub-block; the larger the size of the image layer to be displayed in the image frame sub-block corresponding to the display controller, the larger the workload required for the display controller to generate and store the corresponding image frame sub-block; the larger the size of the corresponding image frame sub-block of the display controller, the larger the workload required for the display controller to generate and store the corresponding image frame sub-block.

In some embodiments, a plurality of load parameters and corresponding relations between a plurality of reference clock frequencies and clock frequencies of the display controller may be preset, and by querying the corresponding relations, the current load parameters of the display controller and the clock frequencies corresponding to the reference clock frequencies may be determined.

In some embodiments, the clock frequency corresponding to the display controller with the load parameter as the reference value may be set as the reference clock frequency based on determining the reference value of the load parameter; for a display controller whose load parameter is not the reference value, a ratio between the load parameter of the display controller and the reference value may be determined, and a clock frequency corresponding to the display controller may be determined based on a product between the reference clock frequency and the ratio.

In the above embodiment, by determining the clock frequency corresponding to the display controller based on the load parameter and the reference clock frequency of the display controller, the load parameter of the display controller characterizes the workload required for generating and storing the image frame sub-blocks corresponding to the display controller, and the clock frequency corresponding to each display controller is in a proportional relationship with the load parameter. In this way, the clock frequency of each display controller can be better adapted to the current load parameter due to the proportional relation between the clock frequency corresponding to each display controller and the load parameter, so that the resource utilization rate can be improved while the display refresh rate requirement is met, and the power consumption is saved.

In some embodiments, the determining the clock frequency corresponding to the display controller based on the load parameter and the reference clock frequency in the step S222 may include the following step S231 or step S232:

In step S231, when the load parameter of the display controller is the maximum value of the load parameters corresponding to the plurality of display controllers, the clock frequency corresponding to the display controller is determined to be the reference clock frequency.

Step S232, determining a ratio between the load parameter of the display controller and the maximum value, and determining a clock frequency corresponding to the display controller based on a product between the reference clock frequency and the ratio, when the load parameter of the display controller is not the maximum value of the load parameters respectively corresponding to the plurality of display controllers.

In some embodiments, the load parameter includes a number of image layers to be displayed in a corresponding image frame sub-block of the display controller. In the case that the first number of image layers to be displayed in the image frame sub-block corresponding to the display controller is the maximum value in the number of image layers to be displayed in the image frame sub-block corresponding to the plurality of display controllers, determining that the clock frequency corresponding to the display controller is the reference clock frequency; and under the condition that the first number of the image layers to be displayed in the image frame sub-block corresponding to the display controller is not the maximum value in the number of the image layers to be displayed in the image frame sub-block corresponding to the plurality of display controllers, determining the ratio between the first number and the maximum value, and determining the product between the reference clock frequency and the ratio as the clock frequency corresponding to the display controller.

In some embodiments, the load parameter includes a size of an image layer to be displayed in a corresponding image frame sub-block of the display controller. In the case that the first size of the image layer to be displayed in the image frame sub-block corresponding to the display controller is the maximum value in the sizes of the image layers to be displayed in the image frame sub-blocks corresponding to the plurality of display controllers, determining that the clock frequency corresponding to the display controller is the reference clock frequency; and determining a ratio between the first size and the maximum value under the condition that the first size of the image layer to be displayed in the image frame sub-block corresponding to the display controller is not the maximum value in the sizes of the image layers to be displayed in the image frame sub-blocks corresponding to the display controllers respectively, and determining the product between the reference clock frequency and the ratio as the clock frequency corresponding to the display controller.

In some embodiments, the load parameter includes a size of a corresponding image frame sub-block of the display controller. In the case that the second size of the image frame sub-block corresponding to the display controller is the maximum value of the sizes of the image frame sub-blocks respectively corresponding to the plurality of display controllers, determining that the clock frequency corresponding to the display controller is the reference clock frequency; and under the condition that the second size of the image frame sub-block corresponding to the display controller is not the maximum value in the sizes of the image frame sub-blocks respectively corresponding to the plurality of display controllers, determining the ratio between the second size and the maximum value, and determining the product between the reference clock frequency and the ratio as the clock frequency corresponding to the display controller.

In the above embodiment, when the load parameter of the display controller is the maximum value of the load parameters respectively corresponding to the plurality of display controllers, the clock frequency corresponding to the display controller is determined to be the reference clock frequency; and under the condition that the load parameter of the display controller is not the maximum value of the load parameters respectively corresponding to the plurality of display controllers, determining the ratio between the load parameter of the display controller and the maximum value, and determining the clock frequency corresponding to the display controller based on the product of the reference clock frequency and the ratio. In this way, the clock frequency of the display controller with the largest load parameter among the plurality of display controllers is the highest (i.e. the reference clock frequency), and for other display controllers with the workload smaller than the display controller with the largest workload, the ratio between the clock frequency of the other display controllers and the reference clock frequency can be in a proportional relation with the ratio between the load parameter of the other display controllers and the maximum value of each load parameter, i.e. the clock frequency corresponding to the display controller with the smaller load parameter is reduced in proportion to the reference clock frequency, so that the clock frequency of each display controller can be better adapted to the current load parameter, thereby improving the resource utilization rate and saving the power consumption while meeting the display refresh rate requirement.

Fig. 3A is a schematic diagram of a composition structure of a display system according to an embodiment of the present disclosure, as shown in fig. 3A, the display system 300 includes: the main processor 310, a plurality of display controllers 320, a memory 330 and a display panel 340, wherein the memory 330 includes a plurality of first buffer sub-areas 3310, the plurality of display controllers 320 are in one-to-one correspondence with the plurality of first buffer sub-areas 3310, wherein:

the display controller 320 is configured to: responding to the received clock signal, and acquiring a corresponding image content sub-block from the currently rendered image content of one frame; generating image frame sub-blocks based on the image content sub-blocks and storing the image frame sub-blocks into the corresponding first buffer sub-regions 3310;

The main processor 310 is configured to: acquiring clock frequencies respectively corresponding to the display controllers 320; for each display controller 320, adjusting a clock signal corresponding to the display controller 320 based on a clock frequency corresponding to the display controller 320; in response to each display controller 320 completing the storage of the image frame sub-blocks, a target image frame is obtained using the image frame sub-blocks stored in each first buffer sub-region and sent to the display panel 340 for display by the display panel 340.

In practice, the number of the main processors may be one or more. In the case where the number of main processors is one, the clock signal corresponding to each display controller can be adjusted by the one main processor. In the case where the number of the main processors is plural, the clock signals corresponding to at least one display controller may be respectively provided by the plural main processors.

In some embodiments, with continued reference to fig. 3A, the plurality of first buffer regions 3310 are obtained by equally sizing the first buffer region 331; or the plurality of first buffer areas 3310 are obtained by dividing the first buffer area 331 based on the number of the plurality of display controllers 320 and the distribution state of the image layers in the currently rendered image content of one frame.

In some embodiments, referring to fig. 3B, the number of the main processors 310 is plural, and each display controller 320 corresponds to one main processor 310; each host processor 310 is configured to: for each display controller 320 corresponding to the main processor 310, a clock frequency corresponding to the display controller 320 is obtained, and a clock signal corresponding to the display controller 320 is adjusted based on the clock frequency corresponding to the display controller 320.

In some embodiments, the number of main processors may be equal to the number of display controllers, and the plurality of main processors may be in one-to-one correspondence with the plurality of display controllers.

In some embodiments, the number of main processors is a plurality, and the number of main processors may be less than the number of display controllers. Each host processor may correspond to one or more display controllers, respectively.

In some embodiments, the main processor is further configured to: and reducing the frequency of a clock signal of a first display controller in the plurality of display controllers when the first display controller has completed storing the image frame sub-blocks and at least one second display controller in the plurality of display controllers has not completed storing the image frame sub-blocks.

In some embodiments, each of the first buffer sub-regions is the same size; or the number and/or the size of the image layers to be displayed in the image frame sub-blocks to be stored in each first buffer sub-region are the same.

In some embodiments, referring to fig. 3C, the display system 300 further includes a graphics renderer 350;

a graphics renderer 350 for rendering the graphics contents to be displayed according to a current graphics rendering frame rate, and storing a currently rendered frame of the graphics contents in the second buffer 332 of the memory 330; the second buffer 332 is divided into a plurality of second buffer sub-areas (not shown), and the plurality of display controllers 320 are in one-to-one correspondence with the plurality of second buffer sub-areas;

The display controller 320 is configured to read the corresponding image content sub-block from the corresponding second buffer sub-area in response to receiving the clock signal.

In some embodiments, referring to fig. 3D and 3E, the display system 300 further includes a DMA controller 360;

the main processor 310 is further configured to: in response to each of the display controllers 320 completing the storage of the image frame sub-blocks, the DMA controller 360 is driven to compose a target image frame from the image frame sub-blocks stored in each of the first buffer sub-areas and then transmit the target image frame to the display panel 340.

Fig. 4 is a schematic diagram of a composition structure of a display controller according to an embodiment of the present disclosure, as shown in fig. 4, the display controller 400 includes:

A second obtaining module 410, configured to obtain, in response to receiving the clock signal, a corresponding image content sub-block from a currently rendered image content frame; wherein the clock signal is adjusted based on a clock frequency corresponding to the display controller;

a generating module 420, configured to generate an image frame sub-block based on the image content sub-block;

A storage module 430, configured to store the image frame sub-block into a first target buffer sub-area; the first target buffer subarea is a first buffer subarea corresponding to the display controller in a plurality of first buffer subareas; the plurality of first buffer subareas are in one-to-one correspondence with the plurality of display controllers, and the plurality of image frame subblocks stored in the plurality of first buffer subareas are used for determining target image frames.

The application of the display method provided by the embodiment of the disclosure in an actual scene is described below. The display method provided by the embodiment of the disclosure can be applied to any display system or a system with a display subsystem, such as a display subsystem in a mobile device, a display subsystem in a desktop device, a display subsystem in an augmented Reality (Augmented Reality, AR)/Virtual Reality (VR) wearable glass system, or a dashboard display subsystem, etc.

The display method provided by the embodiment of the disclosure can be applied to a variable refresh rate scheme in a display system.

In some variable refresh rate schemes, only one display controller is used to drive the display of image frames in a display panel. For example, an image frame to be displayed may be generated in a display frame buffer using a display controller and then sent to a display panel through a display interface using a DMA channel. In this scheme, however, there is a lack of flexibility in adjusting the display refresh rate because only one display controller is used and the upper performance limit of one display controller may have a limit on the display refresh rate. When the graphics rendering frame rate changes, the display refresh rate may not be well adjusted or fine tuned to match the graphics rendering frame rate, resulting in the display panel potentially dropping frames if the graphics rendering frame rate is higher than the display refresh rate limit of a single display controller. Further, since a single display controller uses a single pixel processing clock (corresponding to the clock signal in the foregoing embodiment) to generate the entire image frame, the power consumption will be fixed and cannot be adjusted or scaled according to actual needs.

In the embodiment of the present disclosure, the plurality of display controllers may be configured to be mapped into the plurality of first buffer sub-areas of the display frame buffer, that is, the plurality of display controllers may be configured to correspond to the plurality of first buffer sub-areas in the display frame buffer one by one, and the size of each first buffer sub-area may be predefined.

In theory, each pixel in the display frame buffer can be used as a first buffer area, i.e. each pixel distribution corresponds to a display controller.

In practice, there are 4 or 9 corresponding first buffer sub-regions within the display frame buffer, as there is a hardware cost, and in some embodiments the number of display controllers may be 2×2=4, or 3×3=9.

In some implementations, the display frame buffer may be divided into a plurality of first buffer sub-regions according to the following rules:

1) The divided first buffer sub-area should be kept to have the same aspect ratio as the display frame buffer area, that is, the same aspect ratio as the image frame to be displayed, so that the displayed image frame is more natural; for example: the aspect ratio of the image frame to be displayed is 16:9 and the aspect ratio of the single first buffer sub-area is also 16:9.

2) The minimum size of each first buffer subarea is not smaller than a preset minimum size threshold value; for example, the minimum size threshold may be 64×64, so if the size of the display frame buffer is 64×64, only one first buffer sub-area is defined.

3) If the size of the display frame buffer is not divisible by 3 x 3, the display frame buffer is divided into 2 x 2 first buffer sub-regions.

In some embodiments, the display frame buffer may be a buffer in a double rate synchronous dynamic random access memory (DDR) that is the same size as the resolution of the display panel.

Because the method provided by the embodiment of the disclosure adopts a plurality of display controllers, the display refresh rate can be finely adjusted to be more accurately matched with the graphics rendering frame rate. In addition, the method provided by the embodiment of the disclosure can independently set the clock rate (corresponding to a plurality of clock signals) of pixel processing for each display controller, so that the power consumption can be finely adjusted to save power.

In the embodiment of the disclosure, the plurality of display controllers can work simultaneously aiming at different first buffer subareas of the display frame buffer area, so that the synthesis of the image frames to be displayed in the display frame buffer area can be completed at one time, and the synthesis efficiency of the image frames to be displayed is improved. For example, the synthesis efficiency of the image frame may be improved by 4 times for a scheme of dividing the display frame buffer into 2×2 first buffer sub-areas, and by 9 times for a scheme of dividing the display frame buffer into 3×3 first buffer sub-areas.

In some embodiments, each display controller may be designed with separate clock signals, clock gating signals, and the like. Thus, each display controller may be controlled individually. The clock signal of each display controller may be controlled by a CPU-type main processor. In practice, each display controller may have a dedicated host processor, or multiple display controllers may share a host processor.

In some implementations, in a variable refresh rate mode, the refresh rate is refreshed for a target displayFps (or Hz), the synthesis time to complete a single image frame isSecond, then the first of the entire display frame bufferThe completion time of storing the image frame sub-blocks in the first buffer sub-areas isIn the case where the equation in the above equation 1-1 is established, the entire display system can be operated normally.

In practice, there are two cases of region division of the display frame buffer:

The first case is that the size of the region division in the display frame buffer is the same, i.e. the size of each divided first buffer sub-region is the same. In this way, a different number of image layers may be included in the image frame sub-blocks to be stored in each first buffer sub-region. The greater the number of image layers contained in the image frame sub-block to be stored in the first buffer sub-region, the greater the workload of the display controller corresponding to the first buffer sub-region.

The second case is that the size of the region division within the display frame buffer is different, but the number of image layers contained in the image frame sub-blocks to be stored within each first buffer sub-region is the same. In this case, the workload may be determined using the size of each first buffer sub-region, so that the larger the size, the larger the workload of the display controller corresponding to the first buffer sub-region. In practice, the image frame sub-blocks to be stored in the first buffer sub-region of the largest size in the display frame buffer may be synthesized on time to satisfy the equation in equation 1-1 above. Assuming that the synthesis completion time of the image frame sub-block to be stored in the first buffer sub-region having the largest size in the display frame buffer is T seconds in the case where the equation in the above equation 1-1 is satisfied, the clock rate of the display controller corresponding to the first buffer sub-region having the largest size isHz。

In some embodiments, one of two methods may be employed to set the clock frequency of all display controllers:

1) Setting the clock frequency of all display controllers to be Hz. This approach will allow the image frame sub-blocks in the smaller size first buffer sub-area, or the image frame sub-blocks containing the smaller number of image layers, to be synthesized in advance, in which case the main processor, which then controls the clock signals of the display controllers, may turn off the clock signals of the display controllers to save power consumption.

2) Setting the clock frequency of the display controller corresponding to the first buffer subarea with the largest size asHz, for each other first buffer zone, determining the ratio between the size of the other first buffer zone and the size of the largest first buffer zone, and comparing the ratio withThe product of the first buffer sub-region is determined as the clock signal of the display controller corresponding to the other first buffer sub-region, so that the larger the size is, the higher the clock frequency of the display controller corresponding to the first buffer sub-region is, thereby improving the resource utilization rate and saving the power consumption.

In the embodiment of the disclosure, the multiple display controllers are adopted, so that the completely programmable mapping from the display controllers to each first buffer subarea in the display frame buffer area is realized, the sizes of the first buffer subareas in the display frame buffer area are completely programmable, and in addition, the clock signals of each display controller can be separately controlled. In this way, greater flexibility is provided for setting up the display system to achieve fine-grained display refresh control, so that the display refresh rate can be increased, and power consumption can be saved.

Based on the foregoing embodiments, the embodiments of the present disclosure provide a display apparatus, which includes units included, and modules included in the units, which may be implemented by a processor in a computer device; of course, the method can also be realized by a specific logic circuit; in an implementation, the Processor may be a central processing unit (Central Processing Unit, CPU), a microprocessor (Microprocessor Unit, MPU), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), or a field programmable gate array (Field Programmable GATE ARRAY, FPGA), or the like.

Fig. 5 is a schematic diagram of a composition structure of a display device according to an embodiment of the disclosure, and as shown in fig. 5, a display device 500 includes: a first acquisition module 510, a first adjustment module 520, and a get module 530, wherein:

A first obtaining module 510, configured to obtain clock frequencies corresponding to the plurality of display controllers respectively; wherein the plurality of display controllers are in one-to-one correspondence with the plurality of first buffer subareas;

a first adjustment module 520, configured to adjust, for each of the display controllers, a clock signal corresponding to the display controller based on a clock frequency corresponding to the display controller, where the clock signal is used to drive the display controller to obtain a corresponding image content sub-block from a currently rendered image content, generate an image frame sub-block based on the image content sub-block, and store the image frame sub-block in a corresponding first buffer sub-area;

And a obtaining module 530, configured to obtain, in response to each of the display controllers completing storage of the image frame sub-blocks, the target image frame using the image frame sub-blocks stored in each of the first buffer sub-areas.

In some embodiments, the first acquisition module is further to: acquiring a current graphic rendering frame rate; determining a target display refresh rate based on the graphics rendering frame rate; and determining clock frequencies respectively corresponding to the display controllers based on the target display refresh rate.

In some embodiments, the first acquisition module is further to: determining a reference duration threshold based on the target display refresh rate; the reference time length threshold value does not exceed the single frame refresh time length corresponding to the target display refresh rate; determining a reference clock frequency based on the reference time duration threshold; and determining clock frequencies respectively corresponding to the display controllers based on the reference clock frequency.

In some embodiments, the first acquisition module is further to: determining clock frequencies respectively corresponding to the display controllers as the reference clock frequency; or, determining a load parameter of each display controller, and determining a clock frequency corresponding to the display controller based on the load parameter and the reference clock frequency; the load parameters of the display controllers represent the workload required by generating and storing the image frame sub-blocks corresponding to the display controllers, and the clock frequency corresponding to each display controller is in a proportional relation with the load parameters.

In some embodiments, the first acquisition module is further configured to one of: determining that the clock frequency corresponding to the display controller is the reference clock frequency under the condition that the load parameter of the display controller is the maximum value of the load parameters corresponding to the display controllers; and under the condition that the load parameter of the display controller is not the maximum value of the load parameters respectively corresponding to the plurality of display controllers, determining the ratio between the load parameter of the display controller and the maximum value, and determining the clock frequency corresponding to the display controller based on the product of the reference clock frequency and the ratio.

In some embodiments, the load parameter of the display controller includes at least one of: the method comprises the steps of displaying the number of image layers to be displayed in image frame sub-blocks corresponding to the display controller, displaying the size of the image layers to be displayed in the image frame sub-blocks corresponding to the display controller and displaying the size of the image frame sub-blocks corresponding to the display controller.

In some embodiments, the apparatus further comprises: and the reducing module is used for reducing the frequency of the clock signal of the first display controller under the condition that the first display controller in the plurality of display controllers has completed storing the image frame sub-blocks and at least one second display controller in the plurality of display controllers has not completed storing the image frame sub-blocks.

In some embodiments, the plurality of first buffer sub-regions is obtained by region-dividing the first buffer region; the apparatus further comprises one of: a first dividing module, configured to divide the first buffer into a plurality of first buffer sub-areas with the same size based on the number of the plurality of display controllers; and the second dividing module is used for dividing the first buffer area into a plurality of first buffer subareas based on the number of the display controllers and the distribution state of the image layers in the currently rendered image content of one frame.

The description of the apparatus embodiments above is similar to that of the method embodiments above, with similar advantageous effects as the method embodiments. In some embodiments, functions or modules included in the apparatus provided by the embodiments of the present disclosure may be used to perform the methods described in the embodiments of the method, and for technical details not disclosed in the embodiments of the apparatus of the present disclosure, please understand with reference to the description of the embodiments of the method of the present disclosure.

It should be noted that, in the embodiment of the present disclosure, if the method is implemented in the form of a software functional module, and sold or used as a separate product, the method may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present disclosure may be essentially or portions contributing to the related art, and the software product may be stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the present disclosure are not limited to any specific hardware, software, or firmware, or any combination of the three.

The disclosed embodiments provide a computer readable storage medium having stored thereon a computer program which when executed by a processor performs some or all of the steps of the above method. The computer readable storage medium may be transitory or non-transitory.

The disclosed embodiments provide a computer program comprising computer readable code which, when run in a computer device, performs some or all of the steps for implementing the methods described above.

Embodiments of the present disclosure provide a computer program product comprising a computer program or instructions which, when executed by a processor, implement some or all of the steps of the above-described method. The computer program product may be realized in particular by means of hardware, software or a combination thereof. In some embodiments, the computer program product is embodied as a computer storage medium, and in other embodiments, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

It should be noted here that: the above description of various embodiments is intended to emphasize the differences between the various embodiments, the same or similar features being referred to each other. The above description of apparatus, storage medium, computer program and computer program product embodiments is similar to that of method embodiments described above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the disclosed apparatus, storage medium, computer program and computer program product, please refer to the description of the embodiments of the disclosed method.

It should be noted that, fig. 6 is a schematic diagram of a hardware entity of a computer device in an embodiment of the disclosure, as shown in fig. 6, the hardware entity of the computer device 600 includes: a processor 601, a communication interface 602, and a memory 603, wherein:

the processor 601 generally controls the overall operation of the computer device 600.

The communication interface 602 may enable a computer device to communicate with other terminals or servers over a network.

The memory 603 is configured to store instructions and applications executable by the processor 601, and may also cache data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or processed by various modules in the processor 601 and the computer device 600, which may be implemented by a FLASH memory (FLASH) or a random access memory (Random Access Memory, RAM). Data transfer may be performed between the processor 601, the communication interface 602, and the memory 603 via the bus 604.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the size of the sequence numbers of the steps/processes described above does not mean the order of execution, and the order of execution of the steps/processes should be determined by their functions and inherent logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read Only Memory (ROM), a magnetic disk or an optical disk, or the like, which can store program codes.

Or the integrated units of the present disclosure may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the present disclosure may be embodied essentially or in part in a form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.

The foregoing is merely an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A display method, the method comprising:

2. The method of claim 1, wherein the obtaining clock frequencies respectively corresponding to the plurality of display controllers comprises:

Acquiring a current graphic rendering frame rate;

Determining a target display refresh rate based on the graphics rendering frame rate;

and determining clock frequencies respectively corresponding to the display controllers based on the target display refresh rate.

3. The method of claim 2, wherein the determining the respective clock frequencies of the plurality of display controllers based on the target display refresh rate comprises:

Determining a reference duration threshold based on the target display refresh rate; the reference time length threshold value does not exceed the single frame refresh time length corresponding to the target display refresh rate;

determining a reference clock frequency based on the reference time duration threshold;

And determining clock frequencies respectively corresponding to the display controllers based on the reference clock frequency.

4. The method of claim 3, wherein the determining the respective clock frequencies of the plurality of display controllers based on the reference clock frequency comprises:

Determining clock frequencies respectively corresponding to the display controllers as the reference clock frequency;

Or alternatively, the first and second heat exchangers may be,

Determining a load parameter of each display controller, and determining a clock frequency corresponding to the display controller based on the load parameter and the reference clock frequency; the load parameters of the display controllers represent the workload required by generating and storing the image frame sub-blocks corresponding to the display controllers, and the clock frequency corresponding to each display controller is in a proportional relation with the load parameters.

5. The method of claim 4, wherein the determining the clock frequency corresponding to the display controller based on the load parameter and the reference clock frequency comprises one of:

Determining that the clock frequency corresponding to the display controller is the reference clock frequency under the condition that the load parameter of the display controller is the maximum value of the load parameters corresponding to the display controllers;

And under the condition that the load parameter of the display controller is not the maximum value of the load parameters respectively corresponding to the plurality of display controllers, determining the ratio between the load parameter of the display controller and the maximum value, and determining the clock frequency corresponding to the display controller based on the product of the reference clock frequency and the ratio.

6. The method of claim 4, wherein the load parameter of the display controller comprises at least one of: the method comprises the steps of displaying the number of image layers to be displayed in image frame sub-blocks corresponding to the display controller, displaying the size of the image layers to be displayed in the image frame sub-blocks corresponding to the display controller and displaying the size of the image frame sub-blocks corresponding to the display controller.

7. The method according to any one of claims 1 to 6, further comprising:

And reducing the frequency of a clock signal of a first display controller in the plurality of display controllers when the first display controller has completed storing the image frame sub-blocks and at least one second display controller in the plurality of display controllers has not completed storing the image frame sub-blocks.

8. The method according to any one of claims 1 to 6, wherein the plurality of first buffer sub-areas are obtained by area-dividing a first buffer area; the method further comprises the steps of:

Dividing the first buffer into a plurality of first buffer sub-areas having the same size based on the number of the plurality of display controllers;

Or alternatively, the first and second heat exchangers may be,

The first buffer area is divided into the plurality of first buffer sub-areas based on the number of the plurality of display controllers and the distribution state of the image layers in the currently rendered image content of one frame.

9. The method of any one of claims 1 to 6, wherein the currently rendered frame of image content is stored in a second buffer, the plurality of display controllers being in one-to-one correspondence with a plurality of second buffer sub-regions in the second buffer;

The clock signal corresponding to the display controller is further used for driving the display controller to read the corresponding image content sub-block from the corresponding second buffer sub-area.

10. A display system comprising a main processor, a plurality of display controllers, a memory and a display panel, wherein the memory comprises a plurality of first buffer subareas, the plurality of display controllers are in one-to-one correspondence with the plurality of first buffer subareas, and wherein:

11. The display system of claim 10, wherein the number of main processors is plural, and each display controller corresponds to one main processor;

Each of the main processors is respectively used for: and aiming at each display controller corresponding to the main processor, acquiring the clock frequency corresponding to the display controller, and adjusting the clock signal corresponding to the display controller based on the clock frequency corresponding to the display controller.

12. The display system of claim 10, wherein the main processor is further configured to: and reducing the frequency of a clock signal of a first display controller in the plurality of display controllers when the first display controller has completed storing the image frame sub-blocks and at least one second display controller in the plurality of display controllers has not completed storing the image frame sub-blocks.

13. The display system of claim 10, wherein the display system is configured to display the plurality of images,

The plurality of first buffer subareas are obtained by equally dividing the first buffer areas; or alternatively

The plurality of first buffer subareas are obtained by dividing the first buffer areas based on the number of the plurality of display controllers and the distribution state of image layers in the currently rendered image content of one frame.

14. The display system of claim 10, wherein the display system further comprises a graphics renderer;

the image renderer is used for rendering the image content to be displayed according to the current image rendering frame rate and storing the current rendered image content of one frame into a second buffer area of the memory; the second buffer area is divided into a plurality of second buffer subareas, and the plurality of display controllers are in one-to-one correspondence with the plurality of second buffer subareas;

the display controller is configured to read the corresponding image content sub-block from the corresponding second buffer sub-area in response to receiving the clock signal.

15. The display system of any one of claims 10 to 14, further comprising a direct memory access controller;

The main processor is further configured to: and responding to the fact that each display controller finishes storing the image frame sub-blocks, driving the direct memory access controller to form target image frames from the image frame sub-blocks stored in each first buffer subarea, and then sending the target image frames to the display panel.

16. A display device, the device comprising:

17. A display controller, comprising:

18. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that the processor implements the steps of the method of any of claims 1 to 9 when the program is executed.

19. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, realizes the steps in the method of any one of claims 1 to 9.

20. A computer program product comprising a computer program or instructions which, when executed by a processor, carries out the steps of the method of any one of claims 1 to 9.