CN117913084A - Photoelectric chip hybrid packaging structure and packaging method based on 2.5D packaging technology - Google Patents

Abstract

The invention relates to a photoelectric chip mixed packaging structure based on a 2.5D packaging technology, which comprises the following components: the optical fiber array is horizontally coupled with a photosensitive area on a first side surface of the high-dimensional matrix optical chip, and an adhesion reinforcing layer is arranged between the middle layer and the high-dimensional matrix optical chip and between the middle layer and the high-dimensional matrix optical chip, wherein the first side surface extends out of the middle layer to suspend the optical fiber array, and the center of gravity of a multilayer structure formed by the high-dimensional matrix optical chip, the optical fiber array, the adhesion reinforcing layer and the middle layer is deviated along a direction away from the center of gravity of the middle layer; a plurality of electrical chips surrounds the high-dimensional matrix optical chip, and a plurality of the electrical chips around a second side of the high-dimensional matrix optical chip disposed opposite to the first side are offset in a direction away from the high-dimensional matrix optical chip. Correspondingly, a packaging method for preparing the mixed packaging structure is also provided.

Description

Photoelectric chip hybrid packaging structure and packaging method based on 2.5D packaging technology

Technical Field

The invention relates to the technical field of advanced packaging based on a silicon optical platform, such as semiconductors, optical communication, laser radars and the like, in particular to a photoelectric chip hybrid packaging structure and a packaging method based on a 2.5D packaging technology.

Background

With the continued development of big data, artificial intelligence, telemedicine, internet of things, electronic commerce, 5G communications, global data traffic has exploded, lower cost, more reliable, faster and higher density circuits are the goal of integrated circuit packaging pursuits.

In order to meet the requirement of internet traffic, the bandwidth of the data center node needs to reach 10Tb/s, and in order to slow down the trend of increasing the energy consumption of the data center, a method for reducing the power consumption of a system and devices is needed. Under the drive of ultra-high data capacity, the traditional electric chip manufacturing process gradually approaches to 10nm size, the CMOS technology is about to meet physical limit, and the silicon optical chip is widely considered to organically combine mature microelectronic and photoelectronic technologies in the industry due to the fact that light has the performances of small signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS, so that the chip size, cost and power consumption can be reduced, reliability can be improved, and the silicon optical chip is expected to become a 'super-mole' high-speed information engine. Therefore, the introduction of silicon optical technology is necessary, and since the goal of the introduction of silicon optical technology is to increase the input/output (I/O) bandwidth and minimize the power consumption, how the optical integrated circuit (PIC) and the Electrical Integrated Circuit (EIC) are packaged is important, and these factors directly affect the I/O bandwidth and power consumption.

Most of the existing optoelectronic integrated semiconductor packaging structures directly bond an optical integrated Chip and an electrical integrated Chip on a substrate, and are electrically connected with the substrate by a wire-bonding (wire-bonding) or Flip-Chip bonding (Flip-Chip) method. Because the silicon optical process node is relatively backward compared with the electric chip, the silicon optical process node developed by the current single chip integration is a 45nm and 32nm process, which is far different from the process node below 10nm of the electric chip, so that the current photoelectric integrated semiconductor packaging structure is difficult to meet the requirement of high-density integrated packaging.

Based on this, in the prior art, an optoelectronic integrated semiconductor package structure is proposed, such as CN116960003a, where an optical chip and an electrical chip are encapsulated by a TSV substrate, a rewiring layer, an optical waveguide wiring layer and a micro-mirror, so that stacking interconnection and staggered routing of electrical signal wiring and optical signal wiring can be realized, so as to reduce the package area, increase the wiring density, effectively shorten the transmission paths of optical signals and electrical signals, reduce the signal attenuation, improve the integrated operation capability, and meet the requirements of high-density integrated package.

In another example, CN116960002a, through a rewiring layer, a metal pillar, a three-dimensional optical waveguide wiring, a packaging layer, an optical chip, an electrical chip, a metal bump, a substrate and a connector, the optical chip and the electrical chip can be sealed, so as to realize stacked interconnection and staggered routing of an electrical signal wiring and an optical signal wiring, so as to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of the optical signal and the electrical signal, reduce the signal attenuation, and lead the optical waveguide out from the side of the packaging body, so that the modularization combination capability can be increased, the system packaging is realized, and the requirement of high-density integrated packaging is met.

For another example, CN219625758U integrates optical chips and electrical chips with different process nodes through a subsequent process, and uses a rewiring layer to realize signal connection between the optical chips and the electrical chips, so as to realize a low-cost and high-density photoelectric co-packaging structure, and simultaneously make the electrical chips and the optical chips located on the same side of the substrate and far from one side of the substrate in flat contact with the heat dissipation cover plate, improve the transmission rate, and also consider the heat dissipation requirement of the photoelectric packaging structure.

However, the above-mentioned hybrid packaging structure of the optoelectronic chip is based on a 2.5D packaging technology to perform hybrid packaging between a plurality of small-scale optical chips and a plurality of electrical chips, and although the computing capability can be improved by integrating a plurality of small-scale optical chips and connecting a plurality of electrical chips for each optical chip, it is difficult for the mask plate under the conventional wafer area to scale the computing array to an application level due to the limitation of the structural size of the conventional small-scale optical chip.

Based on this, the present inventors have proposed a high-dimensional matrix optical chip, such as CN116736933A, CN117234276a, whose photon calculation unit size is smaller than 100 μm. However, there is no hybrid packaging structure and process for high-dimensional matrix optical chips and electrical chips, and because the 2.5D packaging technology has too dense routing and warpage easily occurs in the silicon interposer (or the middle layer or the interposer), when the large-scale optical chips and electrical chips are subjected to hybrid packaging, there is a high requirement on reasonable layout of the hybrid packaging structure. That is, there is a need for a hybrid package structure for high-dimensional matrix optical chips and electrical chips.

Disclosure of Invention

The invention aims to provide a photoelectric chip mixed packaging structure based on a 2.5D packaging technology, which partially solves or alleviates the defects in the prior art and can realize mixed packaging between a high-dimensional matrix optical chip and a plurality of electric chips.

In order to solve the technical problems, the invention adopts the following technical scheme:

a hybrid packaging structure for an optoelectronic chip based on 2.5D packaging technology, comprising: the optical fiber array comprises an intermediate layer, a plurality of electric chips, a high-dimensional matrix optical chip and an optical fiber array, wherein the electric chips are flip-chip mounted on the intermediate layer, the high-dimensional matrix optical chip is flip-chip mounted on the intermediate layer through an optical chip bonding pad on the lower surface, the optical fiber array is horizontally coupled with a photosensitive area on a first side surface in the high-dimensional matrix optical chip, and an adhesion reinforcing layer is arranged between the intermediate layer and the high-dimensional matrix optical chip and the electric chips and is used for bonding the lower surface and the bottom of the electric chips, the first side surface extends out of the intermediate layer so that the optical fiber array is suspended, and the center of gravity of a multilayer structure formed by the high-dimensional matrix optical chip, the optical fiber array, the adhesion reinforcing layer and the intermediate layer is offset along a direction away from the center of gravity of the intermediate layer; the plurality of electric chips surround the high-dimensional matrix optical chip, and the plurality of electric chips around a second side surface of the high-dimensional matrix optical chip, which is opposite to the first side surface, are offset in a direction away from the high-dimensional matrix optical chip, so that the center of gravity of the multilayer structure formed by the high-dimensional matrix optical chip, the optical fiber array, all the electric chips, the adhesion reinforcing layer and the intermediate layer is close to the center of gravity of the intermediate layer.

In some embodiments of the invention, the adhesion enhancing layer is formed of an adhesive material filled between the plurality of conductive bumps between the photo-chip pad and the intermediate layer, and between the plurality of conductive bumps between the electrical chip and the intermediate layer; the conductive bumps comprise first conductive bumps for electrical connection and second conductive bumps for stress adjustment.

As described above, since the optical chip has a portion extending out of the intermediate layer, the electric chip corresponding to the other side of the optical chip opposite to the extending portion is moved rightward for balancing; meanwhile, in order to avoid the longer line between the optical chip and the electrical chip, it is desirable to make the electrical chip as close to the optical chip as possible without greatly increasing the size of the whole package structure (for example, without extending the right side of the middle layer to the right, thereby increasing the distance between the electrical chip and the optical chip to achieve the purpose of balancing the center of gravity). Therefore, on one hand, the bonding reinforcing layer is arranged, and on the other hand, the problem that the middle layer is warped and cracked due to the fact that the center of gravity is shifted is avoided by arranging more conductive protruding points. And, the more the bump, the larger the welding area, and the better the connectivity between the optical chip and the intermediate layer, and between the electric chip and the intermediate layer.

In some embodiments of the present invention, the hybrid packaging structure of an optoelectronic chip further includes a heat dissipation cover, the heat dissipation cover at least covers the plurality of electrical chips, the high-dimensional matrix optical chip and the optical fiber array, an opening is disposed on a side adjacent to the high-dimensional matrix optical chip so that one end of the optical fiber array passes through the opening to be optically coupled with the photosensitive area on the first side, and an upper surface of the optical fiber array is adhered to an inner side of the heat dissipation cover through an adhesive material. Most of the weight of the optical fiber array is dispersed on the heat dissipation cover, so that the influence of the optical fiber array on the center of gravity of the multilayer structure is reduced, and the occurrence of cracking of a coupling surface between the optical fiber array and the optical chip can be avoided.

In some embodiments of the present invention, the upper surface of the high-dimensional matrix optical chip and the upper surface of the electrical chip are adhered to the inner side surface of the heat dissipation cover by a heat-conductive adhesive material.

In some embodiments of the invention, the first side extends beyond the intermediate layer by a length of 1mm to 5mm.

In some embodiments of the present invention, the first spacing between the front and back sides of the high-dimensional matrix optical chip and the corresponding side plurality of electrical chips is 0.1mm to 0.5mm.

In some embodiments of the present invention, a wiring layer is provided between the intermediate layer and the adhesion enhancing layer, and the wiring layer has a line width of 0.5 μm to 10 μm and a line distance of 0.5 μm to 10 μm.

In some embodiments of the invention, the routing layer is 3-5 layers.

In some embodiments of the present invention, the hybrid package structure of an optoelectronic chip further includes: the base plate is used for bearing the middle layer, and the main board is used for bearing the base plate, and the base plate is electrically connected with the main board through socket or BGA welding.

In some embodiments of the present invention, the high-dimensional matrix optical chip is a photonic chip with a size of 64×64 or more.

Based on the above packaging structure, the invention also provides a manufacturing method of the photoelectric chip hybrid packaging structure, which comprises the following steps:

providing an intermediate layer and a high-dimensional matrix optical chip, wherein a first side surface of the high-dimensional matrix optical chip is provided with at least one photosensitive area, the photosensitive area is provided with an optical interface, the lower surface of the high-dimensional matrix light is arranged on the upper surface of the intermediate layer, and the first side surface extends out of the intermediate layer;

providing a plurality of electric chips, arranging the electric chips on the intermediate layer, surrounding three side surfaces of the high-dimensional matrix optical chip, and electrically connecting the electric chips with the high-dimensional matrix optical chip;

providing a heat dissipation cover which covers the intermediate layer, the high-dimensional matrix optical chips and all the electric chips, wherein one side of the heat dissipation cover corresponding to the optical interface is provided with an opening for an optical fiber array to enter into butt joint with the optical interface, and the top of the optical interface is fixed with the heat dissipation cover through an adhesive material;

When the high-dimensional matrix optical chip and the electric chip are arranged on the intermediate layer, the high-dimensional matrix optical chip, all the electric chips and the intermediate layer are adhered into a whole by filling the space between the lower surface of the high-dimensional matrix optical chip and the intermediate layer and the space between the electric chip and the intermediate layer with adhesive materials.

The bonding material is filled between the plurality of conductive convex points welded between the lower surface of the high-dimensional matrix optical chip and the middle layer, and the bonding material is filled between the plurality of conductive convex points welded between the electric chip and the middle layer, so that the optical chip and the middle layer are bonded together through the bonding material while the optical chip and the middle layer are bonded together through the conductive convex points, and the electric chips and the middle layer are bonded together through the bonding material while the electric chips and the middle layer are also bonded together through the conductive convex points, namely each structure in the multilayer structure is welded or bonded with the whole packaging structure, and the multilayer structure is integrated, so that the stability and rigidity of the whole packaging structure are greatly improved.

The beneficial effects are that: in the conventional packaging structure, for improving the computing power, a plurality of small-scale optical chips and a plurality of electrical chips are mixed and packaged based on MIZ, wherein, since the optical chip bonding pads and the photosensitive areas of the small-scale optical chips are arranged on the same surface, such as the lower surface, the optical chips can be electrically connected with the corresponding metal wiring layers through the optical chip bonding pads on the lower surface so as to be electrically connected with a small number of electrical chips, and the optical coupling state of the photosensitive areas and the optical fiber couplers is erected on the wiring layers and the optical fiber couplers. However, the computational power of such a package structure is still to be improved, and such a package structure is also only suitable for hybrid packaging between small-scale optical chips and electrical chips, limited by the size of each electronic computing unit itself (200 μm-300 μm) in the optical chip.

In order to achieve miniaturization and high integration of a photon calculation unit and thus achieve miniaturization of a high-dimensional matrix optical chip, the inventor proposes a large-scale optical chip (such as CN116736933A, CN 117234276A), wherein the size of the photon calculation unit is smaller than 100 μm, based on the fact, the application provides a packaging structure for carrying out mixed packaging on the large-scale optical chip and a large number of electric chips based on a 2.5 packaging technology, in particular, in order to ensure that the large-scale optical chip has enough channels and is connected with a wiring layer so as to achieve electrical interconnection with the large number of electric chips, a photosensitive area of the large-scale optical chip is arranged on a side face (namely, the photosensitive area and an optical chip bonding pad are respectively arranged on different side faces), a horizontal coupling mode is adopted between the large-scale optical chip and an optical fiber array, in order to facilitate horizontal coupling and simultaneously avoid the lower side of the optical fiber array after horizontal coupling from bumping into an intermediate layer, and the large-scale optical chip is provided with the photosensitive area (namely, one side where an optical interface is arranged extends out of the intermediate layer so that the optical fiber array is suspended and has a certain gap with the intermediate layer; and the optical chip, the electric chip and the middle layer are connected into a whole by utilizing the reinforcing layer to increase the thickness of the middle layer, so that better connectivity is ensured, and the risk of uneven stress or collision crack (namely bump crack) of the middle layer (such as a silicon intermediate layer) caused by the fact that the center of gravity of the formed multi-layer structure is deviated because the optical chip extends out of one side of the middle layer is reduced, and the risk of warping or cracking is further reduced.

However, the properties of the intermediate layer determine the limit size, and the cost and the size of the intermediate layer are geometrically increased, so that the optical chip cannot be simply increased in size, but the optical chip is miniaturized, that is, the miniaturized high-dimensional matrix optical chip becomes a future development trend. However, the trend of miniaturization tends to make the conductive bumps and traces on the wiring layer denser, so that the problems of heat accumulation and stress concentration are easy to occur, and the wiring layer is weaker and is easy to generate warping and cracks. Thus, on the one hand, in order to increase the stability and rigidity of the multilayer structure, an adhesive material is used to fill between densely arranged conductive bumps; on the other hand, the heat of the optical chip and the electric chip is conducted to the heat dissipation cover by adopting the heat dissipation material with high heat conductivity coefficient.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale. It will be apparent to those of ordinary skill in the art that the drawings in the following description are of some embodiments of the invention and that other drawings may be derived from these drawings without inventive faculty.

FIG. 1 is a top view of a hybrid package structure for an optoelectronic chip in accordance with an exemplary embodiment of the present invention;

fig. 2 is a cross-sectional view of a hybrid package structure of an optoelectronic chip according to an exemplary embodiment of the present invention.

Reference numerals: 01 an intermediate layer; 02 electrical chip; 03 high-dimensional matrix optical chip, 031 lower surface, 032 first side, 033 photosensitive area, 034 second side, 035 optical interface; 04 an optical fiber array; 05 an adhesive reinforcing layer; 06 conductive bumps; 07 a heat radiation cover; 08 a bonding material; 09 adhesive material; 10 wiring layers (Redistribution Layer, RDL, or "redistribution layers"); a substrate 11; 12 motherboard.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In this document, suffixes such as "module", "component", or "unit" used to represent elements are used only for facilitating the description of the present invention, and have no particular meaning in themselves. Thus, "module," "component," or "unit" may be used in combination. The terms "upper," "lower," "inner," "outer," "front," "rear," "one end," "the other end," and the like herein refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The terms "mounted," "configured to," "connected," and the like, herein, are to be construed broadly as, for example, "connected," whether fixedly, detachably, or integrally connected, unless otherwise specifically defined and limited; the two components can be mechanically connected, can be directly connected or can be indirectly connected through an intermediate medium, and can be communicated with each other. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art. Herein, "and/or" includes any and all combinations of one or more of the associated listed items. Herein, "plurality" means two or more, i.e., it includes two, three, four, five, etc.

"Layer" herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire upper or lower layer structure or may have a degree less than the extent of the upper or lower layer structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layers may be located between the upper or lower surfaces of the continuous structure, or between any pair of horizontal planes therebetween. The layers may have one or more layers thereon, above and/or below, horizontally, vertically and/or so. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The "scale" of the optical chip herein refers to the size of the photon-calculating array on the mask plate under a conventional wafer area (e.g., an 8-inch or 12-inch wafer), and is generally expressed in the form of X1X 2, where X1 represents the number of rows in the photon-calculating array and X2 represents the number of columns in the photon-calculating array. Herein, the photonic computing array of greater than or equal to 64×64 in the optical chip is a large-scale, or referred to as a high-dimensional matrix optical chip.

Referring to fig. 1, a top view of a hybrid package structure of an optoelectronic chip based on 2.5D packaging technology according to an exemplary embodiment of the present invention is shown. Specifically, the photoelectric chip hybrid packaging structure comprises: an intermediate layer (such as a silicon Interposer-Si Interposer) 01, a plurality of electrical chips 02 flip-chip mounted on the intermediate layer 01, a high-dimensional matrix optical chip 03 flip-chip mounted on the intermediate layer 01 via optical chip pads on a lower surface 031, an optical fiber array 04 horizontally coupled to a photosensitive region 033 on a first side 032 of the high-dimensional matrix optical chip 03 (specifically, the optical fiber array 04 is horizontally coupled to the photosensitive region 033 via an optical port on a top), and an adhesion reinforcing layer 05 disposed between the intermediate layer 01 and the high-dimensional matrix optical chip 03 and the electrical chips 02 for adhering the lower surface 031 and the bottom of the electrical chips, wherein the first side 032 extends outside the intermediate layer 01 such that the optical fiber array 04 is suspended, and the center of gravity of a multilayer structure formed by the high-dimensional matrix optical chip 03, the optical fiber array 04, the adhesion reinforcing layer 05 and the intermediate layer 01 is shifted in a direction away from the center of gravity of the intermediate layer 01; and a plurality of electric chips 02 are wound around the high-dimensional matrix optical chip 03, and the plurality of electric chips around the second side 034 of the high-dimensional matrix optical chip 03, which is disposed opposite to the first side 032, are offset in a direction away from the high-dimensional matrix optical chip 03, so that the center of gravity of the multilayer structure formed by the high-dimensional matrix optical chip 03, the optical fiber array 04, all electric chips 02, the adhesion reinforcing layer 05, and the intermediate layer 01 is close to the center of gravity of the intermediate layer 01.

In this embodiment, the "offset" means that the second spacing L2 between the second side 034 of the high-dimensional matrix optical chip and each of the corresponding electrical chips 02 is greater than the first spacing L1 between the electrical chips 02 connected to the second side 034.

In this embodiment, the above-mentioned "horizontal coupling" means that the optical interface on the optical chip for interfacing with the optical fiber array is disposed on the side end surface of the optical chip, not on the upper end surface (or upper surface) or the lower end surface (or lower surface), so that the optical fiber array is located on one side of the optical chip, not on the bottom or top of the optical chip.

Preferably, the first spacing L1 between the front and rear sides of the high-dimensional matrix optical chip and the corresponding side plurality of electrical chips is 0.1mm-0.5mm.

In some embodiments, the length L0 of the first side 032 of the high-dimensional matrix optical chip 03 extending out of the intermediate layer 01 is 1mm-5mm.

Preferably, a first pitch between the front and rear sides of the high-dimensional matrix optical chip and the corresponding side plurality of electrical chips is 0.1mm to 0.5mm, and a second pitch between the second side and the corresponding side plurality of electrical chips is greater than the first pitch.

Preferably, the high-dimensional matrix optical chip 03 is a 64×64 photonic chip, or a 128×128 photonic chip.

In some embodiments, the adhesion enhancing layer 05 is formed by an adhesive material (such as glue) filled between the plurality of conductive bumps 06 between the optical chip pads on the lower surface 031 of the high-dimensional matrix optical chip 03 and the intermediate layer 01, and between the plurality of conductive bumps 06 between the electrical chip 02 and the intermediate layer 01; wherein the plurality of conductive bumps 06 comprise a first conductive bump for electrical connection and stress, and a second conductive bump for adjusting stress.

Since the left side (or first side) of the optical chip extends out of the way, the electrical chip is moved to the right for balancing, but it is desirable that the electrical chip is as close to the optical chip as possible, so that a long line between the optical chip and the electrical chip can be avoided. Therefore, by providing the above-described adhesion reinforcing layer 05 on the one hand, and providing more conductive bumps 06 on the other hand, the problem of warpage and cracking of the intermediate layer due to the shift of the center of gravity is avoided. And, the more the bump, the larger the welding area, and the better the connectivity between the optical chip and the intermediate layer, and between the electric chip and the intermediate layer.

Still further, referring to fig. 2, the hybrid package structure for an optoelectronic chip further includes a heat dissipation cover 07, the heat dissipation cover 07 at least covers the plurality of electrical chips 02, the high-dimensional matrix optical chip 03 and the optical fiber array 04, an opening is disposed on a side adjacent to the high-dimensional matrix optical chip 03 to enable the optical fibers of the optical fiber array 04 to pass through the opening to be optically coupled with the photosensitive region 033 on the first side 032, and an upper surface of the optical fiber array 04 is adhered to an inner side of the heat dissipation cover 07 through an adhesive material 08 (such as a heat-conducting adhesive).

In this embodiment, most of the weight of the optical fiber array 04 is dispersed to the heat dissipating cover 07 by the adhesive material 08, so that the influence of the optical fiber array 04 on the center of gravity of the multilayer structure is reduced, and the occurrence of cracking of the coupling surface between the optical fiber array 04 and the high-dimensional matrix optical chip 03 can be avoided.

Further, the upper surface of the high-dimensional matrix optical chip 03 and the upper surface of the electric chip 02 are adhered to the inner side surface of the heat dissipating cover 07 by a heat conductive adhesive material 09.

In some embodiments, the wiring layer 10 is provided between the intermediate layer 01 and the adhesion reinforcing layer 05, and the line width in the wiring layer 10 is 0.5 μm to 10 μm and the line pitch is 0.5 μm to 10 μm. Preferably, the wiring layer 10 is 3-5 layers.

In some embodiments, the optoelectronic chip hybrid package structure further includes: a substrate 11 for carrying the interlayer 01, and a motherboard 12 (e.g., a PCBA board) for carrying the substrate 11.

Preferably, the substrate 11 is electrically connected to the motherboard 12 by socket pins or BGA solder.

The invention also provides a manufacturing method of the photoelectric chip mixed packaging structure, which comprises the following steps:

Providing an intermediate layer and a high-dimensional matrix optical chip, wherein the first side surface of the high-dimensional matrix optical chip is provided with at least one photosensitive area, the photosensitive area is provided with an optical interface, the lower surface of the high-dimensional matrix optical chip is arranged on the upper surface of the intermediate layer, and the first side surface of the high-dimensional matrix optical chip extends out of the intermediate layer;

Providing a plurality of electric chips, arranging the electric chips on the middle layer, surrounding the three sides of the high-dimensional matrix optical chip, and electrically connecting the high-dimensional matrix optical chip;

And providing a heat dissipation cover which covers the intermediate layer, the high-dimensional matrix optical chips and all the electric chips, wherein one side of the heat dissipation cover corresponding to the optical interface is provided with an opening for the optical fiber array to enter into butt joint with the optical interface, and the top of the optical interface is fixed with the heat dissipation cover through an adhesive material.

When the high-dimensional matrix optical chip and the electric chip are arranged on the intermediate layer, the bonding material is filled between the lower surface of the high-dimensional matrix optical chip and the intermediate layer and between the electric chip and the intermediate layer, so that the high-dimensional matrix optical chip, the photoelectric chip and the intermediate layer are bonded into a whole.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In this embodiment, the center of gravity of the multilayer structure "approaching" the center of gravity of the intermediate layer 01 includes that the centers of gravity of the two are coincident, or that the centers of gravity of the two are close, or that the distance between the centers of gravity of the two is small, which is insufficient to cause the problem of warpage and cracking of the intermediate layer.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims (10)

1. The utility model provides a photoelectric chip hybrid packaging structure based on 2.5D packaging technology which characterized in that includes: the optical fiber array comprises an intermediate layer, a plurality of electric chips, a high-dimensional matrix optical chip and an optical fiber array, wherein the electric chips are flip-chip mounted on the intermediate layer, the high-dimensional matrix optical chip is flip-chip mounted on the intermediate layer through an optical chip bonding pad on the lower surface, the optical fiber array is horizontally coupled with a photosensitive area on a first side surface in the high-dimensional matrix optical chip, and an adhesion reinforcing layer is arranged between the intermediate layer and the high-dimensional matrix optical chip and the electric chips and is used for bonding the lower surface and the bottom of the electric chips, the first side surface extends out of the intermediate layer so that the optical fiber array is suspended, and the center of gravity of a multilayer structure formed by the high-dimensional matrix optical chip, the optical fiber array, the adhesion reinforcing layer and the intermediate layer is offset along a direction away from the center of gravity of the intermediate layer;

The plurality of electric chips surround the high-dimensional matrix optical chip, and the plurality of electric chips around a second side surface of the high-dimensional matrix optical chip, which is opposite to the first side surface, are offset in a direction away from the high-dimensional matrix optical chip, so that the center of gravity of the multilayer structure formed by the high-dimensional matrix optical chip, the optical fiber array, all the electric chips, the adhesion reinforcing layer and the intermediate layer is close to the center of gravity of the intermediate layer.

2. The 2.5D packaging technology based hybrid packaging structure of claim 1, wherein the adhesion enhancing layer is formed of an adhesive material filled between a plurality of conductive bumps between the optical chip pad and the intermediate layer, and between a plurality of conductive bumps between the electrical chip and the intermediate layer; the conductive bumps comprise first conductive bumps for electrical connection and second conductive bumps for stress adjustment.

3. The 2.5D packaging technology-based hybrid packaging structure of an optoelectronic chip according to claim 1, further comprising a heat-dissipating cover that encapsulates at least the plurality of electrical chips, the high-dimensional matrix optical chip, and the optical fiber array, wherein one side adjacent to the high-dimensional matrix optical chip is provided with an opening such that one end of the optical fiber array is optically coupled with the photosensitive region on the first side surface through the opening, and wherein an upper surface of the optical fiber array is adhered to an inner side surface of the heat-dissipating cover by an adhesive material.

4. The 2.5D packaging technology-based hybrid packaging structure for an optoelectronic chip according to claim 3, wherein the upper surface of the high-dimensional matrix optical chip and the upper surface of the electrical chip are adhered to the inner side surface of the heat dissipation cover by a heat-conducting adhesive material.

5. The hybrid packaging structure of a photovoltaic chip based on 2.5D packaging technology according to claim 1, wherein the length of the first side extending out of the intermediate layer is 1mm-5mm; and/or, a first spacing between the front side and the rear side of the high-dimensional matrix optical chip and the plurality of electric chips on the corresponding side is 0.1mm-0.5mm, and a second spacing between the second side and the plurality of electric chips on the corresponding side is larger than the first spacing.

6. The 2.5D packaging technology-based hybrid packaging structure of an optoelectronic chip according to any one of claims 1 to 5, wherein a wiring layer is provided between the intermediate layer and the adhesion reinforcing layer, and a line width in the wiring layer is 0.5 μm-10 μm and a line pitch is 0.5 μm-10 μm.

7. The hybrid packaging structure of a photovoltaic chip based on 2.5D packaging technology according to claim 6, wherein the wiring layer is 3-5 layers.

8. The optoelectronic chip hybrid package structure based on 2.5D packaging technology of any one of claims 1-7, further comprising: the base plate is used for bearing the middle layer, and the main board is used for bearing the base plate, and the base plate is electrically connected with the main board through socket or BGA welding.

9. The hybrid packaging structure of an optoelectronic chip based on 2.5D packaging technology according to any one of claims 1 to 7, wherein the high-dimensional matrix optical chip is a photonic chip with a size of 64×64 or more.

10. The manufacturing method of the photoelectric chip mixed packaging structure is characterized by comprising the following steps:

providing an intermediate layer and a high-dimensional matrix optical chip, wherein a first side surface of the high-dimensional matrix optical chip is provided with at least one photosensitive area, the photosensitive area is provided with an optical interface, the lower surface of the high-dimensional matrix light is arranged on the upper surface of the intermediate layer, and the first side surface extends out of the intermediate layer;

providing a plurality of electric chips, arranging the electric chips on the intermediate layer, surrounding three side surfaces of the high-dimensional matrix optical chip, and electrically connecting the electric chips with the high-dimensional matrix optical chip;

providing a heat dissipation cover which covers the intermediate layer, the high-dimensional matrix optical chips and all the electric chips, wherein one side of the heat dissipation cover corresponding to the optical interface is provided with an opening for an optical fiber array to enter into butt joint with the optical interface, and the top of the optical interface is fixed with the heat dissipation cover through an adhesive material;

When the high-dimensional matrix optical chip and the electric chip are arranged on the middle layer, the bonding material is used for filling between a plurality of conductive bumps welded between the lower surface of the high-dimensional matrix optical chip and the middle layer and between the electric chip and a plurality of conductive bumps welded between the middle layer, so that the high-dimensional matrix optical chip, all the electric chips and the middle layer are bonded into a whole.