CN117812801A - Circuit board, substrate and backlight module - Google Patents

Abstract

The invention relates to the technical field of illumination and display, in particular to a circuit board, a substrate and a backlight module, which are used for improving the antioxidation capability of a connecting pad on the circuit board. A circuit board, the circuit board comprising: a substrate; a plurality of connection pads located on one side of the substrate; an insulating layer positioned on one side of the plurality of connection pads away from the substrate; a first via penetrating the insulating layer to the connection pad, the first via exposing the connection pad; and an oxidation-resistant layer located on a side of the insulating layer away from the substrate; the oxidation resistant layer includes at least one oxidation resistant pattern; the antioxidation pattern is electrically connected with the connection pad through the first via hole; the orthographic projection of the antioxidation pattern on the substrate and the orthographic projection of the connection pad electrically connected with the antioxidation pattern on the substrate are at least partially overlapped. The circuit board, the substrate and the backlight module are used for illumination or image display.

Description

Circuit board, substrate and backlight module

Technical Field

The present invention relates to the field of lighting and display technologies, and in particular, to a circuit board, a substrate, and a backlight module.

Background

The sub-millimeter light emitting diode (Mini Light Emitting Diode, mini LED for short) and the Micro light emitting diode (Micro Light Emitting Diode, micro LED for short) have the advantages of self-luminescence, high efficiency, high brightness, high reliability, energy saving, high reaction speed and the like, and are applied to the fields of Micro display, mobile phones, televisions and the like for medium-sized display to cinema large-screen display and the like.

Disclosure of Invention

The embodiment of the invention provides a circuit board, a substrate and a backlight module, which are used for improving the antioxidation capability of a connecting pad on the circuit board, so as to improve the fixed yield of the circuit board and an electronic element and provide the yield of the substrate.

In order to achieve the above purpose, the embodiment of the invention provides the following technical scheme:

some embodiments of the present invention provide a wiring board including: a substrate; a plurality of connection pads located on one side of the substrate; an insulating layer positioned on one side of the plurality of connection pads away from the substrate; a first via penetrating the insulating layer to the connection pad, the first via exposing the connection pad; and an oxidation-resistant layer located on a side of the insulating layer away from the substrate; the oxidation resistant layer includes at least one oxidation resistant pattern; the antioxidation pattern is electrically connected with the connection pad through the first via hole; the orthographic projection of the antioxidation pattern on the substrate and the orthographic projection of the connection pad electrically connected with the antioxidation pattern on the substrate are at least partially overlapped.

According to the invention, the antioxidation layer is arranged on one side of the connecting pad of the circuit board, which is far away from the substrate, and the antioxidation layer comprises a plurality of antioxidation patterns, the antioxidation patterns are electrically connected with the connecting pad through the first through holes on the insulating layer, and the antioxidation patterns are overlapped with the connecting pad, so that the antioxidation patterns can protect the connecting pad electrically connected with the antioxidation patterns, the antioxidation capability of the connecting pad is improved, the oxidation risk and the oxidation rate of the connecting pad are reduced, and further, the electric connection and fixation of the connecting pad and the electronic element are prevented from being influenced, and the die bonding yield of the circuit board and the substrate can be improved. It can be understood that when die bonding is performed, the solder (omitted from the figure, not shown) is required to be used for firmly connecting the antioxidation pattern and the electronic component, the metal in the solder can react with the metal in the antioxidation pattern in a diffusion manner to form an intermetallic compound, the antioxidation pattern can prevent the metal in the solder from further diffusing to the connection pad, further the reaction with the metal in the connection pad can be avoided, when the electronic component needs to be reworked and removed, the electronic component is removed, and meanwhile, the antioxidation pattern is possibly removed together with the removal part, so that the connection pad remains intact, the risk that the electronic component is removed together with the connection pad in the process of removing the electronic component can be reduced, the damage to the circuit board is avoided, and the repairability rate of the circuit board is improved.

In some embodiments, the circuit board has a functional area, the plurality of connection pads includes a plurality of first connection pads located in the functional area, and the plurality of oxidation resistant patterns includes a plurality of first oxidation resistant patterns located in the functional area; the circuit board comprises a first conductive layer and a second conductive layer which are sequentially stacked on one side of the substrate; the first conductive layer comprises a signal line positioned in the functional area; the first connection pads are located on the second conductive layer, electrically connected with the signal lines and electrically connected with the first oxidation resistant patterns.

In some embodiments, the second connection pad and the signal line electrically connected to the second connection pad are in an integral structure.

In some embodiments, the circuit board further has a binding area located at one side of the functional area, the plurality of connection pads further includes a plurality of second connection pads located at the binding area, and the plurality of antioxidation patterns includes a plurality of second antioxidation patterns located at the display binding area; the second connection pad is located on the first conductive layer, is electrically connected with the signal line, and is electrically connected with the second oxidation resistant pattern.

In some embodiments, the circuit board further has a binding area located at one side of the functional area, the plurality of connection pads further includes a plurality of second connection pads located at the binding area, and the plurality of antioxidation patterns includes a plurality of second antioxidation patterns located at the binding area; the second connection pad is positioned on the second conductive layer; the first conductive layer further includes a plurality of connection patterns located at the bonding region, the connection patterns being located between the substrate and the second connection pad, connecting the signal line and the second connection pad; the second connection pad is also electrically connected with the second oxidation resistant pattern.

In some embodiments, the circuit board includes a third conductive layer disposed on one side of the substrate, the plurality of connection pads being located on the third conductive layer; the third conductive layer further includes a signal line electrically connected to the connection pad.

In some embodiments, the wiring board further includes an insulating layer disposed between the plurality of connection pads and the oxidation-resistant layer and sequentially laminated in a direction away from the substrate; the circuit board also has a first via penetrating the insulating layer to the connection pad, the first via exposing a portion of the connection pad; the antioxidation pattern is connected with the connection pad through the first via hole.

In some embodiments, the oxidation resistant pattern is located within the first via; the antioxidation pattern is contacted with the hole wall of the first via hole, or a space is reserved between the antioxidation pattern and the hole wall of the first via hole.

In some embodiments, a distance between a boundary line of the orthographic projection of the connection pad on the substrate and an inner boundary line of the orthographic projection of the first via on the substrate ranges from: 0 μm to 1 μm.

In some embodiments, a portion of the oxidation resistant pattern is located within the first via, and another portion of the oxidation resistant pattern overlaps a surface of the insulating layer on a side remote from the substrate.

In some embodiments, a spacing range between inner boundary lines of the orthographic projection of the antioxidant pattern on the substrate is: 1 μm to 10 μm.

In some embodiments, the material of the oxidation resistant layer comprises nickel and/or a nickel alloy.

In some embodiments, where the material of the oxidation resistant layer comprises a nickel alloy, the nickel alloy comprises greater than or equal to 40% nickel by mass.

In some embodiments, the connection pad includes a body portion, and/or at least one guard portion disposed on one side of the body portion in a stacked manner; the material of the main body part comprises copper; the material of the guard includes nickel, nickel alloy or copper alloy.

In some embodiments, where the connection pad includes a body portion and two guard portions, the two guard portions are a first guard portion and a second guard portion, respectively, the body portion being located between the first guard portion and the second guard portion.

In some embodiments, where the connection pad includes a body portion and one guard portion, the guard portion is located on a side of the body portion adjacent the substrate.

Some embodiments of the present invention also provide a substrate comprising: the wiring board as in any one of the above embodiments, and a plurality of electronic components; the electronic component includes at least one pin electrically connected with the oxidation-resistant pattern in the circuit board.

The beneficial effects achieved by the substrate provided by some embodiments of the present invention are the same as those achieved by the circuit board provided by some embodiments, and are not described herein.

In some embodiments, the electronic component comprises a micro light emitting device.

Some embodiments of the present invention further provide a backlight module, including: the substrate as in the above embodiments, and an optical film set on the light-emitting side of the substrate.

The beneficial effects of the backlight module provided by some embodiments of the present invention are the same as those of the circuit board provided by the above embodiments, and are not described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present invention, the drawings that are required to be used in some embodiments of the present invention will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present invention, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic views, not limiting the actual size of the products, etc. according to the embodiments of the present invention.

FIG. 1a is a block diagram of a display device according to some embodiments of the present invention;

FIG. 1b is a block diagram of another display device according to some embodiments of the invention;

FIG. 2 is a block diagram of a backlight module according to some embodiments of the present invention;

FIG. 3 is a block diagram of a substrate according to some embodiments of the invention;

FIG. 4 is a partial physical view of a substrate in one implementation;

FIG. 5a is a schematic diagram of a circuit board according to some embodiments of the present invention;

FIG. 5b is a block diagram of another circuit board according to some embodiments of the invention;

FIG. 5c is a block diagram of a circuit board according to another embodiment of the present invention;

FIG. 5d is a block diagram of another circuit board according to some embodiments of the invention;

FIG. 6 is a block diagram of a connection pad in some embodiments of the invention;

fig. 7 a-7 g are step diagrams of a method for fabricating a substrate according to some embodiments of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments obtained by a person skilled in the art based on the embodiments provided by the present invention fall within the scope of protection of the present invention.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the invention. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

The use of "configured to" herein is meant to be an open and inclusive language that does not exclude devices configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

The terms "first," "second," and the like herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As shown in fig. 1a, some embodiments of the present invention provide a display device 3000.

In some examples, the display device 3000 described above may be in any display device that displays both motion (e.g., video) and stationary (e.g., still image) and text or images. More particularly, it is contemplated that the display device of the embodiments may be implemented in or associated with a variety of electronics such as, but not limited to, mobile phones, wireless devices, personal Data Assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., displays of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images on a piece of jewelry), and the like.

Exemplary, the display device 3000 includes: frames, driver chips, and other electronic components, etc.

In some examples, as shown in fig. 1a, the display device 3000 further includes: a substrate 1000.

For example, when the substrate 1000 is applied to display, the substrate 1000 can be used as a display panel as it is, and a screen can be displayed, and the display device 3000 is an active light emitting display device. At this time, since the substrate 1000 itself can emit light, and a backlight module is not required to be additionally disposed, the substrate 1000 can be directly used as a display panel, and a screen can be displayed.

In other examples, as shown in fig. 1b, the display device 3000 further includes: a backlight module 2000, and a display panel 2001 positioned on the light emitting side of the backlight module 2000.

Illustratively, the backlight module 2000 may provide backlight for the display panel 2001. The light emitting side of the backlight module 2000 refers to the side of the backlight module 2000 emitting light.

The display panel 2001 is a liquid crystal display panel, and the display panel 2001 may display a screen under a backlight provided by the backlight module 2000, so that the display device 3000 achieves a display function, and the display device 3000 is a liquid crystal display (Liquid Crystal Display, abbreviated as LCD) device.

For example, the types of the backlight module 2000 in the display device 3000 may be various, and may be set according to actual situations, which is not limited by the present disclosure.

For example, the backlight module 2000 may be a side-in type backlight module, and the backlight module 2000 may be a direct type backlight module.

For convenience of description, the following embodiments of the present invention will be described with reference to the backlight module 2000 as a direct type backlight module.

For example, the backlight module 2000 includes a substrate 1000. At this time, the substrate 1000 is applied to the backlight, the substrate 1000 is used as a light source in the backlight module 2000 to backlight the display panel 2001, and the display panel 2001 is used for displaying the screen to be displayed.

As shown in fig. 2, the backlight module 2000 further includes: an optical film set 1001 on the light-emitting side of the substrate 1000.

Illustratively, the optical patch set 1001 includes: the diffusion plate, the quantum dot film, the diffusion sheet, the composite film, and the like provided on the light-emitting side of the substrate 1000 are laminated in this order.

For example, the diffusion plate and the diffusion sheet are used to eliminate the lamp shadow and to homogenize the light emitted from the substrate 1000, thereby improving the uniformity of the light.

For example, the quantum dot film is used to convert light emitted from the substrate 1000. Alternatively, in the case where light emitted from the substrate 1000 is blue light, the quantum dot film may convert the blue light into white light and improve the purity of the white light.

For example, the composite film is used to increase the brightness of light emitted from the substrate 1000.

It can be understood that the brightness of the light emitted from the substrate 1000 after being incident on the optical film set 1001 is enhanced, and the purity and uniformity of the emitted light are higher.

In some examples, the backlight module 2000 further includes: support columns disposed between the substrate 1000 and the diffusion plate of the optical film set 1001.

Illustratively, the support posts may be secured to the substrate 1000 by glue. The support column can be used for supporting the optical film set 1001 and enabling the light emitted by the substrate 1000 to obtain a certain light mixing distance, so that the lamp shadow can be further eliminated and the uniformity of the light can be improved.

In some embodiments, as shown in fig. 3, the substrate 1000 includes: a circuit board 100, and a plurality of electronic components 200. The plurality of electronic components 200 are electrically connected to the wiring board 100.

For example, a driving signal transmitted to the electronic component 200 through the wiring board 100, thereby driving the electronic component 200 to operate, and the like.

For example, the plurality of electronic components 200 may include a plurality of micro light emitting devices and a plurality of control chips. For example, one control chip may control at least one micro light emitting device.

For example, the Micro light emitting device may include a Mini LED or a Micro LED, and the control chip may include a microchip, a Micro sensor, a Micro driver, and the like.

For example, a Mini LED is used as the substrate 1000 of the electronic component, and the substrate 1000 may be used directly for display or for providing backlight. In the case that the substrate 1000 is used for providing backlight or applied to the backlight module 2000, the circuit board 100 may be provided with a larger number of Mini LEDs with higher density, so as to realize area dimming within a smaller range, so that the backlight provided by the backlight module 2000 within a smaller light mixing distance has better brightness uniformity and higher color contrast, so that the display device 3000 can save more power, and the display device 3000 can realize ultra-thin design, high color rendering performance, and the like. Meanwhile, the design of the substrate 1000 can be matched with a flexible substrate for use, and can be matched with the curved design of an LCD (liquid crystal display), so that the curved display effect similar to that of OLED (Organic Light Emitting Diode ) display can be realized under the condition of ensuring the image quality.

For example, a Micro LED is used as the substrate 1000 of the electronic component, and the substrate 1000 may be used directly for display or for providing backlight. Under the condition that the substrate 1000 is directly used for display, the defects of wire bonding and reliability of a forward-mounted electronic element (such as a Micro LED) can be overcome, meanwhile, the advantages of COB (Chip On Board)/COG (Chip On Glass) packaging are combined, the space between the electronic elements in the substrate can be further reduced, the visual effect of a corresponding display device is greatly improved, and meanwhile, the viewing distance can be greatly reduced, so that the indoor display device can further replace the market of the original LCD device. On the other hand, the high-quality display effect of the curved surface can be realized by matching with the flexible substrate, and the self-luminous characteristic of the flexible substrate has very wide market in the aspect of special modeling requirements (such as automobile display).

The electronic component 200 may be a micro resistor or a micro capacitor, for example.

As shown in fig. 3, the circuit board 100 includes: a substrate 1.

For example, the substrate 1 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethylene Terephthalate ) substrate, a PEN (Polyethylene Naphthalate Two Formic Acid Glycol Ester, polyethylene naphthalate) substrate, a PI (Polyimide) substrate, or the like. The substrate 1 may be a rigid substrate. For example, the material of the substrate may be glass or the like. The substrate 1 may be a printed circuit board (Printed Circuit Board, abbreviated as PCB), an aluminum substrate, or the like.

In one implementation manner, the substrate of the circuit board is provided with a signal line and a bonding pad electrically connected with the signal line, and the material of the bonding pad is copper (Cu) or copper alloy (for example CuNi), however, the bonding pad is easily oxidized in the back-end high temperature process (fig. 4 (a) is the bonding pad, and fig. 4 (b) is the bonding pad oxidized after the back-end high temperature process), so that when the circuit board is fixed with the electronic component (for short, die bonding yield is reduced, and connection stability of the electronic component and the circuit board is affected. In die bonding, it is necessary to use solder (including tin Sn) to reliably and firmly connect the leads of the electronic component to the pads. Sn in the solder reacts rapidly with CuNi and/or Cu in the bond pad to produce intermetallic compounds. When the dummy solder and the soldering offset error occur in the die bonding process and maintenance is needed, the electronic component needs to be removed, and because the intermetallic compound is tightly combined with the bonding pad, part of the bonding pad structure is removed while the electronic component is removed, so that the bonding pad on the circuit board is partially lost or damaged (the position of the broken line frame in fig. 4 (c) is a physical bonding pad lost position), the bonding pad is difficult to repair, the whole circuit board cannot be used, and the repairability of the circuit board is reduced.

Based on this, as shown in fig. 3, some embodiments of the present invention provide a wiring board 100, the wiring board 100 further comprising: a plurality of connection pads 2 located on one side of the substrate 1.

Illustratively, the connection pad 2 may be a portion of a pad, for example, the connection pad 2 may be a portion of the electronic component 200 electrically connected to the pad. Alternatively, the connection pad 2 may be part of a bonding pin.

Illustratively, the electronic component 200 includes at least one pin 210.

For example, the electronic component 200 includes two pins 210.

For example, two adjacent connection pads 2 are electrically connected to two pins 210 of one electronic component 200. The distribution of the plurality of connection pads 2 on the substrate 1 is related to the arrangement and the arrangement density of the electronic components 200 to be fixed.

For example, in the case where the plurality of electronic components 200 are arranged in an array, the plurality of connection pads 2 are also arranged in an array.

Illustratively, the circuit board 100 further includes: an insulating layer 3 on the side of the plurality of connection pads 2 remote from the substrate 1.

The insulating layer 3 may be a single-layer structure or a multi-layer structure, for example.

For example, the insulating layer 3 may have a double-layer structure, and the insulating layer 3 includes a passivation layer PVX and a planarization layer PLN stacked in this order.

For another example, the insulating layer 3 may have a three-layer structure, and the insulating layer includes a passivation layer PVX, a planarization layer PLN, and a passivation layer PVX that are sequentially stacked.

Wherein, passivation layer PVX in the insulating layer can realize the electrical isolation between connection pad 2 and oxidation resistant layer 4 below, avoids the short circuit of connection pad 2 and oxidation resistant layer 4, and planarization can be realized to the planarization layer PLN, and then the formation of oxidation resistant layer is convenient.

Illustratively, the circuit board 100 further includes: a first via H penetrating the insulating layer 3 to the connection pad 2, the first via H exposing the connection pad 2.

For example, the first via H is a through hole penetrating the insulating layer 3, exposing the surface of the connection pad 2 on the side away from the substrate 1.

In some examples, the circuit board 100 further includes: an oxidation-resistant layer 4 on the side of the insulating layer 3 remote from the substrate 1; the oxidation resistant layer 4 comprises at least one oxidation resistant pattern 41; the oxidation-resistant pattern 41 is electrically connected with the connection pad 2; the orthographic projection of the oxidation preventing pattern 41 on the substrate 1 and the orthographic projection of the connection pad 2 electrically connected with the oxidation preventing pattern 41 on the substrate 1 are overlapped at least partially.

Illustratively, the oxidation resistant layer 4 includes an oxidation resistant pattern 41. Alternatively, the oxidation resistant layer 4 includes a plurality of oxidation resistant patterns 41.

For example, the number of the oxidation preventing patterns 41 may be less than or equal to the number of the connection pads 2.

For example, one oxidation preventing pattern 41 may be electrically connected to a corresponding one of the connection pads 2 through one first via.

Illustratively, the oxidation-resistant pattern 41 and the connection pad 2 electrically connected thereto are disposed at least partially overlapping.

For example, the antioxidation pattern 41 covers a portion of the connection pad 2, and the orthographic projection of the antioxidation pattern 41 on the substrate 1 is located within the orthographic projection range of the corresponding connection pad 2 on the substrate 1.

As another example, the antioxidation pattern 41 completely covers the connection pad 2, and the orthographic projection of the connection pad 2 on the substrate 1 is located within the orthographic projection range of the corresponding antioxidation pattern 41 on the substrate 1.

As another example, the antioxidation pattern 41 completely covers the connection pad 2, and the orthographic projection of the connection pad 2 on the substrate 1 coincides with the orthographic projection of the corresponding antioxidation pattern 41 on the substrate 1.

It will be appreciated that the oxidation resistant pattern 41 and the connection pad 2 are both conductors. The electronic component may be electrically connected to the connection pad through the oxidation-resistant pattern.

For example, the antioxidation layer 4 has antioxidation, is located on one side of the connection pad 2 far away from the substrate 1, and completely covers the connection pad 2 or covers a part of the connection pad 2, so that the connection pad 2 can be protected, the antioxidation capability of the connection pad 2 is improved, oxidation of the connection pad 2 is avoided, further, the electrical connection of the connection pad and the electronic element is avoided, and the die bonding yield of the substrate can be improved.

According to the invention, the antioxidation layer 4 is arranged on one side of the connection pad 2 of the circuit board 100 far away from the substrate 1, and the antioxidation layer 4 comprises a plurality of antioxidation patterns 41, the antioxidation patterns 41 are electrically connected with the connection pad 2 through the first through holes H on the insulation layer 3, and the antioxidation patterns 41 are overlapped with the connection pad 2, so that the antioxidation patterns 41 can protect the connection pad 2 electrically connected with the antioxidation patterns, the antioxidation capability of the connection pad 2 is improved, the oxidation rate of the connection pad 2 is reduced, even the connection pad 2 is prevented from being oxidized, the oxidation risk of the connection pad 2 is further reduced, the electrical connection and fixation of the connection pad 2 and the electronic element 200 are prevented from being influenced, and the die bonding yield of the circuit board and the substrate can be improved. In addition, when the solder is used to realize firm connection between the antioxidation pattern 41 and the electronic component 200, the metal in the solder can react with the metal in the antioxidation pattern 41 in a diffusion manner to form intermetallic compounds, and the antioxidation pattern 41 can prevent the metal in the solder from further diffusing to the connection pad 2, so that the reaction with the metal in the connection pad 2 can be avoided, when the electronic component 200 needs to be reworked and removed, the situation that part of the antioxidation pattern 41 or the connection pad 2 is removed while the electronic component 200 is removed is avoided, so that the connection pad 2 remains intact, the risk that the electronic component 200 is removed while the connection pad 2 is connected in the process of removing the electronic component 200 can be reduced, the damage to the circuit board 100 is avoided, and the repairability of the circuit board 100 is improved.

Illustratively, each of the pins 210 of the electronic component 200 is electrically connected to one of the oxidation-resistant patterns 41.

For example, the leads 210 of the electronic component 200 are electrically connected to the connection pads 2 through the oxidation-resistant pattern 41.

In some examples, as shown in fig. 5a and 5b, the oxidation preventing pattern 41 is located in the first via H.

For example, the entire oxidation preventing pattern 41 is located in the first via H, and the height of the oxidation preventing pattern 41 is less than or equal to the depth of the first via H.

As shown in fig. 5a and 5b, the oxidation preventing pattern 41 is in contact with the wall of the first via H, or a space is provided between the oxidation preventing pattern 41 and the wall of the first via H.

For example, the oxidation preventing pattern 41 may completely fill the first via H, or the oxidation preventing pattern 41 may fill a portion of the first via H, or the oxidation preventing pattern 41 may be attached to the surface of the connection pad, have the same or similar morphology as the connection pad, and all sides of the oxidation preventing pattern 41 are in contact with the wall of the first via 118. In this way, the connection pad 2 exposed through the first via hole H can be prevented from easily contacting the outside, so that the oxidation risk of the connection pad 2 is prevented from being increased, the oxidation resistance of the connection pad 2 and the circuit board 100 can be improved, and the die bonding yield of the substrate is improved.

For another example, any one side surface of the oxidation preventing pattern 41 is in contact with the wall of the first via H. Therefore, the connection pad 2 exposed through the first via hole H can be prevented from easily contacting the outside, and the oxidation risk of the connection pad 2 is further prevented from being increased, so that the oxidation resistance of the connection pad and the circuit board can be improved, and the die bonding yield of the substrate is further improved.

As another example, the sidewall of the oxidation resistant pattern 41 has a certain distance from the wall of the first via H. Thus, the oxidation rate of the connection pad 2 can be reduced, the oxidation resistance of the connection pad can be improved, and the die bonding yield of the substrate can be further improved.

In the case where reworking (reworking) is required, such as occurrence of a cold joint or a shift, in which the circuit board is electrically connected to the electronic component by using tin solder, the electronic component needs to be removed and soldered again. With the above arrangement, since the antioxidation pattern 41 is located in the first via H and the electronic component 200 is directly soldered with the antioxidation pattern 41, when the electronic component 200 is removed, the partial antioxidation pattern 41 is removed, thereby avoiding removing the electronic component 200 and removing the connection pad 2 or a part of the connection pad 2, and further avoiding damaging the connection pad 2, and when the electronic component 200 is soldered again, even if the antioxidation pattern 41 is partially damaged, the connection pad 2 is still intact, and the reliability of re-soldering and electrical connection of the electronic component 200 is not affected, so as to improve the repairability of the circuit board, improve the die bonding yield of the substrate, and improve the overall yield of the substrate.

In some examples, the spacing between the boundary line of the front projection of the connection pad 2 on the substrate 1 and the inner boundary line of the front projection of the first via H on the substrate 1 ranges from: 0 μm to 1 μm.

For example, the cross-sectional shape of the first via H may be rectangular or inverted trapezoidal.

In the case where the cross-sectional shape of the first via H is rectangular, the boundary line of the orthographic projection of the first via H on the substrate 1 is a single closed figure, that is, the boundary line of the orthographic projection of the first via H on the substrate 1 is one.

In the case where the cross-sectional shape of the first via hole H is an inverted trapezoid, the length of the upper base of the trapezoid is smaller than that of the lower base. Of course, the trapezoid may be an isosceles trapezoid. At this time, the boundary line of the orthographic projection of the first via H on the substrate is two closed patterns, and one closed pattern is inside the other closed pattern. The inner closed pattern constitutes the inner boundary of the orthographic projection of the first via on the substrate.

For example, the spacing between the boundary line of the front projection of the connection pad 2 on the substrate 1 and the inner boundary line of the front projection of the first via H on the substrate 1 may be 0 μm, 0.3 μm, 0.5 μm, 0.8 μm or 1 μm.

In other examples, as shown in fig. 5c, a portion of the oxidation preventing pattern 41 is located in the first via hole, and another portion of the oxidation preventing pattern 41 overlaps the surface of the insulating layer 3 on the side away from the substrate 1.

For example, a portion of the oxidation-resistant pattern 41 protrudes outside the first via hole and overlaps the surface of the insulating layer 3 on the side away from the substrate 1.

It will be appreciated that the antioxidation pattern 41 is formed after the insulating layer 3 is formed and the first via is formed on the circuit board, so that a portion of the antioxidation pattern may overlap the insulating layer.

By adopting the above arrangement, the oxidation risk and oxidation rate of the connection pad 2 can be reduced, so as to improve the oxidation resistance of the connection pad 2 and the circuit board 100, and improve the die bonding yield of the substrate. In addition, since the antioxidation pattern 41 is manufactured after the insulating layer 3 is formed and the first via hole is formed on the circuit board, the welding yield of the antioxidation pattern 41 and the electronic component 200 can be improved, the influence of the wettability of the antioxidation pattern 41 formed on the insulating layer 3 and the first via hole H later can be avoided, further, the mutual diffusion between the antioxidation pattern 41 and the solder is avoided, and the welding firmness of the antioxidation pattern 41 and the electronic component is avoided.

Illustratively, the spacing between the boundary line of the orthographic projection of the oxidation-resistant pattern 41 on the substrate 1 and the inner boundary line of the orthographic projection of the first via on the substrate 1 is in the range: 1 μm to 10 μm.

For example, the spacing between the boundary line of the orthographic projection of the oxidation resistant pattern 41 on the substrate 1 and the inner boundary line of the orthographic projection of the first via on the substrate may be 1 μm, 3 μm, 5 μm, 7 μm or 10 μm.

In some embodiments, the material of the oxidation resistant layer 4 comprises nickel and/or a nickel alloy.

For example, the material of the oxidation-resistant layer 4 may be nickel.

As another example, the material of the oxidation resistant layer 4 may be a nickel alloy.

For another example, the material of the oxidation resistant layer 4 may be nickel or nickel alloy, and in this case, the oxidation resistant layer 4 may have a two-layer structure, and the side close to the connection pad may be a nickel layer, and the nickel layer is a nickel alloy layer thereon.

Illustratively, the nickel alloy includes: niAl, niMo, niW, niTi or NiW, etc.

In some examples, where the material of the oxidation resistant layer 4 comprises a nickel alloy, the mass percent of nickel in the nickel alloy is greater than or equal to 40%.

For example, the percentage of nickel in the nickel alloy may be 40%, 50%, 60%, 70%, or 90%.

In one implementation, copper or copper alloy is used to form the bond pad, and the gold-plating process for copper or copper alloy requires an acid-washing process to remove the oxide layer. The acid washing process is easy to cause the loss of an oxidation resistant layer or a bonding pad, the cost of the gold melting process is high, the reagents of the acid washing process are mostly cyanide, and the environmental pollution is high.

In the embodiment of the invention, nickel and/or nickel alloy is used as the material of the oxidation resistant layer 4, the oxidation resistance of the nickel and/or nickel alloy is high, cyanide is not needed for cleaning, the environmental hazard is low, the manufacturing cost is low, the etching difficulty of the oxidation resistant layer 4 is low, and the accuracy of the etching morphology is high. In addition, nickel and/or nickel alloy can form a laminated structure with the connection pad, and solder tin can be prevented from further diffusing downwards when being welded with an electronic element, and tin can be prevented from diffusing to the connection pad, so that the connection pad 2 can be prevented from being damaged when reworking (reworking) is required, the repairability rate of the circuit board 100 is improved, and the die bonding yield is improved. The oxidation-resistant layer 4 may be formed by deposition using a magnetron deposition process, so that the process flow of the circuit board 100 may be simplified.

In some embodiments, as shown in fig. 6, the connection pad 2 includes a main body portion 21, and/or at least one guard portion 22 provided in a stacked manner on one side of the main body portion. The material of the main body portion 21 includes copper. The material of the guard 22 includes nickel, nickel alloy or copper alloy.

The protection portion 22 can protect the main body portion, prevent the main body portion from oxidation, or reduce the oxidation rate of the main body portion, so as to improve the die bonding yield of the substrate.

For example, the connection pad 2 may include only the main body portion 21. The material of the main body part is copper.

In another example, in the case where the connection pad 2 includes the main body portion 21 and one guard portion 22, the guard portion is located on a side of the main body portion close to the substrate.

As another example, the connection pad 2 may include a main body portion 21, and two guard portions 22 disposed at opposite sides of the main body portion. Under the condition that the connecting pad comprises a main body part and two protection parts, the two protection parts are a first protection part and a second protection part respectively, and the main body part is positioned between the first protection part and the second protection part. Here, the materials of the two guard portions may be the same or different.

For example, the nickel alloy may include: nickel aluminum alloy (NiAl), nickel molybdenum alloy (NiMO), nickel tungsten alloy (NiW), nickel titanium alloy (NiTi), and the like. The copper alloy may include: copper nickel alloy (CuNi), copper nickel aluminum alloy (cunai), copper magnesium aluminum alloy (CuMgAl), copper titanium alloy (CuTi), and the like.

It is understood that the circuit board 100 includes various functional structures such as signal lines, pads or connection pads, and the functional structures have various arrangements, for example, various signal lines and connection pads may be arranged in the same layer, or may be arranged in different layers, and may be selected according to practical situations, which is not limited by the present invention.

In some embodiments, as shown in fig. 5B, the circuit board 100 has a functional area F and a bonding area B.

Illustratively, the binding area B is located on one side of the functional area F.

For example, the functional region F is a region where electronic components are disposed. In the case where the substrate to which the wiring board is applied is used to provide backlight, the functional region F is used to provide backlight. In the case where the substrate to which the wiring board is applied is used for direct display, the functional area F is used for providing a display screen.

For example, the bonding area B is an area of the circuit board for bonding with the driving chip.

In some examples, as shown in fig. 5b, the plurality of connection pads 2 includes a plurality of first connection pads 2a located in the functional area F, and the plurality of oxidation resistant patterns 41 includes a plurality of first oxidation resistant patterns 41a located in the functional area F.

Illustratively, the wiring board 100 includes a first conductive layer ET1 and a second conductive layer ET2 sequentially stacked on one side of a substrate 1. The first conductive layer ET1 includes a signal line 51. The plurality of first connection pads 2a are located in the second conductive layer ET2, and the first connection pads 2a are electrically connected to the signal lines 51 and the first oxidation preventing patterns 41a.

Here, the signal line 51, the first connection pad 2a and the first oxidation preventing pattern 41a are respectively located at different film layers of the circuit board.

For example, the second conductive layer ET2 may include a plurality of conductive patterns 52, the plurality of conductive patterns located in the functional region F constitute a plurality of pads, and the first connection pad 2a is a portion of the conductive patterns or pads.

The signal line 51 extends to the bonding area B and is electrically connected to the bonding pin, so that a driving signal of the driving chip can be received.

Illustratively, the plurality of connection pads 2 further includes a plurality of second connection pads 2b located at the bonding area, and the plurality of oxidation resistant patterns 41 includes a plurality of second oxidation resistant patterns 41b located at the bonding area.

For example, the cross-sectional shape of the first connection pad 2a may be the same as or different from the cross-sectional shape of the second connection pad 2 b.

For example, the cross-sectional shape of the first antioxidant pattern 41a may be the same as or different from the cross-sectional shape of the second antioxidant pattern 41b.

In some examples, as shown in fig. 5c, the second connection pad 2b is located on the first conductive layer ET1, and the second connection pad 2b is electrically connected to the signal line 51 and the second oxidation preventing pattern 41b.

Here, the first connection pad 2a and the second connection pad 2b are located at different film layers.

The electrical connection manner of the second connection pad 2b and the corresponding signal line is various, and may be selected according to practical situations, which is not limited in the present invention.

For example, the signal line in the first conductive layer is closer to the substrate than the second connection pad, and the second connection pad is lapped on the signal line, and the surface of the second connection pad, which is close to one side of the substrate, is in contact with the signal line, so that the electrical connection with the signal line is realized. The surface of the second connecting pad far away from one side of the substrate is contacted with the second oxidation resistant pattern, so that the second connecting pad is electrically connected with the second oxidation resistant pattern.

As another example, as shown in fig. 5c, the second connection pad 2b and the signal line 51 electrically connected to the second connection pad 2b are integrally formed.

The second connection pad 2b may be electrically connected to one end of the corresponding signal line 51. Thus, the second connection pad 2b and the corresponding signal line 51 can be formed in one patterning process, and the manufacturing process flow of the circuit board can be simplified.

Here, the second conductive layer may not be disposed in the bonding region B, and the second oxidation preventing pattern 41B may be disposed in the same layer as the first connection pad 2 a. Therefore, the thickness of the film layer of the binding area B can be reduced, and the light and thin design of the circuit board and the substrate is facilitated.

At this time, in the bonding region B, the first via hole penetrating through the insulating layer penetrates through the insulating layer between the first conductive layer and the second conductive layer. The insulating layer may include, for example, a passivation layer, a planarization layer, and a passivation layer, which are stacked in this order. Of course, the passivation layer is used for electrically isolating the second oxidation-resistant pattern from the first conductive layer, and the planarization layer is used for planarization.

In yet other examples, as shown in fig. 5b, the second connection pad 2b is located on the second conductive layer ET2. At this time, the first connection pad 2a and the second connection pad 2b are arranged on the same layer and are both located on the second conductive layer ET2, so that the first connection pad 2a and the second connection pad 2b can be formed simultaneously in one patterning process, which is beneficial to simplifying the manufacturing process of the circuit board and the substrate.

At this time, in the bonding region, the first via penetrates through the insulating layer between the second conductive layer ET2 and the oxidation resistant layer 4.

Illustratively, the first conductive layer ET1 further includes a plurality of connection patterns 53 located at the bonding region, the connection patterns 53 being located between the substrate 1 and the second connection pads 2b, connecting the signal lines 51 and the second connection pads 2b. The second connection pad 2b is also electrically connected to the second oxidation preventing pattern 41 b.

For example, a part of the connection pattern 53 is in contact with the signal line 51, and is electrically connected to the signal line 51.

For example, the connection pattern 53 and the signal line 51 may be formed in an integrated structure in one patterning process, so that a manufacturing process of the circuit board may be simplified.

In other embodiments, as shown in fig. 5d, the circuit board 100 includes a third conductive layer ET3 disposed on one side of the substrate, and the plurality of connection pads 2 are located on the third conductive layer ET3. The third conductive layer ET3 further includes a signal line 51 electrically connected to the connection pad 2.

Here, the circuit board includes only one conductive layer, i.e., the third conductive layer. The connection pad and the signal line are both positioned on the third conductive layer. The connection pad is also electrically connected with the oxidation-resistant pattern.

It can be understood that the driving mode of the substrate provided in any of the above embodiments may be a Passive Matrix (PM) driving mode or an Active Matrix (AM) driving mode. The AM driving may include a driving chip driving and a TFT (Thin Film Transistor ) driving, among others.

Next, a method for manufacturing a substrate is described, in which the circuit board includes a first conductive layer ET1 and a second conductive layer ET2, and the method includes S100 to S700.

S100, as shown in fig. 7a, a substrate is provided, and an alignment mark layer DW and a buffer layer Buf are sequentially formed on one side of the substrate 1.

Illustratively, the material of the alignment mark layer DW may be a metal, or may be a metal alloy, such as Mo, ti, cu, moNb (molybdenum niobium) alloy, MTD (moti) alloy, or the like.

For example, the alignment mark layer DW may be formed by depositing the above metal or metal alloy material using magnetron sputtering (dispenser).

Illustratively, the thickness of the alignment mark layer ranges from

The manufacturing method for forming the alignment mark layer can comprise the following steps: forming a layer of marking film, and patterning the marking film to form an alignment marking layer.

Of course, a Black Matrix (BM) may be used as the marker layer.

The alignment mark is used for realizing the installation alignment of patterns of different film layers on the substrate.

Illustratively, the material of the buffer layer Buf may be silicon nitride (SiN). The buffer layer may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD for short).

Exemplary, the thickness of the buffer layer Buf ranges from

S200, as shown in fig. 7b, a first conductive layer ET1 is formed on a side of the buffer layer Buf away from the substrate.

The first conductive layer may be formed by a plurality of processes, and may be selected according to actual needs.

For example, in the case where the first conductive layer includes a single-layer structure, the material of the first conductive layer is Cu.

For example, in the case where the first conductive layer includes a multilayer structure, the first conductive layer includes a body layer made of copper and a shield layer made of MoNb, mo, ti, moTi, moW, moTa (molybdenum-tantalum alloy), MTD.

For example, in the case where the first conductive layer includes a two-layer structure, a seed layer (including a protective layer and a bulk layer sequentially laminated on a buffer layer) having a thickness in the range ofFor example, the thickness of the body part in the seed layer may be +.>Then the thickness of the main copper layer is 1-10 μm through electroplating process.

For another example, in the case where the first conductive layer includes a three-layer structure, a protective layer, a body layer, and a protective layer may be sequentially deposited on the buffer layer using a Sputer process. The thickness of the main body portion in the first conductive layer is in the range of 0.6 μm to 4 μm, for example, the thickness of the main body portion is 2.7 μm. The thickness range of the protective layer isFor example, the protective layer has a thickness of

It can be appreciated that the method for forming the first conductive layer includes: the first conductive film is formed, and the first conductive film is patterned to form a first conductive layer having a pattern corresponding to the signal line, the connection pad, or the like.

S300, as shown in fig. 7c, a first insulating layer 31 is formed on the side of the first conductive layer ET1 remote from the substrate 1.

The first insulating layer 31 may include a first passivation layer PVX1, a first planarization layer PLN1, and a second passivation layer PVX2, which are sequentially stacked, for example.

The first passivation layer PVX1 and the second passivation layer PVX2 are the same in material and thickness, and may be formed by the same process.

For example, the material of the first passivation layer PVX1 may be SiN.

For example, the first passivation layer PVX1 may be formed using a CVD process.

For example, the first passivation layer PVX1 has a thickness in the range of

Illustratively, the material of the first planar layer PLN1 may be Optical Cement (OC for short).

The thickness of the first planar layer PLN1 is in the range of 2 μm to 10 μm, for example. For example, the thickness of the planarization layer is 4 μm.

It will be appreciated that the thickness of the planar layer may be adjusted and set according to the thickness of the first conductive layer. For example, the thickness of the planar layer is greater than the thickness of the first conductive layer. The first insulating layer 31 here is the insulating layer 3 above.

In addition, the manufacturing method of the first flat layer includes: a flat film is formed on a side of the passivation layer away from the substrate, and a via hole is formed in the flat film and in the first passivation layer at a position corresponding to the signal line in the first conductive layer to expose a portion of the signal line. And the second passivation layer does not cover the through holes.

S400, as shown in fig. 7d, a second conductive layer ET2 is formed on the side of the first insulating layer 31 remote from the substrate.

The second conductive layer ET2 may be manufactured by various processes, and may be selected according to practical needs.

For example, in the case where the second conductive layer ET2 includes a two-layer structure, the second conductive layer includes a protective layer and a body layer sequentially laminated on the insulating layer, the body layer having a thickness in the range ofFor exampleThe thickness of the body part may be +.>The material of the protective layer can be MTD, mo, moTi, moW, moTa, ti, W, etc., and the thickness of the protective layer is in the range of +.>

For another example, in the case where the second conductive layer includes a three-layer structure, the first protective layer, the body layer, and the second protective layer may be sequentially deposited on the buffer layer using a Sputer process. The thickness of the main body part in the second conductive layer is in the range ofFor example, the thickness of the body part may be +.>The material of the first protective layer may be MTD, mo, moTi, moW, moTa, ti, W, etc., wherein the thickness of the first protective layer is in the range +.>The material of the second protective layer may be Ni or a Ni alloy (for example NiAl, niMO, niW, niTi, niW), the percentage of Ni in the Ni alloy being greater than 40%. The material of the second protective layer can also be Cu alloy (such as CuNi, cuNiAl, cuMgAl, cuTi, etc.), wherein the thickness of the second protective layer is in the range of +. >

It can be appreciated that the manufacturing method for forming the second conductive layer ET2 includes: and forming a second conductive film, patterning the second conductive film, and forming a second conductive layer having a pattern corresponding to the connection pad and the like.

S500, as shown in fig. 7e, a second insulating layer 32 is formed on the side of the second conductive layer ET2 away from the substrate.

The second insulating layer may include a third passivation layer PVX3 and a second planarization layer PLN2 stacked in this order, for example.

For example, the material of the third passivation layer PVX3 may be SiN.

For example, the third passivation layer PVX3 may be formed using a CVD process.

For example, the thickness of the third passivation layer PVX3 ranges from

Illustratively, the material of the second planar layer PLN2 may be Optical Cement (OC for short).

The thickness of the second planar layer PLN2 is illustratively in the range of 2 μm to 10 μm. For example, the thickness of the planarization layer is 4 μm.

It is understood that a first via hole penetrating the second insulating layer to the second conductive layer is formed on the second insulating layer 32.

S600, as shown in fig. 7f, an oxidation-resistant layer 4 is formed on the side of the second insulating layer 32 remote from the substrate 1.

Illustratively, the material of the oxidation resistant layer 4 may be Ni or a Ni alloy (e.g., niAl, niMo, niW, niTi, niW, etc.).

Illustratively, the oxidation resistant layer may be deposited using a Sputer process.

It is understood that the oxidation resistant layer 4 includes a plurality of oxidation resistant patterns 41. The structure of the oxidation preventing layer 4 and the oxidation preventing pattern 41 may be referred to the description of some embodiments of the present invention, and will not be repeated here.

The antioxidation layer is formed after the second insulating layer, so that the residue of the second insulating layer can be avoided, the influence on the wettability of antioxidation is avoided, the influence on the welding of the antioxidation layer and the pins of the electronic element is avoided, and the die bonding yield can be improved.

S700, as shown in fig. 7g, the electronic component 200 is fixed on the oxidation-resistant layer 4.

Illustratively, solder is placed onto the oxidation resistant pattern, and the pins of the electronic component are secured to the oxidation resistant pattern using a reflow process or the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will recognize that changes and substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (18)

1. A circuit board, the circuit board comprising:

a substrate;

a plurality of connection pads located on one side of the substrate;

an insulating layer positioned on one side of the plurality of connection pads away from the substrate;

a first via penetrating the insulating layer to the connection pad, the first via exposing the connection pad; the method comprises the steps of,

an oxidation resistant layer positioned on one side of the insulating layer away from the substrate; the oxidation resistant layer includes at least one oxidation resistant pattern; the antioxidation pattern is electrically connected with the connection pad through the first via hole; the orthographic projection of the antioxidation pattern on the substrate and the orthographic projection of the connection pad electrically connected with the antioxidation pattern on the substrate are at least partially overlapped.

2. The circuit board of claim 1, wherein the circuit board has a functional area, the plurality of connection pads includes a plurality of first connection pads located in the functional area, the number of the antioxidant patterns is a plurality, and the plurality of the antioxidant patterns includes a plurality of first antioxidant patterns located in the functional area;

the circuit board comprises a first conductive layer and a second conductive layer which are sequentially stacked on one side of the substrate;

The first conductive layer includes a signal line;

the first connection pads are located on the second conductive layer, electrically connected with the signal lines and electrically connected with the first oxidation resistant patterns.

3. The circuit board of claim 2, further comprising a bonding area located on one side of the functional area, wherein the plurality of connection pads further comprises a plurality of second connection pads located on the bonding area, and wherein the plurality of antioxidant patterns comprises a plurality of second antioxidant patterns located on the bonding area;

the second connection pad is located on the first conductive layer, is electrically connected with the signal line, and is electrically connected with the second oxidation resistant pattern.

4. The circuit board of claim 3, wherein the second connection pad and the signal line electrically connected to the second connection pad are in an integral structure.

5. The circuit board of claim 2, further comprising a bonding area located on one side of the functional area, wherein the plurality of connection pads further comprises a plurality of second connection pads located on the bonding area, and wherein the plurality of oxidation resistant patterns comprises a plurality of second oxidation resistant patterns located on the bonding area;

The second connection pad is positioned on the second conductive layer;

the first conductive layer further includes a plurality of connection patterns located at the bonding region, the connection patterns being located between the substrate and the second connection pad, connecting the signal line and the second connection pad;

the second connection pad is also electrically connected with the second oxidation resistant pattern.

6. The circuit board of claim 1, wherein the circuit board comprises a third conductive layer disposed on one side of the substrate, the plurality of connection pads being located on the third conductive layer;

the third conductive layer further includes a signal line electrically connected to the connection pad.

7. The circuit board of claim 1, wherein the oxidation-resistant pattern is located within the first via;

the antioxidation pattern is contacted with the hole wall of the first via hole, or a space is reserved between the antioxidation pattern and the hole wall of the first via hole.

8. The circuit board of claim 7, wherein a spacing between a boundary line of the orthographic projection of the connection pad on the substrate and an inner boundary line of the orthographic projection of the first via on the substrate ranges from: 0 μm to 1 μm.

9. The circuit board of claim 1, wherein a portion of the oxidation-resistant pattern is located within the first via and another portion of the oxidation-resistant pattern overlaps a surface of the insulating layer on a side remote from the substrate.

10. The circuit board of claim 9, wherein a spacing between a boundary line of the orthographic projection of the oxidation-resistant pattern on the substrate and an inner boundary line of the orthographic projection of the first via on the substrate ranges from: 1 μm to 10 μm.

11. The circuit board of claim 1, wherein the material of the oxidation resistant layer comprises nickel and/or a nickel alloy.

12. The wiring board of claim 11, wherein in the case where the material of the oxidation-resistant layer comprises a nickel alloy, the mass percentage of nickel in the nickel alloy is 40% or more.

13. The circuit board of claim 1, wherein the connection pad comprises a main body portion, and/or at least one protection portion provided on one side of the main body portion in a stacked manner;

the material of the main body part comprises copper;

the material of the guard includes nickel, nickel alloy or copper alloy.

14. The circuit board of claim 13, wherein in the case where the connection pad includes a main body portion and two guard portions, the two guard portions are a first guard portion and a second guard portion, respectively, the main body portion is located between the first guard portion and the second guard portion.

15. The circuit board of claim 13, wherein in the case where the connection pad includes a main body portion and a shield portion, the shield portion is located on a side of the main body portion adjacent to the substrate.

16. A substrate, the substrate comprising: the wiring board as set forth in any one of claims 1 to 15, and a plurality of electronic components; the electronic component includes at least one pin electrically connected with the oxidation-resistant pattern in the circuit board.

17. The substrate of claim 16, wherein the electronic component comprises a micro light emitting device.

18. A backlight module, comprising: the substrate of claim 16 or 17, and a set of optical films on the light exit side of the substrate.