CN117806857B

CN117806857B - Fault location information generation method and device, electronic equipment and storage medium

Info

Publication number: CN117806857B
Application number: CN202310944736.3A
Authority: CN
Inventors: 韩蕾; 张秀波; 王相宇
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-07-28
Filing date: 2023-07-28
Publication date: 2024-05-14
Anticipated expiration: 2043-07-28
Also published as: CN117806857A

Abstract

The embodiment of the invention provides a fault location information generation method, a device, electronic equipment and a storage medium, which relate to the technical field of fault location information generation, and are characterized in that a first control system is configured for a coprocessor and a second control system is configured for a main processor; the first control system is a microcontroller real-time operating system; when a fault signal aiming at the server is obtained through the main processor, the fault signal is sent to the microcontroller real-time operating system through the second control system; the microcontroller real-time operating system generates fault positioning information aiming at the server based on the fault signal, so that excessive occupation of a main processor when the server is subjected to fault positioning is effectively avoided, and the data processing efficiency of the processor is improved.

Description

Fault location information generation method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of fault location information generation technologies, and in particular, to a fault location information generation method, a fault location information generation device, an electronic apparatus, and a computer readable storage medium.

Background

With the rapid development of internet technology, servers have become an integral part of modern society. However, during server operation, a wide variety of faults may occur, with IERR faults being a relatively common type of fault. IERR (Internal Error) refers to internal errors, typically caused by hardware failures such as CPU or motherboard power supply. The occurrence frequency of hardware faults is high, if the IERR faults cannot be accurately detected and processed, the server is down, normal operation of the service is affected, and the stability and reliability of the operation of the server are greatly affected. Therefore, how to improve the positioning efficiency for the server IERR fault becomes a technical problem to be overcome by those skilled in the art.

Disclosure of Invention

The embodiment of the invention provides a fault location information generation method, a device, electronic equipment and a computer readable storage medium, which are used for solving the problem of improving the location efficiency of an IERR fault of a server.

The embodiment of the invention discloses a fault location information generation method, which is applied to a baseboard management controller, wherein the baseboard management controller is configured on a server and comprises a main processor and a coprocessor, and the main processor and the coprocessor perform data interaction through a shared memory, and comprises the following steps:

Configuring a first control system for the coprocessor and a second control system for the main processor; the first control system is a microcontroller real-time operating system;

when a fault signal aiming at the server is obtained through the main processor, the fault signal is sent to the microcontroller real-time operating system through the second control system;

And generating fault positioning information for the server based on the fault signal by the microcontroller real-time operating system.

Optionally, the method further comprises:

And integrating a file analysis library in the microcontroller real-time operating system.

Optionally, the method further comprises:

And in the power-on stage of the baseboard management controller, initializing operation and enabling operation are carried out on the coprocessor.

Optionally, the coprocessor includes a coprocessor control register, and instruction memory address limit register, and data memory address limit register, and a cache function control register, and a cacheable region declaration register, and the step of performing an initialization operation and an enabling operation on the coprocessor includes:

And executing initialization operation and enabling operation on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register and the cacheable region statement register.

Optionally, the coprocessor has a corresponding flash memory chip configured with a corresponding first pin control register, and a second pin control register, and a pin address decoding range register, and further comprising:

Determining serial peripheral interface configuration parameters for the first pin control register, the second pin control register, and the pin address decode range register.

Optionally, a corresponding asynchronous transceiver serial port is provided between the baseboard management controller and the coprocessor, and the microcontroller real-time operating system has a corresponding entry function, and further includes:

Initializing the serial port of the asynchronous receiving and transmitting transmitter to determine initial configuration parameters of a data receiving and transmitting register corresponding to the serial port of the asynchronous receiving and transmitting transmitter by adopting the entry function.

Optionally, the method further comprises:

Determining an initialization operation function for the main processor and the coprocessor;

And determining an interactive link aiming at the shared memory through initializing an operation function.

Optionally, the method further comprises:

And adopting the microcontroller real-time operating system to create a received data task aiming at the fault signal.

Optionally, the step of generating, by the microcontroller real-time operating system, fault location information for the server based on the fault signal includes:

when the microcontroller real-time operating system receives a first interrupt signal sent by the second control system, a fault location resolving task aiming at the fault signal is created by the microcontroller real-time operating system;

Unlocking the shared memory, and receiving the fault signal by the microcontroller real-time operating system through the data receiving task;

And generating fault positioning information aiming at the server based on the fault signal by adopting the fault positioning resolving task through the microcontroller real-time operating system.

Optionally, the method further comprises:

generating a fault detection process for the fault signal;

Constructing a dual-core communication drive write function for the main processor and the coprocessor;

determining asset information for the server;

And calling the dual-core communication driving write function through the fault detection process to store the asset information into the shared memory.

Optionally, the baseboard management controller is configured with a corresponding complex programmable logic device and a platform environment type control interface link; the complex programmable logic device is used for acquiring a fault signal, and the step of sending the fault signal to the microcontroller real-time operating system comprises the following steps of:

And responding to the fault signal, acquiring register information for expressing the fault signal through the platform environment type control interface link, and storing the register information into the file analysis library.

Optionally, the method is characterized by further comprising:

and when the file analysis inventory is detected to be in the register information, storing the register information into the shared memory.

Optionally, the method further comprises:

And deleting the history register information when the file analysis is detected to be stored in the register information and the file analysis is detected to be stored in the history register information.

Optionally, the method further comprises:

generating an execution starting instruction for the fault location resolution task;

Calling the dual-core communication drive write function through the fault detection process to send the execution starting instruction to the microcontroller real-time operating system;

Optionally, the step of generating, by the microcontroller real-time operating system, fault location information for the server based on the fault signal using the fault location calculation task includes:

and responding to the start execution instruction, and generating fault location information for the server by adopting the microcontroller real-time operating system through the fault location calculation task based on the register information.

Optionally, the microcontroller real-time operating system is further configured to generate a fault diagnosis result for the fault location information, and send the fault diagnosis result to the shared memory after sending a second interrupt signal to the second operating system.

Optionally, the method further comprises:

And when the second operating system receives the second interrupt signal, reading the fault diagnosis result from the shared memory, and generating log alarm information for the fault diagnosis result.

The embodiment of the invention also discloses a fault location information generating device, which is applied to a baseboard management controller, wherein the baseboard management controller is configured on a server and comprises a main processor and a coprocessor, the main processor and the coprocessor perform data interaction through a shared memory, and the device comprises:

the microcontroller real-time operating system configuration module is used for configuring a first control system for the coprocessor and configuring a second control system for the main processor; the first control system is a microcontroller real-time operating system;

The fault signal sending module is used for sending the fault signal to the microcontroller real-time operating system through the second control system when the fault signal aiming at the server is obtained through the main processor;

And the fault positioning information generation module is used for generating fault positioning information aiming at the server based on the fault signal through the microcontroller real-time operating system.

Optionally, the method further comprises:

and the file analysis library integration module is used for integrating the file analysis library in the microcontroller real-time operating system.

Optionally, the method further comprises:

And the initialization operation and enabling operation execution module is used for executing initialization operation and enabling operation on the coprocessor in the power-on stage of the baseboard management controller.

Optionally, the coprocessor includes a coprocessor control register, and instruction memory address limit register, and data memory address limit register, and a cache function control register, and a cacheable region declaration register, and the initialization operation and enabling operation execution module includes:

An initialization and enable execution sub-module configured to execute an initialization operation and an enable operation on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register, and the cacheable region declaration register.

And the serial peripheral interface configuration parameter determination submodule is used for determining the serial peripheral interface configuration parameters aiming at the first pin control register, the second pin control register and the pin address decoding range register.

And the initial configuration parameter determination submodule is used for initializing the serial port of the asynchronous receiving and transmitting transmitter so as to determine initial configuration parameters of a data receiving and transmitting register corresponding to the serial port of the asynchronous receiving and transmitting transmitter by adopting the entry function.

Optionally, the method further comprises:

An initialization operation function determination submodule for determining an initialization operation function for the main processor and the coprocessor;

And the interactive link determination submodule is used for determining the interactive link aiming at the shared memory through initializing an operation function.

Optionally, the method further comprises:

and the received data task creation sub-module is used for creating the received data task aiming at the fault signal by adopting the microcontroller real-time operating system.

Optionally, the fault location information generating module includes:

The fault location calculation task creation sub-module is used for creating a fault location calculation task aiming at the fault signal through the microcontroller real-time operating system when the microcontroller real-time operating system receives a first interrupt signal sent by the second control system;

The fault signal receiving sub-module is used for unlocking the shared memory and receiving the fault signal by adopting the data receiving task through the microcontroller real-time operating system;

And the fault positioning information generation sub-module is used for generating fault positioning information aiming at the server based on the fault signal by adopting the fault positioning calculation task through the microcontroller real-time operating system.

Optionally, the method further comprises:

A fault detection process generation sub-module for generating a fault detection process for the fault signal;

a dual-core communication driving write function construction sub-module for constructing dual-core communication driving write functions for the main processor and the coprocessor;

An asset information determination sub-module for determining asset information for the server;

And the asset information storage sub-module is used for calling the dual-core communication drive write function through the fault detection process to store the asset information into the shared memory.

And the fault signal sending sub-module is used for responding to the fault signal, acquiring register information for expressing the fault signal through the platform environment type control interface link, and storing the register information into the file analysis library.

Optionally, the method further comprises:

And the register information storage sub-module is used for storing the register information into the shared memory when the fact that the file analysis inventory is stored in the register information is detected.

Optionally, the method further comprises:

And the history register information deleting sub-module is used for deleting the history register information when the fact that the file analysis is stored in the register information is detected and the file analysis is stored in the history register information.

Optionally, the method further comprises:

the start execution instruction generation sub-module is used for generating a start execution instruction aiming at the fault location resolving task;

the execution starting instruction sending submodule is used for calling the dual-core communication driving write function through the fault detection process to send the execution starting instruction to the microcontroller real-time operating system;

The fault location information generation submodule includes:

and the fault location information generating unit is used for responding to the start execution instruction, adopting the microcontroller real-time operating system to generate fault location information aiming at the server based on the register information through the fault location resolving task.

Optionally, the method further comprises:

And the fault diagnosis result reading sub-module is used for reading the fault diagnosis result from the shared memory and generating log alarm information aiming at the fault diagnosis result when the second operating system receives the second interrupt signal.

The embodiment of the invention also discloses a server, wherein the server is provided with a baseboard management controller, the baseboard management controller comprises a main processor and a coprocessor, the main processor and the coprocessor perform data interaction through a shared memory, and the baseboard management controller is used for configuring a first control system for the coprocessor and configuring a second control system for the main processor; the first control system is a microcontroller real-time operating system; when a fault signal aiming at the server is obtained through the main processor, the fault signal is sent to the microcontroller real-time operating system through the second control system; and generating fault positioning information for the server based on the fault signal by the microcontroller real-time operating system.

The embodiment of the invention also discloses electronic equipment, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;

The memory is used for storing a computer program;

The processor is configured to implement the method according to the embodiment of the present invention when executing the program stored in the memory.

Embodiments of the present invention also disclose a computer-readable storage medium having instructions stored thereon, which when executed by one or more processors, cause the processors to perform the method according to the embodiments of the present invention.

The embodiment of the invention has the following advantages:

According to the embodiment of the invention, a first control system is configured for the coprocessor, and a second control system is configured for the main processor; the first control system is a microcontroller real-time operating system; when a fault signal aiming at the server is obtained through the main processor, the fault signal is sent to the microcontroller real-time operating system through the second control system; the microcontroller real-time operating system generates fault positioning information aiming at the server based on the fault signal, so that excessive occupation of a main processor when the server is subjected to fault positioning is effectively avoided, and the data processing efficiency of the processor is improved.

Drawings

FIG. 1 is a flow chart of steps of a fault location information generation method provided in an embodiment of the present invention;

FIG. 2 is a schematic diagram of a server according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a register configuration according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an implementation flow for freertos systems provided in an embodiment of the present invention;

FIG. 5 is a schematic diagram of an execution flow for a Linux system according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a baseboard management controller and a central processing unit of a server according to an embodiment of the present invention;

FIG. 7 is a timing diagram of a data flow provided in an embodiment of the present invention;

Fig. 8 is a block diagram of a fault location information generating device provided in an embodiment of the present invention;

FIG. 9 is a block diagram of the hardware architecture of an electronic device provided in an embodiment of the present invention;

fig. 10 is a schematic diagram of a computer readable medium provided in an embodiment of the invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

In order to enable those skilled in the art to better understand the embodiments of the present invention, some technical terms related to the embodiments of the present invention are described below.

BMC Board Management Controller, baseboard management controller, is a specialized service processor that uses sensors to monitor the status of a computer, web server, or other hardware driven device and communicates with the system administrator via separate connection lines. BMCs are part of the intelligent platform control interface (IPMI, INTELLIGENT PLATFORM MANAGEMENT INTERFACE) and are typically contained within a motherboard or main circuit board of a device being monitored. The sensors of the BMC are used to measure internal physical variables such as: temperature, humidity, power supply voltage, fan speed, communication parameters, and Operating System (OS) functions. If any of these variables is outside the scope of the established limits, it will notify the administrator. The administrator will take the correct action using the remote control. The monitoring device may be power cycled or restarted when necessary. In this way, a single administrator can remotely control numerous servers and other devices simultaneously. This saves the overall cost of the network and ensures reliability.

JSON (JavaScript Object Notation, JS object numbered musical notation) is a lightweight, text-based, readable format. It stores and presents data in a text format that is completely independent of the programming language based on a subset of ECMAScript (European Computer Manufacturers Association, js specification by the european computer institute). The compact and clear hierarchical structure makes JSON an ideal data exchange language. Is easy to read and write by people, is easy to analyze and generate by machines, and effectively improves the network transmission efficiency.

FreeRtso: the microcontroller operates the system in real time. FreeRTOS is a mini real-time operating system kernel. The functions of the lightweight operating system include task management, time management, semaphore, message queue, memory management, recording function, software timer, coroutine and the like, and can basically meet the requirements of smaller systems.

AST2600: a new generation of BMC chips.

IERR: internal errors.

Linux, collectively called GNU/Linux, is a free-to-use and freely-spread UNIX-like operating system, which is mainly inspired by Minix and Unix ideas and is a POSIX-based multi-user, multi-tasking, multi-thread and multi-CPU supporting operating system.

The CPU central processing unit (Central Processing Unit, CPU for short) is used as the operation and control core of the computer system and is the final execution unit for information processing and program running. Since the generation of the CPU, great development is made on the aspects of logic structure, operation efficiency and functional extension.

Currently, related art realizes fault detection through a BMC chip on a server motherboard. The BMC chip is carried with the linux system to detect IEER faults, and the method can effectively detect hardware faults, but can only provide basic hardware monitoring functions and cannot meet the requirements of a high-end server. Therefore, how to continuously improve the accuracy and real-time performance of fault detection of the server IEER becomes one of the hot spots of current research.

The complexity of the accurate positioning algorithm of the server IERR fault is high and the data volume is large, so that the CPU occupancy rate is high, and meanwhile, the operation of other programs can be influenced, even the system is blocked, and the stability and the response speed of the system are influenced. How to alleviate the CPU resource occupancy caused by the execution of a large number of algorithms by the BMC chip is a difficult problem.

Therefore, the invention provides a method for realizing the accurate positioning algorithm of the server IERR based on the coprocessor carrying Freertos, which can be based on an AST2600 hardware platform, and utilizes the characteristics of light weight, high real-time performance and good stability of a coprocessor, low power consumption, safety, reliability, flexibility and easiness and freertos operating system to run freertos on the coprocessor to finish the development of the accurate positioning algorithm of the server IERR, and simultaneously run linxu on the main processor to finish the collection of auxiliary CPU registers and the alarm processing of fault results aiming at the characteristics of high performance, high processing capacity and complex functions of the linxu system of the main processor. The method can effectively improve the accuracy and the instantaneity of the fault detection of the server IEER. Meanwhile, the accurate positioning algorithm of the server IERR fault is completed by the coprocessor, so that the occupancy rate of the main processor can be greatly reduced, and the data processing efficiency of the processor is improved.

Referring to fig. 1, a step flowchart of a fault location information generating method provided in an embodiment of the present invention may specifically include the following steps:

step 101, configuring a first control system for the coprocessor and a second control system for the main processor; the first control system is a microcontroller real-time operating system;

step 102, when a fault signal for the server is acquired through the main processor, the fault signal is sent to the microcontroller real-time operating system through the second control system;

and step 103, generating fault positioning information for the server based on the fault signal by the microcontroller real-time operating system.

In a specific implementation, the embodiment of the present invention may be applied to a baseboard management controller in a server, and for example, the baseboard management controller of the embodiment of the present invention may be a baseboard management controller on which an AST2600 chip is mounted.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a server according to an embodiment of the present invention, where the server may include a main processor and a coprocessor, and the main processor may be Cortex A7, the coprocessor may be Cortex M3, and the Cortex M3 may be a 32-bit processor core, for example. The internal data path is 32 bits, the registers are 32 bits, and the memory interface is also 32 bits. CM3 adopts a harvard architecture, has independent instruction buses and data buses, and allows instruction fetching and data access without any violation.

Of course, the above examples are merely examples, and those skilled in the art may use any other CPU as a main processor or a coprocessor according to actual needs, which is not limited in this regard.

The main processor of the embodiment of the invention can perform data interaction with the coprocessor through the shared memory based on the data bus.

The embodiment of the invention can respectively install independent operating systems for the main processor and the coprocessor, specifically can configure a first control system for the coprocessor and a second control system for the main processor; the first control system may install a microcontroller real-time operating system freeRtso for the coprocessor. The second control system may be a linux operating system.

By way of example, communication can be established between the main processor Cortex A7 of the AST2600 and the coprocessor Cortex M3 through a Bus, when an IERR fault occurs in the server, a fault signal caterr is triggered, when the Linux system running on the main processor receives a caterr signal, register information for expressing the caterr signal is directly collected and transmitted to the freertos system running on the coprocessor, after receiving an execution starting instruction and CPU register information, the freertos system runs a fault accurate positioning algorithm in real time to perform fault detection, the detection end feeds back a detection result to the linu system, and the Linux system performs log alarm and other operations, so that excessive occupation of the main processor when fault positioning on the server is effectively avoided.

On the basis of the above embodiments, modified embodiments of the above embodiments are proposed, and it is to be noted here that only the differences from the above embodiments are described in the modified embodiments for the sake of brevity of description.

In an alternative embodiment of the present invention, further comprising:

In practical application, the fault accurate positioning algorithm needs to involve the analysis processing of a large number of json files, and before the Cortex M3 is loaded with the freertos system, the freertos system does not have a json file analysis library.

Therefore, in a specific implementation, before carrying out the hardware platform, the embodiment of the invention may first complete the integration of the third party json library and freertso systems, and for example, the json-c library with an open source may be selected to be integrated into freertso systems.

According to the embodiment of the invention, the file analysis library is integrated in the real-time operating system of the microcontroller, so that the expansion of the freertos system on the json data generation and analysis functions is realized.

In an alternative embodiment of the present invention, further comprising:

In practice, initialization may set up the coprocessor, while enabling operations may make the coprocessor available.

In particular, the first initial configuration parameter may be an initial configuration parameter for the coprocessor.

Referring to fig. 3, fig. 3 is a schematic diagram of a register according to an embodiment of the present invention.

In a specific implementation, the initializing and enabling operations may involve parameter configurations of CM3 coprocessor control registers, CM3 instruction memory address limit registers, CM3 data memory address limit registers, CM3 cache function control registers, and CM3 cacheable region declaration registers, and in particular, the initializing operations and enabling operations may be performed on control registers, instruction memory address limit registers, the data memory address limit registers, the cache function control registers, and the cacheable region declaration registers, respectively.

According to the embodiment of the invention, the initialization operation and the enabling operation of the coprocessor are performed on the coprocessor control register, the instruction memory address limit register, the data memory address limit register, the cache function control register and the cacheable region statement register, so that the initialization and the enabling of the coprocessor are completed, the stability of the coprocessor in running is ensured, and the success rate of the freertos system in starting is improved.

In practical applications, ce is an abbreviation of chip enable, which may be a pin that is required for a flash memory chip to read and write.

The coprocessor of the embodiment of the invention can be provided with a corresponding FLASH memory chip FLASH, and the embodiment of the invention can configure the serial peripheral interface FSPI of the FLASH memory chip before starting Freetos the system.

Referring to fig. 3, an embodiment of the present invention may determine a serial peripheral interface configuration parameter for a CE first pin control register, a CE1 second pin control register, and a CE1 pin address decode range register, and configure a serial peripheral interface FSPI of a flash memory chip through the serial peripheral interface configuration parameter.

According to the embodiment of the invention, before the microcontroller starts the real-time operating system, the configuration parameters of the serial peripheral interface aiming at the first pin control register, the second pin control register and the pin address decoding range register are determined, and the serial peripheral interface FSPI of the FLASH memory chip is configured through the configuration parameters of the serial peripheral interface, so that the stability of the FLASH memory chip FLASH is improved, and the data interaction efficiency between the main processor and the coprocessor is improved.

Based on this, the data execution flow of the freertos system is described below after the freertos system is started, after the preparation flow before the freertos system is started.

In an alternative embodiment of the present invention, there is a corresponding asynchronous transceiver serial port between the baseboard management controller and the coprocessor, and the microcontroller real-time operating system has a corresponding entry function, and further includes:

And determining initial configuration parameters of a data receiving and sending register corresponding to the serial port of the asynchronous receiving and sending transmitter by adopting the entry function.

An asynchronous transceiver UART, a universal asynchronous transceiver (Universal Asynchronous Receiver/Transmitter), commonly referred to as UART, is an asynchronous transceiver that is part of the server hardware. The baseboard management controller and the coprocessor of the embodiment of the invention can be provided with corresponding asynchronous receiving and transmitting transmitters, and the asynchronous receiving and transmitting transmitters can be configured with asynchronous receiving and transmitting transmitter serial ports.

In a specific implementation, after the Freetos system is started, the initial configuration parameters of the data receiving and sending registers corresponding to the serial port of the asynchronous receiving and sending transmitter can be determined by adopting the inlet function main so as to realize that the printing information of the freertos system can be normally output to the serial port of the BMC terminal, thereby improving the generation efficiency of the fault location information.

In an alternative embodiment of the present invention, further comprising:

In practical application, the shared memory and the inter-core interrupt are the most basic bottom configuration of communication between the main processor and the coprocessor, so that the embodiment of the invention can determine the initialization operation function for the main processor and the coprocessor, the initialization operation function can be used for determining the shared memory for the main processor and the coprocessor and the interactive link for the shared memory, thereby completing the parameter configuration of the shared memory, completing the configuration and enabling of the register of the communication soft interrupt between the main processor and the slave processor and ensuring the correct bottom interactive link of the double processor.

In an alternative embodiment of the present invention, further comprising:

For example, the embodiment of the invention can create a data receiving task for communication between the master processor and the slave processor, and the data receiving task can be used for receiving data information sent by the linux system by the freertos system and performing corresponding processing according to the data information.

In an alternative embodiment of the present invention, the step of generating, by the microcontroller real-time operating system, fault location information for the server based on the fault signal includes:

In a specific implementation, the embodiment of the invention can adopt the microcontroller real-time operating system to create the fault location resolving task, and the microcontroller real-time operating system can execute the fault location resolving task after receiving the execution starting instruction sent by the linux system so as to generate the fault location information aiming at the server.

Based on the above, after the data execution flow of the freertos system is completed, the following is a description of the data execution flow of the Linux system after the Linux system is started.

Optionally, the method further comprises:

generating a fault detection process for the fault signal;

determining asset information for the server;

In a specific implementation, the embodiment of the invention can generate a fault detection process aiming at a fault signal and construct a dual-core communication driving write function aiming at a main processor and a coprocessor. The embodiment of the invention can also determine the asset information aiming at the server and store the asset information into the file analysis library so as to call the dual-core communication drive write function to store the asset information into the shared memory through the fault detection process.

For example, after bois (Basic Input Output System, basic input/output system) is started, the asset information of the devices such as the CPU, the memory, the high-speed serial computer expansion bus pcie and the like required by the fault detection may be sent to the bmc, the bmc may be stored in a json format to a designated position, specifically, the fault detection process is started normally, and the fault detection process may be used to call a dual-core communication driving write function to write the information required by the fault detection such as the asset information into a preset designation of the shared memory, and optionally, the formulated area may be preset.

In an alternative embodiment of the present invention, the baseboard management controller is configured with a corresponding complex programmable logic device and platform environment type control interface link; the complex programmable logic device is used for acquiring a fault signal, and the step of sending the fault signal to the microcontroller real-time operating system comprises the following steps of:

The baseboard management controller is configured with a corresponding complex programmable logic device cpld and a platform environment type control interface link, when a server fails IEER, a fault signal caterr can be triggered, the caterr signal can be captured by the complex programmable logic device cpld, the BMC detects the signal in real time, when the BMC detects the signal, the BMC can trigger an application of an automatic collection register, the application can collect the register information of the CPU directly through the platform environment type control interface link peci and store the register information in json format, so that asset information, CPU register information and the like between a Linux system and the freertos system can be transmitted based on json file format, and fault positioning efficiency is improved.

In an alternative embodiment of the present invention, further comprising:

Illustratively, when IEER fault detection threads in the fault diagnosis process detect that the json file of the CPU register exists, the file information of the last IEER fault detection is cleaned up, and then the CPU register information in the json format is stored in the shared memory.

According to the embodiment of the invention, when the file analysis inventory is detected to be in the register information, the register information is stored into the shared memory; when the file analysis is detected to be stored in the register information and the file analysis is detected to be stored in the history register information, the history register information is deleted, so that the redundancy of the register information is avoided.

In an alternative embodiment of the present invention, further comprising:

And calling the dual-core communication driving write function through the fault detection process to send the execution starting instruction to the microcontroller real-time operating system.

The Linux system may generate an execution start instruction for the fault location resolution task, and call the dual-core communication driving write function through the fault detection process to send the execution start instruction to the microcontroller real-time operating system freertos, and after the fault location resolution task of the freertos system determines that the execution start instruction is received, may call the fault accurate location entry function to perform fault detection to locate the fault firmware.

In a specific implementation, freertos systems can also sort fault diagnosis results and write the fault diagnosis results into idle channels in the shared memory, so that conditions are created for the main processor to read the fault diagnosis results through the shared memory based on the Linux system.

Optionally, the method further comprises:

In a specific implementation, after the fault diagnosis result is read through the shared memory based on the Linux system, the main processor of the embodiment of the invention can generate log alarm information aiming at the fault diagnosis result, so that the maintenance of technicians is facilitated.

In order that those skilled in the art will better understand the embodiments of the present invention, a complete example will be described below.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a baseboard management controller and a server cpu according to an embodiment of the present invention.

The baseboard management controller may include a main processor and a coprocessor, and data interaction between the main processor and the coprocessor may be performed through a shared memory based on a data bus (a first sub-bus is an M bus, a second sub-bus is an AHB bus, and a third sub-bus is an APB bus).

Referring to fig. 7, fig. 7 is a timing diagram of a data flow provided in an embodiment of the present invention.

By establishing communication between a main processor Cortex A7 and a coprocessor Cortex M3 of AST2600, when an IERR fault trigger caterr signal occurs in a server, the main processor Linux system directly collects CPU register information and transmits the CPU register information to a coprocessor freertos system, a freertos system receives a fault accurate positioning instruction and the CPU register information and then runs a fault accurate positioning algorithm in real time to perform fault detection, a detection result is fed back to the linu system after the detection is finished, and a Linux system performs log alarm and other operations.

Specifically, before the Cortex M3 is loaded with freertos systems, considering that a fault accurate positioning algorithm involves analysis processing of a large number of json files, the freertos system does not have json file analysis libraries, and before the hardware platform is loaded, integration of a third-party json library and a freertso system is finished, and an open-source json-c library can be selected to realize integrated work, so that json data generation and analysis function expansion of the freertos system are finished;

The BMC chip is electrified to start, cortex A7 starts a boot program of a diskless start read-only memory interface, in an SPL (auxiliary program loader, secondary programloader) stage, initialization and enabling of Cortex M3 are achieved, the initialization and enabling relate to parameter configuration of a CM3 coprocessor control register, a CM3 instruction memory address limit register, a CM3 data memory address limit register, a CM3 cache function control register and a CM3 cacheable area statement register, the configuration is completed to enable the Cortex M3, meanwhile, the configuration also needs to be conducted on FLASH chip selection, the configuration relates to parameter configuration of a CE first pin control register, a CE1 second pin control register and a CE1 pin address decoding range register, the configuration is successful, the Cortex M3 smoothly loads a freertos system, freertos serves as a lightweight operating system, and can achieve quick starting of a millisecond level, and meanwhile, the Cortex A7 loads a Linux system;

based on this, after the preparation process before the freertos system is started, the following is a description of the data execution process of the freertos system after the freertos system is started;

referring to fig. 4, fig. 4 is a schematic diagram of an execution flow for freertos systems provided in an embodiment of the present invention;

Freertos, an entry function main, wherein the configuration of UART serial port data receiving and transmitting registers of the BCM is executed in the entry function in the first step, so that printing information of the freertos system can be normally output to a serial port of a BMC terminal, and debugging and problem analysis are facilitated;

The shared memory and the inter-core interrupt are the most basic bottom configuration of communication between the main processor and the coprocessor, so that the initialization operation function of dual-core communication is executed in the second step, the function mainly completes the parameter configuration of the dual-core shared memory, the register configuration and the enabling of the dual-core communication soft interrupt, and the correct interaction link of the bottom layer of the dual processor is ensured;

thirdly, creating a data receiving task of dual-core communication, wherein the task is responsible for a freertos system to receive data information sent by a linux system and performs corresponding processing according to the data information;

fourthly, creating a task of starting fault accurate positioning and resolving; the task is executed after receiving a fault starting accurate positioning instruction sent by the linux system.

Freertos after judging that a fault accurate positioning instruction is received in a fault accurate positioning calculation task, starting to call a fault accurate positioning entry function to perform fault detection; IEER after the fault detection is judged by a series of complex processes, the fault firmware is positioned, and meanwhile, the fault diagnosis result is arranged and written into the shared memory idle channel, and a soft interrupt signal is sent to the main processor.

Referring to fig. 5, fig. 5 is a schematic diagram of an execution flow for a Linux system according to an embodiment of the present invention;

After the Linux operating system is started, the whole software flow comprises:

After bois is started, asset information of a CPU, a memory, pcie equipment and the like required by fault detection is sent to bmc, the bmc is stored to a designated position in json format, a fault detection process is started normally, and the fault detection process calls a dual-core communication driving write function to write information required by fault detection accurate positioning of the asset information and the like into a designated area of a shared memory, wherein the designated area can be preset;

When IEER is out of order, a caterr signal is triggered, the signal is captured by cpld, the BMC detects the signal in real time, and when the BMC detects the signal, the application of an automatic collection register is triggered, and the application directly collects the register information of the CPU through a peci link and stores the register information in json format;

When IEER fault detection threads in the fault diagnosis process detect that the json file of the CPU register exists, clearing the file information of the last IEER fault detection, and then storing the CPU register information in the json format into a shared memory;

the thread invokes a dual-core communication driven write function to send a start fault precise location instruction to the freertos system.

The Linux system of the main processor performs the read-write operation of dual-core communication by registering a callback processing function, the SIGUSER semaphore is set as an interrupt semaphore, when a soft interrupt signal sent by freertos is received, the callback function of the signal is triggered, a fault diagnosis result is read from a shared memory in the callback function, and finally, the Linux generates log alarm information to facilitate maintenance.

By the method, the server IERR faults can be rapidly and accurately detected, the influence diffusion of the faults on the system is avoided, the influence of the system faults on users is reduced, so that the time and cost of fault elimination are reduced, the satisfaction of the users and the stability and reliability of the server are improved, the real-time performance and stability of the system are guaranteed, the significance of operation and maintenance of the server is great, efficient fault positioning of operation and maintenance personnel is greatly facilitated, a foundation is laid for products to win client praise, powerful technical support is provided for subsequent market and client expansion, and the brand competitiveness of the products is effectively improved, so that the method has wide application prospect.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.

Referring to fig. 8, a block diagram of a fault location information generating device provided in an embodiment of the present invention is shown, which may specifically include the following modules:

A microcontroller real-time operating system configuration module 601, configured to configure a first control system for the coprocessor and a second control system for the main processor; the first control system is a microcontroller real-time operating system;

a fault signal sending module 602, configured to send, when a fault signal for the server is obtained by the main processor, the fault signal to the microcontroller real-time operating system through the second control system;

And the fault location information generation module 603 is configured to generate, by the microcontroller real-time operating system, fault location information for the server based on the fault signal.

Optionally, the method further comprises:

Optionally, the fault location information generating module includes:

Optionally, the method further comprises:

The fault location information generation submodule includes:

Optionally, the method further comprises:

For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.

In addition, the embodiment of the invention also provides electronic equipment, which comprises: the processor, the memory, store the computer program on the memory and can run on the processor, this computer program realizes each course of the above-mentioned fault location information generation method embodiment when being carried out by the processor, and can reach the same technical result, in order to avoid repetition, will not be repeated here.

The embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, realizes the processes of the above-mentioned fault location information generation method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here. The computer readable storage medium is, for example, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a magnetic disk or an optical disk.

Fig. 9 is a schematic diagram of a hardware structure of an electronic device implementing various embodiments of the present invention.

The electronic device 900 includes, but is not limited to: radio frequency unit 901, network module 902, audio output unit 903, input unit 904, sensor 905, display unit 906, user input unit 907, interface unit 908, memory 909, processor 910, and power source 911. It will be appreciated by those skilled in the art that the electronic device structure shown in fig. 7 is not limiting of the electronic device and that the electronic device may include more or fewer components than shown, or may combine certain components, or a different arrangement of components. In the embodiment of the invention, the electronic equipment comprises, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted terminal, a wearable device, a pedometer and the like.

It should be understood that, in the embodiment of the present invention, the radio frequency unit 901 may be used for receiving and transmitting signals during the process of receiving and transmitting information or communication, specifically, receiving downlink data from a base station and then processing the downlink data by the processor 910; and, the uplink data is transmitted to the base station. Typically, the radio frequency unit 901 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 901 may also communicate with networks and other devices via a wireless communication system.

The electronic device provides wireless broadband internet access to the user via the network module 902, such as helping the user to send and receive e-mail, browse web pages, and access streaming media, etc.

The audio output unit 903 may convert audio data received by the radio frequency unit 901 or the network module 902 or stored in the memory 909 into an audio signal and output as sound. Also, the audio output unit 903 may also provide audio output (e.g., a call signal reception sound, a message reception sound, etc.) related to a specific function performed by the electronic device 900. The audio output unit 903 includes a speaker, a buzzer, a receiver, and the like.

The input unit 904 is used to receive an audio or video signal. The input unit 904 may include a graphics processor (Graphics Processing Unit, GPU) 9041 and a microphone 9042, the graphics processor 9041 processing image data of still pictures or video obtained by an image capturing device (such as a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 906. The image frames processed by the graphics processor 9041 may be stored in memory 909 (or other storage medium) or transmitted via the radio frequency unit 901 or the network module 902. The microphone 9042 may receive sound and may be capable of processing such sound into audio data. The processed audio data may be converted into a format output that can be transmitted to the mobile communication base station via the radio frequency unit 901 in the case of a telephone call mode.

The electronic device 900 also includes at least one sensor 905, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 9061 according to the brightness of ambient light, and the proximity sensor can turn off the display panel 9061 and/or the backlight when the electronic device 900 moves to the ear. As one of the motion sensors, the accelerometer sensor can detect the acceleration in all directions (generally three axes), and can detect the gravity and direction when stationary, and can be used for recognizing the gesture of the electronic equipment (such as horizontal and vertical screen switching, related games, magnetometer gesture calibration), vibration recognition related functions (such as pedometer and knocking), and the like; the sensor 905 may further include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which are not described herein.

The display unit 906 is used to display information input by a user or information provided to the user. The display unit 906 may include a display panel 9061, and the display panel 9061 may be configured in the form of a Liquid crystal display (Liquid CRYSTAL DISPLAY, LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 907 is operable to receive input numeric or character information, and to generate key signal inputs related to user settings and function controls of the electronic device. In particular, the user input unit 907 includes a touch panel 9071 and other input devices 9072. Touch panel 9071, also referred to as a touch screen, may collect touch operations thereon or thereabout by a user (such as operations of the user on touch panel 9071 or thereabout using any suitable object or accessory such as a finger, stylus, or the like). The touch panel 9071 may include two parts, a touch detection device and a touch controller. The touch detection device detects the touch azimuth of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 910, and receives and executes commands sent by the processor 910. In addition, the touch panel 9071 may be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. The user input unit 907 may also include other input devices 9072 in addition to the touch panel 9071. In particular, other input devices 9072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail herein.

Further, the touch panel 9071 may be overlaid on the display panel 9061, and when the touch panel 9071 detects a touch operation thereon or thereabout, the touch operation is transmitted to the processor 910 to determine a type of touch event, and then the processor 910 provides a corresponding visual output on the display panel 9061 according to the type of touch event. Although in fig. 7, the touch panel 9071 and the display panel 9061 are two independent components for implementing the input and output functions of the electronic device, in some embodiments, the touch panel 9071 and the display panel 9061 may be integrated to implement the input and output functions of the electronic device, which is not limited herein.

The interface unit 908 is an interface to which an external device is connected to the electronic apparatus 900. For example, the external devices may include a wired or wireless headset port, an external power (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 908 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the electronic apparatus 900 or may be used to transmit data between the electronic apparatus 900 and an external device.

The memory 909 may be used to store software programs as well as various data. The memory 909 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, application programs (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data (such as audio data, phonebook, etc.) created according to the use of the handset, etc. In addition, the memory 909 may include high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.

The processor 910 is a control center of the electronic device, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and processes data by running or executing software programs and/or modules stored in the memory 909, and calling data stored in the memory 909, thereby performing overall monitoring of the electronic device. Processor 910 may include one or more processing units; preferably, the processor 910 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 910.

The electronic device 900 may also include a power supply 911 (e.g., a battery) for powering the various components, and the power supply 911 may preferably be logically coupled to the processor 910 by a power management system, such as to perform charge, discharge, and power consumption management functions.

In addition, the electronic device 900 includes some functional modules that are not shown, and will not be described herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.

In yet another embodiment provided by the present invention, as shown in fig. 10, there is further provided a computer-readable storage medium 1001 having instructions stored therein, which when run on a computer, cause the computer to perform the fault location information generation method described in the above embodiment.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. The fault location information generation method is characterized in that the method is applied to a baseboard management controller, the baseboard management controller is configured on a server, the baseboard management controller comprises a main processor and a coprocessor, the main processor and the coprocessor perform data interaction through a shared memory, and the fault location information generation method comprises the following steps:

Generating, by the microcontroller real-time operating system, fault location information for the server based on the fault signal;

the step of generating, by the microcontroller real-time operating system, fault location information for the server based on the fault signal includes:

Creating a fault location calculation task aiming at the fault signal through the microcontroller real-time operation system;

unlocking the shared memory, and receiving the fault signal by the microcontroller real-time operating system through a data receiving task;

2. The method as recited in claim 1, further comprising:

3. The method as recited in claim 2, further comprising:

4. The method of claim 3, wherein the coprocessor includes a coprocessor control register and an instruction memory address limit register and a data memory address limit register and a cache function control register and a cacheable region declaration register, the step of performing initialization operations and enabling operations on the coprocessor comprising:

5. The method of claim 4, wherein the coprocessor has a corresponding flash chip configured with a corresponding first pin control register and a second pin control register and a pin address decode range register, further comprising:

6. The method of claim 3, wherein the baseboard management controller and the coprocessor have corresponding asynchronous transceiver serial ports therebetween, the microcontroller real-time operating system has corresponding entry functions, further comprising:

7. The method as recited in claim 6, further comprising:

8. The method as recited in claim 7, further comprising:

9. The method of claim 8, wherein creating, by the microcontroller real-time operating system, a fault location resolution task for the fault signal comprises:

And when the microcontroller real-time operating system receives a first interrupt signal sent by the second control system, creating a fault location resolving task aiming at the fault signal through the microcontroller real-time operating system.

10. The method as recited in claim 9, further comprising:

generating a fault detection process for the fault signal;

determining asset information for the server;

11. The method of claim 10, wherein the baseboard management controller is configured with a corresponding complex programmable logic device and a platform environment type control interface link; the step of sending the fault signal to the microcontroller real-time operating system through the second control system comprises the following steps:

12. The method as recited in claim 11, further comprising:

13. The method as recited in claim 11, further comprising:

14. The method according to claim 12 or 13, further comprising:

15. The method of claim 14, wherein the step of generating fault location information for the server based on the fault signal using the fault location resolution task by the microcontroller real-time operating system comprises:

16. The method of claim 15, wherein the microcontroller real-time operating system is further configured to generate a fault diagnosis result for the fault location information and send the fault diagnosis result to the shared memory after sending a second interrupt signal to the second control system.

17. The method as recited in claim 16, further comprising:

and when the second control system receives the second interrupt signal, reading the fault diagnosis result from the shared memory, and generating log alarm information for the fault diagnosis result.

18. The fault location information generating device is applied to a baseboard management controller, the baseboard management controller is configured on a server, the baseboard management controller comprises a main processor and a coprocessor, the main processor and the coprocessor perform data interaction through a shared memory, and the fault location information generating device comprises:

The fault positioning information generation module is used for creating a fault positioning resolving task aiming at the fault signal through the microcontroller real-time operating system; unlocking the shared memory, and receiving the fault signal by the microcontroller real-time operating system through a data receiving task; and generating fault positioning information aiming at the server based on the fault signal by adopting the fault positioning resolving task through the microcontroller real-time operating system.

19. The server is characterized by being provided with a baseboard management controller, wherein the baseboard management controller comprises a main processor and a coprocessor, the main processor and the coprocessor perform data interaction through a shared memory, and the baseboard management controller is used for configuring a first control system for the coprocessor and configuring a second control system for the main processor; the first control system is a microcontroller real-time operating system; when a fault signal aiming at the server is obtained through the main processor, the fault signal is sent to the microcontroller real-time operating system through the second control system; creating a fault location calculation task aiming at the fault signal through the microcontroller real-time operation system; unlocking the shared memory, and receiving the fault signal by the microcontroller real-time operating system through a data receiving task; and generating fault positioning information aiming at the server based on the fault signal by adopting the fault positioning resolving task through the microcontroller real-time operating system.

20. An electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

The memory is used for storing a computer program;

The processor being configured to implement the method of any of claims 1-16 when executing a program stored on a memory.