CN117790424A

CN117790424A - Fan-out type packaging structure and preparation method thereof

Info

Publication number: CN117790424A
Application number: CN202410199735.5A
Authority: CN
Inventors: 简志宏; 徐玉鹏; 何正鸿
Original assignee: Yongsi Semiconductor Ningbo Co ltd
Current assignee: Yongsi Semiconductor Ningbo Co ltd
Priority date: 2024-02-23
Filing date: 2024-02-23
Publication date: 2024-03-29

Abstract

The invention provides a fan-out type packaging structure and a preparation method of the fan-out type packaging structure, relating to the technical field of semiconductor packaging, the fan-out type packaging structure comprises a fan-out wiring substrate layer, at least one first chip, at least one second chip, at least one pseudo-structure chip and a plastic package body, first chip, second chip and pseudo-structure chip's subsides are realized at first for first chip, second chip and pseudo-structure chip all paste the dress on fan-out wiring stratum basale, and first chip and second chip set up along first direction interval side by side, then utilize the plastic envelope body to realize cladding protection. Through setting up pseudo-structure chip, and pseudo-structure chip pastes along first direction and establish on fan-out wiring stratum basale, can play the effect of supporting fan-out wiring stratum basale on the one hand, promotes the structural strength of device, pressfitting fan-out wiring stratum basale in order to prevent to take place warpage, and on the other hand pseudo-structure chip can also dispel the heat to fan-out wiring stratum basale, promotes the heat dispersion of device.

Description

Fan-out type packaging structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a fan-out type packaging structure and a preparation method of the fan-out type packaging structure.

Background

In the prior art, BGA ball array package (Ball Grid Array Package) packages are widely used in the semiconductor industry. Generally, a BGA package structure is required to realize heat dissipation by mounting a heat dissipation cover, which requires the heat dissipation cover to satisfy heat dissipation, however, as the calculation force needs are improved, a plurality of chips are required to be integrated to improve the calculation force, and a conventional BGA package heat dissipation structure is mounted by flip chips and is limited by the area of the flip chips, so that the input/output bumps are limited.

Furthermore, the chip reconfiguration wiring and the addition of the input/output salient points are performed by adopting the fan-out type packaging technology, so that the chip performance is improved, however, the inventor researches that the chip area of the traditional single-chip fan-out type packaging structure is larger than the chip range, a certain bottom size space of a heat dissipation cover is required to be occupied, more fan-out type packaging products cannot be arranged, and the integration level is affected. In addition, the conventional multi-chip package structure is difficult to solve the problem of warpage and heat dissipation.

Disclosure of Invention

The invention aims at providing a fan-out type packaging structure and a preparation method of the fan-out type packaging structure, which can realize multi-chip fan-out packaging, improve the integration level of devices, effectively solve the problem of warpage of a wiring layer between chips and improve the heat dissipation performance.

Embodiments of the invention may be implemented as follows:

in a first aspect, the present invention provides a fan-out package structure, comprising:

a fan-out wiring base layer;

at least one first chip mounted on the fan-out wiring substrate layer;

at least one second chip, the second chip is attached to the fan-out wiring substrate layer and is arranged at intervals side by side with the first chip;

a dummy structure chip mounted on the fan-out wiring substrate layer, the dummy structure chip being disposed on the same side of the first chip and the second chip while being spaced apart from the first chip and the second chip;

the plastic package body is arranged on the fan-out wiring substrate layer and is coated outside the first chip, the second chip and the pseudo-structure chip;

wherein the first chip and the second chip are arranged on the fan-out wiring substrate layer along a first direction, the fan-out wiring substrate layer is electrically connected with the first chip and the second chip at the same time, the dummy structure chip is attached to the fan-out wiring substrate layer along the first direction, and is used for supporting the fan-out wiring substrate layer and radiating the fan-out wiring substrate layer.

In an alternative embodiment, two ends of the dummy structure chip are respectively flush with two opposite side edges of the first chip and the second chip.

In an alternative embodiment, the dummy structure chip is attached to one side of the fan-out wiring substrate layer and is further provided with an electrostatic pillar, and the electrostatic pillar extends to the fan-out wiring substrate layer to eliminate static electricity on the fan-out wiring substrate layer and conduct heat of the fan-out wiring substrate layer to the dummy structure chip.

In an optional embodiment, the fan-out package structure further includes a substrate and a heat dissipation cover, one side of the fan-out wiring substrate layer away from the plastic package body is disposed on the substrate, the middle part of the heat dissipation cover is attached to one side of the plastic package body away from the fan-out wiring substrate layer, and the edge of the heat dissipation cover is attached to the substrate.

In an optional embodiment, a heat dissipation glue layer is disposed on a side, away from the fan-out wiring substrate layer, of the plastic package body, and the heat dissipation cover is attached to the surface of the plastic package body through the heat dissipation glue layer.

In an alternative embodiment, the heights of the first chip and the second chip relative to the fan-out wiring substrate layer are smaller than or equal to the thickness of the plastic package body, so that the plastic package body covers or exposes the surfaces of the first chip and the second chip.

In an alternative embodiment, the plastic package body is completely attached to the heat dissipation cover, the first chip, the second chip and the dummy structure chip are all disposed in a chip area of the fan-out wiring substrate layer, edges of the first chip, the second chip and the dummy structure chip overlap with edges of the chip area, and an area Sb of the chip area is 4/5-1 of a top area Sc of the plastic package body.

In an alternative embodiment, the side wall of the plastic package body is flush with the side wall of the fan-out wiring substrate layer, and the distance between the edge of the chip area and the side wall of the plastic package body is more than 10 μm.

In an alternative embodiment of the present invention, the substrate is also provided with a passive component, the heat dissipation cover is arranged outside the passive component.

In a second aspect, the present invention provides a method for preparing a fan-out package structure, for preparing a fan-out package structure according to any one of the foregoing embodiments, where the preparation method includes:

attaching at least one first chip, at least one second chip and at least one pseudo-structure chip to the carrier along the reconstructed wafer area;

plastic packaging is carried out on the carrier to form a plastic packaging body, and the plastic packaging body is coated outside the first chip, the second chip and the pseudo-structure chip;

forming a fan-out wiring substrate layer on the surface of the plastic package body, wherein a plurality of chip areas are formed in the fan-out wiring substrate layer, and the edges of the first chip, the second chip and the pseudo-structure chip are overlapped with the edges of the chip areas;

and cutting the fan-out wiring substrate layer and the plastic package body along the cutting path to form the chip module.

In an alternative embodiment, the fan-out wiring substrate layer includes a plurality of fan-out areas that are bonded to each other, the chip area is located in the fan-out area, the dicing street is located in the fan-out area and is spaced apart from the chip area, and the dicing street encloses to form a wiring area, and an edge of the wiring area is located between an edge of the chip area and an edge of the fan-out area.

In an alternative embodiment, the area Sa of the fan-out area is 5/4 to 5 times the area Sb of the chip area.

In an alternative embodiment, the area Sb of the chip region is 4/5-1 times the area Sc of the wiring region.

In an alternative embodiment, the distance between the edge of the chip region and the edge of the wiring region is above 10 μm.

In an alternative embodiment, two dicing lanes are provided between two adjacent wiring areas.

In an alternative embodiment, after the step of attaching the first chip, the second chip and the dummy structure chip to the carrier along the reconstituted wafer area, the method further includes:

and attaching stress pseudo chips to the edge of the reconstructed wafer area.

In an alternative embodiment, after the step of cutting the fan-out wiring substrate layer and the plastic package along the dicing streets, the manufacturing method further includes:

mounting the chip module on a substrate, wherein one side of the fan-out wiring basal layer far away from the plastic package body is arranged on the substrate;

and a heat dissipation cover is attached to one side of the plastic package body, which is far away from the fan-out wiring substrate layer, and the edge of the heat dissipation cover is attached to the substrate.

In an alternative embodiment, before the step of cutting the fan-out wiring substrate layer and the plastic package along the dicing streets, the manufacturing method further includes:

grinding the plastic package body to expose the surfaces of the first chip, the second chip and the pseudo-structure chip;

and stripping the carrier.

The beneficial effects of the embodiment of the invention include, for example:

according to the fan-out type packaging structure and the preparation method thereof, firstly, the fan-out technology is utilized to realize the mounting of the first chip, the second chip and the pseudo-structure chip, so that the first chip, the second chip and the pseudo-structure chip are all mounted on the fan-out wiring substrate layer, the first chip and the second chip are arranged at intervals side by side along the first direction, the pseudo-structure chip is located on the same side of the first chip and the second chip and is spaced from the first chip and the second chip at the same time, and then the plastic package body is utilized to realize cladding protection. Through setting up pseudo-structure chip, and pseudo-structure chip pastes along first direction and establish on the fan-out wiring stratum basale, can play the effect of supporting the fan-out wiring stratum basale on the one hand, promotes the structural strength of device, pressfitting fan-out wiring stratum basale takes place the warpage with the fan-out wiring stratum basale that prevents first chip and second chip below, and on the other hand pseudo-structure chip can also dispel the heat to the fan-out wiring stratum basale, promotes the heat dispersion of device.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a multi-chip fan-out package structure provided in the prior art;

fig. 2 is a schematic diagram of a first cross-sectional structure of a fan-out package structure according to an embodiment of the present invention;

fig. 3 is a top view of a fan-out package structure according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a second cross-sectional structure of a fan-out package according to an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a fan-out package according to another preferred embodiment of the present invention;

fig. 6 to fig. 12 are process flow diagrams of a method for manufacturing a fan-out package structure according to an embodiment of the present invention.

Icon: 100-fan-out package structure; 110-a fan-out wiring substrate layer; 120-a first chip; 130-a second chip; 140-pseudo-structure chip; 141-electrostatic column; 150-plastic package body; 151-a heat radiation adhesive layer; 160-a substrate; 161-dispensing an adhesive layer; 163-passive components; 170-a heat sink cap; 180-reconstructing the wafer area; 181-stress pseudochips; 200-carrier; 210-dicing streets; 230-positioning the wiring layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.

As disclosed in the background art, the existing fan-out package device adopts a single chip structure when heat dissipation is required by using a heat dissipation cover, that is, a fan-out area is arranged below a single chip, and wires are arranged in the fan-out area, however, the following defects exist in this way (see fig. 1):

first, due to the structural specificity of the wiring, the wiring area is large, resulting in a large overall fan-out structure size. If the quantity of chips below the heat dissipation cover is required to be improved, a plurality of single-chip fan-out structures can be stacked at intervals in parallel, the size of the heat dissipation cover is definitely increased, the occupied area of the whole flip structure is larger, and the improvement of the integration level of devices is not facilitated.

Second, conventional chip fan-out designs require more fan-out area for a single chip, while when they employ multiple chip designs, the heat sink covers require larger size designs. And when designing the heat dissipation glue film, the heat dissipation glue film covers the back of the chip, has the clearance between the adjacent chips, and the heat dissipation area that leads to the contact is less.

Third, conventional heat spreader layers have indium fins adhered to the back side thereof, however, when an indium material is used as the heat spreader, it is necessary to perform reflow soldering, and thus, it is necessary to use a flux. However, since the soldering flux has volatility and the melting point of the indium heat sink is low, the soldering flux can continuously release gas in the process of reflow, and the gas volatilized by the soldering flux can squeeze the melted heat sink, so that the formed mixture overflows to gaps between adjacent chip structures, and the chip structures are affected. Meanwhile, too much mixture overflows, so that a large number of holes are formed between the chip and the heat dissipation cover, and the heat dissipation performance of the product is affected. And the mixture overflows between the welding structures of the components and the components, which is easy to cause the electrical failure of the components.

Fourth, in the existing multi-chip package structure, only a plurality of chips are packaged together after being spaced, so that the problems of warping and heat dissipation caused by the dielectric material after the wafer is reconstructed are difficult to solve. And because the wafer is warped, after the fan-out structure is integrated by a plurality of chips to be used for ball implantation, the power supply performance of the solder balls can be influenced. In addition, in the conventional fan-out type packaging structure, when the reconstituted wafer is cut, the layout of the cutting lines is improper, and single cutting is adopted, so that the edge wiring layer and the dielectric layer are easily pulled and layered, and the performance of the chip is influenced.

In order to solve the above-mentioned problems, the embodiments of the present invention provide a novel fan-out package structure and a method for manufacturing the same, and it should be noted that features in the embodiments of the present invention may be combined with each other without collision.

Referring to fig. 2 and 3, the present embodiment provides a fan-out package structure 100, which can realize multi-chip fan-out package, improve the integration level of devices, effectively solve the warpage problem of the wiring layer between chips, and improve the heat dissipation performance.

The fan-out package structure 100 provided by the embodiment of the invention comprises a fan-out wiring substrate layer 110, at least one first chip 120, at least one second chip 130, at least one dummy structure chip 140 and a plastic package body 150, wherein the first chip 120 is attached to the fan-out wiring substrate layer 110; the second chip 130 is mounted on the fan-out wiring substrate layer 110 and is arranged side by side with the first chip 120 at intervals; the dummy structure chip 140 is mounted on the fan-out wiring base layer 110, and the dummy structure chip 140 is disposed on the same side of the first chip 120 and the second chip 130 while being spaced apart from the first chip 120 and the second chip 130; the plastic package body 150 is disposed on the fan-out wiring substrate layer 110 and is coated outside the first chip 120, the second chip 130 and the dummy structure chip 140; the first chip 120 and the second chip 130 are arranged on the fan-out wiring substrate layer 110 along the first direction, the fan-out wiring substrate layer 110 is electrically connected with the first chip 120 and the second chip 130 at the same time, the dummy structure chip 140 is attached to the fan-out wiring substrate layer 110 along the first direction, and the dummy structure chip 140 is used for supporting the fan-out wiring substrate layer 110 and dissipating heat from the fan-out wiring substrate layer 110.

In this embodiment, the fan-out wiring substrate layer 110 includes a plurality of dielectric layers and a plurality of wiring layers, and solder balls are further formed on a side of the fan-out wiring substrate layer 110 away from the plastic package body 150, and electrical connection is achieved with the outside through the solder balls. The basic structure and process steps of the fan-out wiring substrate layer 110 may refer to the existing fan-out packaging process.

It should be noted that, in the present embodiment, the first chip 120, the second chip 130 and the dummy structure chip 140 may be one or more, and when the first chip 120 and the second chip 130 are plural, the plural first chips 120 may be disposed on two sides of the dummy structure chip 140, and the plural second chips 130 may be disposed on two sides of the dummy structure chip 140. In this embodiment, the first chip 120, the second chip 130 and the dummy structure chip 140 are all described as single, wherein the chip types of the first chip 120 and the second chip 130 may be the same or different.

In this embodiment, the fan-out process is first utilized to implement the mounting of the first chip 120, the second chip 130 and the dummy structure chip 140, so that the first chip 120, the second chip 130 and the dummy structure chip 140 are all mounted on the fan-out wiring substrate layer 110, wherein the first chip 120 and the second chip 130 are arranged at intervals side by side along the first direction, the dummy structure chip 140 is located on the same side of the first chip 120 and the second chip 130 and is spaced apart from the first chip 120 and the second chip 130 at the same time, and then the plastic package 150 is utilized to implement the cladding protection. Through setting up pseudo-structure chip 140, and pseudo-structure chip 140 pastes along first direction and establish on fan-out wiring stratum basale 110, can play the effect of supporting fan-out wiring stratum basale 110 on the one hand, promotes the structural strength of device, pressfitting fan-out wiring stratum basale 110 takes place the warpage with the fan-out wiring stratum basale 110 that prevents first chip 120 and second chip 130 below, has also guaranteed the power supply performance of solder ball after the follow-up ball of planting simultaneously. On the other hand, the dummy structure chip 140 can also radiate heat to the fan-out wiring substrate layer 110, so as to improve the heat radiation performance of the device.

It should be noted that, in the first direction in this embodiment, the direction of the central line between the center of the first chip 120 and the center of the second chip 130 can be represented by the first direction, which can represent the arrangement direction of the first chip 120 and the second chip 130, and can represent the long-side direction of the dummy structure chip 140, by arranging the dummy structure chip 140 along the first direction, the fan-out type wiring base layer and the plastic package 150 can be prevented from being warped in the first direction, so that the structures of the first chip 120 and the second chip 130 are prevented from being affected.

It should be noted that, since the first chip 120 and the second chip 130 are both subjected to the plastic packaging process, the gap between the first chip 120 and the second chip 130 is more than 3 times of the diameter of the filling particles of the plastic packaging material, so as to ensure a good plastic packaging effect.

In this embodiment, two ends of the dummy structure chip 140 are flush with two opposite side edges of the first chip 120 and the second chip 130, respectively. Specifically, the width of the dummy structure chip 140 in the first direction is equal to the sum of the widths of the first chip 120, the second chip 130, and the gap therebetween in the first direction, and an effective wiring area can be defined by the width of the dummy structure chip 140 in the first direction, that is, an effective area where fan-out is required can be constructed by the first chip 120, the second chip 130, and the dummy structure chip 140, and wafer structural stress is balanced by the area. Of course, in other preferred embodiments, the width of the dummy structure chip 140 in the first direction may be greater than the sum of the widths of the first chip 120, the second chip 130, and the gap therebetween in the first direction, thereby making the dummy structure chip 140 wider and covering more chip area.

In the present embodiment, the dummy structure chip 140 is added to increase the wiring range, and since the dummy structure chip 140 itself does not have an electrical function, the area below the dummy structure chip can be used as the wiring area, and thus the area of the chip where the wiring layer is provided can be made wider.

In some embodiments, the dummy structure chip 140 is further provided with an electrostatic pillar 141 attached to one side of the fan-out wiring substrate layer 110, and the electrostatic pillar 141 extends to the fan-out wiring substrate layer 110 to eliminate static electricity on the fan-out wiring substrate layer 110. In particular, the method comprises the steps of, the dummy structure chip 140 is a dummy chip without electrical functions, the material is silicon, and can be formed after an oxide layer is manufactured on the silicon material. The electrostatic pillars 141 may be copper pillars that can be directly formed on the oxide layer by electroplating, and can be in contact with pads on the fan-out wiring substrate layer 110, so that static electricity on the fan-out wiring substrate layer 110 can be guided to the dummy structure chip 140, and electrostatic discharge is achieved to eliminate static electricity. Meanwhile, through the electrostatic pillars 141, parasitic inductance in the wiring layer can be connected to the dummy structure chip 140.

In other preferred embodiments of the present invention, it is also unnecessary to provide the electrostatic pillars 141 on the dummy structure chip 140, while directly contacting the dummy structure die 140 with pads on the fan-out wiring substrate layer 110, it also enables static elimination.

In the present embodiment, the electrostatic pillars 141 can also function as heat-dissipating pillars that are connected to the dummy structure chips 140 to achieve heat transfer. By providing the heat dissipation columns, heat generated in the fan-out wiring substrate layer 110 can be conducted to the dummy structure chip 140 to dissipate heat, and heat dissipation efficiency is further improved.

Referring to fig. 4 and 5, in some embodiments, the fan-out package structure 100 further includes a substrate 160 and a heat dissipation cover 170, wherein a side of the fan-out wiring substrate layer 110 away from the plastic package body 150 is disposed on the substrate 160, a middle portion of the heat dissipation cover 170 is attached to a side of the plastic package body 150 away from the fan-out wiring substrate layer 110, and an edge of the heat dissipation cover 170 is attached to the substrate 160. Specifically, the heat dissipation cover 170 may be a metal cover, which is attached to the plastic package body 150, so that heat can be transferred to the outside, and the heat dissipation effect is improved by transferring the heat of the first chip 120, the second chip 130 and the dummy structure chip 140.

It should be noted that, the fan-out wiring base layer 110, the first chip 120, the second chip 130, the dummy structure chip 140 and the plastic package body 150 form a chip module, the chip module is separately prepared, then the chip module can be attached to the substrate 160, specifically, the solder balls at the bottom side of the fan-out wiring base layer 110 and the bonding pads on the substrate 160 can be correspondingly welded, thereby fixing the chip module, and then the heat dissipation cover 170 is attached after dispensing and fixing.

It should be noted that the size of the heat dissipation cover 170 in this embodiment is larger than the size of the chip module, i.e. larger than the top area of the plastic package body 150, so as to ensure that the package is placed in the reconstructed package size. Specifically, the side length of the heat dissipating cover 170 is between 17-30.05mm, i.e. the size is between 17mm to 30.5mm, and preferably the size of the heat dissipating cover 170 is around 24.8 mm. The peripheral dimension of the entire package structure, i.e., the fan-out package structure 100, may be greater than the dimension of the heat dissipation cover 170, and the peripheral width of the fan-out package structure 100 may be between 20mm x 20mm and 35mm x 35mm, i.e., the peripheral dimension of the fan-out package structure 100 is between 20mm x 25mm. In this embodiment, a glue dispensing layer 161 is disposed around the chip module, and the glue dispensing layer 161 can adhesively fix the chip module on the substrate 160 and protect the bottom soldering structure.

In this embodiment, the heights of the first chip 120 and the second chip 130 with respect to the fan-out wiring substrate layer 110 are less than or equal to the thickness of the plastic package body 150, so that the plastic package body 150 covers or exposes the surfaces of the first chip 120 and the second chip 130. In some embodiments, as shown in fig. 3, the first chip 120 and the second chip 130 are completely encapsulated in the plastic package body 150, and at this time, the heights of the first chip 120 and the second chip 130 relative to the fan-out wiring substrate layer 110 are smaller than the thickness of the plastic package body 150, so that the plastic package body 150 can be utilized to better protect the first chip 120 and the second chip 130.

In other preferred embodiments of the present invention, referring to fig. 4, the plastic package 150 exposes the surfaces of the first chip 120 and the second chip 130, and in particular, the back surfaces of the first chip 120 and the second chip 130 may be exposed by grinding the plastic package 150, where the heights of the first chip 120 and the second chip 130 with respect to the fan-out wiring substrate layer 110 are equal to the thickness of the plastic package 150. When the heat dissipation cover 170 is attached, the heat dissipation cover 170 can be attached to the back of the plastic package body 150 and the back of the chip, so that the heat conduction effect is further improved, and the heat dissipation effect is further improved.

In this embodiment, a heat dissipation glue layer 151 is disposed on a side of the plastic package body 150 away from the fan-out wiring substrate layer 110, and a heat dissipation cover 170 is attached to the surface of the plastic package body 150 through the heat dissipation glue layer 151. Specifically, after the inner side surface of the heat dissipation cover 170 is coated with the heat dissipation adhesive layer 151, the heat dissipation adhesive layer 151 can be directly attached to the surface of the plastic package body 150, and the heat dissipation adhesive layer 151 can perform the functions of heat conduction and adhesion fixation, so as to ensure that the heat dissipation cover 170 is stably adhered. In addition, in the embodiment, the heat dissipation adhesive layer 151 is disposed on the surface of the entire plastic package body 150, so that the plastic package body 150 can completely encapsulate the first chip 120 and the second chip 130, and the problem caused by the mixture overflowing between adjacent chips in the conventional technology can be avoided.

In the present embodiment, the edge of the heat dissipating cover 170 is bent toward the substrate 160 and then attached to the substrate 160, and the heat dissipating cover may be bonded and fixed by the heat dissipating adhesive layer 151.

In the embodiment, the plastic package body 150 is completely attached to the heat dissipation cover 170, the first chip 120, the second chip 130 and the dummy structure chip 140 are all disposed in the chip area of the fan-out wiring substrate layer 110, and the edges of the first chip 120, the second chip 130 and the dummy structure chip 140 overlap with the edges of the chip area, and the area Sb of the chip area is 4/5-1 of the top area Sc of the plastic package body 150. Specifically, the dimension of the top surface of the plastic package body 150, that is, the dimension of the dicing area after the wafer is reconstituted, that is, the dimension of the wiring area, and the chip area is determined by the first chip 120, the second chip 130 and the dummy structure chip 140, and the layout of the wiring layer is in the wiring area, so that the area of the wiring area is smaller than that of the prior art, the wiring area can not be diced during dicing, and the device performance is ensured.

In this embodiment, the side wall of the plastic package body 150 is flush with the side wall of the fan-out wiring substrate layer 110, the distance between the edge of the chip area and the side wall of the plastic package body 150 is more than 10 μm, and part of the wiring layer extends to the area. Specifically, the chip area and the wiring area characterized by the top surface of the plastic package 150 are divided in position, and a gap of 40 μm is preferably left between the edges of the two.

In this embodiment, the substrate 160 is further provided with a passive component 163, and the heat dissipation cover 170 is covered outside the passive component 163. Specifically, the passive component 163 may be a capacitor, an inductor, or the like, and the passive component 163 is packaged on the surface of the substrate 160 by a ferrite box, so that the integration level of the whole device can be further improved, and more functions can be integrated.

The embodiment of the invention also provides a preparation method of the fan-out type packaging structure 100, which is used for preparing the fan-out type packaging structure 100, and the preparation method comprises the following steps:

s1: the first chip 120, the second chip 130, and the dummy structure chip 140 are attached to the carrier 200 along the reconstituted wafer area 180.

Referring to fig. 6, specifically, the first chip 120 and the second chip 130 are mounted on the carrier 200 with the pads facing downward, and in actual mounting of the chips, a UV adhesive layer may be coated on the surface of the carrier 200, and then the first chip 120, the second chip 130, and the dummy structure chip 140 may be mounted at predetermined positions. The carrier 200 may be glass, silicon oxide, metal, or the like.

Of course, in other embodiments, the pads of the first chip 120 and the second chip 130 may be attached to the carrier 200 upwards, so that the subsequent growth of the metal pillars on the pads and the electrostatic pillars 141 is facilitated.

In some embodiments, referring to fig. 7, after the steps of attaching the first chip 120, the second chip 130, and the dummy structure chip 140 to the carrier 200 along the reconstituted wafer area 180, the method further includes: a stress pseudodie 181 is attached to the edge of the reconstituted wafer area 180. Specifically, before plastic packaging, a plurality of stress pseudodie 181 are further provided in advance at the edge of the reconstituted wafer area 180, and the stress pseudodie 181 has no electrical performance and can play a role in reducing the stress of the wafer at the edge of the reconstituted wafer. And, the stress pseudochip 181 is 20% -80% of the size of the fan-out area.

In other preferred embodiments, referring to fig. 8, a rectangular wafer area may be formed on a panel (panel), that is, a panel-level package structure is completed, a rectangular reconstituted wafer area 180 is formed, and a stress pseudochip 181 is attached at the edge. The size of the panel (panel) may be 3000mm or more.

S2: the carrier 200 is molded to form the molded body 150.

Specifically, referring to fig. 9, the plastic package 150 is coated outside the first chip 120, the second chip 130 and the dummy structure chip 140. Referring to fig. 10, after forming the plastic package body 150, in other preferred embodiments, the plastic package body 150 may be polished to expose the surfaces of the first chip 120, the second chip 130 and the dummy structure chip 140, and specifically, the plastic package body 150 may be surface polished by using a polishing wheel.

After the molding is completed, the carrier 200 may be peeled off.

S3: a fan-out wiring base layer 110 is formed on the surface of the molding body 150.

Specifically, referring to fig. 11 and 12, a plurality of chip areas are formed in the fan-out wiring base layer 110, and edges of the first chip 120, the second chip 130, and the dummy structure chip 140 overlap with edges of the chip areas. Wherein the fan-out wiring base layer 110 is disposed at the pad sides of the first chip 120 and the second chip 130.

In actual wiring, a dielectric layer may be formed on the surface of the plastic package body 150 by a spin coating process, wherein the dielectric material may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like, then a photomask is covered on the dielectric layer, a pattern layer opening is formed by an exposure and development process, and then the electrostatic column 141 is formed by an electroplating process. The spin coating, exposure developing and electroplating processes are then repeated to form a fan-out wiring substrate layer 110 having a plurality of dielectric layers and a plurality of wiring layers, and finally solder balls are formed on the fan-out wiring substrate layer 110.

In the wiring, wiring is performed in accordance with a predetermined wiring region, that is, in the case where a plurality of wiring layers are formed in the fan-out wiring base layer 110, the wiring is performed in the wiring region. The adverse effect on the subsequent cutting process caused by wiring outside the chip area can be avoided.

The fan-out wiring substrate layer 110 includes a plurality of fan-out areas a bonded to each other, a chip area B is located in the fan-out area, the dicing street 210 is located in the fan-out area and spaced apart from the chip area, and the dicing street 210 encloses a wiring area C, and an edge of the wiring area is located between an edge of the chip area and an edge of the fan-out area.

It should be noted that after the preparation of the fan-out wiring substrate layer 110 is completed, the preparation of the reconstituted wafer is completed, and the reconstituted wafer is divided into a plurality of fan-out areas at this time, meanwhile, a plurality of stress dummy chips 181 are further provided in advance in the edge area of the reconstituted wafer, and the stress dummy chips 181 have no electrical performance, and can play a role in reducing the stress of the wafer at the edge of the reconstituted wafer. And, the stress pseudochip 181 is 20% -80% of the size of the fan-out area.

Preferably, the area Sa of the fan-out area a is 5/4-5 times the area Sb of the chip area B, that is, the balance of the chip area can be improved, the structural stress of the wafer can be balanced, and the warpage can be reduced. And the area Sb of the chip area is 4/5-1 times the area Sc of the wiring area C, which is defined by the dicing streets 210, and the size of which can be defined according to the mounting size of the heat dissipation cover 170. After the actual dicing, the size of the routing area is the same as the top side of the plastic package 150, i.e., the size of the chip module is characterized.

Further, in the present embodiment, the distance between the edge of the chip region and the edge of the wiring region is 10 μm or more. Preferably, a space of 40 μm may be provided between the edge of the chip region and the edge of the wiring region.

It should be noted that, when the fan-out wiring substrate layer 110 is formed by the wiring, a positioning line may be additionally disposed in the fan-out area, and the positioning line may be independent from the wiring layer and exposed on the surface of the fan-out wiring substrate layer 110, so that the positioning line is conveniently used for positioning during the subsequent cutting. For example, a positioning circuit layer 230 may be added outside the wiring area, and precise positioning of the dicing street 210 can be achieved by using the positioning circuit layer 230.

S5: the fan-out wiring substrate layer 110 and the molding body 150 are cut along the dicing streets 210 to form a chip module.

Specifically, with continued reference to fig. 12, 1 and 2, two dicing streets 210 are provided between adjacent two wiring regions. That is, the secondary cutting mode can be adopted to cut along the wiring area, so that the size of the cutting channel 210 can be reduced, the oversized cutting channel 210 is avoided, mechanical stress generated by primary cutting can be avoided, the wiring layer and the dielectric layer at the edge are prevented from being pulled and layered, and the device performance is ensured. Of course, in other preferred embodiments of the present invention, a single dicing street 210 may be used to effect dicing, which is not specifically described herein.

In summary, in the fan-out package structure 100 and the method for manufacturing the same provided in the present embodiment, firstly, the fan-out process is utilized to mount the first chip 120, the second chip 130 and the dummy structure chip 140, so that the first chip 120, the second chip 130 and the dummy structure chip 140 are all mounted on the fan-out wiring substrate layer 110, wherein the first chip 120 and the second chip 130 are arranged at intervals side by side along the first direction, and the dummy structure chip 140 is located at the same side of the first chip 120 and the second chip 130 and is spaced apart from the first chip 120 and the second chip 130 at the same time, and then the plastic package body 150 is utilized to realize the cladding protection. Through setting up pseudo-structure chip 140, and pseudo-structure chip 140 pastes along the first direction and establish on fan-out wiring stratum basale 110, can play the effect of supporting fan-out wiring stratum basale 110 on the one hand, promotes the structural strength of device, pressfitting fan-out wiring stratum basale 110 takes place the warpage with the fan-out wiring stratum basale 110 that prevents first chip 120 and second chip 130 below, and on the other hand pseudo-structure chip 140 can also dispel the heat to fan-out wiring stratum basale 110, promotes the heat dispersion of device.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A fan-out package structure, comprising:

a fan-out wiring base layer;

at least one first chip mounted on the fan-out wiring substrate layer;

at least one dummy structure chip mounted on the fan-out wiring substrate layer, the dummy structure chip being disposed on the same side of the first chip and the second chip while being spaced apart from the first chip and the second chip;

the first chip and the second chip are arranged on the fan-out wiring substrate layer along a first direction, the fan-out wiring substrate layer is electrically connected with the first chip and the second chip at the same time, the pseudo-structure chip is attached to the fan-out wiring substrate layer along the first direction, and the pseudo-structure chip is used for supporting the fan-out wiring substrate layer and radiating the fan-out wiring substrate layer.

2. The fan-out package structure of claim 1, wherein two ends of the dummy structure chip are flush with two opposite side edges of the first chip and the second chip, respectively.

3. The fan-out package structure of claim 1, wherein the dummy structure die is attached to one side of the fan-out wiring substrate layer and is further provided with an electrostatic post extending to the fan-out wiring substrate layer to dissipate static electricity on the fan-out wiring substrate layer and conduct heat of the fan-out wiring substrate layer to the dummy structure die.

4. The fan-out package structure of claim 1, further comprising a substrate and a heat-dissipating cover, wherein a side of the fan-out wiring substrate layer away from the plastic package body is disposed on the substrate, a middle portion of the heat-dissipating cover is attached to a side of the plastic package body away from the fan-out wiring substrate layer, and an edge of the heat-dissipating cover is attached to the substrate.

5. The fan-out package structure of claim 4, wherein a heat dissipation glue layer is disposed on a side of the plastic package body away from the fan-out wiring substrate layer, and the heat dissipation cover is attached to the surface of the plastic package body through the heat dissipation glue layer.

6. The fan-out package structure of claim 4, wherein the first and second chips have a height relative to the fan-out routing substrate layer that is less than or equal to a thickness of the plastic package body such that the plastic package body encapsulates or exposes surfaces of the first and second chips.

7. The fan-out package structure of claim 4, wherein the plastic package body is completely attached to the heat dissipation cover, the first chip, the second chip and the dummy structure chip are all disposed in a chip area of the fan-out wiring substrate layer, edges of the first chip, the second chip and the dummy structure chip overlap with edges of the chip area, and an area Sb of the chip area is 4/5-1 of a top area Sc of the plastic package body.

8. The fan-out package structure of claim 7, wherein the sidewalls of the plastic package body are flush with the sidewalls of the fan-out wiring substrate layer, and a distance between the edge of the chip area and the sidewalls of the plastic package body is above 10 μιη.

9. The fan-out package structure of claim 4, wherein the substrate is further provided with a passive component, and the heat dissipation cover is disposed outside the passive component.

10. A method for preparing the fan-out package structure according to any one of claims 1 to 9, wherein the preparing method comprises:

attaching a first chip, a second chip and a pseudo-structure chip on a carrier along the reconstructed wafer area;

and cutting the fan-out wiring substrate layer and the plastic package body along the cutting path to form a single chip module.

11. The method of manufacturing a fan-out package structure according to claim 10, wherein the fan-out wiring substrate layer includes a plurality of fan-out areas bonded to each other, the chip area is located in the fan-out area, the dicing street is located in the fan-out area and is spaced apart from the chip area, and the dicing street encloses a wiring area, and an edge of the wiring area is located between an edge of the chip area and an edge of the fan-out area.

12. The method for manufacturing a fan-out package structure according to claim 11, wherein the area Sa of the fan-out area is 5/4-5 times the area Sb of the chip area.

13. The method of fabricating a fan-out package structure of claim 11, wherein the area Sb of the chip region is 4/5-1 times the area Sc of the routing region.

14. The method of manufacturing a fan-out package according to claim 11, wherein two dicing streets are provided between two adjacent wiring regions.

15. The method of manufacturing a fan-out package structure of claim 10, wherein after the step of attaching the first chip, the second chip, and the dummy structure chip to the carrier along the reconstituted wafer area, the method further comprises:

and attaching stress pseudo chips to the edge of the reconstructed wafer area.

16. The method of manufacturing a fan-out package structure of claim 10, further comprising, after the step of cutting the fan-out wiring substrate layer and the plastic package body along dicing streets:

17. The method of manufacturing a fan-out package structure of claim 10, wherein prior to the step of cutting the fan-out wiring substrate layer and the plastic package along dicing streets, the method further comprises:

and stripping the carrier.