CN117767918A - Trigger circuit and electronic device - Google Patents

Trigger circuit and electronic device Download PDF

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Publication number
CN117767918A
CN117767918A CN202211139843.0A CN202211139843A CN117767918A CN 117767918 A CN117767918 A CN 117767918A CN 202211139843 A CN202211139843 A CN 202211139843A CN 117767918 A CN117767918 A CN 117767918A
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China
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type transistor
node
circuit
signal
inverter
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CN202211139843.0A
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Chinese (zh)
Inventor
周润发
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211139843.0A priority Critical patent/CN117767918A/en
Priority to PCT/CN2023/070546 priority patent/WO2024060469A1/en
Publication of CN117767918A publication Critical patent/CN117767918A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

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  • Logic Circuits (AREA)

Abstract

The present disclosure provides a flip-flop circuit and an electronic device. The trigger circuit comprises a plurality of signal inversion elements, wherein the substrate of the P-type transistor of each signal inversion element is correspondingly connected with a bias voltage providing circuit, the bias voltage providing circuit is used for responding to the input end signal of the corresponding signal inversion element, providing a first substrate bias voltage for the P-type transistor when the P-type transistor in the signal inversion element is conducted, providing a second substrate bias voltage for the P-type transistor when the P-type transistor in the signal inversion element is not conducted, and the first substrate bias voltage is smaller than the second substrate bias voltage and larger than PN junction conducting voltage, and the signal inversion element is used for inverting the input end signal. The embodiment of the disclosure can repair signal timing deviation caused by element aging.

Description

Trigger circuit and electronic device
Technical Field
The disclosure relates to the technical field of integrated circuits, and in particular relates to a trigger circuit capable of correcting a signal duty cycle deviation problem and electronic equipment using the same.
Background
NBTI (Negative Bias Temperature Instability ) is a major reliability problem faced by current and future processes.
NBTI mainly refers to instability caused by drift of device parameters (such as on voltage Vt, transconductance Gm, drain current Id) and the like along with time when the PMOS is in an inversion working state, and is mainly caused by degradation of the PMOS in a static stress process. After the PMOS is subjected to long-time stress, if an effective recovery time is not obtained, signal waveform deformity (including duty cycle variation) and timing drift in the logic circuit are caused, and even potential circuit failure is caused.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a flip-flop circuit and an electronic device for overcoming the problem that PMOS causes a change in the waveform of an output signal after long-term use at least to some extent.
According to a first aspect of the present disclosure, there is provided a flip-flop circuit, including a plurality of signal inverting elements, wherein a substrate of a P-type transistor of each of the signal inverting elements is correspondingly connected to a bias supply circuit, the bias supply circuit is configured to supply a first substrate bias to the P-type transistor when the P-type transistor in the signal inverting element is turned on, and to supply a second substrate bias to the P-type transistor when the P-type transistor in the signal inverting element is turned off, the first substrate bias being smaller than the second substrate bias and greater than a PN junction turn-on voltage, and the signal inverting element is configured to invert an input signal.
In one exemplary embodiment of the disclosed embodiments, each of the bias supply circuits includes: the first switch element is connected with the first substrate bias voltage at a first end, connected with the substrate of the P-type transistor in the signal inversion element corresponding to the bias voltage providing circuit at a second end, and connected with the grid electrode of the P-type transistor of the signal inversion element corresponding to the bias voltage providing circuit at a control end; and the first end of the second switching element is connected with the second substrate bias voltage, the second end of the second switching element is connected with the second end of the first switching element, and the control end of the second switching element is connected with the drain electrode of the P-type transistor of the signal inversion element corresponding to the bias voltage providing circuit.
In one exemplary embodiment of the disclosed embodiments, the flip-flop circuit includes: the input end of the first inverter is the input end of the trigger circuit, the output end of the first inverter is connected with a first node, the substrate of the P-type transistor in the first inverter is connected with a first bias voltage providing circuit, and the first inverter is one of the plurality of signal inverting elements; the first transmission gate, the first control end connects the clock signal, the second control end connects the complementary clock signal, the input end connects the said first node, the output end connects the second node; the input end of the second inverter is connected with the second node, the output end of the second inverter is connected with the third node, the substrate of the P-type transistor in the second inverter is connected with a second bias voltage providing circuit, and the second inverter is one of the plurality of signal inverting elements; the first control end of the second transmission gate is connected with the complementary clock signal, the second control end of the second transmission gate is connected with the clock signal, the input end of the second transmission gate is connected with the third node, and the output end of the second transmission gate is connected with the fourth node; the input end of the third inverter is connected with the fourth node, the output end of the third inverter is connected with the fifth node, the substrate of the P-type transistor in the third inverter is connected with a third bias voltage providing circuit, and the third inverter is one of the plurality of signal inverting elements; the input end of the fourth inverter is connected with the fifth node, the output end of the fourth inverter is a first output end of the trigger circuit, the substrate of the P-type transistor in the fourth inverter is connected with a fourth bias voltage providing circuit, and the fourth inverter is one of the plurality of signal inverting elements; and the input end of the fifth inverter is connected with the output end of the fourth inverter, the output end is the second output end of the trigger circuit, the substrate of the P-type transistor in the fifth inverter is connected with the third bias voltage providing circuit, and the fifth inverter is one of the signal inverting elements.
In one exemplary embodiment of the present disclosure, further comprising: and the first feedback circuit is connected with the third node at the input end, connected with the second node at the output end and used for inverting the potential of the third node according to the clock signal and the complementary clock signal and feeding back the potential to the second node, and comprises an odd number of signal inverting elements.
In one exemplary embodiment of the disclosed embodiments, the first feedback circuit includes: the source electrode of the first P-type transistor is connected with the power supply voltage, and the grid electrode of the first P-type transistor is connected with the third node; a source electrode of the second P-type transistor is connected with a drain electrode of the first P-type transistor, a grid electrode of the second P-type transistor is connected with the clock signal, and a drain electrode of the second P-type transistor is connected with the second node; the source electrode of the first N-type transistor is grounded, and the grid electrode of the first N-type transistor is connected with the third node; and the source electrode of the second N-type transistor is connected with the drain electrode of the first N-type transistor, the grid electrode of the second N-type transistor is connected with the complementary clock signal, and the drain electrode of the second N-type transistor is connected with the second node.
In an exemplary embodiment of the disclosed embodiments, the substrates of the first and second P-type transistors are each connected to a fifth bias supply circuit.
In an exemplary embodiment of the disclosed embodiments, the first feedback circuit includes an odd number of inverters and a first feedback transmission gate connected in series, and two control terminals of the first feedback transmission gate are respectively connected to the clock signal and the complementary clock signal.
In one exemplary embodiment of the present disclosure, further comprising: and the input end of the second feedback circuit is connected with the fifth node, the output end of the second feedback circuit is connected with the fourth node and is used for inverting the potential of the fifth node according to the clock signal and the complementary clock signal and feeding back the potential of the fifth node to the fourth node, and the second feedback circuit comprises an odd number of signal inverting elements.
In one exemplary embodiment of the disclosed embodiments, the second feedback circuit includes: a third P-type transistor, the source electrode of which is connected with the power supply voltage, and the grid electrode of which is connected with the fifth node; a source electrode of the fourth P-type transistor is connected with a drain electrode of the third P-type transistor, a grid electrode of the fourth P-type transistor is connected with the complementary clock signal, and a drain electrode of the fourth P-type transistor is connected with the fourth node; the source electrode of the third N-type transistor is grounded, and the grid electrode of the third N-type transistor is connected with the fifth node; and a source electrode of the fourth N-type transistor is connected with a drain electrode of the third N-type transistor, a grid electrode of the fourth N-type transistor is connected with the clock signal, and a drain electrode of the fourth N-type transistor is connected with the fourth node.
In an exemplary embodiment of the disclosed embodiments, the third P-type transistor and the fourth P-type transistor are both connected to the fourth bias supply circuit.
In an exemplary embodiment of the disclosed embodiments, the second feedback circuit includes an odd number of inverters and a second feedback transmission gate connected in series, and two control terminals of the second feedback transmission gate are respectively connected to the clock signal and the complementary clock signal.
In one exemplary embodiment of the present disclosure, further comprising: and the input end of the reset circuit is used for receiving a reset signal, and the output end of the reset circuit is connected with the fourth node and is used for responding to the reset signal to output a reset level to the fourth node.
In an exemplary embodiment of the embodiments of the present disclosure, the reset level is a low level, the reset circuit includes a first reset transistor, the first reset transistor is an N-type transistor, a source of the first reset transistor is grounded, a drain of the first reset transistor is connected to the fourth node, and a gate of the first reset transistor is used to connect to a first reset signal.
In an exemplary embodiment of the embodiments of the present disclosure, the reset level is a high level, the reset circuit includes a second reset transistor, the second reset transistor is a P-type transistor, a source of the second reset transistor is connected to a power supply voltage, a drain of the second reset transistor is connected to the fourth node, and a gate of the second reset transistor is connected to a second reset signal.
According to a second aspect of the present disclosure, there is provided an electronic device comprising a trigger circuit as claimed in any one of the preceding claims.
According to the embodiment of the disclosure, by improving the substrate bias voltage of the P-type transistor when the P-type transistor is turned on, the NBTI effect of the P-type transistor caused by the increase of stress time and the insufficient recovery time can be effectively overcome, and the signal deformation caused by the NBTI effect is corrected.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic diagram of a flip-flop circuit in an embodiment of the present disclosure.
FIG. 2 is a schematic diagram of a bias supply circuit in an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a flip-flop circuit in one embodiment of the present disclosure.
Fig. 4 is a timing diagram of the circuit shown in fig. 3.
Fig. 5A and 5B are timing diagrams of the flip-flop circuits before and after modification, respectively.
Fig. 6 is a schematic diagram of a first feedback circuit in one embodiment of the present disclosure.
Fig. 7 is a schematic diagram of a second feedback circuit in an embodiment of the present disclosure.
Fig. 8 is a schematic diagram of a reset circuit in one embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are only schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a flip-flop circuit in an embodiment of the present disclosure.
Referring to fig. 1, the flip-flop circuit 100 includes a plurality of signal inverting elements 1, wherein a substrate of a P-type transistor of each signal inverting element 1 is correspondingly connected to a bias providing circuit 2, the bias providing circuit 2 is configured to respond to an input signal of the corresponding signal inverting element 1, provide a first substrate bias V1 to the P-type transistor when the P-type transistor in the signal inverting element is turned on, provide a second substrate bias V2 to the P-type transistor when the P-type transistor in the signal inverting element is turned off, and the first substrate bias V1 is smaller than the second substrate bias V2 and greater than a PN junction turn-on voltage, and the signal inverting element 1 is configured to invert an input signal.
In the disclosed embodiment, the flip-flop circuit 100 may be, for example, a D flip-flop. Fig. 1 shows a D flip-flop. The D flip-flop is an information storage device with a memory function and two stable states. The two stable states of the D trigger are respectively 0 and 1, and can be turned from one stable state to the other stable state under the action of a certain external signal. The D flip-flop is composed of a plurality of gates, the triggering mode is two types of level triggering and edge triggering, the level triggering and the edge triggering are adopted, the level triggering can be performed when CP (clock pulse) is equal to 1, the edge triggering is performed when CP (positive transition 0-1) is adopted, and the edge D flip-flop has a hold blocking effect during cp=1, so that the data state change of the input end of the D flip-flop can not influence the output state of the D flip-flop during cp=1. The D flip-flop of the embodiments of the present disclosure may be edge triggered or level triggered.
In the embodiment of the disclosure, the flip-flop shown in fig. 1 is taken as an example, and in other embodiments of the disclosure, the flip-flop may be in other circuit forms, and a P-type transistor connected to the bias supply circuit may be located in other positions where the NBTI effect may exist.
Propagation delay time t of P-type transistor d The following formula is satisfied:
wherein V is DD Is a power supply circuit, I D Is the drain current of the P-type transistor, W, L is the channel width and the channel length of the P-type transistor, mu eff Is carrier mobility, V T Is the threshold voltage of the P-type transistor, C OX Is the capacitance per unit area of the oxide layer between the gate and the substrate.
Carrier mobility μ as stress time increases eff Decrease the threshold voltage V T Drift, resulting in a transmission delay time t d Increasing, a timing drift (duty cycle change) is formed.
The embodiment of the disclosure can reduce the threshold voltage V when the P-type transistor is on by connecting the bias supply circuit 2 to the substrate of the P-type transistor and enabling the bias supply circuit 2 to increase the substrate bias of the substrate output of the P-type transistor when the corresponding P-type transistor is on (i.e. the gate voltage of the P-type transistor is lower than the threshold voltage VT) T Correction for carrier mobility mu eff Reducing the resulting transmission delay time t d And (5) increasing and repairing the time sequence drift.
FIG. 2 is a schematic diagram of a bias supply circuit in an embodiment of the present disclosure.
Referring to fig. 2, in the embodiment of the present disclosure, each bias supply circuit 2 includes:
the first switch element K1, the first end connects the first substrate bias voltage V1, the second end connects the substrate of the P type transistor in the signal inversion component 1 that the bias voltage provides the circuit corresponds to, the control end connects the grid of the P type transistor of the signal inversion component that the bias voltage provides the circuit corresponds to;
and the first end of the second switching element K2 is connected with the second substrate bias voltage V2, the second end of the second switching element K2 is connected with the second end of the first switching element, and the control end of the second switching element K2 is connected with the drain electrode of the P-type transistor of the signal inversion element 1 corresponding to the bias voltage providing circuit.
In the embodiment shown in fig. 2, an inverter is taken as an example of the signal inverting element 1, and in other embodiments, the signal inverting element 1 may be other elements with an inverting function, such as a logic gate circuit of a not gate, a nand gate, a nor gate, and the like. In addition, the first switching element K1 and the second switching element K2 are P-type transistors.
The signal inverting element 1 includes a P-type transistor MP and an N-type transistor MN, wherein a power supply voltage of a source connection of the P-type transistor MP is equal to the second substrate bias voltage V2, i.e., in one embodiment, the second substrate bias voltage V2 is equal to a power supply voltage of the flip-flop circuit 100.
When the input signal Vin of the signal inverting element 1 is at a low level, the first switching element K1 is turned on, the P-type transistor MP is turned on, the substrate bias voltage of the P-type transistor MP is equal to the first substrate bias voltage V1, the N-type transistor MN is turned off, the output signal Vout of the signal inverting element 1 is equal to a high level, and the second switching element K2 is turned off.
When the input signal Vin of the signal inverting element 1 is at a high level, the first switching element K1 is turned off, the P-type transistor MP is turned off, the N-type transistor MN is turned on, the output signal Vout of the signal inverting element 1 is equal to a low level, the second switching element K2 is turned on, and the substrate bias voltage of the P-type transistor MP is equal to the second substrate bias voltage V2, i.e. the power supply voltage connected to the source of the P-type transistor MP, so that the threshold voltage V when the P-type transistor MP is turned on T Compared with negative bias when the P-type transistor MP is not turned on, the drain current is increased, thereby reducing the transmission delay time t d 。
Next, an application scenario of the bias supply circuit shown in fig. 2 will be described by a specific circuit.
Fig. 3 is a schematic diagram of a flip-flop circuit in one embodiment of the present disclosure.
Referring to fig. 3, the flip-flop circuit 300 may include:
the input end of the first inverter OP1 is the input end of the trigger circuit, the output end of the first inverter OP1 is connected with the first node N1, the substrate of the P-type transistor in the first inverter OP1 is connected with the first bias voltage providing circuit 31, and the first inverter OP1 is one of a plurality of signal inverting elements;
the first transmission gate TG1, the first control end connects clock signal CLK, the second control end connects complementary clock signal CLKB, the input end connects first node N1, the output end connects second node N2;
a second inverter OP2, an input terminal is connected to the second node N2, an output terminal is connected to the third node N3, a substrate of a P-type transistor in the second inverter OP2 is connected to the second bias voltage providing circuit 32, and the second inverter OP2 is one of a plurality of signal inverting elements;
the second transmission gate TG2, the first control end connects complementary clock signal CLKB, the second control end connects clock signal CLK, the input end connects third node N3, the output end connects fourth node N4;
a third inverter OP3, an input terminal is connected to the fourth node N4, an output terminal is connected to the fifth node N5, a substrate of a P-type transistor in the third inverter OP3 is connected to the third bias voltage providing circuit 33, and the third inverter OP3 is one of a plurality of signal inverting elements;
a fourth inverter OP4, an input terminal of which is connected to the fifth node N5, an output terminal of which is the first output terminal Q of the flip-flop circuit, a substrate of a P-type transistor in the fourth inverter OP4 being connected to the fourth bias supply circuit 34, the fourth inverter OP4 being one of a plurality of signal inverting elements;
and a fifth inverter OP5, an input terminal of which is connected to an output terminal of the fourth inverter OP4, an output terminal of which is a second output terminal QB of the flip-flop circuit, a substrate of the P-type transistor in the fifth inverter OP5 is connected to the third bias supply circuit 33, and the fifth inverter OP5 is one of the plurality of signal inverting elements.
Wherein the complementary clock signal CLKB is exactly opposite to the level state of the clock signal CLK.
In the embodiment shown in fig. 3, the structure and operation principle of the bias supply circuit to which each inverter is correspondingly connected are the same as those of the embodiment shown in fig. 2. The output node of the first bias supply circuit 31 is A1, the output node of the second bias supply circuit 32 is A2, the output node of the third bias supply circuit 33 is A3, and the output node of the fourth bias supply circuit 34 is A4. The substrate of the P-type transistor of the fifth inverter OP5 is connected to the output node A3 of the third bias supply circuit 33.
The first transmission gate TG1 is configured to control an output signal of the first inverter OP1 to be transmitted from the first node N1 to the second node N2 when the clock signal CLK is at a high level; the transmission gate TG2 is for controlling the output signal of the second inverter OP2 to be transmitted from the third node N3 to the fourth node N4 when the clock signal CLK is at a low level.
The structure of the first transmission gate TG1 can be seen as an example of a broken line frame on the left side of fig. 3. The first transmission gate TG1 may be formed by a P-type transistor MPTG and an N-type transistor MNTG, wherein a first end of the P-type transistor MPTG is connected to the first node N1, a second end of the P-type transistor MPTG is connected to a gate of the second node N2 and is connected to the complementary clock signal CLKB; the first end of the N-type transistor MNTG is connected to the first node N1, the second end is connected to the second node N2, and the gate is connected to the clock signal CLK. When the clock signal CLK is low and the complementary clock signal CLKB is high, the N-type transistor MNTG is turned off, the P-type transistor MPTG is turned off, and the first transmission gate TG1 is turned off; when the clock signal CLK is at a high level and the complementary clock signal CLKB is at a low level, the N-type transistor MNTG is turned on and the P-type transistor MPTG is turned on, and the first transmission gate TG1 transmits the signal of the first node N1 to the second node N2.
The second transmission gate TG2 may have the same structure as the first transmission gate TG1, and only the gate of the P-type transistor is connected to the clock signal CLK and the gate of the N-type transistor is connected to the complementary clock signal CLKB, so that the second transmission gate TG2 is turned on only when the clock signal CLK is low and the complementary clock signal CLKB is high, and transmits the signal of the third node N3 to the fourth node N4.
The first transmission gate TG1 and the second transmission gate TG2 are used to realize timing control of signals transmitted inside the flip-flop circuit, and the signal timing of each node will be described below by taking the circuit shown in fig. 3 as an example.
Fig. 4 is a timing diagram of the circuit shown in fig. 3.
Referring to fig. 4, the clock signal CLK is a periodic signal in which high and low levels alternate. The input signal D of the flip-flop circuit goes from low level to high level at the rising edge at the first time T1. The output node A1 of the first bias supply circuit 31 supplies the second substrate bias voltage V2. Meanwhile, the first inverter OP1 outputs an inverted signal of D, i.e., a low level, to the first node N1, the clock signal CLK is at a high level at the first time T1, the first transmission gate TG1 is turned on, the signal of the first node N1 is transmitted to the second node N2, the P-type transistor in the second inverter OP2 is turned on, the second bias voltage providing circuit 32 provides the first substrate bias voltage V1 to the P-type transistor in the second inverter OP2 through the output node A2, and the second inverter OP2 outputs a complete rising edge to the third node N3.
Since the clock signal CLK is at the high level at the first time T1, the second transmission gate TG2 is not turned on until the clock signal CLK transitions to the low level at the second time T2, the second transmission gate TG2 is turned on, the high level of the third node N3 is transmitted to the fourth node N4, the output terminal of the third inverter OP3 outputs the low level to the fifth node N5, the output node A3 of the third bias supply circuit 33 supplies the higher second substrate bias voltage V2, and the output node A4 of the fourth bias supply circuit 34 supplies the lower first substrate bias voltage V1.
At a third time T3, the input signal D of the flip-flop circuit is shifted from a high level to a low level, the first inverter OP1 outputs a high level to the first node N1, and the output node A1 of the first bias supply circuit 31 outputs a lower first substrate bias voltage V1; at this time, the clock signal CLK is at a high level, the first transmission gate TG1 is turned on, the signal of the first node N1 is transmitted to the second node N2, the second inverter OP2 outputs a low level to the third node N3, and the output node A2 of the second bias supply circuit 32 outputs a higher second substrate bias V2.
Since the clock signal CLK is at the high level at the third time T3, the second transmission gate TG2 is turned off and the fourth node N4 maintains the high level. At the fourth time T4, the clock signal CLK is turned to low level, the second transmission gate TG2 is turned on, the low level of the third node N3 is transmitted to the fourth node N4, and the third inverter OP3 outputs the high level to the fifth node N5, at this time, the third bias supply circuit 33 outputs the lower first substrate bias V1 through the output node A3, and the fourth bias supply circuit 34 outputs the lower second substrate bias V2 through the output node A4.
Similar to the above, at the fifth time T5, since the rising edge of the input signal D occurs when the clock signal CLK is at the low level, the first transmission gate TG1 is turned off, and the low level of the first node N1 is not transmitted from the first node N1 to the second node N2 until the sixth time T6 when the clock signal CLK is at the high level. When the second inverter OP2 inverts the signal of the second node N2 and outputs a high level to the third node N3, the second transmission gate TG2 is turned off until the clock signal CLK transitions to a low level at the seventh time T7, and the second transmission gate TG2 is turned on to transmit the high level of the third node N3 to the fourth node N4, so that the third inverter OP3 generates a low level signal to the fifth node N5.
At the eighth time T8, the input signal D has a falling edge, the clock signal CLK is low, and the first transmission gate TG1 is turned off. The high level of the first node N1 is not transmitted to the second node N2 until the clock signal CLK is high at the ninth time T9 and the first transmission gate TG1 is turned on. At a tenth time T10, the clock signal CLK has a falling edge, the second transmission gate TG2 is turned on, and the signal of the third node N3 is transmitted to the fourth node N4, so that the third inverter OP3 has a high level signal to the fifth node N5.
In the above process, the voltages of the output nodes A1, A2, A3, A4 of each bias voltage providing circuit are changed along with the input signals of the corresponding inverters, which is not described herein.
As can be seen from the timing chart shown in fig. 4, the duration of the output signal of the control flip-flop circuit is an integer multiple of the period of the clock signal CLK through the first transmission gate TG1 and the second transmission gate TG 2.
Fig. 5A and 5B are timing diagrams of the flip-flop circuits before and after modification, respectively.
Referring to fig. 5A, when the bias supply circuit is not added, after the input signal D is transmitted to the input terminal of the first inverter OP1 at the first time T1, the output terminal of the first inverter OP1 outputs an inverted signal of the input signal D. The first transmission gate TG1 is turned on, the second node N2 is at a low level, the third node N3 is used as an output node of the second inverter OP2, and is affected by the NBTI effect of the P-type transistor in the second inverter OP2, and the second transmission gate TG2 is turned off.
At the second time T2, the clock signal CLK has a falling edge, the second transmission gate TG2 is turned on, and the high level signal of the third node N3 is transmitted to the fourth node N4, so that the third inverter OP3 outputs a low level to the fifth node N5.
At the third time T3, when the input signal D is changed from the high level to the low level, the P-type transistor in the first inverter OP1 is turned on, and is affected by the NBTI effect, and the transmission delay time of the P-type transistor increases, so that the signal output from the first inverter OP1 to the second node N2 is deformed. At this time, the clock signal CLK is at a high level, and the first transmission gate TG1 is turned on, but the rising amplitude is small due to the deformation of the signal of the second node N2, and the rising edge cannot be transmitted to the second node N2. Moreover, at the fourth time T4, when the falling edge of the clock signal CLK occurs and the first transmission gate TG1 is turned off, the signal rising amplitude of the first node N1 still does not reach the transmission requirement through the first transmission gate TG1, so that the new medicine of the second node N2 is always maintained at the low level. Correspondingly, timing misalignments of signals at other locations occur.
The rising edge of the first node N1 is not transmitted to the second node N2 until after one clock period, when the first transmission gate TG1 is turned on again, but at this time the signal timing has been greatly different from the input signal D.
It can also be seen that the rising edge of the output signal of the third inverter OP3 (fifth node N5) is also distorted.
Referring to fig. 5B, after the bias supply circuit is added, since the substrate bias of the P-type transistor is reduced when each inverter outputs a rising edge of a signal, the output delay time (i.e., signal distortion) of the rising edge of the signal is reduced, the signal of the first node N1 is transmitted to the second node N2 while the first transmission gate TG1 is turned on, and the signal morphology and timing of the subsequent nodes are also repaired.
Therefore, the embodiment of the disclosure can repair the deformation of the rising edge of the output signal of each signal inversion element caused by NBTI effect by reducing the substrate bias voltage of the P-type transistor when the P-type transistor of the signal inversion element is turned on, and then effectively repair the signal timing.
In another embodiment of the present disclosure, to further control the signal timing, the flip-flop circuit may further include a first feedback circuit FB1, an input terminal of the first feedback circuit FB1 is connected to the third node N3, an output terminal of the first feedback circuit FB1 is connected to the second node N2, and the first feedback circuit FB1 includes an odd number of signal inverting elements for inverting the potential of the third node N3 and feeding back the inverted potential to the second node N2 according to the clock signal CLK and the complementary clock signal CLKB.
Fig. 6 is a schematic diagram of a first feedback circuit in one embodiment of the present disclosure.
Referring to fig. 6, in one embodiment, the first feedback circuit FB1 may include:
the source electrode of the first P-type transistor MP1 is connected with the power supply voltage VDD, and the grid electrode of the first P-type transistor is connected with the third node N3;
the source electrode of the second P-type transistor MP2 is connected with the drain electrode of the first P-type transistor MP1, the grid electrode of the second P-type transistor MP2 is connected with the clock signal CLK, and the drain electrode of the second P-type transistor MP2 is connected with the second node N2;
the source electrode of the first N-type transistor MN1 is grounded, and the grid electrode of the first N-type transistor MN1 is connected with the third node N3;
the source of the second N-type transistor MN2 is connected with the drain of the first N-type transistor MN1, the gate is connected with the complementary clock signal CLKB, and the drain is connected with the second node N2.
In the embodiment shown in fig. 6, when the clock signal CLK is at a high level and the complementary clock signal CLKB is at a low level, the second P-type transistor MP2 and the second N-type transistor MN2 are turned off, and the first feedback circuit FB1 does not operate.
Only when the clock signal CLK is at a low level and the complementary clock signal CLKB is at a high level, the second P-type transistor MP2 is turned on and the second N-type transistor MN2 is turned on, and the first feedback circuit FB1 outputs a signal to the second node N2 according to the signal of the third node N3.
Accordingly, the first feedback circuit FB1 may output a feedback signal to the second node N2 only when the clock signal CLK is at a low level, thereby adjusting the signal of the third node N3 to align with the falling edge of the clock signal CLK, and adjusting the signal timing of the third node N3 to align with the clock signal.
For example, when the clock signal CLK transitions from high to low (i.e., a falling edge occurs), if the voltage of the second node N2 is high, the voltage of the third node N3 is low after the inversion of the second inverter OP2, at this time, the first P-type transistor MP1 is turned on, the first N-type transistor MN1 is turned off, and the first feedback circuit FB1 outputs a high level to the second node N2, which is aligned with the falling edge of the clock signal CLK; if the voltage of the second node N2 is low, the voltage of the third node N3 is high after the inversion of the second inverter OP2, and at this time, the first P-type transistor MP1 is turned off, the first N-type transistor MN1 is turned on, and the first feedback circuit FB1 outputs a low level to the second node N2, which is aligned with the falling edge of the clock signal CLK.
In order to prevent the signal quality of the feedback signal outputted from the first feedback circuit FB1 to the second node N2 from being affected by the NBTI effect, in one embodiment, the substrates of the first P-type transistor MP1 and the second P-type transistor MP2 may each be connected to a fifth bias providing circuit (not shown). The fifth bias voltage providing circuit is configured to provide the first P-type transistor MP1 and the second P-type transistor MP2 with the first substrate bias voltage V1 when the first P-type transistor MP1 and the second P-type transistor MP2 are turned on, and provide the first P-type transistor MP1 and the second P-type transistor MP2 with the second substrate bias voltage V2 when the first P-type transistor MP1 and the second P-type transistor MP2 are turned off. Wherein the second substrate bias voltage V2 is, for example, equal to the supply voltage VDD.
In addition to the first feedback circuit FB1 shown in fig. 6, in another embodiment, the first feedback circuit FB1 may be implemented by an odd number of inverters in series and a first feedback transmission gate (not shown), where two control terminals of the first feedback transmission gate are respectively connected to the clock signal CLK and the complementary clock signal CLKB to implement the same control logic as the embodiment shown in fig. 4, that is, when the clock signal CLK is at a high level, the first feedback circuit FB1 does not output a signal to the second node N2; when the clock signal CLK is at a low level, the first feedback circuit FB1 outputs an inverted signal of the third node N3 to the second node N2, thereby adjusting the signal timings of the second node N2 and the third node N3 to be aligned with the falling edge of the clock signal CLK.
In another embodiment, the flip-flop circuit may also be provided with a second feedback circuit FB2 between the fourth node N4 and the fifth node N5 to further adjust the timing inside the flip-flop circuit. The input end of the second feedback circuit FB2 is connected to the fifth node N5, the output end is connected to the fourth node N4, and the second feedback circuit FB2 includes an odd number of signal inverting elements, which are configured to invert the potential of the fifth node N5 according to the clock signal CLK and the complementary clock signal CLKB and then feed back the inverted potential to the fourth node N4.
It should be noted that, the first feedback circuit FB1 and the second feedback circuit FB2 may be separately provided, or may be provided together, which is not particularly limited in this disclosure.
Fig. 7 is a schematic diagram of a second feedback circuit in an embodiment of the present disclosure.
Referring to fig. 7, in one embodiment, the second feedback circuit FB2 may include:
the source electrode of the third P-type transistor MP3 is connected with the power supply voltage VDD, and the grid electrode of the third P-type transistor MP3 is connected with the fifth node N5;
the source electrode of the fourth P-type transistor MP4 is connected with the drain electrode of the third P-type transistor MP3, the grid electrode of the fourth P-type transistor MP4 is connected with the complementary clock signal CLKB, and the drain electrode of the fourth P-type transistor MP4 is connected with the fourth node N4;
the source electrode of the third N-type transistor MN3 is grounded, and the grid electrode of the third N-type transistor MN3 is connected with the fifth node N5;
the source of the fourth N-type transistor MN4 is connected with the drain of the third N-type transistor MN3, the gate is connected with the clock signal CLK, and the drain is connected with the fourth node N4.
The second feedback circuit FB2 is similar to the first feedback circuit FB1 in structure and principle, and is used for transmitting the inverted signal of the fifth node N5 to the fourth node N4 when the clock signal CLK is at a low level and the complementary clock signal CLKB is at a high level, which will not be described herein.
In one embodiment, the fourth bias supply circuit 34 is connected for the substrates of the third P-type transistor MP3 and the fourth P-type transistor MP 4. Since the control signal of the first substrate bias voltage V1 in the fourth bias voltage providing circuit 34 is the signal of the fifth node N5, the control signal of the second substrate bias voltage V2 is the inverse signal of the fifth node N5, it is possible to input the first substrate bias voltage V1 to the third P-type transistor MP3 and the fourth P-type transistor MP4 when the signal of the fifth node N5 is low and the third P-type transistor MP3 is on, input the second substrate bias voltage V2 to the third P-type transistor MP3 and the fourth P-type transistor MP4 when the signal of the fifth node N5 is high and the third P-type transistor MP3 is off, and correct the distortion of the output signal of the second feedback circuit FB2 due to the NBTI effect.
The second feedback circuit FB2 may also be formed by an odd number of inverters and a second feedback transmission gate connected in series, where two control ends of the second feedback transmission gate FB2 are respectively connected to the clock signal CLK and the complementary clock signal CLKB, and are used to control the second feedback circuit FB2 to operate when the clock signal CLK is at a low level and the complementary clock signal CLKB is at a high level.
By setting the first feedback circuit FB1 and the second feedback circuit FB2, the signal transmission speed between nodes can be increased through the clock signal CLK, and charge-discharge conflict with a main signal is avoided.
In yet another embodiment, the flip-flop circuit may include a reset circuit RST having an input for receiving a reset signal and an output coupled to the fourth node N4 for outputting a reset level to the fourth node N4 in response to the reset signal.
Fig. 8 is a schematic diagram of a reset circuit in one embodiment of the present disclosure.
Referring to fig. 8, the reset circuit 81 may include a first reset transistor MNS and a second reset transistor MPS, which are selectively set according to a reset level, i.e., only one of the first reset transistor MNS and the second reset transistor MPS may be set.
When the reset level is a low level, the reset circuit 81 may include a first reset transistor MNS, which is an N-type transistor, having a source grounded, a drain connected to the fourth node N4, and a gate connected to the first reset signal RST1, and an active level of the first reset signal RST1 is a high level.
When the reset level is at the high level, the reset circuit 81 may include a second reset transistor MPS, the second reset transistor MPS is a P-type transistor, a source of the second reset transistor MPS is connected to the power voltage VDD, a drain of the second reset transistor MPS is connected to the fourth node N4, a gate of the second reset transistor is connected to the second reset signal RST2, and an active level of the second reset signal RST2 is at the low level.
The reset circuit 81, the first feedback circuit FB1 and the second feedback circuit FB2 may be selectively set, or may be set simultaneously, which is not particularly limited in the present disclosure.
According to a second aspect of the present disclosure, there is provided an electronic device comprising a trigger circuit as in any of the embodiments described above.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (15)

1. A flip-flop circuit comprising a plurality of signal inverting elements, wherein the P-type transistors of each of said signal inverting elements have their substrates correspondingly connected to a bias supply circuit for supplying a first substrate bias to the P-type transistors of said signal inverting elements when the P-type transistors of said signal inverting elements are on, and a second substrate bias to the P-type transistors of said signal inverting elements when the P-type transistors of said signal inverting elements are not on, said first substrate bias being less than said second substrate bias and greater than the PN junction turn-on voltage, said signal inverting elements being for inverting the input signals.
2. The flip-flop circuit of claim 1 wherein each of said bias supply circuits comprises:
the first switch element is connected with the first substrate bias voltage at a first end, connected with the substrate of the P-type transistor in the signal inversion element corresponding to the bias voltage providing circuit at a second end, and connected with the grid electrode of the P-type transistor of the signal inversion element corresponding to the bias voltage providing circuit at a control end;
and the first end of the second switching element is connected with the second substrate bias voltage, the second end of the second switching element is connected with the second end of the first switching element, and the control end of the second switching element is connected with the drain electrode of the P-type transistor of the signal inversion element corresponding to the bias voltage providing circuit.
3. The flip-flop circuit according to claim 1 or 2, wherein said flip-flop circuit comprises:
the input end of the first inverter is the input end of the trigger circuit, the output end of the first inverter is connected with a first node, the substrate of the P-type transistor in the first inverter is connected with a first bias voltage providing circuit, and the first inverter is one of the plurality of signal inverting elements;
the first transmission gate, the first control end connects the clock signal, the second control end connects the complementary clock signal, the input end connects the said first node, the output end connects the second node;
the input end of the second inverter is connected with the second node, the output end of the second inverter is connected with the third node, the substrate of the P-type transistor in the second inverter is connected with a second bias voltage providing circuit, and the second inverter is one of the plurality of signal inverting elements;
the first control end of the second transmission gate is connected with the complementary clock signal, the second control end of the second transmission gate is connected with the clock signal, the input end of the second transmission gate is connected with the third node, and the output end of the second transmission gate is connected with the fourth node;
the input end of the third inverter is connected with the fourth node, the output end of the third inverter is connected with the fifth node, the substrate of the P-type transistor in the third inverter is connected with a third bias voltage providing circuit, and the third inverter is one of the plurality of signal inverting elements;
the input end of the fourth inverter is connected with the fifth node, the output end of the fourth inverter is a first output end of the trigger circuit, the substrate of the P-type transistor in the fourth inverter is connected with a fourth bias voltage providing circuit, and the fourth inverter is one of the plurality of signal inverting elements;
and the input end of the fifth inverter is connected with the output end of the fourth inverter, the output end is the second output end of the trigger circuit, the substrate of the P-type transistor in the fifth inverter is connected with the third bias voltage providing circuit, and the fifth inverter is one of the signal inverting elements.
4. The flip-flop circuit of claim 3 further comprising:
and the first feedback circuit is connected with the third node at the input end, connected with the second node at the output end and used for inverting the potential of the third node according to the clock signal and the complementary clock signal and feeding back the potential to the second node, and comprises an odd number of signal inverting elements.
5. The flip-flop circuit of claim 4 wherein said first feedback circuit comprises:
the source electrode of the first P-type transistor is connected with the power supply voltage, and the grid electrode of the first P-type transistor is connected with the third node;
a source electrode of the second P-type transistor is connected with a drain electrode of the first P-type transistor, a grid electrode of the second P-type transistor is connected with the clock signal, and a drain electrode of the second P-type transistor is connected with the second node;
the source electrode of the first N-type transistor is grounded, and the grid electrode of the first N-type transistor is connected with the third node;
and the source electrode of the second N-type transistor is connected with the drain electrode of the first N-type transistor, the grid electrode of the second N-type transistor is connected with the complementary clock signal, and the drain electrode of the second N-type transistor is connected with the second node.
6. The flip-flop circuit of claim 5 wherein said first P-type transistor and said second P-type transistor are each connected to a fifth bias supply circuit.
7. The flip-flop circuit of claim 4 wherein said first feedback circuit comprises an odd number of inverters in series and a first feedback transmission gate, two control terminals of said first feedback transmission gate being connected to said clock signal and said complementary clock signal, respectively.
8. The flip-flop circuit of claim 3 further comprising:
and the input end of the second feedback circuit is connected with the fifth node, the output end of the second feedback circuit is connected with the fourth node and is used for inverting the potential of the fifth node according to the clock signal and the complementary clock signal and feeding back the potential of the fifth node to the fourth node, and the second feedback circuit comprises an odd number of signal inverting elements.
9. The flip-flop circuit of claim 8 wherein said second feedback circuit comprises:
a third P-type transistor, the source electrode of which is connected with the power supply voltage, and the grid electrode of which is connected with the fifth node;
a source electrode of the fourth P-type transistor is connected with a drain electrode of the third P-type transistor, a grid electrode of the fourth P-type transistor is connected with the complementary clock signal, and a drain electrode of the fourth P-type transistor is connected with the fourth node;
the source electrode of the third N-type transistor is grounded, and the grid electrode of the third N-type transistor is connected with the fifth node;
and a source electrode of the fourth N-type transistor is connected with a drain electrode of the third N-type transistor, a grid electrode of the fourth N-type transistor is connected with the clock signal, and a drain electrode of the fourth N-type transistor is connected with the fourth node.
10. The flip-flop circuit of claim 9 wherein said third P-type transistor and said fourth P-type transistor are both connected to said fourth bias supply circuit.
11. The flip-flop circuit of claim 8 wherein said second feedback circuit comprises an odd number of inverters in series and a second feedback transmission gate, two control terminals of said second feedback transmission gate being connected to said clock signal and said complementary clock signal, respectively.
12. The flip-flop circuit of claim 3 further comprising:
and the input end of the reset circuit is used for receiving a reset signal, and the output end of the reset circuit is connected with the fourth node and is used for responding to the reset signal to output a reset level to the fourth node.
13. The flip-flop circuit of claim 12 wherein said reset level is a low level and said reset circuit comprises a first reset transistor, said first reset transistor being an N-type transistor, said first reset transistor having a source connected to ground, a drain connected to said fourth node, and a gate for connecting a first reset signal.
14. The flip-flop circuit of claim 12 wherein said reset level is high and said reset circuit comprises a second reset transistor, said second reset transistor being a P-type transistor, said second reset transistor having a source connected to a supply voltage and a drain connected to said fourth node, a gate for connecting a second reset signal.
15. An electronic device comprising the flip-flop circuit according to any of claims 1-14.
CN202211139843.0A 2022-09-19 2022-09-19 Trigger circuit and electronic device Pending CN117767918A (en)

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JP3814385B2 (en) * 1997-10-14 2006-08-30 株式会社ルネサステクノロジ Semiconductor integrated circuit device
US20100102872A1 (en) * 2008-10-29 2010-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Dynamic Substrate Bias for PMOS Transistors to Alleviate NBTI Degradation
CN105897223B (en) * 2016-03-31 2018-10-12 中国人民解放军国防科学技术大学 A kind of primary particle inversion resistant d type flip flop
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