CN117762836A - Acceleration unit, special data processor, host and read-write signal transmission method - Google Patents

Abstract

The embodiment of the application provides an acceleration unit, a special data processor, a host and a read-write signal transmission method, wherein the acceleration unit is arranged on the special data processor connected with the host, and the acceleration unit comprises: the first register is used for storing doorbell signals written in by the host, wherein the doorbell signals are used for indicating the host to request to read and write the storage system; and the forwarding subunit is used for reading the doorbell signal from the first register after detecting that the doorbell signal is written into the first register, writing the read doorbell signal into the second register, and modifying the identification bit corresponding to the second register in the third register into a first identification, so that a processing unit included in the special data processor reads the doorbell signal from the second register according to the first identification, and acquiring a read-write request for reading and writing the storage system from the host according to the doorbell signal. The acceleration unit that this scheme provided can reduce the occupation rate of host computer treater to improve user's use experience.

Description

Acceleration unit, special data processor, host and read-write signal transmission method

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to an acceleration unit, a special data processor, a host and a read-write signal transmission method.

Background

NVMe storage devices refer to storage devices that support the Non-volatile memory host controller interface specification (Non-Volatile Memory express, NVMe) protocol. Because the NVMe protocol adopts simplified instructions, a software stack with lower delay, queue parallelism and larger queue depth, the I/O overhead and delay of a hardware layer can be reduced to a great extent, so that the storage device supporting the NVMe protocol has the hardware characteristics of high bandwidth and low delay and is widely applied to computing devices.

At present, a processor in a host processes a read-write request for reading and writing the storage device, so that the functions of establishing connection with the storage device, reading and writing data and the like are realized.

However, when a processor in the host computer processes a read-write request for reading from and writing to the storage device, excessive processor computing resources are occupied, resulting in less time for the processor to run the primary tasks.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide an acceleration unit, a dedicated data processor, a host, and a method for transmitting read/write signals, so as to at least solve or alleviate the above-mentioned problems.

According to a first aspect of embodiments of the present application, there is provided an acceleration unit provided to a dedicated data processor connected to a host, the acceleration unit including: the device comprises a first register, a forwarding subunit, a second register and a third register; the first register is used for storing a doorbell signal written by the host, wherein the doorbell signal is used for indicating the host to request to read and write a storage system; and the forwarding subunit is used for reading the doorbell signal from the first register after detecting that the doorbell signal is written into the first register, writing the read doorbell signal into the second register, and modifying an identification bit corresponding to the second register in a third register into a first identification, so that a processing unit included in the special data processor reads the doorbell signal from the second register according to the first identification, and acquires a read-write request for reading and writing the storage system from the host according to the doorbell signal.

In one possible implementation, the acceleration unit includes at least two first registers and at least two second registers, the third register includes at least two identification bits, different first registers correspond to different second registers, different first registers correspond to different transmit queues in the host, and different identification bits correspond to different second registers; the first register is configured to store a doorbell signal written by the host after the send queue corresponding to the first register is written with a read-write request, where the read-write request is used to read and write to the storage system; and the forwarding subunit is used for reading the doorbell signal from the first register after the first register is detected to be written into the doorbell signal, writing the read doorbell signal into a second register corresponding to the first register, and modifying the identification bit corresponding to the second register in the third register into a first identification.

In one possible implementation, the first register communicates with the host over a register interface based connection bus.

According to a second aspect of embodiments of the present application, there is provided a special-purpose data processor comprising: a processing unit and an acceleration unit as described in the first aspect of the present application; and the processing unit is used for reading a doorbell signal from a second register according to the first identifier when the identifier bit in a third register included in the acceleration unit is detected to be the first identifier, and acquiring a read-write request for reading and writing the storage system from the host according to the read doorbell signal, wherein after the second register is written into the doorbell signal by the forwarding subunit, the identifier bit corresponding to the second register in the third register is set to be the first identifier.

In a possible implementation manner, the processing unit is configured to determine a sending queue of the host to which the read-write request is written according to the doorbell signal, and obtain the read-write request from the sending queue.

In one possible implementation manner, the processing unit is configured to read the storage system when the read-write request is a read request, send the read data to the host, and obtain write data from the host and write the write data to the storage system when the read-write request is a write request.

In one possible implementation, when the acceleration unit includes at least two first registers and at least two second registers, and a third register includes at least two identification bits, where different first registers correspond to different second registers, different first registers correspond to different transmit queues in the host, and different identification bits correspond to different second registers; the processing unit is configured to traverse the third register according to a preset traversal period, so as to detect whether each second register is written with a doorbell signal according to at least two identification bits in the third register.

In one possible implementation manner, the processing unit is configured to, when detecting that the identification bit in the third register is the first identification, read a doorbell signal stored in the second register according to the base address of the second register, the sequence numbers of the second registers corresponding to the identification bit in the at least two second registers, and the capacity of the second registers, and set the identification bit to a fourth identification after reading the doorbell signal.

According to a third aspect of embodiments of the present application, there is provided a host comprising: a processor; the host is connected with a special data processor as described in the second aspect of the application; the processor is used for writing a doorbell signal into a first register included in the special data processor after writing a read-write request for the storage system into the transmission queue, so that the special data processor obtains the read-write request for reading and writing the storage system from the host according to the doorbell signal.

According to a fourth aspect of the embodiments of the present application, there is provided a read/write signal transmission method, applied to a dedicated data processor, including: storing a doorbell signal written by a host through a first register, wherein the doorbell signal is used for indicating that the host requests to read and write a storage system; after the doorbell signal is detected to be written into the first register, reading the doorbell signal from the first register, writing the read doorbell signal into the second register, and modifying an identification bit corresponding to the second register in a third register into a first identification; and reading the doorbell signal from the second register according to the first identifier, and acquiring a read-write request for reading and writing the storage system from the host according to the doorbell signal.

According to the scheme provided by the embodiment of the application, the acceleration unit comprises a first register, a forwarding subunit, a second register and a third register, the first register stores doorbell signals sent by the host, the forwarding subunit forwards the doorbell signals to the second register and modifies the identification bit corresponding to the second register in the third register into a first identification, so that the processing unit can read doorbell signals from the second register through the first identification and acquire read-write requests for reading and writing the storage system from the host through the doorbell signals, the host can read and write the storage system through the special data processor, and because the host processes the read-write requests through the special data processor, the host can access any storage system through the special data processor, so that complexity of accessing different storage systems is unloaded, consumption of a client of the storage system is reduced, the occupancy rate of the processor is low, and the calculation performance of the processor in the host is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings may also be obtained according to these drawings for a person having ordinary skill in the art.

FIG. 1 is a schematic diagram of an acceleration unit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another acceleration unit provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a special-purpose data processor provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a host provided in an embodiment of the present application;

fig. 5 is a flowchart of a read-write signal transmission method provided in an embodiment of the present application.

Detailed Description

The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of the present application, certain specific details are set forth in detail. The present application will be fully understood by those skilled in the art without a description of these details. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the substance of the present application. The figures are not necessarily drawn to scale.

As previously described, NVMe storage devices refer to storage devices that support the Non-volatile memory host controller interface specification (Non-Volatile Memory express, NVMe) protocol. Because the NVMe protocol adopts simplified instructions, a software stack with lower delay, queue parallelism and larger queue depth, the I/O overhead and delay of a hardware layer can be reduced to a great extent, so that the storage device supporting the NVMe protocol has the hardware characteristics of high bandwidth and low delay and is widely applied to computing devices.

When an application program running on a host needs to read and write the storage device, a read-write request needs to be sent out, and at present, the processor in the host processes the read-write request for reading and writing the storage device, so that the functions of establishing connection with the storage device, reading and writing data and the like are realized. However, when a processor in the host computer processes a read-write request for reading from and writing to the storage device via the network, excessive computing resources are occupied by the processor, resulting in less time for the processor to run the primary tasks.

The application provides an acceleration unit, the acceleration unit includes first register, transmit subunit, second register and third register, first register stores the doorbell signal that the host computer sent, transmit subunit transmits doorbell signal to the second register, and the sign bit that corresponds to the second register in the third register is modified into first sign, thereby can make processing unit read doorbell signal from the second register through first sign, and obtain the read-write request to the memory system through doorbell signal from the host computer, thereby the host computer can read and write to the memory system through special data processor, because the host computer processes the read-write request through special data processor, the host computer can access any memory system through special data processor, thereby the complexity of access different memory systems has been uninstalled, and the consumption of operation memory system customer end, the occupation rate of processor is lower, the computational performance of processor in the host computer has been improved. .

Embodiments of the present application are further described below with reference to the accompanying drawings of embodiments of the present application.

Fig. 1 is a schematic diagram of an acceleration unit provided in an embodiment of the present application, where the acceleration unit 100 is disposed in a dedicated data processor connected to a host, as shown in fig. 1, and the acceleration unit 100 includes: a first register 101, a forwarding sub-unit 102, a second register 103 and a third register 104.

The first register 101 may store a doorbell signal written by the host, wherein the doorbell signal is used to indicate that the host requests a read from or write to the storage system. The forwarding subunit 102 may read the doorbell signal from the first register 101 after detecting that the doorbell signal is written into the first register 101, write the read doorbell signal into the second register 103, and modify the identification bit corresponding to the second register 103 in the third register 104 to be a first identification, so that a processing unit included in the special data processor reads the doorbell signal from the second register 103 according to the first identification, and obtains a read-write request for reading and writing to the storage system from the host according to the doorbell signal.

When a program in the host computer needs to read and write a storage system, an NVMe driver running in the host computer writes a doorbell signal into a first register 101 included in the special data processor, the first register 101 stores the doorbell signal written by the host computer, after detecting that the doorbell signal is written in the first register 101, the forwarding subunit 102 reads the doorbell signal in the first register 101 according to a preset forwarding rule, and writes the doorbell signal into a second register 103, the forwarding subunit 102 modifies an identification bit corresponding to the second register 103 in a third register 104 into a first identification after writing the doorbell signal into the second register 103, and when detecting that the identification bit in the third register is the first identification, a processing unit in the special data processor determines a second register 103 corresponding to the first identification according to the first identification, reads the doorbell signal in the second register 103, and processes the doorbell signal.

The processing unit processes the doorbell signal, and can acquire a read-write request for reading and writing the storage system from the host according to the doorbell signal, so that the host can read and write the storage system through the special data processor.

In this embodiment of the present application, the acceleration unit 100 includes a first register 101, a forwarding subunit 102, a second register 103, and a third register 104, where the first register 101 stores doorbell signals sent by a host, the forwarding subunit 102 forwards doorbell signals to the second register 103, and modifies an identification bit corresponding to the second register 103 in the third register 104 into a first identification, so that a processing unit can read doorbell signals from the second register 103 through the first identification, and obtain a read-write request for reading and writing to a storage system from the host through the doorbell signals, so that the host can read and write to the storage system through a special data processor, and because the host processes the read-write request through the special data processor, the host can access any storage system through the special data processor, thereby unloading complexity of accessing different storage systems, and running consumption of a client of the storage system, and having a low processor occupancy rate, and improving calculation performance of the processor in the host.

Fig. 2 is a schematic diagram of another acceleration unit provided in the embodiment of the present application, as shown in fig. 2, the acceleration unit 100 includes at least two first registers 101 and at least two second registers 103, the third register 104 includes at least two identification bits, the different first registers 101 correspond to the different second registers 103, the different first registers 101 correspond to different transmission queues in the host, and the different identification bits correspond to the different second registers 103.

The first register 101 may store a doorbell signal written by the host after a read-write request is written in a transmission queue corresponding to the first register 101, where the read-write request is used to read and write to the storage system, and the forwarding subunit 102 may read the doorbell signal from the first register 101 after detecting that the first register 101 is written in the doorbell signal, write the read doorbell signal into the second register 103 corresponding to the first register 101, and modify an identification bit corresponding to the second register 103 in the third register 104 into the first identification.

The acceleration unit 100 may include a plurality of first registers 101 and a plurality of second registers 103, and the third register 104 includes a plurality of identification bits, where the plurality of first registers 101 are in one-to-one correspondence with a transmission queue in the host, the plurality of first registers 101 are in one-to-one correspondence with the plurality of second registers 103, and the plurality of identification bits are in one-to-one correspondence with the plurality of second registers 103, for example: if 10 transmission queues are provided in the host, the acceleration unit 100 includes 10 first registers 101 and 10 second registers 103, 10 identification bits are in the third register 104, the 10 first registers 101 and 10 transmission queues are in one-to-one correspondence, different transmission queues are in one-to-one correspondence with different first registers 101, 10 first registers 101 and 10 second registers 103, different first registers 101 are in one-to-one correspondence with different second registers 103, 10 second registers 103 are in one-to-one correspondence with 10 identification bits, and different second registers 103 are in one-to-one correspondence with different identification bits.

When a read-write request is written in a transmission queue corresponding to the first register 101, the first register 101 receives a doorbell signal sent by a host and stores the doorbell signal, at this time, the forwarding subunit 102 detects that the doorbell signal is written in the first register 101, the forwarding subunit 102 reads the doorbell signal, writes the doorbell signal into a second register 103 corresponding to the first register 101, and sets an identification bit corresponding to the second register 103 in a third register 104 as a first identification, for example: when a read-write request is written in the first transmission queue in the host, the doorbell signal written by the host is stored in the register 1 corresponding to the first transmission queue, the forwarding subunit 102 detects that the register 1 is written by the host, forwards the doorbell signal to the register 2 corresponding to the register 1, and modifies the identification bit corresponding to the register 2 in the register 3 to be a first identification, for example, to be "1".

It should be appreciated that the acceleration unit 100 may be provided with a plurality of first registers 101 and a plurality of second registers 103, and the number of enabled first registers 101 and second registers 103 may be determined according to a transmission queue in the host, for example: the acceleration unit 100 is provided with 20 first registers 101 and 20 second registers 103, and if there are 10 transmission queues in the host, 10 first registers 101 and 10 second registers 103 are enabled. It should be noted that, the forwarding subunit 102 may preset a correspondence between the first register 101 and the second register 103, so that the doorbell signal in the first register 101 may be read and then written into the corresponding second register 103.

In this embodiment of the present application, a plurality of first registers 101 and a plurality of second registers 103 are provided in the acceleration unit 100, and the third register 104 includes a plurality of identification bits, where different first registers 101 correspond to different transmission queues in the host, different first registers 101 correspond to different second registers 103, and different second registers 103 correspond to different identification bits, so that when all of the plurality of transmission queues are written with read-write requests, a plurality of doorbell signals sent by the host are stored through the plurality of first registers 101, and the doorbell signals corresponding to the plurality of read-write requests can be processed in parallel, and because the first registers 101 and the second registers 103 correspond to each other one by one, the second registers 103 corresponding to the identification bits can be located through the identification bits in the third registers 104 for the first identification, and the corresponding first registers 101 are located according to the second registers 103, so that the write-write requests can be located to the transmission queues of the write-write requests, and the read-write data can be improved.

In one possible implementation, the first register 101 communicates with the host over a register interface based connection bus.

The first register 101 communicates with the host via a register interface based connection bus, for example: communication with the host over the PCIe bus, transmitting doorbell signals over the PCIe bus, etc.

In this embodiment of the present application, the first register 101 communicates with the host through the connection bus based on the register interface, so that the first register is applicable to various special data processors connected with the host through different buses, and has high applicability.

Fig. 3 is a schematic diagram of a special-purpose data processor provided in an embodiment of the present application, and as shown in fig. 3, the special-purpose data processor 200 includes a processing unit 201 and the acceleration unit 100 in any of the foregoing embodiments. When detecting that the identification bit in the third register 104 included in the acceleration unit 100 is the first identification, the processing unit 201 may read the doorbell signal from the second register 103 according to the first identification, and obtain a read-write request for reading and writing the storage system from the host according to the read doorbell signal, where after the second register 103 is written into the doorbell signal by the forwarding subunit 102, the identification bit corresponding to the second register 103 in the third register 104 is set to the first identification.

The special purpose data processor 200 may be an intelligent network card connected to a host, for example: the special data processor 200 may be a data processing unit (Data Processing Unit, DPU), and the processing unit 201 in the special data processor 200 may determine, when detecting that the identification bit in the third register 104 included in the acceleration unit 100 is the first identification, the second register 103 to which the doorbell signal is written according to the first identification, read the doorbell signal in the second register 103, and process the doorbell signal, so that a read-write request for reading and writing to the storage system may be obtained from the host according to the doorbell signal. It will be appreciated that after the doorbell signal is written in the second register 103, the forwarding subunit 102 modifies the identification bit in the third register 104 corresponding to the second register 103 to the first identification.

In this embodiment of the present application, the special data processor 200 includes an acceleration unit 100 and a processing unit 201, where the first register 101 in the acceleration unit 100 may store a doorbell signal sent by a host, the forwarding subunit 102 in the acceleration unit 100 forwards the doorbell signal to the second register 103, and modifies an identification bit corresponding to the second register 103 in the third register 104 to a first identification, and the processing unit 201 of the special data processor 200 may read the doorbell signal stored in the second register 103 in the acceleration unit 100 according to the first identification, thereby obtaining a read-write request for reading and writing a storage system from the host according to the doorbell signal, so that the host may read and write the storage system through the special data processor 200, and since the host processes the read-write request through the special data processor 200, the host may access any storage system through the special data processor 200, thereby unloading the complexity of accessing different storage systems, and the consumption of operating the client of the storage system, and the occupancy rate of the processor is lower, thereby improving the computing performance of the processor in the host.

In one possible implementation, the processing unit may determine a transmit queue in the host to which the read-write request is written according to the doorbell signal, and obtain the read-write request from the transmit queue.

The processing unit processes the doorbell signal to determine a transmission queue written with the read-write request, namely a storage area for storing the read-write request in the host, and reads the read-write request stored in the storage area after the processing unit determines the storage area, so that the read-write request can be used for reading and writing the storage system.

In the embodiment of the application, the processing unit can determine the sending queue of the read-write request written in the host according to the doorbell signal, and acquire the read-write request from the sending queue, so that the read-write request is processed by the special data processor.

In one possible implementation, the processing unit 201 may read the storage system when the read-write request is a read request, send the read data to the host, and obtain the write data from the host and write the write data to the storage system when the read-write request is a write request.

After the processing unit 201 in the special data processor 200 obtains the read-write request in the host according to the doorbell signal, the read-write request is analyzed, if the read-write request is a request for reading the data in the storage system, the data is read from the storage system according to the read-write request, and the read data is written to the corresponding storage position in the host according to the read-write request, if the read-write request is a request for writing the data into the storage system, the write data is read from the host according to the read-write request, and the write data is written into the storage system, thereby realizing the reading and writing of the data in the storage system by the special data processor 200.

In the embodiment of the application, the read-write request is processed by the special data processor 200, so that the read-write of the storage system can be realized, and the host can access any storage system through the special data processor 200 because the read-write request is processed by the special data processor 200, so that the complexity of accessing different storage systems is relieved, the consumption of running the clients of the storage systems is reduced, the occupancy rate of the processor is lower, and the calculation performance of the processor in the host is improved.

In one possible implementation, when the acceleration unit 100 includes at least two first registers 101 and at least two second registers 103, and the third register 104 includes at least two identification bits, where the different first registers 101 correspond to the different second registers 103, the different first registers 101 correspond to different transmission queues in the host, the different identification bits correspond to the different second registers 103, and the processing unit may traverse the third register 104 according to a preset traversal period, so as to detect whether each second register 103 is written to the doorbell signal according to at least two identification bits in the third register 104.

When the acceleration unit 100 includes a plurality of first registers 101 and a plurality of second registers 103, and the third register 104 includes a plurality of identification bits, the plurality of first registers 101 are in one-to-one correspondence with a transmission queue in the host, the plurality of first registers 101 are in one-to-one correspondence with the plurality of second registers 103, and the plurality of identification bits are in one-to-one correspondence with the plurality of second registers 103, for example: if 10 transmission queues are provided in the host, the acceleration unit 100 includes 10 first registers 101 and 10 second registers 103, 10 identification bits are in the third register 104, the 10 first registers 101 and 10 transmission queues are in one-to-one correspondence, different transmission queues are in one-to-one correspondence with different first registers 101, 10 first registers 101 and 10 second registers 103, different first registers 101 are in one-to-one correspondence with different second registers 103, 10 second registers 103 are in one-to-one correspondence with 10 identification bits, and different second registers 103 are in one-to-one correspondence with different identification bits.

The processing unit 201 in the special data processor 200 traverses the plurality of identification bits in the third register 104 according to a predetermined traversal period, for example: the processing unit 201 traverses the plurality of identification bits in the third register included in the acceleration unit 100 every 1 second to detect whether the identification bits in the third register 104 included in the acceleration unit 100 are the first identifications, thereby detecting whether the doorbell signals are written in the at least two second registers 103, it being understood that the doorbell signals in the second registers 103 are written by the forwarding sub-unit 102 in the acceleration unit 100 according to the doorbell signals written by the host according to the corresponding first registers 101, and the identification bits in the third register 104 are modified to the first identifications by the forwarding sub-unit 102 after being written in the second registers 103.

In this embodiment of the present application, the processing unit 201 may traverse the plurality of identification bits in the third register 104 according to a preset traversal period, so as to detect whether each second register 103 in the acceleration unit 100 is written with a doorbell signal, and because the third register 104 is traversed, compared with traversing the plurality of second registers 103, the traversal time is shorter, and the doorbell signal can be responded in time when the second register 103 is written with a doorbell signal, thereby improving the efficiency of processing the doorbell signal.

In one possible implementation, the processing unit may, when detecting that the flag bit in the third register 104 is the first flag, read the doorbell signal stored in the second register 103 according to the base address of the second register 103, the sequence numbers of the second registers 103 corresponding to the flag bit in at least two second registers 103, and the capacity of the second registers 103, and set the flag bit to the fourth flag after reading the doorbell signal.

When the processing unit detects that the identification bit in the third register 104 is the first identification, according to the base address of the second register 103, the sequence number of the second register 103 in at least two second registers 103 corresponding to the first identification in the third register 104, and the capacity of the second register 103, the address of the second register 103 is determined, so as to read the doorbell signal stored in the second register 103, in an example, when the capacities of the second registers 103 are the same, the start address of the second register 103 may be determined according to dbl_regs_addr=dbl_regs_base+bitmap_idx dbl_reg_len, dbl_regs_addr represents the start address of the second register 103, dbl_regs_base represents the base address of the second register 103, bitmap_idx represents the second sequence number of the second register 103 in at least two second registers 103, and dbl_reg_103 represents the second capacity of the second register. For example: the base address of the second register 103 is 1 st bit, the serial number of the second register 103 is 0, that is, the first second register 103, the start address of the second register 103 is 1 st bit, and if the serial number of the second register 103 is 1, the capacity of the second register 103 is 8 th bit, the start address of the second register 103 is 9 th bit.

After reading the doorbell signal stored in the second register 103 according to the first identification, the processing unit modifies the identification bit in the third register 104 corresponding to the second register 103 to a fourth identification, for example: modified to "0".

In this embodiment of the present application, the processing unit 201 traverses the third register, so that the second register 103 to which the doorbell signal is written is determined according to the identification bit of the third register 104, after the doorbell signal is written in the second register 103, the doorbell signal can be processed in time, and after the new doorbell signal stored in the second register 103 is read, the identification bit corresponding to the second register 103 in the third register 104 is updated to the fourth identification, so that repeated reading of the doorbell signal stored in the second register 103 can be avoided, the accuracy of the doorbell signal is improved, and the efficiency of processing the doorbell signal is improved.

Fig. 4 is a schematic diagram of a host according to an embodiment of the present application, as shown in fig. 4, the host 300 includes: a processor 301. The host 300 is connected to the special data processor 200 in any of the above embodiments, and the processor 301 may write a doorbell signal to the first register 101 included in the special data processor 200 after writing a read-write request to the storage system into the send queue, so that the special data processor 200 obtains the read-write request to read from and write to the storage system from the host 300 according to the doorbell signal.

The processor 301 of the host 300 may write a read-write request to the transmit queue when a read-write request is required to the storage system, and after the processor 301 writes the read-write request to the transmit queue, the host 300 generates a doorbell signal and transmits the doorbell signal to the first register 101.

In an example, the host 300 includes a plurality of sending queues, after writing the read-write request into the sending queues, the host 300 sends the doorbell signal to the first register 101 corresponding to the sending queues, and the above embodiments are visible in the interaction process, which is not described herein.

In this embodiment of the present application, after writing the read-write request into the transmit queue, the processor 301 included in the host 300 may write the doorbell signal into the first register 101 included in the special data processor 200, so that the special data processor 200 may obtain, according to the doorbell signal, the read-write request for reading and writing the storage system from the host 300, so that the host 300 may read and write the storage system through the special data processor 200, thereby implementing the read-write of the storage system.

A specific application of the special purpose data processor is described below with one specific embodiment.

Fig. 5 is a flowchart of a read/write signal transmission method provided in an embodiment of the present application, as shown in fig. 5, the read/write signal transmission method includes the following steps 501 to 503:

step 501, storing a doorbell signal written by a host through a first register.

The doorbell signal written by the host is received and stored through the first register, and the doorbell signal is generated after the host writes the read-write request into the transmission queue, namely the doorbell signal is used for indicating the host to request to read and write the storage system.

In one example, a plurality of doorbell signals written to by a host may be stored through a plurality of first registers.

Step 502, after detecting that the doorbell signal is written into the first register, reading the doorbell signal from the first register, writing the read doorbell signal into the second register, and modifying an identification bit corresponding to the second register in the third register to the first identification.

In an example, if the acceleration unit has a plurality of first registers and a plurality of second registers, and the third register includes a plurality of identification bits, the doorbell signal in the first register may be read and written into the second register corresponding to the first register, and the identification bit corresponding to the second register in the third register may be modified to the first identification.

Step 503, reading the doorbell signal from the second register according to the first identifier, and obtaining a read-write request for reading and writing the storage system from the host according to the doorbell signal.

In the embodiment of the application, the doorbell signal sent by the host is stored through the first register, then the doorbell signal is forwarded to the second register, and the identification bit corresponding to the second register in the third register is modified to be the first identification, so that the doorbell signal in the second register can be read according to the first identification, a read-write request for reading and writing the storage system can be obtained from the host through the doorbell signal, the host can read and write the storage system through the special data processor, and the host can access any storage system through the special data processor because the host processes the read-write request through the special data processor, so that the complexity of accessing different storage systems is relieved, the consumption of running the client of the storage system is reduced, the occupancy rate of the processor is lower, and the calculation performance of the processor in the host is improved.

It should be understood that each embodiment in this specification is described in an incremental manner, and the same or similar parts between each embodiment are referred to each other, and each embodiment focuses on differences from other embodiments. In particular, for method embodiments, the description is relatively simple as it is substantially similar to the methods described in the apparatus and system embodiments, with reference to the description of other embodiments being relevant.

It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

It should be understood that elements described herein in the singular or shown in the drawings are not intended to limit the number of elements to one. Furthermore, modules or elements described or illustrated herein as separate may be combined into a single module or element, and modules or elements described or illustrated herein as a single may be split into multiple modules or elements.

It is also to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. The use of these terms and expressions is not meant to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible and are intended to be included within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.

Claims (10)

1. An acceleration unit provided to a dedicated data processor connected to a host, the acceleration unit comprising: the device comprises a first register, a forwarding subunit, a second register and a third register;

the first register is used for storing a doorbell signal written by the host, wherein the doorbell signal is used for indicating the host to request to read and write a storage system;

and the forwarding subunit is used for reading the doorbell signal from the first register after detecting that the doorbell signal is written into the first register, writing the read doorbell signal into the second register, and modifying an identification bit corresponding to the second register in a third register into a first identification, so that a processing unit included in the special data processor reads the doorbell signal from the second register according to the first identification, and acquires a read-write request for reading and writing the storage system from the host according to the doorbell signal.

2. The acceleration unit of claim 1, wherein the acceleration unit comprises at least two of the first registers and at least two of the second registers, the third register comprises at least two identification bits, different ones of the first registers correspond to different ones of the second registers, different ones of the first registers correspond to different ones of the transmit queues in the host, and different ones of the identification bits correspond to different ones of the second registers;

the first register is configured to store a doorbell signal written by the host after the send queue corresponding to the first register is written with a read-write request, where the read-write request is used to read and write to the storage system;

and the forwarding subunit is used for reading the doorbell signal from the first register after the first register is detected to be written into the doorbell signal, writing the read doorbell signal into a second register corresponding to the first register, and modifying the identification bit corresponding to the second register in the third register into a first identification.

3. Acceleration unit according to any one of the claims 1-2, characterized in that,

the first register communicates with the host via a register interface based connection bus.

4. A special-purpose data processor, comprising: a processing unit and an acceleration unit according to any one of the claims 1-4;

and the processing unit is used for reading a doorbell signal from a second register according to the first identifier when the identifier bit in a third register included in the acceleration unit is detected to be the first identifier, and acquiring a read-write request for reading and writing the storage system from a host according to the read doorbell signal, wherein after the second register is written into the doorbell signal by the forwarding subunit, the identifier bit corresponding to the second register in the third register is set to be the first identifier.

5. The special-purpose data processor of claim 4, wherein,

and the processing unit is used for determining a sending queue written with the read-write request in the host according to the doorbell signal and acquiring the read-write request from the sending queue.

6. The special purpose data processor as recited in claim 5,

the processing unit is configured to read the storage system when the read-write request is a read request, send the read data to the host, acquire write data from the host when the read-write request is a write request, and write the write data to the storage system.

7. The special-purpose data processor of claim 5, wherein when the acceleration unit includes at least two first registers and at least two second registers, and a third register includes at least two identification bits, wherein different ones of the first registers correspond to different ones of the second registers, different ones of the first registers correspond to different ones of the transmit queues in the host, different ones of the identification bits correspond to different ones of the second registers;

the processing unit is configured to traverse the third register according to a preset traversal period, so as to detect whether each second register is written with a doorbell signal according to at least two identification bits in the third register.

8. The special purpose data processor as recited in claim 7,

and the processing unit is used for reading doorbell signals stored in the second registers according to the base address of the second registers, the serial numbers of the second registers corresponding to the identification bits in the at least two second registers and the capacity of the second registers when the identification bits in the third registers are detected to be the first identifications, and setting the identification bits as fourth identifications after the doorbell signals are read.

9. A host, comprising: a processor;

said host being connected to a dedicated data processor as claimed in any one of claims 5 to 8;

the processor is used for writing a doorbell signal into a first register included in the special data processor after writing a read-write request for the storage system into the transmission queue, so that the special data processor obtains the read-write request for reading and writing the storage system from the host according to the doorbell signal.

10. A read-write signal transmission method, applied to a special data processor, characterized by comprising the following steps:

storing a doorbell signal written by a host through a first register, wherein the doorbell signal is used for indicating that the host requests to read and write a storage system;

after the doorbell signal is detected to be written into the first register, reading the doorbell signal from the first register, writing the read doorbell signal into the second register, and modifying an identification bit corresponding to the second register in a third register into a first identification;

and reading the doorbell signal from the second register according to the first identifier, and acquiring a read-write request for reading and writing the storage system from the host according to the doorbell signal.