CN117762347A - Cross-cell encoding method and memory storage device - Google Patents

Abstract

The invention provides a cross-cell coding method and a memory storage device. The method comprises the following steps: receiving a first write instruction from the host system, the first write instruction indicating that first data is stored and the first data belongs to a first code group; reading first parity data corresponding to the first coding group from the rewritable nonvolatile memory module according to the first writing instruction and caching the first parity data into the buffer memory; performing a first cross-cell encoding operation according to the first data and the first parity data to update the first parity data; and storing the first data and the updated first parity data into a rewritable nonvolatile memory module. Therefore, the execution efficiency of the cross-unit coding operation can be considered, and meanwhile, the use of a buffer memory is saved.

Description

Cross-cell encoding method and memory storage device

Technical Field

The present invention relates to a memory control technology, and in particular, to a cross-unit encoding method and a memory storage device.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.

As the data storage density of the rewritable nonvolatile memory module increases, the data protection technology for performing data encoding protection for a single physical unit (e.g., a single physical page) is insufficient to ensure the correctness of the data. Therefore, the partial type of rewritable nonvolatile memory module further adopts a cross-cell data encoding technology to perform cross-cell encoding on a plurality of entity units (such as a plurality of entity pages) belonging to the same encoding group, so as to improve the stability of data storage. In addition, to further avoid reducing the data correction capability of cross-cell encoding due to simultaneous corruption of consecutive physical cells, multiple physical cells belonging to the same encoding group may be dispersed in the rewritable nonvolatile memory module. However, since the plurality of entity units belonging to the same coding group are too dispersed in the rewritable nonvolatile memory module, during the process of writing data, the data belonging to one or more coding groups are largely stored in the buffer memory until the cross-unit coding for each coding group is completed, thereby largely occupying the buffer space of the system.

Disclosure of Invention

The invention provides a cross-unit coding method, a memory storage device and a memory control circuit unit, which can give consideration to the execution efficiency of cross-unit coding operation and save the use of a buffer memory.

Example embodiments of the present invention provide a cross-cell encoding method for a rewritable nonvolatile memory module, the cross-cell encoding method comprising: receiving a first write instruction from a host system, wherein the first write instruction indicates that first data is stored, and the first data belongs to a first encoding group; reading first parity data corresponding to the first coding group from the rewritable nonvolatile memory module according to the first writing instruction and caching the first parity data into a buffer memory; performing a first cross-cell encoding operation according to the first data and the first parity data to update the first parity data, wherein the first cross-cell encoding operation involves cross-cell encoding data stored in a plurality of first physical cells dispersed in the rewritable non-volatile memory module; and storing the first data and the updated first parity data into the rewritable non-volatile memory module.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: receiving a first write instruction from the host system, wherein the first write instruction indicates that first data is stored and the first data belongs to a first encoding group; reading first parity data corresponding to the first coding group from the rewritable nonvolatile memory module according to the first writing instruction and caching the first parity data into a buffer memory; performing a first cross-cell encoding operation according to the first data and the first parity data to update the first parity data, wherein the first cross-cell encoding operation involves cross-cell encoding data stored in a plurality of first physical cells dispersed in the rewritable non-volatile memory module; and storing the first data and the updated first parity data into the rewritable non-volatile memory module.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit including a host interface, a memory interface, an encoding circuit, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the encoding circuit. The memory management circuit is to: receiving a first write instruction from the host system, wherein the first write instruction indicates that first data is stored and the first data belongs to a first encoding group; reading first parity data corresponding to the first coding group from the rewritable nonvolatile memory module according to the first writing instruction and caching the first parity data into a buffer memory; performing, by the encoding circuit, a first cross-cell encoding operation according to the first data and the first parity data to update the first parity data, wherein the first cross-cell encoding operation involves cross-cell encoding data stored in a plurality of first physical cells dispersed in the rewritable non-volatile memory module; and storing the first data and the updated first parity data into the rewritable non-volatile memory module.

Based on the above, after receiving a first write instruction from the host system indicating to store the first data belonging to the first code group, the first parity data corresponding to the first code group may be read from the rewritable nonvolatile memory module to the buffer memory according to the first write instruction. Based on the first data and the first parity data, a first cross-cell encoding operation may be performed to update the first parity data. In particular, the first cross-cell encoding operation involves cross-cell encoding data dispersed among a plurality of first physical cells stored in a rewritable non-volatile memory module. Thereafter, the first data and the updated first parity data may be stored into the rewritable nonvolatile memory module. Therefore, the execution efficiency of the cross-unit coding operation can be considered, and meanwhile, the use of a buffer memory is saved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram of a cross-cell encoding operation shown in accordance with an example embodiment of the invention;

FIG. 8 is a schematic diagram of a cross-cell encoding operation shown in accordance with an example embodiment of the invention;

FIG. 9 is a schematic diagram of a cross-cell encoding operation shown in accordance with an exemplary embodiment of the present invention;

FIG. 10 is a schematic diagram of a cross-cell encoding operation shown in accordance with an exemplary embodiment of the present invention;

fig. 11 is a flowchart illustrating a cross-cell encoding method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

Host system 11 may be coupled to memory storage device 10 through data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by a wired or wireless connection through the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used for connecting to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. For example, the connection interface unit 41 may be compatible with a peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of Electrical and electronics Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, S) interface standard, an eMCP interface standard, a CF interface standard, an Integrated drive electronics interface (Integrated DeviceElectronics, IDE) standard, or other suitable standard.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for controlling the rewritable nonvolatile memory module 43. For example, the memory control circuit unit 42 can instruct the rewritable nonvolatile memory module 43 to perform operations such as writing, reading and erasing of data according to the instruction of the host system 11. For example, the memory control circuit unit 42 may include a flash memory controller.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a dual Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a triple Level memory Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. For example, the memory management circuit 51 may include a central processing unit (Central Processing Unit, CPU), or other programmable general purpose or special purpose microprocessor, digital signal processor (DigitalSignal Processor, DSP), programmable controller, application specific integrated circuit (Application SpecificIntegrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. For example, the host interface 52 may be compatible with PCI Express standards, SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51. The memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. For example, the memory management circuit 51 can issue operation instructions to the rewritable nonvolatile memory module 43 through the memory interface 53 to instruct the rewritable nonvolatile memory module 43 to perform various operations such as reading, writing or erasing of data.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. For example, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (errordetecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for buffering data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. The physical programming unit is a basic unit for performing programming operations to write data. For example, a physical programming unit may include one or more physical pages or physical fans. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an example embodiment, a dummy block may include one or more physical erase units. The physical erase unit is a basic unit for performing an erase operation to erase data. For example, a physical erased cell may include one or more physical blocks.

In an exemplary embodiment, the entity units 610 (0) -610 (A) in the storage area 601 are configured to store user data (e.g., user data from the host system 11 of FIG. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

In an example embodiment, the memory management circuit 51 may configure the logic units 612 (0) -612 (C) to map the physical units 610 (0) -610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

In an exemplary embodiment, the memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

Fig. 7 is a schematic diagram illustrating a cross-cell encoding operation according to an example embodiment of the present invention. Referring to fig. 7, it is assumed that the data frames 701 (1) to 701 (N) respectively include data to be stored into a single physical unit. For example, the data frame 701 (i) contains data to be stored in the physical unit 610 (i) of fig. 6, the data frame 701 (j) contains data to be stored in the physical unit 610 (j) of fig. 6, and i is different from j, and so on.

In an example embodiment, data frames 701 (1) -701 (N) belong to code group 701. Thus, in a cross-unit encoding operation for data frames 701 (1) -701 (N), data frames 701 (1) -701 (N) may be sequentially subjected to a particular encoding operation to generate data frame 702 corresponding to encoding group 701. The data in the data box 702 is also referred to as parity (parity) data. For example, the encoding algorithm employed by the cross-cell encoding operation may include an eXclusive OR (OR) code, a Reed-Solomon (RS) code, OR other type of algorithm, as the invention is not limited.

In an example embodiment, after generating the data frame 702, in a cross-cell decoding operation for the encoded group 701 (i.e., the data frames 701 (1) to 701 (N)), the data frames 701 (1) to 701 (N) belonging to the encoded group 701 and the data frame 702 corresponding to the encoded group 701 may be used to jointly detect errors in the data frames 701 (1) to 701 (N). For example, if the data frame 702 is generated by performing a cross-unit encoding operation on the data frames 701 (1) to 701 (N) based on XOR codes, the data frames 701 (1) to 701 (N) and 702 can be used to jointly detect errors in 1 data frame in the encoding group 701. Alternatively, if the frame 702 is generated by performing a cross-unit encoding operation on the frames 701 (1) to 701 (N) based on the RS code, the frames 701 (1) to 701 (N) and 702 may be used to jointly detect errors in 2 frames in the encoded group 701, and so on.

In an example embodiment, data belonging to the code group 701 (e.g., data in data frames 701 (1) -701 (N)) may be stored in discrete physical units (e.g., discrete physical pages) in the rewritable nonvolatile memory module 43. That is, in an example embodiment, the cross-cell encoding operations performed for the data blocks 701 (1) -701 (N) may involve cross-cell encoding data stored in discrete physical cells in the rewritable non-volatile memory module 43.

In an example embodiment, data belonging to the code group 701 (e.g., data in data frames 701 (1) -701 (N)) may be centrally stored in consecutive physical units (e.g., consecutive physical pages) in the rewritable nonvolatile memory module 43. That is, in an example embodiment, the cross-cell encoding operations performed for the data blocks 701 (1) -701 (N) may also involve cross-cell encoding data stored centrally in consecutive physical cells in the rewritable non-volatile memory module 43.

In an example embodiment, the foregoing cross-cell encoding/decoding operation is also referred to as a redundant array of independent disks (Redundant Array of Independent Disks, RAID) encoding/decoding operation. In an example embodiment, memory management circuitry 51 may perform the cross-cell encoding/decoding operations through error checking and correction circuitry 54. For example, error checking and correction circuit 54 may include encoding/decoding circuitry to perform the cross-cell encoding/decoding operations.

In an example embodiment, after performing a cross-unit encoding operation for at least two data frames (e.g., data frames 701 (i) and 701 (j)) belonging to the encoding group 701 (e.g., data frames 701 (1) to 701 (N)), a data frame 702 corresponding to the encoding group 701 may be initially generated. The memory management circuit 51 may then store the data frame 702 into the rewritable non-volatile memory module 43.

In an example embodiment, after storing the data frame 702 to the rewritable nonvolatile memory module 43, the memory management circuit 51 may read the data frame 702 from the rewritable nonvolatile memory module 43. Then, a cross-cell encoding operation may again be performed on another data frame (e.g., data frame 701 (k)) and data frame 702 belonging to the encoding group 701 (e.g., data frames 701 (1) -701 (N)) to update the data frame 702. The updated data frame 702 may again be stored into the rewritable non-volatile memory module 43.

In an example embodiment, after performing a complete cross-cell encoding operation for all data frames belonging to the encoding group 701 (e.g., data frames 701 (1) -701 (N)), the data in the data frame 702 updated multiple times may be determined to correspond to parity data of the encoding group 701 and may be stored in the rewritable nonvolatile memory module 43. Thereafter, in a cross-cell decoding operation for the code group 701, this parity data may be used to detect errors in one or more data frames in the code group 701.

In an example embodiment, the memory management circuit 51 may receive a write instruction (also referred to as a first write instruction) from the host system 11. This first write instruction indicates that particular data (also referred to as first data) is stored. This first data belongs to a certain coding group (also referred to as a first coding group). According to the first write instruction, the memory management circuit 51 may read parity data (also referred to as first parity data) corresponding to the first encoding group from the rewritable nonvolatile memory module 43 and cache the first parity data in the buffer memory 55. Taking fig. 7 as an example, the first data and the first parity data may include data in a data frame 701 (i) and a data frame 702, respectively.

In an example embodiment, after reading the first parity data from the rewritable nonvolatile memory module 43 and buffering the first parity data in the buffer memory 55, the error checking and correcting circuit 54 may perform a cross-cell encoding operation (also referred to as a first cross-cell encoding operation) corresponding to the first encoding group according to the first data and the first parity data to update the first parity data. For example, the first cross-cell encoding operation may involve cross-cell encoding data dispersed among a plurality of physical cells (also referred to as first physical cells) stored in the rewritable non-volatile memory module 43. Taking fig. 7 as an example, the first entity unit may include a plurality of entity units for storing data frames 701 (1) to 701 (N). For example, the first entity unit may comprise at least two discrete entity units.

In an example embodiment, the memory management circuit 51 may store the first data and the updated first parity data into the rewritable nonvolatile memory module 43. In an example embodiment, the first parity data restored to the rewritable nonvolatile memory module 43 may be repeatedly read from the rewritable nonvolatile memory module 43 and updated through the cross-cell encoding operation corresponding to the first encoding group. The updated first parity data may then be restored to the rewritable nonvolatile memory module 43 again. Details of the relevant operations are detailed above and are not repeated here. In addition, after completing a complete cross-cell encoding operation on the first encoding group, the resulting first parity data may be used to detect errors in one or more data frames in the first encoding group.

In an example embodiment, after receiving the first write instruction, the memory management circuit 51 may receive another write instruction (also referred to as a second write instruction) from the host system 11. The second write instruction indicates that particular data (also referred to as second data) is stored. The second data belongs to another coding group (also referred to as a second coding group). It should be noted that the first code group is different from the second code group. Taking fig. 7 as an example, assuming that the data frames 701 (1) to 701 (N) belong to the first code group, the second data is not included in the data frames 701 (1) to 701 (N).

In an example embodiment, during the execution of the first cross-cell encoding operation, according to the second write instruction, the memory management circuit 51 may read parity data (also referred to as second parity data) corresponding to the second encoding group from the rewritable nonvolatile memory module 43 and cache the second parity data in the buffer memory 55. That is, during the first cross-cell encoding operation performed on the first data and the first parity data, the first parity data and the second parity data may be stored in the buffer memory 55 at the same time.

In an example embodiment, after the second parity data is buffered in the buffer memory 55 and the first cross-cell encoding operation is completed, the error checking and correction circuit 54 may perform a cross-cell encoding operation (also referred to as a second cross-cell encoding operation) corresponding to the second encoding group according to the second data and the second parity data to update the second parity data. For example, the second cross-cell encoding operation may involve cross-cell encoding data dispersed among a plurality of physical cells (also referred to as second physical cells) stored in the rewritable non-volatile memory module 43. Similar to the first entity unit, the second entity unit may include at least two discrete entity units. Furthermore, the second entity unit may not include any of the first entity units.

In an example embodiment, the memory management circuit 51 may store the second data and the updated second parity data into the rewritable nonvolatile memory module 43. In an example embodiment, the second parity data restored to the rewritable nonvolatile memory module 43 may be repeatedly read from the rewritable nonvolatile memory module 43 and updated through the cross-cell encoding operation corresponding to the second encoding group. The updated second parity data may then be restored to the rewritable nonvolatile memory module 43 again. Details of the relevant operations are detailed above and are not repeated here. In addition, after completing a complete cross-cell encoding operation on the second encoding group, the resulting second parity data may be used to detect errors in one or more data frames in the second encoding group.

In an example embodiment, the memory management circuit 51 may reserve a buffer space in the buffer memory 55 for performing both the first and second cross-unit encoding operations. Thus, during the first cross-cell encoding operation performed on the first data and the first parity data, it is ensured that at least the first parity data and the second parity data can be loaded into the buffer memory 55 at the same time and not be rewritten with each other.

In an exemplary embodiment, the first data and the second data are sequentially stored in consecutive physical units in the rewritable nonvolatile memory module 43. For example, the first data and the second data may be sequentially written into a plurality of consecutive physical units in the rewritable nonvolatile memory module 43.

In an example embodiment, after receiving the second write instruction, the memory management circuit 51 may receive another write instruction (also referred to as a third write instruction) from the host system 11. The third write instruction indicates that particular data (also referred to as third data) is stored. The third data belongs to another coding group (also referred to as a third coding group). It should be noted that the third code group is different from the first code group and the second code group.

In an example embodiment, during the execution of the second cross-cell encoding operation, according to the third write instruction, the memory management circuit 51 may read parity data (also referred to as third parity data) corresponding to the third encoding group from the rewritable nonvolatile memory module 43 and cache the third parity data in the buffer memory 55. That is, during the second cross-cell encoding operation performed on the second data and the second parity data, the second parity data and the third parity data may be stored in the buffer memory 55 at the same time.

It should be noted that the second cross-cell encoding operation is performed after the first cross-cell encoding operation is completed, and the first parity data in the buffer memory 55 is restored to the rewritable nonvolatile memory module 43 after the update is completed. Thus, in an example embodiment, during the second cross-cell encoding operation performed on the second data and the second parity data, the third parity data may replace or overwrite at least a portion of the previously cached first parity data in the buffer memory 55. Thus, the amount of buffer memory 55 can be saved.

In an exemplary embodiment, after the third parity data is buffered in the buffer memory 55 and the second cross-cell encoding operation is completed, the error checking and correction circuit 54 may perform a cross-cell encoding operation (also referred to as a third cross-cell encoding operation) corresponding to the third encoding group according to the third data and the third parity data to update the third parity data. For example, the third cross-cell encoding operation may involve cross-cell encoding data dispersed among a plurality of physical cells (also referred to as third physical cells) stored in the rewritable non-volatile memory module 43. Similar to the first entity unit, the third entity unit may also comprise at least two discrete entity units. Furthermore, the third entity unit may not comprise any one of the first entity units and/or any one of the second entity units.

In an example embodiment, the memory management circuit 51 may store the third data and the updated third parity data into the rewritable nonvolatile memory module 43. In an example embodiment, the third parity data restored to the rewritable nonvolatile memory module 43 may be repeatedly read from the rewritable nonvolatile memory module 43 and updated through the cross-cell encoding operation corresponding to the third encoding group. The updated third parity data may then be restored to the rewritable nonvolatile memory module 43 again. Details of the relevant operations are detailed above and are not repeated here. In addition, after completing a complete cross-cell encoding operation on the third encoding group, the resulting third parity data may be used to detect errors in one or more data frames in the third encoding group.

Fig. 8 is a schematic diagram illustrating a cross-cell encoding operation according to an example embodiment of the present invention. Referring to fig. 8, the memory management circuit 51 may receive a write command 801 (1) (i.e., a first write command) from the host system 11. Write instruction 801 (1) is used to indicate stored data 802 (1) (i.e., first data). The data 802 (1) belongs to code group a (i.e., the first code group). According to the write instruction 801 (1), the memory management circuit 51 may read parity data 803 (1) (i.e., first parity data) corresponding to the encoded group a from the rewritable nonvolatile memory module 43. Then, the memory management circuit 51 may load the parity data 803 (1) into the buffer memory 55 and buffer the parity data 803 (1) in the reserved buffer space 810.

After the parity data 803 (1) is loaded into the buffer memory 55, the encoding circuit 81 in the error checking and correcting circuit 54 may perform a cross-unit encoding operation (i.e., a first cross-unit encoding operation) corresponding to the encoding group a according to the data 802 (1) and the parity data 803 (1). For example, in a first cross-unit encoding operation, encoding circuit 81 may update parity data 803 (1) based on data 802 (1). The memory management circuit 51 may store the data 802 (1) into the rewritable nonvolatile memory module 43. In addition, after the first cross-cell encoding operation is completed, the memory management circuit 51 may restore the updated parity data 803 (1) to the rewritable nonvolatile memory module 43.

On the other hand, following the write instruction 801 (1), the memory management circuit 51 may receive the write instruction 801 (2) (i.e., the second write instruction) from the host system 11. Write instruction 801 (2) is used to indicate stored data 802 (2) (i.e., second data). The data 802 (2) belongs to code group B (i.e., the second code group). Coding group a and coding group B are independent and do not affect each other.

It should be noted that in the example embodiment of fig. 8, during the execution of the first cross-cell encoding operation, according to the write instruction 801 (2), the memory management circuit 51 may read the parity data 803 (2) (i.e., the second parity data) corresponding to the encoding group B from the rewritable nonvolatile memory module 43 in advance without waiting for the completion of the first cross-cell encoding operation. The memory management circuitry 51 may then load the parity data 803 (2) into the buffer memory 55 and buffer the parity data 803 (2) in the pre-reserved buffer space 820. At this time, the buffer spaces 810 and 820 in the buffer 55 may store parity data 803 (1) and 803 (2), respectively.

Fig. 9 is a schematic diagram illustrating a cross-cell encoding operation according to an example embodiment of the present invention. Referring to fig. 9, following the example embodiment of fig. 8, after loading the parity data 803 (2) into the buffer memory 55, the encoding circuit 81 may perform a cross-unit encoding operation (i.e., a second cross-unit encoding operation) corresponding to the encoding group B according to the data 802 (2) and the parity data 803 (2). For example, in a second cross-unit encoding operation, encoding circuitry 81 may update parity data 803 (2) based on data 802 (2). The memory management circuit 51 may store the data 802 (2) into the rewritable nonvolatile memory module 43. In addition, after the second cross-cell encoding operation is completed, the memory management circuit 51 may restore the updated parity data 803 (2) to the rewritable nonvolatile memory module 43.

On the other hand, following the write instruction 801 (2), the memory management circuit 51 may receive the write instruction 801 (3) (i.e., the third write instruction) from the host system 11. The write command 801 (3) is used to indicate the stored data 802 (3) (i.e., the third data). The data 802 (3) belongs to code group C (i.e., the third code group). Code group a, code group B, and code group C are independent and do not affect each other.

It should be noted that in the example embodiment of fig. 9, during the execution of the second cross-cell encoding operation, according to the write instruction 801 (3), the memory management circuit 51 may read the parity data 803 (3) (i.e., the third parity data) corresponding to the encoding group C from the rewritable nonvolatile memory module 43 in advance without waiting for the completion of the second cross-cell encoding operation. The memory management circuitry 51 may then load the parity data 803 (3) into the buffer memory 55 and cache the parity data 803 (3) in the buffer space 810.

It should be noted that in the exemplary embodiment of fig. 9, the parity data 803 (3) may replace or overwrite at least a portion of the parity data 803 (1) originally cached in the buffer space 810 to save the space occupied by the buffer memory 55. At this time, the buffer spaces 810 and 820 in the buffer 55 may store parity data 803 (3) and 803 (2), respectively.

Fig. 10 is a schematic diagram illustrating a cross-cell encoding operation according to an example embodiment of the present invention. Referring to fig. 10, following the example embodiment of fig. 9, after loading the parity data 803 (3) into the buffer memory 55, the encoding circuit 81 may perform a cross-unit encoding operation (i.e., a third cross-unit encoding operation) corresponding to the encoding group C according to the data 802 (3) and the parity data 803 (3). For example, in a third cross-cell encoding operation, encoding circuit 81 may update parity data 803 (3) based on data 802 (3). The memory management circuit 51 may store the data 802 (3) into the rewritable nonvolatile memory module 43. In addition, after the third cross-cell encoding operation is completed, the memory management circuit 51 may restore the updated parity data 803 (3) to the rewritable nonvolatile memory module 43.

Similarly, following the write instruction 801 (3), the memory management circuit 51 may receive the write instruction 801 (4) (also referred to as a fourth write instruction) from the host system 11. Write instruction 801 (4) is used to indicate stored data 802 (4) (also referred to as fourth data). The data 802 (4) belongs to code group D (i.e., the fourth code group). Code group a, code group B, code group C, and code group D are each independent and do not affect each other.

It should be noted that in the exemplary embodiment of fig. 10, the data 802 (4) may also belong to the code group a or the code group B, as long as it does not belong to the code group C. If the data 802 (4) belongs to the code group A, the parity data 803 (4) may be the parity data 803 (1) that was previously updated and restored to the rewritable nonvolatile memory module 43. Alternatively, if the data 802 (4) belongs to the code group B, the parity data 803 (4) may be the parity data 803 (2) that was previously updated and restored into the rewritable nonvolatile memory module 43.

Similarly, in the example embodiment of FIG. 10, in performing the third cross-cell encoding operation, the memory management circuitry 51 may read parity data 803 (4) (also referred to as fourth parity data) corresponding to encoding group D (or encoding group A or encoding group B) from the rewritable non-volatile memory module 43 in advance according to the write instruction 801 (3) without waiting for the third cross-cell encoding operation to complete. The memory management circuitry 51 may then load the parity data 803 (4) into the buffer memory 55 and cache the parity data 803 (4) in the buffer space 820.

Similarly, in the example embodiment of FIG. 10, parity data 803 (4) may replace or overwrite at least a portion of the data of parity data 803 (2) originally cached in buffer space 820 to save the space available for buffer memory 55. At this time, the buffer spaces 810 and 820 in the buffer 55 may store parity data 803 (3) and 803 (4), respectively. The parity data 803 (4) currently cached in the buffer memory 55 may then be updated according to the data 802 (4) and restored to the rewritable nonvolatile memory module 43 after the update is completed. Details of the relevant operations are detailed above and are not repeated here.

Fig. 11 is a flowchart illustrating a cross-cell encoding method according to an exemplary embodiment of the present invention. Referring to fig. 11, in step S1101, a first write command is received from a host system, wherein the first write command indicates to store first data, and the first data belongs to a first encoding group. In step S1102, according to a first write instruction, first parity data corresponding to a first code group is read from a rewritable nonvolatile memory module and cached in a buffer memory. In step S1103, a first cross-cell encoding operation is performed according to the first data and the first parity data to update the first parity data, wherein the first cross-cell encoding operation involves cross-cell encoding data dispersed among a plurality of first physical cells stored in the rewritable nonvolatile memory module. In step S1104, the first data and the updated first parity data are stored in the rewritable nonvolatile memory module.

However, the steps in fig. 11 are described in detail above, and will not be described again here. It should be noted that each step in fig. 11 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 11 may be used with the above exemplary embodiment, or may be used alone, which is not limited by the present invention.

In summary, the cross-cell encoding method, the memory storage device and the memory control circuit unit according to the present invention can read the parity data corresponding to the specific encoding group from the rewritable nonvolatile memory module and update the parity data by the cross-cell encoding operation corresponding to the specific encoding group when necessary. The updated parity data may be restored to the rewritable nonvolatile memory module to reduce the occupation of the available space of the buffer memory. In addition, by reserving the buffer space available for at least two cross-unit encoding operations in the buffer memory, during the execution of the cross-unit encoding operation for the previous instruction, parity data for the cross-unit encoding operation corresponding to the next instruction can be read out from the rewritable nonvolatile memory module in advance, thereby effectively improving the overall performance of the system.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (12)

1. A method of cross-cell encoding for a rewritable non-volatile memory module, the method comprising:

receiving a first write instruction from a host system, wherein the first write instruction indicates that first data is stored, and the first data belongs to a first encoding group;

reading first parity data corresponding to the first coding group from the rewritable nonvolatile memory module according to the first writing instruction and caching the first parity data into a buffer memory;

performing a first cross-cell encoding operation according to the first data and the first parity data to update the first parity data, wherein the first cross-cell encoding operation involves cross-cell encoding data stored in a plurality of first physical cells dispersed in the rewritable non-volatile memory module; and

Storing the first data and the updated first parity data into the rewritable non-volatile memory module.

2. The method of cross-cell encoding according to claim 1, wherein the plurality of first entity cells comprises at least two discrete entity cells.

3. The cross-cell encoding method of claim 1, further comprising:

receiving a second write instruction from the host system after receiving the first write instruction, wherein the second write instruction indicates that second data is stored and the second data belongs to a second encoding group;

during execution of the first cross-cell encoding operation, reading second parity data corresponding to the second encoding group from the rewritable non-volatile memory module and caching the second parity data into the buffer memory according to the second write instruction;

performing a second cross-cell encoding operation according to the second data and the second parity data after the first cross-cell encoding operation is completed, to update the second parity data, wherein the second cross-cell encoding operation involves performing the cross-cell encoding on data dispersed among a plurality of second physical cells stored in the rewritable non-volatile memory module; and

And storing the second data and the updated second parity data into the rewritable nonvolatile memory module.

4. A cross-cell encoding method according to claim 3, further comprising:

a buffer space is reserved in the buffer memory for performing both the first and second cross-unit encoding operations.

5. The method of cross-cell encoding of claim 3, wherein the first data and the second data are stored in consecutive ones of a plurality of physical cells in the rewritable non-volatile memory module.

6. A cross-cell encoding method according to claim 3, further comprising:

receiving a third write instruction from the host system after receiving the second write instruction, wherein the third write instruction indicates that third data is stored and the third data belongs to a third encoding group;

during execution of the second cross-cell encoding operation, reading third parity data corresponding to the third encoding group from the rewritable non-volatile memory module and caching the third parity data into the buffer memory according to the third write instruction, wherein in the buffer memory the third parity data replaces or overwrites at least a portion of the first parity data;

Performing a third cross-cell encoding operation according to the third data and the third parity data after the second cross-cell encoding operation is completed, to update the third parity data, wherein the third cross-cell encoding operation involves performing the cross-cell encoding on data dispersed among a plurality of third physical cells stored in the rewritable non-volatile memory module; and

and storing the third data and the updated third parity data into the rewritable nonvolatile memory module.

7. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

receiving a first write instruction from the host system, wherein the first write instruction indicates that first data is stored and the first data belongs to a first encoding group;

reading first parity data corresponding to the first coding group from the rewritable nonvolatile memory module according to the first writing instruction and caching the first parity data into a buffer memory;

Performing a first cross-cell encoding operation according to the first data and the first parity data to update the first parity data, wherein the first cross-cell encoding operation involves cross-cell encoding data stored in a plurality of first physical cells dispersed in the rewritable non-volatile memory module; and

storing the first data and the updated first parity data into the rewritable non-volatile memory module.

8. The memory storage device of claim 7, wherein the plurality of first physical units comprises at least two discrete physical units.

9. The memory storage device of claim 7, wherein the memory control circuit unit is further to:

receiving a second write instruction from the host system after receiving the first write instruction, wherein the second write instruction indicates that second data is stored and the second data belongs to a second encoding group;

during execution of the first cross-cell encoding operation, reading second parity data corresponding to the second encoding group from the rewritable non-volatile memory module and caching the second parity data into the buffer memory according to the second write instruction;

Performing a second cross-cell encoding operation according to the second data and the second parity data after the first cross-cell encoding operation is completed, to update the second parity data, wherein the second cross-cell encoding operation involves performing the cross-cell encoding on data dispersed among a plurality of second physical cells stored in the rewritable non-volatile memory module; and

and storing the second data and the updated second parity data into the rewritable nonvolatile memory module.

10. The memory storage device of claim 9, wherein the memory control circuit unit is further to:

a buffer space is reserved in the buffer memory for performing both the first and second cross-unit encoding operations.

11. The memory storage device of claim 9, wherein the first data and the second data are stored in consecutive ones of a plurality of physical units in the rewritable non-volatile memory module.

12. The memory storage device of claim 9, wherein the memory control circuit unit is further to:

Receiving a third write instruction from the host system after receiving the second write instruction, wherein the third write instruction indicates that third data is stored and the third data belongs to a third encoding group;

during execution of the second cross-cell encoding operation, reading third parity data corresponding to the third encoding group from the rewritable non-volatile memory module and caching the third parity data into the buffer memory according to the third write instruction, wherein in the buffer memory the third parity data replaces or overwrites at least a portion of the first parity data;

performing a third cross-cell encoding operation according to the third data and the third parity data after the second cross-cell encoding operation is completed, to update the third parity data, wherein the third cross-cell encoding operation involves performing the cross-cell encoding on data dispersed among a plurality of third physical cells stored in the rewritable non-volatile memory module; and

and storing the third data and the updated third parity data into the rewritable nonvolatile memory module.