CN117751088A - Micromechanical ultrasonic transducer with insulating layer and method of manufacture - Google Patents

Abstract

A multiple silicon-on-insulator (SOI) Micromachined Ultrasonic Transducer (MUT) device is disclosed. The apparatus includes a multi-SOI substrate and a MUT. The MUT is attached to a surface of a multi-SOI substrate. The multi-SOI substrate has a first SOI layer and at least a second SOI layer disposed over the first SOI layer. The first SOI layer and the second SOI layer each include an insulating layer and a semiconductor layer. The first SOI layer further defines a cavity below the membrane of the MUT and one or more trenches at least partially surrounding the perimeter of the cavity.

Description

Micromechanical ultrasonic transducer with insulating layer and method of manufacture

Background

The present disclosure relates to semiconductor and microelectromechanical systems (MEMS) technology, such as MEMS ultrasound transducers, that may be used in a medical setting.

Micromachined Ultrasonic Transducers (MUTs) offer great potential in many fields including, but not limited to, medical imaging, air-coupled imaging, distance monitoring, fingerprint monitoring, nondestructive defect monitoring, back-side illumination, biological MEMS, and diagnostics. Crosstalk is a problem that MUTs often face.

The use of silicon-on-insulator (SOI) substrates has become more prevalent in MEMS devices. SOI wafers enable the fabrication of the most advanced MEMS, complementary Metal Oxide Semiconductor (CMOS), power and Radio Frequency (RF) components used in consumer, automotive, industrial and medical applications. SOI wafers provide a high quality single crystal silicon layer on a high quality silicon dioxide layer (buried oxide or BOX) that can be used to design several MEMS devices. SOI wafers provide precise control over several material parameters that enable the design and fabrication of unique device configurations.

Despite these advantages, conventional SOI wafer technology is challenged in that precise control of geometry requires advanced MEMS devices that require three-dimensional (3D) vertical integration with CMOS circuitry. These challenges have been alleviated by using a dual SOI technique that delaminates two SOI substrates.

Disclosure of Invention

Dual SOI technology may also improve the functionality of various microelectromechanical systems (MEMS) devices, such as Micromechanical Ultrasonic Transducers (MUTs) including piezoelectric MUTs (pmuts) and capacitive MUTs (cmuts). The use of dual SOI technology may enable a designer more flexibility in sizing and positioning cavities (or waveguides) and trenches etched in the Buried Oxide (BOX) and semiconductor layers of the device. Thus, the dual SOI design may improve acoustic wave transmission (e.g., by increasing wave output power) and reduce cross-talk.

In addition, the multi-SOI process disclosed herein may enable better critical dimension control during the process of etching trenches and cavities in MUT devices, thereby enhancing design flexibility. In addition, the multi-SOI process may provide more precise alignment tolerances, thereby mitigating the effects of alignment errors.

In some aspects, a multiple silicon-on-insulator (SOI) Micromachined Ultrasonic Transducer (MUT) device is disclosed. The apparatus includes a multi-SOI substrate. The device also includes a MUT having a membrane. The apparatus also discloses that the MUT is attached to the surface of a multi-SOI substrate. The apparatus also discloses that the multi-SOI substrate includes a first SOI layer and at least a second SOI layer disposed over the first SOI layer, the first SOI layer and the second SOI layer each including an insulating layer and a semiconductor layer. The first SOI layer also includes a cavity located under the membrane of the MUT. One or more grooves at least partially surround the perimeter of the cavity.

In some embodiments, the MUT is a piezoelectric micromachined ultrasonic transducer (pMUT).

In some embodiments, the MUT is a capacitive micromachined ultrasonic transducer (cMUT).

In some embodiments, the second SOI layer has a height of 40 microns to 80 microns.

In some embodiments, the insulating layer is a Buried Oxide (BOX) layer.

In some embodiments, the height of the BOX layer is 1 micron to 5 microns.

In some embodiments, the semiconductor layers of the first SOI layer and at least the second SOI layer are handle layers; wherein the cavity is created by etching at least one of the handle layer and the BOX layer.

In some embodiments, the device includes a through silicon via.

In some embodiments, the semiconductor layer is a silicon film layer.

In some embodiments, the multi-SOI substrate is a dual SOI substrate.

In some embodiments, the cavity includes a deposited oxide layer.

In some embodiments, the trench is etched to a depth that spans one or more layers of the device.

In some embodiments, the apparatus further comprises a handle layer below the first SOI layer.

In some embodiments, the handle layer is a semiconductor layer.

In some embodiments, the semiconductor layer of the second SOI layer includes a metal coating.

In some embodiments, the cavity is filled with a gas.

In some embodiments, the cavity comprises a vacuum.

In some embodiments, the insulating layer comprises a non-oxide insulator.

In one aspect, a multiple silicon-on-insulator (SOI) Micromachined Ultrasonic Transducer (MUT) array is disclosed. The array includes a multi-SOI substrate. The array also includes a plurality of MUTs each having a membrane. A plurality of MUTs are attached to a surface of a multi-SOI substrate. The multi-SOI substrate includes a second SOI layer disposed over the first SOI layer, each of the first SOI layer and the second SOI layer including an insulating layer and a semiconductor layer. The first SOI layer also includes a plurality of cavities, each cavity being located below a membrane of a MUT of the plurality of MUTs. The first SOI layer also includes one or more trenches at least partially surrounding a perimeter of a cavity of the plurality of cavities of the plurality of MUTs.

In one aspect, a method of fabricating a dual silicon-on-insulator (SOI) Micromachined Ultrasonic Transducer (MUT) array is provided. The method includes defining at least one trench in the first SOI layer by etching an oxide layer of the first SOI layer to include a width of the at least one trench. The method further includes applying a photoresist layer to the oxide layer of the first SOI layer. The method further includes defining a cavity in the first SOI layer by pattern etching the photoresist layer and the oxide layer to include a width of the cavity. The method further includes etching the cavity and the at least one trench. The method further includes applying an oxide layer to the cavity and the at least one trench.

Incorporated by reference

All publications, patents, and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference.

Drawings

The features and advantages of the present subject matter will be better understood by reference to the following detailed description that sets forth illustrative embodiments, and the accompanying drawings thereof:

fig. 1A is a schematic diagram illustrating a cross section of a generalized MUT array attached to an acoustic medium according to an embodiment.

Figure 1B illustrates a top view of a MUT array according to an embodiment.

Fig. 1C is a block diagram of an imaging apparatus according to an embodiment.

Fig. 1D illustrates a top view of a MUT according to an embodiment.

Fig. 1E illustrates a cross-sectional view of the MUT taken along direction 4-4 in fig. 1D, according to an embodiment.

Figure 2 is a graph illustrating motion amplitude of approximately 22mm in span for a MUT array having 128 elements in the azimuth direction, according to an embodiment. The central two MUTs are actuated and the response of the other 126 MUTs is monitored. Gray scale indicates positive (toward white) or negative (toward black) diaphragm deflection. Two transmit elements are eliminated from the figure so that crosstalk ripple can be seen. The dashed line 230 approximately represents an imaging cone defined by a wave having a velocity of 1,480 m/s.

Fig. 3 is a diagram illustrating fourier transforms (also referred to as f-k maps) in space and time of the data of fig. 2, representing the data in the spatial and frequency domains, according to an embodiment. The amplitude is plotted in dB against the maximum amplitude of the fourier data, where the white data has higher amplitude black-blue data. Data circled between 2MHz to 4MHz and 0.5 musec to 1.5 musec is unwanted crosstalk.

Fig. 4 is an ultrasound image taken with a MUT array similar to fig. 2 and 3, according to an embodiment. The "spotlight" effect is highlighted by two arrows, while the "ghost" artifact is circled.

Fig. 5 illustrates a dual SOI MEMS device according to an embodiment.

Fig. 6 illustrates a dual SOI MEMS device according to an embodiment.

Fig. 7 illustrates a process for etching cavities and trenches in a "handle" wafer of dual SOI substrates.

Fig. 8 shows a process of etching cavities and trenches in a "handle" wafer of a dual SOI substrate.

Detailed Description

Described herein are multi-SOI structures for use as substrates for microelectromechanical system (MEMS) fabrication, in particular, micromechanical Ultrasonic Transducers (MUTs) including piezoelectric MUTs (pmuts) and capacitive MUTs (cmuts). In the specific embodiments disclosed herein, the multi-SOI structure is a dual SOI structure.

The disclosed multi-SOI structure may provide many benefits to MUT array designers. The depth of the device enables buried cavities and trenches to be etched longer than for single SOI structures due to the addition of the additional SOI layer. The disclosed system allows the designer flexibility in choosing where to place the trenches in the MEMs devices and arrays and how large cavities and trenches to fabricate. This flexibility may enhance the capability of the MEMS MUT array to increase the output power of the generated acoustic signal to penetrate deeply into the subject and mitigate the effects of cross-talk from interface waves traveling through the silicon substrate of the array.

The output power may be increased by etching buried cavities or waveguides in the multi-SOI substrate. The cavities may be etched such that they span multiple layers of the multi-SOI substrate. The methods disclosed herein for multi-SOI MEMS device fabrication may enable precise control of cavity thickness and depth through multiple iterations of etching and masking. To keep the edges of the cavity original, an oxide layer may be applied to the cavity. The oxide may be applied by thermally growing the oxide or depositing the oxide, for example by Plasma Enhanced Chemical Vapor Deposition (PECVD).

To mitigate the effects of cross-talk, designers can place buried trenches at different locations within a multi-SOI substrate. The trenches may introduce an impedance mismatch between the substrate of the MEMS device and any material within the crosstalk trenches. The impedance mismatch may disrupt the crosstalk wave by attenuation, reflection, and scattering. The designer may etch the trenches to different depths and at different locations near the cavity. In many cases, the pattern of etched trenches need not be uniform across the MEMS device (e.g., MUT) array.

The disclosed system may enable electronic devices to communicate with each other using Through Silicon Vias (TSVs). A TSV may be a vertical conductive structure for connecting multiple silicon wafers vertically stacked in a single package. With multi-SOI systems, a designer may be able to create a vertical electrical connection that is capable of connecting many devices. The use of TSVs may increase interconnect and device density, shorten the connections between devices, and thereby reduce electrical losses. TSVs may be encoded in a multi-SOI substrate from the top layer to the bottom layer of the device. For example, a mask may be used to define the width of the recess, thereby forming the recess in the multi-SOI substrate. Then, a recess defined in the substrate may be etched (e.g., by an anisotropic process). The recess may then be filled with a conductive material (such as a metal, metal alloy) or a conductive ceramic compound (such as TiN or a doped semiconductor or semiconductor alloy).

The multi-SOI process disclosed herein may enable better critical dimension control during the process of etching trenches and cavities in MUT devices, thereby enhancing design flexibility. In addition, the multi-SOI process may provide more precise alignment tolerances, thereby mitigating the effects of alignment errors. For example, a multi-SOI process may reduce the tolerance required to compensate for alignment errors from about 10 micrometers (μm) to about 3 μm. Cavities and trenches in a multi-SOI structure may be etched from the top of the SOI layer rather than from the bottom, as SOI structures are typically etched. This may prevent artifacts such as taper from forming from the etching process.

Certain definitions

Unless defined otherwise, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Any reference herein to "or" is intended to encompass "and/or (and/or)" unless otherwise specified.

MEMS device

Fig. 5 illustrates a dual SOI MEMS device 500 according to an embodiment. In this embodiment, the device is a pMUT device. In other embodiments, the multi-SOI MEMS device may have 3, 4, 5, 6, or 10 or more SOI layers. Although the semiconductor used in the present embodiment is silicon, in other embodiments the semiconductor material may be germanium, silicon germanium, carbon doped silicon germanium or other materials. Typically, pMUT arrays will achieve a similar structure that repeats in a periodic fashion, but with spatially varying trench locations.

The surface layer 510 includes a piezoelectric layer sandwiched between two conductive layers, and is attached to a double SOI substrate. The conductive layer may include an electrode made of a material including SRO (SrRuO ₃ ) Titanium, and platinum. When a voltage is applied to the conductive layerThe piezoelectric layer may be stressed when in use. The stress may actuate the membrane under the piezoelectric and conductive layers to produce an acoustic output wave. The piezoelectric layer may be made of piezoelectric materials such as PZT, KNN, PZT-N, PMN-Pt, alN, sc-AlN, znO, PVDF and LiNiO3. The thickness of the piezoelectric layer may vary between 100nm and 5 μm or possibly more. In other embodiments, the surface layer 510 may also include a multilayer piezoelectric element (multi-modal) that includes a plurality of piezoelectric layers and electrodes.

The insulating layer 520 may be an oxide layer deposited on the multi-SOI substrate. The oxide layer may be silicon dioxide, silicon nitride or silicon oxynitride. The insulating layer 520 may be 0.1 μm to 0.3 μm thick. The insulator may be thermally grown or deposited.

The second SOI layer 530 may include a silicon film layer disposed over an insulating layer. The insulating layer may be an oxide layer, which may be referred to as a buried oxide layer (BOX). However, the insulating layer may also be composed of a non-oxide insulator such as sapphire. The insulating layer may be used to reduce parasitic capacitance in the MEMS device by physically separating the conductive layers from each other, thereby preventing conductive layers from accumulating charge.

The silicon membrane layer may facilitate transmission and reception of acoustic waves by the pMUT transducer. When the piezoelectric layer is stressed, the transducer may emit sound waves, thereby actuating the silicon membrane layer. When the reflected wave is incident on the transducer, it may provide pressure to the membrane layer, which may cause a change in charge in the piezoelectric layer.

Silicon can be used to bond the silicon film layer to the insulating layer directly or by fusion bonding. In another example, the following method may be used in combination with the silicon and oxide layers: the silicon wafer may be oxidized and then an etch stop layer implanted. The oxide layer may then be bonded to the underlying silicon wafer. The bonded layers may then be annealed. The silicon wafer may be polished and etched down to the etch stop layer. Finally, the etch stop layer may be removed and the top silicon layer further polished.

The first SOI layer 540 may include a silicon layer disposed over an insulating layer, which itself is disposed over a silicon substrate. The first SOI layer may be disposed below the second SOI layer. The first SOI layer may include a cavity and one or more trenches in addition to a silicon layer and an insulating layer similar to those in the second SOI layer.

The dimensions of the cavity 550 may be specific to improve the performance of the pMUT device. For example, the cavity may be etched to a depth that spans the semiconductor layer and the insulating layer, and cut into the silicon substrate to a depth. The designer may also modify the width of the cavity. The depth and width of the modification cavity 550 may be used to shape the output wave produced by the transducer to provide better penetration through the acoustic medium. Increasing the number of layers of the multi-SOI device may increase the depth to which the cavity 550 may be etched. In some embodiments, the cavity 550 may be in a vacuum, but in other embodiments, the cavity may be filled with a gas at a predetermined pressure. The pMUT array may have some cavities filled with vacuum and other cavities filled with gas in order to achieve freedom of vibrating movement of the membrane in some locations and to suppress vibrating movement of the membrane in other locations, respectively.

The grooves 560 may also be sized at the discretion of the designer and placed into the device at the discretion of the designer. One or more trenches may be located around the perimeter of cavity 550 in dual SOI device 500. The trenches may be placed at different locations within the semiconductor material layer. The trenches may also be etched to a depth that spans one or more SOI layers of the pMUT device. The distribution of grooves in the transducer array need not be uniform. Some individual pMUT elements may have multiple grooves disposed alongside them, where other pMUT elements may have only one groove. Furthermore, the trenches within the pMUT array may have different lengths and distances from the surface layer 510, depending on the needs of the dual SOI sensor system.

The substrate 570 may be a semiconductor layer, such as a silicon layer. The substrate 570 may also be referred to as a handle layer and may be substantially larger than any of the SOI layers.

Fig. 6 illustrates a dual SOI MEMS device 600 according to an embodiment. In this embodiment, the device is a cMUT device. Typically, a cMUT array will achieve a similar structure that repeats in a periodic fashion, but with the trench locations spatially varying.

Typically, cMUT devices include a flexible membrane layer formed over a cavity in a semiconductor substrate. The film layer and the substrate serve as electrodes and a Direct Current (DC) bias voltage is applied thereto. The film layer may include a metal coating. When Alternating Current (AC) is applied to the membrane and the substrate layer, electrostatic forces (attractive and repulsive forces between charged objects) caused by the varying voltages cause the flexible membrane to vibrate, producing sound waves.

The dual SOI MEMS cMUT device may be constructed in a similar manner as the dual SOI MEMS pMUT device. The apparatus may comprise, from top to bottom: a surface layer 610 (which may include one or more electrodes), an insulating layer 620, a second SOI layer 630, a first SOI layer 640, and a semiconductor substrate 670. The first SOI layer may comprise a membrane layer and the second SOI layer may comprise one or more cavities 650 and one or more trenches 660 for acoustic wave generation and shaping and cross-talk cancellation.

MUT

The present disclosure may be used in the context of imaging devices utilizing Micromachined Ultrasonic Transducer (MUT) technology, including, for example, piezoelectric micromachined ultrasonic transducer (pMUT) or capacitive micromachined ultrasonic transducer (cMUT) technology.

For proper operation, the MUT may be designed to transfer energy into the acoustic medium to which it is attached. Take the generalized example of the MUT array of fig. 1A as an example. In this case, the MUT is represented by a movable diaphragm 101a, 101b, 101c, the movable diaphragm 101a, 101b, 101c being formed in or atop the substrate 100 by a cavity 120a, 120b, 120 c. The diaphragms 101a, 101b, 101c are acoustically coupled to a semi-infinite acoustic medium 200 at an interface 110. Acoustic medium 200 may be any substance or substances; common mediums include air, water, tissue, electrolytic gel, metal, silicone rubber used as a body-fitting layer, and the like.

During operation, the diaphragms 101a-101c are excited to move primarily in the z-direction. Excitation is typically produced by a piezoelectric effect (for piezoelectric MUT (pMUT)) or a capacitive effect (for capacitive MUT (cMUT)). In both cases, the movement of the diaphragm generates pressure waves that are transmitted into the acoustic medium 200. However, diaphragm movement also creates unwanted waves outside of the acoustic medium 200. The most common unwanted waves are elastic compression waves that travel within the substrate 100 and through the substrate 100, as well as interfacial waves that travel along the interface 110 between the substrate 100 and the acoustic medium 200, as well as other interfaces attached to the substrate 100.

All energy radiated outside the acoustic medium 200 is generally not required. Not only is power wasted, but also the function of the MUT is disturbed. For example, in medical imaging, elastic compression waves will rebound off other surfaces and cause artifacts, such as static images on medically relevant images formed by energy reflected from the acoustic medium 200. As another example, interface waves traveling along interface 110 will create crosstalk in medical imaging, thereby creating point illumination effects and unwanted ghost images.

A general example of a MUT array 210 is shown in fig. 1B. The MUT array 210 includes a substrate 100 and a plurality of MUTs 101. A plurality of MUTs 101 are attached to a surface of a substrate. Each MUT includes a movable diaphragm as shown in fig. 1A. In some embodiments, each of the MUTs 101 is a pMUT. In some embodiments, each of the MUTs 101 is a cMUT. MUT 101 may be arranged in a two-dimensional array 210 arranged in orthogonal directions. That is, MUTs 101 are formed as a two-dimensional mxn array 210 of MUTs 101 having N columns and M rows. The number of columns (N) and the number of rows (M) may be the same or different. In some examples, the array 210 may be curved, for example, to provide a wider angle of the object being imaged. In some examples, the array may provide different packages, such as hexagonal packages, rather than the standard square packages shown in fig. 1B. In some examples, the array may be asymmetric, for example, as described in U.S. patent No. 10,656,007 (incorporated herein by reference in its entirety).

The present disclosure provides, among other things, a novel solution to the problems of compression and interface waves in MUT arrays and their resultant crosstalk. Fig. 2 provides an example of such crosstalk in a MUT array formed from a silicon substrate 100 coupled to a hydroacoustic medium 200. The diagonal corrugations 220 represent the travelling pressure wave. Two dashed lines 230 represent the speed of sound of the aquatic acoustic medium (approximately 1480 m/s). The ripple and high amplitude data 240 under these lines 230 generally represent good acoustic data. Data 250 above two dashed lines 230 represents different forms of crosstalk.

The data in fig. 2 is spatially and temporally fourier transformed to obtain the f-k plot in fig. 3. In FIG. 3, we can see that the crosstalk acoustic energy enclosed by the dashed line 300 is distributed between about 2,000m/s and 6,000m/s. The longitudinal velocity of sound in silicon is about 8,800m/s, while the interfacial wave velocity of Rayleigh and shear waves is between 5,000m/s and 5,500 m/s. This suggests that the crosstalk energy may be due to a combination of interface and bulk waves.

Imaging phantom using a MUT array, such as the MUT array used to generate the outputs depicted in fig. 2 and 3, produces the results shown in fig. 4. Two artifacts are clearly visible: (1) The "spotlight" effect 420, in which the center portion of the image is brighter than the edges, and (2) the "ghost" image 430 of the highly reflective target is apparent at the edges of the image.

Fig. 1C is a block diagram of an imaging device 105 having selectively variable channels 106, 108 controlled by a controller 109 and having imaging calculations performed on a computing device 110 in accordance with the principles described herein. The imaging device 105 may be used to generate images of internal tissues, bones, blood flow, or organs of the human or animal body. Thus, the imaging device 105 may transmit signals into the body and receive reflected signals from the body part being imaged. Such imaging devices may include pmuts or cmuts, which may be referred to as transceivers or imagers, which may be based on photoacoustic or ultrasound effects. The imaging device 105 may also be used to image other objects. For example, the imaging device 105 may be used for medical imaging; flow measurements in pipes, speakers, and microphone arrays; lithotripsy; localized tissue heating for treatment; and highly dense focused ultrasound (HIFU) procedures.

In addition to use with a human patient, the imaging device 105 may also be used to obtain images of internal organs of an animal. Furthermore, in addition to imaging internal organs, the imaging device 105 may also be used to determine the direction and velocity of blood flow in arteries and veins (as in doppler mode imaging), and may also be used to measure tissue stiffness.

The imaging device 105 may be used to perform different types of imaging. For example, the imaging device 105 may be used to perform one-dimensional imaging (also referred to as a-scan), two-dimensional imaging (also referred to as B-scan), three-dimensional imaging (also referred to as C-scan), and doppler imaging. The imaging device 105 may be switched to a different imaging mode and electronically configured under program control.

To facilitate such imaging, the imaging device 105 includes an array of pMUT or cMUT transducers 210, each transducer 210 including an array of transducer elements (i.e., MUTs) 101. MUT 101 functions as follows: 1) Generating pressure waves through the body or other object, 2) receiving reflected waves of the object or other substance within the body to be imaged. In some examples, the imaging device 105 may be configured to transmit and receive ultrasound waveforms simultaneously. For example, some MUTs 101 may transmit pressure waves to a target object being imaged, while other MUTs 101 receive pressure waves reflected from the target object and generate an electrical charge in response to the received waves.

Fig. 1D shows a top view of an exemplary MUT400 (pMUT in this example). Fig. 1E illustrates a cross-sectional view of the MUT400 of fig. 1D taken along line 4-4 in accordance with an embodiment of the disclosure. The MUT400 may be substantially similar to the MUT 101 described herein. As depicted, the MUT may include: a membrane layer 406 suspended from the substrate 402 and disposed over the cavity 404, a bottom electrode (O) 408, a piezoelectric layer 410, and a top electrode (X) 412; the bottom electrode is disposed on a membrane layer (or simply membrane) 406; the piezoelectric layer is disposed on the bottom electrode (O) 408; the top electrode is disposed on the piezoelectric layer 410.

The MUT, whether cMUT or pMUT, may be efficiently formed on a substrate using various semiconductor wafer fabrication operations. The semiconductor wafer may have dimensions of 6 inches, 8 inches, and 12 inches and be capable of holding hundreds of sensor arrays. These semiconductor wafers begin with a silicon substrate on which various processing steps are performed. An example of such an operation is SiO ₂ Formation of a layer (also referred to as insulating oxide). Various other steps are performed (such as adding metal layers to act as interconnects and bond pads) to allow connection to other electronic devices. Another example of machine operation is etching a cavity in a substrate (e.g., a figure1E cavity 404).

Method for manufacturing pMUT with groove

An exemplary method of fabricating a dual SOI pMUT device with trenches is now described.

(a) First, a first SOI substrate including a first SOI layer may be provided. The first SOI layer may include a first silicon layer, a buried oxide layer, and a second silicon layer, wherein the first and second silicon layers are typically monocrystalline silicon. An oxide layer (typically silicon dioxide) may be deposited on the first silicon layer.

(b) The cavity and one or more crosstalk trenches may be patterned and etched in the first SOI layer to form a "handle" wafer. The trench etch may include four steps: (1) etching the oxide layer, (2) etching the first silicon layer by DRIE, (3) etching the BOX (typically by dry RIE or in some cases by wet etching), and (4) etching the second silicon layer to the desired depth by DRIE. After etching, an oxide layer may be deposited over the cavity and trench, and may be used to narrow the trench if desired. The second SOI "device" wafer may then be fusion bonded to the "handle" wafer to form buried trenches and cavities in the dual SOI substrate. The "device" wafer may form a second SOI layer of the dual SOI substrate, wherein the first silicon layer of the first SOI layer forms a second silicon layer of the second SOI layer.

Most SOI wafers are silicon, meaning that the silicon layer of the "device" wafer and the silicon layer of the "handle" wafer are typically monocrystalline silicon. In this case, the insulator BOX is typically thermally grown silicon dioxide. Silicon SOI wafers with monocrystalline silicon handle and device layers and oxide BOX may be generally used. The device layer may be 5 μm but typically varies between 100nm and 100 μm, while the process layer thickness typically varies between 100 μm and 1000 μm. BOX is typically between 100nm and 5 μm, but in many cases 1 μm may be used.

(c) The back side of the wafer or handle layer may be thinned by grinding and optionally polished at this point, if desired. In many embodiments, the handle layer is thinned from 500 μm to 300 μm thick. Common thicknesses typically vary between 50 μm and 1000 μm.

(d) The cavity side trenches 105 (of fig. 1C) may be patterned and etched. The backside of the substrate 100 is typically etchable via DRIE (deep reactive ion etching).

(e) The cavity etch may be timed. The cavity may be etched simultaneously with the cavity side trenches 105. The etch may be selectively stopped on the BOX. The chamber may be etched via other techniques such as KOH, TMAH, HNA, and RIE. After photoresist stripping, the wafer can be considered complete.

(f) An insulating layer may then be deposited on the dual SOI substrate. The insulating layer being typically some SiO ₂ In the form of a thickness of about 0.1 μm to 3 μm. It is typically deposited by thermal oxidation, PECVD deposition, or by another technique.

(g) First metal layer 408 (of fig. 1E) (also referred to as M1 or metal 1) may then be deposited. Typically, this is a combination of films that adhere to the substrate, prevent diffusion of the piezoelectric, aid in the structured deposition/growth of the piezoelectric, and are electrically conductive. On top of Pt for diffusion barrier and conduction, on top of Ti as an adhesion layer (for Pt to SiO 2), SRO (SrRuO 3) can be used for structured film growth. Typically, these layers are thin, less than 200nm, with some films ranging from 10nm to 40nm. Stress, manufacturing and cost issues typically limit stacking to less than 1 μm. The conductor (Pt) is typically thicker than the structural layer (SRO) and the adhesion layer (Ti). Other common structural layers (rather than SRO) include (la0.5sr0.5) CoO3, (la0.5sr0.5) MnO3, laNiO3, ruO2, irO2, baPbO3, to name a few. Pt may be replaced with other conductive materials such as Cu, cr, ni, ag, al, mo, W and NiCr. These other materials typically have drawbacks such as poor diffusion barrier, brittleness, or unfavorable adhesion, and Pt is the most commonly used conductor. The adhesion layer Ti may be replaced with any common adhesion layer such as TiW, tiN, cr, ni, cr, etc.

(h) Piezoelectric material 410 may then be deposited. Some common examples of suitable piezoelectric materials include: PZT, KNN, PZT-N, PMN-Pt, alN, sc-AlN, znO, PVDF and LiNiO3. The thickness of the piezoelectric layer may vary between 100nm and 5 μm or possibly more.

(i) A second metal layer 412 (also referred to as M2 or metal 2) may then be deposited. The second metal layer 412 may be similar to the first metal layer 408 and may be used for similar purposes. For M2, the same stack as M1 may be used, but the opposite: ti is used to adhere on top of Pt to prevent diffusion on top of SRO for the structure.

(j) Then, a second metal layer or M2412 may be patterned and etched, stopping on the piezoelectric layer. Etching may be performed in a number of ways herein, for example by RIE (reactive ion etching), ion milling, wet chemical etching, isotropic gas etching, etc. After patterning and etching, the photoresist for patterning M2 may be stripped by wet and/or dry etching. In many embodiments for fabricating the cmuts and pmuts described herein, any number of etching approaches may be used, and the photoresist is typically stripped after most of the patterning and etching steps.

(k) The piezoelectric layer may then be similarly patterned and etched, stopping at the first metal layer or M1408. Typically, wet, RIE and/or ion mill etching are used.

(l) The first metal layer or M1408 may then be similarly patterned and etched, stopping on the dielectric insulating layer.

(m) if desired, one or both of the following may be added:

(1) The H2 barrier, the diffusion of H2 into the piezoelectric layer, can limit its lifetime. To prevent this, an H2 barrier may be used. This can be achieved using 40nm ALD (atomic layer deposition) alumina (ai 2O 3). Other suitable materials may include SiC, diamond-like carbon, and the like.

(2) A redistribution layer (RDL) may provide a connection between M1, M2 and other connections (e.g., wire bonds, bump bonds, etc.). RDLs may be formed by first adding a dielectric, such as an oxide, etching vias in the dielectric, depositing a conductor (typically Al), and finally patterning the conductor. In addition, a passivation layer (typically oxide + nitride) may be added to prevent physical scratches, accidental shorts, and/or moisture ingress.

Based on the teachings herein one of ordinary skill in the art will appreciate that other methods may be used to achieve similar end results.

Method for manufacturing cMUT with groove

(a) First, a first SOI layer may be provided, the first SOI layer typically having a first layer of monocrystalline silicon, a buried oxide layer, and a monocrystalline silicon substrate.

(b) The first SOI layer may then be thermally oxidized.

(c) The cavities may be patterned and etched in oxide to create "handle" wafers. This is typically achieved by plasma etching or wet etching of the oxide (e.g., HF).

(d) The buried crosstalk trenches can be patterned and etched in the oxide of the "handle" wafer, if desired. This is typically achieved by plasma etching or wet etching of the oxide (e.g., HF).

(e) A "device" wafer comprising a silicon layer and a buried oxide layer may then be fusion bonded to the patterned oxide "handle" wafer, with an additional oxide layer deposited over the silicon layer. If desired, the "device" wafer can be patterned and etched (e.g., via DRIE) prior to fusion bonding to correspond to the buried trenches 104 in the "handle" wafer, such that fusion bonding of the "handle" wafer and the "device" wafer forms buried trenches 104 (e.g., as shown in FIG. 9B).

(f) The "device" wafer may be lapped and polished to the desired diaphragm thickness.

Based on the teachings herein one of ordinary skill in the art will appreciate that other methods may be used to achieve similar end results.

Variable oxide thickness process

Fig. 7 illustrates a process 700 for etching cavities and trenches in a "handle" wafer of dual SOI substrates. First, the first layer is a 65 μm SOI wafer comprising a BOX layer of 1 μm. In other embodiments, the SOI wafer may be between 40 μm and 80 μm, and the BOX layer may be between 1 μm and 5 μm. The SOI layer has been oxidized. Below the SOI wafer is a semiconductor substrate, which may be a 300 μm-700 μm thick "handle" wafer.

A photomask may be used to define the cavity prior to etching. The photomask may define the height and width of the cavity or the height and width of the cavity of the MEMS array.

In a first operation 710, a cavity may be etched. First, the oxide may be etched using a wet or dry etching method. The silicon layer of the SOI wafer may then be etched using a DRIE etch. The BOX layer may be etched again using a wet or dry (e.g., RIE) etching method. Finally, the silicon substrate may be etched. In this embodiment, the cavity is etched to a depth of 80 μm +/-2 μm (65 μm all the way through the first SOI layer and 15 μm into the handle layer).

In a second operation 720, after etching the cavity is completed, the cavity may then be oxidized. Oxidation can leave the cavity shape intact, preserving the ability of the cavity to function as a waveguide. If oxide is not applied to the cavity, the cavity may have tapered edges instead of straight edges.

In a third operation 730, the first SOI layer may be bonded to a 5 μm SOI wafer (which constitutes the second SOI layer). The second SOI layer may additionally include an oxide thermally grown or deposited over the silicon layer.

Although the above steps illustrate a process 700 according to many embodiments, one of ordinary skill in the art will recognize many variations based on the teachings described herein. The steps may be completed in a different order. Steps may be added or omitted. Some steps may include sub-steps. Many of the steps and sub-steps may be repeated as often as necessary.

In some embodiments, the cavity may not etch into the semiconductor or silicon layer below the top layer of the device. In some embodiments, cavities may be etched into the top layer. In other embodiments, particularly embodiments having more than two layers, the cavity may be etched into a layer lower than the layer directly below the top layer of the device.

Variable cavity and trench depth process

Fig. 8 illustrates a process 800 for etching cavities and trenches in a "handle" wafer of a dual SOI substrate.

In a first operation 810, an operator defines a groove size. This may be performed by using a photomask to determine the location of the trenches on the wafer. The photomask may be configured to define a particular pattern or configuration of trenches through the substrate. For example, the locations on the wafer where transducer elements may be placed may be regularly spaced within the mask, but differently configured trenches may be placed beside the space designated for transducer elements. After the masking process, the operator may etch the oxide layer of the "handle" wafer to define the trenches. The oxide layer may be etched by a dry process (e.g., RIE) or a wet process (e.g., hydrofluoric acid (HF)).

In a second operation 820, a photoresist may be applied to an oxide surface of the wafer using a spin-coating process. The photoresist layer may be a polymer material that is sensitive to ultraviolet light. In other embodiments, alternative methods may be used to coat the oxide surface of the wafer, including spray coating, roll coating, dip coating, and extrusion coating.

In a third operation 830, the photoresist layer may be pattern etched to define cavities. Pattern etching may be performed by exposing the photoresist layer to ultraviolet rays through a mask to obtain a desired pattern. The ir aligner can align the mask on the wafer to precisely etch the pattern.

In a fourth operation 840, the cavity may be partially etched while the trench opening is still protected by the photoresist layer. Thus, the etching of the cavity and the trench (which may be etched to different depths) may be controlled separately. The etchant used to etch the cavity may also partially etch the trench if the photoresist layer is not applied.

In a fifth operation 850, the photoresist may be stripped (e.g., chemically stripped). After stripping the photoresist, the oxide layer may be used as a hard mask to complete the etching of the trenches and cavities.

The operator can etch the cavity under the BOX layer and etch the trench using the oxide as a mask. The operator may then deposit oxide onto the chamber. Applying oxide to the cavity enables the cavity to have straight edges rather than tapered edges, thereby enabling better acoustic wave formation.

In MEMS devices with additional layers, the operator can continue to etch deeper cavities and trenches using the underlying oxide layer as a mask.

Although the above steps illustrate a process 800 according to many embodiments, one of ordinary skill in the art will recognize many variations based on the teachings described herein. The steps may be completed in a different order. Steps may be added or omitted. Some steps may include sub-steps. Many of the steps and sub-steps may be repeated as often as necessary.

While preferred embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Many changes, modifications and substitutions will now occur to those skilled in the art without departing from the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention.

Claims (20)

1. A multiple silicon-on-insulator (SOI) Micromachined Ultrasonic Transducer (MUT) device comprising:

a multi-SOI substrate; and

MUT with membrane;

the MUT is attached to a surface of the multi-SOI substrate;

the multi-SOI substrate comprises a first SOI layer and at least a second SOI layer disposed over the first SOI layer, the first SOI layer and the second SOI layer each comprising an insulating layer and a semiconductor layer,

the first SOI layer further comprises:

a cavity located below the membrane of the MUT; and

one or more grooves at least partially surrounding the perimeter of the cavity.

2. The apparatus of claim 1, wherein the MUT is a piezoelectric micromachined ultrasonic transducer (pMUT).

3. The apparatus of claim 1, wherein the MUT is a capacitive micromachined ultrasonic transducer (cMUT).

4. The apparatus of claim 1, wherein the second SOI layer has a height of 40-80 microns.

5. The apparatus of claim 1, wherein the insulating layer is a Buried Oxide (BOX) layer.

6. The device of claim 5, wherein the BOX layer has a height of 1 micron to 5 microns.

7. The apparatus of claim 5, wherein the semiconductor layer of the first SOI layer and the semiconductor layer of at least the second SOI layer are handle layers; wherein the cavity is created by etching at least one of the handle layer and the BOX layer.

8. The apparatus of claim 1, further comprising a through silicon via.

9. The apparatus of claim 1, wherein the semiconductor layer is a silicon film layer.

10. The apparatus of claim 1, wherein the multi-SOI substrate is a dual SOI substrate.

11. The apparatus of claim 1, wherein the cavity comprises a deposited oxide layer.

12. The device of claim 1, wherein the trench is etched to a depth that spans one or more layers of the device.

13. The apparatus of claim 1, further comprising a handle layer below the first SOI layer.

14. The apparatus of claim 13, wherein the handle layer is a semiconductor layer.

15. The apparatus of claim 1, wherein the semiconductor layer of the second SOI layer comprises a metal coating.

16. The device of claim 1, wherein the cavity is filled with a gas.

17. The device of claim 1, wherein the cavity comprises a vacuum.

18. The apparatus of claim 1, wherein the insulating layer comprises a non-oxide insulator.

19. A multi-silicon-on-insulator (SOI) Micromachined Ultrasonic Transducer (MUT) array comprising:

a multi-SOI substrate; and

a plurality of MUTs each having a membrane;

the plurality of MUTs are attached to a surface of the multi-SOI substrate;

the multi-SOI substrate includes a second SOI layer disposed over a first SOI layer, the first SOI layer and the second SOI layer each including an insulating layer and a semiconductor layer, the first SOI layer further comprising:

a plurality of cavities, each cavity being located below a membrane of a MUT of the plurality of MUTs; and

one or more grooves at least partially surrounding a perimeter of a cavity of the plurality of cavities of the plurality of MUTs.

20. A method of fabricating a dual silicon-on-insulator (SOI) Micromachined Ultrasonic Transducer (MUT) array, comprising:

defining at least one trench in a first SOI layer by etching an oxide layer of the first SOI layer to include a width of the at least one trench;

applying a photoresist layer to the oxide layer of the first SOI layer;

defining a cavity in the first SOI layer by pattern etching the photoresist layer and the oxide layer to include a width of the cavity;

etching the cavity and the at least one trench; and

an oxide layer is applied to the cavity and the at least one trench.