CN117742606A - DPU chip, message storage module thereof and message copying method - Google Patents
DPU chip, message storage module thereof and message copying method Download PDFInfo
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Abstract
The invention discloses a DPU chip, a message storage module and a message copying method thereof, and belongs to the technical field of chip design. When receiving a read-write command issued by an external processor, the message copying method provided by the embodiment reads original message data according to the read command, returns the read message data and the generated read rsp information to the value output unit, when the current operation source of the output unit is the read rsp information, determines that the destination of the returned information is internal by analyzing the read rsp information, packages the previously stored write command and the read message data, and then returns the value input unit to perform creation operation, thereby realizing message copying. The copying process is completed only in the memory module by self without participation of an external processor, so that the performance and bandwidth of the high-speed interconnection bus are little influenced, the processor is bypassed, the resources of the processor are not occupied, other instructions can be executed by the processor, and the processing efficiency of the chip is improved.
Description
Technical Field
The invention belongs to the technical field of chip design, and particularly relates to a DPU chip, a message storage module and a message copying method thereof.
Background
In the conventional chip design method, the method for realizing message copying reads out the original message from a memory module (for example, MMU), then the original message is sent to a processor (for example, NP) to splice the command header and the operation data again, then the command header and the operation data are sent to the memory module, and finally the memory module pushes the message copying result to the processor. This approach can result in wasted internal high-speed interconnect bus performance and bandwidth, which can reduce chip efficiency. In the case of small messages, the impact on bus performance is very small, but when the message is large enough, the bus bandwidth waste is immeasurable when the high-speed interconnect bus AXI transmission needs to be used multiple times. Meanwhile, the mode not only occupies the bus bandwidth, but also occupies the instruction memory RAM of the processor, temporarily accesses the data cache Buf and the chip scheduling module, so that the chip efficiency is low.
Disclosure of Invention
In order to solve the problems that the internal high-speed interconnection bus performance and bandwidth are wasted and resources such as a processor instruction memory, temporary access data cache, a chip scheduling module and the like are occupied and the chip processing efficiency is low in the conventional message copying mode, the invention provides a DPU chip, a message storage module and a message copying method thereof.
The invention is realized by the following technical scheme:
a message copying method of a DPU chip message storage module, the message copying method comprising:
when the input unit receives a read-write command issued by an external processor, the command head is stored in a buffer; the read-write command comprises a read command and a write command;
reading the original message according to the reading command, and returning message data and read rsp information to an output unit; the read rsp information comprises a read-write command cache address and a message storage position head pointer;
when the current operation source of the output unit is the read rsp information, determining a destination of the return information by analyzing the read rsp information, and when the return destination is internal, packaging the write command and the read message data and returning to the input unit for creation operation.
The existing message copying mode, particularly when the message is large, needs to interact with the processor for multiple times, which can lead to waste of internal high-speed interconnection bus performance and bandwidth, and occupy bus bandwidth and processor resources, so that the chip processing efficiency is low. When the current operation source of the output unit is the read rsp information, the destination of the returned information is determined to be internal by analyzing the read rsp information, and the previously stored write command and the read message data are packaged and then returned to the input unit for creation operation, so that the message copying process is realized.
As a preferred embodiment, the message copying method of the invention further comprises the following steps:
when the input unit receives a write command and carrying data issued by an external processor and a write command and carrying data returned by an internal output unit at the same time, the current operation source is arbitrated in two modes and transmitted to the creation unit for creating a message operation, and after the message is successfully created, rsp information is returned to the output unit; the write rsp information comprises a read-write command cache address and a message storage position head pointer;
when the output unit receives the read rsp information and the write rsp information at the same time, the current operation source is arbitrated to carry out external or internal return operation.
In a preferred embodiment, the input unit of the present invention receives no intersection between external and internal data paths, and does not affect each other.
As a preferred embodiment, the output unit of the present invention returns no intersection between external and internal data paths, only requiring arbitration when both input sources are present at the same time.
As a preferred embodiment, the message replication method of the present invention further includes:
when the output unit arbitrates that the current operation source is the writing rsp information, determining a destination of the returned information by analyzing the writing rsp information, returning to the outside at the moment, and returning a message creation result to an external processor through a bus.
As a preferred embodiment, the message replication method of the present invention further includes:
when the output unit arbitrates that the current operation source is the read rsp information, determining a destination of the return information by analyzing the read rsp information, and if the return information is the return outside, returning the read message data to an external processor through a bus; if the command is returned to the inside, the command header stored previously is read, packaged with the message data and returned to the input unit for creation operation.
As a preferred embodiment, the read-write command of the present invention is a dual-layer command, wherein the outer-layer command is a read command and the inner-layer command is a write command.
In a second aspect, the present invention provides a DPU chip packet storage module, where the DPU chip packet storage module includes:
the input unit stores the command header in the buffer after receiving the read-write command issued by the external processor; the read-write command comprises a read command and a write command;
the reading unit reads the original message according to the reading command and returns the message data and the read rsp information to the output unit; the read rsp information comprises a read-write command cache address and a message storage position head pointer;
and the output unit is used for determining the destination of the return information by analyzing the read rsp information when the current operation source of the output unit is the read rsp information, and packaging the write command and the read message data and returning the packaged write command and the read message data to the input unit for creating operation.
As a preferred embodiment, the DPU chip packet memory module of the present invention further includes:
the creation unit writes the cached data into the internal memory according to the command and the data cache address transmitted by the input unit, returns a message storage position head pointer, and generates the write rsp information by combining the read-write command cache address.
In a third aspect, the present invention proposes a DPU chip, which is characterized in that the DPU chip includes:
the processor issues a command and receives returned information;
the message storage module receives the instruction issued by the processor and returns information to the processor.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the message copying method provided by the invention automatically copies the message in the message storage module, and the processor only needs to send a command once and receive the message copying result, so that no extra data interaction is needed, the influence of the internal high-speed interconnection bus performance and bandwidth is greatly reduced, the bus bandwidth and the processor resources are not occupied, and the processing efficiency and performance are improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
fig. 1 is a flowchart of a message copying method according to an embodiment of the present invention.
Fig. 2 is a schematic block diagram of a message storage module according to an embodiment of the present invention.
Fig. 3 is a schematic block diagram of a DPU chip according to an embodiment of the present invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Examples:
the existing message copying method is to read out the original message from the storage module, splice the command header and the operation data again in the processor, and send the spliced command header and the operation data to the storage module, and finally push the message copying result to the processor by the storage module. In view of the above problems, the present embodiment provides a message copying method of a DPU chip message storage module, where the message copying method provided in the present embodiment copies (hard copies) an original message in the storage module by itself, and does not need to interact with a processor multiple times, and the processor only needs to send a command once through an internal high-speed interconnection bus and receive a returned message copying result, which has little influence on the performance and bandwidth of the internal high-speed interconnection bus, and does not occupy bus bandwidth and processor resources, thereby improving chip processing efficiency.
As shown in fig. 1, the message replication method provided in this embodiment specifically includes the following steps:
step 1, after the input unit receives a read-write command issued by the external processor through the bus, the command header is stored in the buffer hdr_ram. The Read-write command comprises a Read command and a write command, preferably, an internal and external double-layer command form can be adopted, the external layer command is read_pkt, the internal layer command is create_pkt, and the input unit is used for identifying and distributing the instruction to the Read unit.
Step 2, reading the original message according to the read command, returning the message data and the read message storage position head pointer, generating read rsp information and the message data by combining the read-write command buffer address, and returning the read rsp information and the message data to the output unit; the read rsp information includes a read-write command buffer address and a message storage location head pointer.
And 3, when the current operation source of the output unit is reading rsp information, determining the destination of the return information by analyzing the reading rsp information, and when the return destination is internal, packaging the previously stored write command and the read message data and then returning to the value input unit to perform the creation operation.
When receiving a read-write command issued by an external processor, the message copying method provided by the embodiment reads original message data according to the read command, returns the read message data and the generated read rsp information to the value output unit, when the current operation source of the output unit is the read rsp information, determines that the destination of the returned information is internal by analyzing the read rsp information, packages the previously stored write command and the read message data, and then returns the value input unit to perform creation operation, thereby realizing message copying. The copying process is completed only in the storage module without participation of an external processor, so that the influence on the performance and bandwidth of the high-speed interconnection bus AXI is very small, the processor is bypassed, the resources of the processor are not occupied, the processor can execute other instructions, the processor only needs to wait until the storage module returns a message creation result (message copying result), and the processing efficiency of the chip is improved.
Further, the message replication method provided in this embodiment further includes:
when the input unit receives the writing command and the carrying data sent by the external processor and the writing command and the carrying data returned by the internal output unit, the current operation source is arbitrated under two modes and transmitted to the creation unit for creating the message operation, and after the message is successfully created, the rsp information is returned to the output unit. It should be noted that the input unit manages the received command and the carried data in different buffer FIFOs (i.e., the command and the data are managed separately), and there is no intersection between the data paths from the outside and the inside.
When the output unit receives the read rsp information and the write rsp information at the same time, the current operation source is arbitrated to carry out external or internal return operation. In addition, there is no intersection between the data paths that the output unit returns to the outside and the inside, and arbitration is only required when both input sources are present at the same time.
Specifically, if the output unit arbitrates that the current operation source is writing rsp information, determining the destination of the returned information by analyzing the rsp information, and returning to the outside at this time, and returning the message creation result to the external processor through the bus.
Specifically, if the output unit arbitrates that the current operation source is read rsp information, determining a destination of the returned information by analyzing the read rsp information, and if the returned information is returned to the outside, returning the read message data to the external processor through the bus; if the message is returned to the inside, the command header stored previously is read, and the command header and the read message data are packaged and returned to the input unit for creation operation.
Specifically, the creating unit performs a message creating operation (i.e. a process of writing message data into the memory) according to the current operation source of the input unit Zhong Caichu, and when the message is successfully created, creates the rsp writing information according to the returned message storage position head pointer and combining with the command cache address, and returns the rsp writing information to the output unit.
It should be noted that, both the read rsp information and the write rsp information carry command cache address information, and command header information, such as dest_id, which is used to identify the direction of the returned information, that is, the inside or the outside, that is, the inside, if dest_id is MMU ID, the command header information is obtained by analyzing the command cache address information, and if dest_id is not MMU ID, the command header information is returned to the outside.
Preferably, the present embodiment may implement arbitration of different signal sources in a polling manner.
Based on the same technical concept, the embodiment further provides a DPU chip message storage module, as shown in fig. 2, where the message storage module specifically includes:
an input unit (cmd_in) for storing the command header in the buffer after receiving the read/write command issued by the external processor; the read-write commands include read commands and write commands.
A reading unit (read_pkt) for reading the original message according to the Read command and returning the message data and the Read rsp information to the output unit;
and an output unit (cmd_out) for determining a destination of the return information by parsing the read rsp information when a current operation source of the output unit is the read rsp information, and for encapsulating the previously stored write command and the read message data to return the value input unit for the creation operation when the return destination is internal.
Furthermore, the input unit of the present embodiment may receive the command and the carrying data issued by the external processor through the bus (AXI 4), or may receive the command and the carrying data transmitted by the internal output (cmd_out) unit, and manage the received command and data in different buffer FIFOs respectively. When a write command and carrying data issued by an external processor and a write command and carrying data returned by an internal output unit are received at the same time, a current operation source is arbitrated under two modes and transmitted to a creation unit (create_pkt) for creating a message operation, and after the message is successfully created, rsp information is returned to the output unit. The data paths from the outside and the inside have no cross and do not affect each other. When at the same time
The output unit of the embodiment can receive the write rsp information returned by the creation unit, and also can receive the read rsp information and the read message data returned by the reading unit, and when the output unit receives the read rsp information and the write rsp information at the same time, the output unit arbitrates the current operation source to perform external or internal return operation. In addition, there is no intersection between the data paths that the output unit returns to the outside and the inside, and arbitration is only required when both input sources are present at the same time. Specifically, if the output unit arbitrates that the current operation source is writing rsp information, determining the destination of the returned information by analyzing the rsp information, and returning to the outside at this time, and returning the message creation result to the external processor through the bus. If the current operation source is read rsp information, determining a destination of the returned information by analyzing the read rsp information, and if the returned information is returned to the outside, returning the read message data to an external processor through a bus; if the message is returned to the inside, the command header stored previously is read, and the command header and the read message data are packaged and returned to the input unit for creation operation.
The creating unit of this embodiment performs a message creating operation (i.e. a process of writing message data into the memory) according to the current operation source of the input unit Zhong Caichu, and when the message is successfully created, generates the write rsp information according to the returned message storage location head pointer and in combination with the command cache address, and returns the write rsp information to the output unit.
The present embodiment also proposes a DPU chip, as shown in fig. 3, which includes:
the processor is used for issuing commands and receiving information;
and the message storage module is used for receiving the instruction issued by the processor and returning information to the processor.
The DPU chip provided by the embodiment adopts the message copying mode, namely, the message copying operation is automatically performed in the message storage module, the processor only needs to send a command once and receive a message copying result, no extra data interaction is needed, the influence on the performance and the bandwidth of a high-speed interconnection bus is very small, meanwhile, the bus bandwidth and the resources of the processor are not occupied, the processor can execute other instructions, and the processing efficiency and the performance are improved.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The message copying method of the DPU chip message storage module is characterized by comprising the following steps of:
when the input unit receives a read-write command issued by an external processor, the command head is stored in a buffer; the read-write command comprises a read command and a write command;
reading the original message according to the reading command, and returning message data and read rsp information to an output unit; the read rsp information comprises a read-write command cache address and a message storage position head pointer;
when the current operation source of the output unit is the read rsp information, determining a destination of the return information by analyzing the read rsp information, and when the return destination is internal, packaging the write command and the read message data and returning to the input unit for creation operation.
2. The message copying method of the DPU chip message storage module of claim 1, further comprising:
when the input unit receives a write command and carrying data issued by an external processor and a write command and carrying data returned by an internal output unit at the same time, the current operation source is arbitrated in two modes and transmitted to the creation unit for creating a message operation, and after the message is successfully created, rsp information is returned to the output unit; the write rsp information comprises a read-write command cache address and a message storage position head pointer;
when the output unit receives the read rsp information and the write rsp information at the same time, the current operation source is arbitrated to carry out external or internal return operation.
3. The message copying method of a DPU chip message memory module of claim 2, wherein the input unit receives no intersection between external and internal data paths, and no mutual influence.
4. The message copying method of a DPU chip message memory module of claim 2, wherein the output unit returns no intersection between external and internal data paths, only requiring arbitration when two input sources are present at the same time.
5. The message copying method of the DPU chip message storage module of claim 2, further comprising:
when the output unit arbitrates that the current operation source is the writing rsp information, determining a destination of the returned information by analyzing the writing rsp information, returning to the outside at the moment, and returning a message creation result to an external processor through a bus.
6. The message copying method of the DPU chip message storage module of claim 2, further comprising:
when the output unit arbitrates that the current operation source is the read rsp information, determining a destination of the return information by analyzing the read rsp information, and if the return information is the return outside, returning the read message data to an external processor through a bus; if the command is returned to the inside, the command header stored previously is read, and the command header and the message data are packaged and returned to the input unit.
7. The method for copying a message in a DPU chip message memory module as claimed in any one of claims 1 to 6, wherein the read-write command is a dual-layer command, and wherein the outer-layer command is a read command and the inner-layer command is a write command.
8. The DPU chip message storage module is characterized by comprising:
the input unit stores the command header in the buffer after receiving the read-write command issued by the external processor; the read-write command comprises a read command and a write command;
the reading unit reads the original message according to the reading command and returns the message data and the read rsp information to the output unit; the read rsp information comprises a read-write command cache address and a message storage position head pointer;
and the output unit determines the destination of the return information by analyzing the read rsp information when the current operation source is the read rsp information, and when the return destination is internal, the write command and the read message data are packaged and then returned to the input unit for creation operation.
9. The DPU chip message memory module as recited in claim 8, further comprising:
the creation unit writes the cached data into the internal memory according to the command and the data cache address transmitted by the input unit, returns a message storage position head pointer, and generates the write rsp information by combining the read-write command cache address.
10. A DPU chip, the DPU chip comprising:
the processor issues a command and receives returned information;
the message storage module of any of claims 8-9, which receives a command issued by the processor and returns information to the processor.
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