CN117729087A - Frequency modulation signal generation method and device - Google Patents

Abstract

The application relates to a frequency modulation signal generation method and device, wherein the method comprises the following steps: determining signal parameters of a preset frequency modulation signal; determining the number of signal interleaving units of the frequency modulation signal according to the signal parameters, and constructing a signal interleaving unit set conforming to the number of the signal interleaving units; establishing a corresponding interleaving unit lookup table according to the signal interleaving unit set; and obtaining the frequency modulation signal through signal conversion by using the interleaving unit lookup table. The phase expression of the linear frequency modulation signals is utilized to realize the generation of multipath parallel linear frequency modulation signals, and the bandwidth of the interleaved wideband linear frequency modulation signals can break through the limitation of the sampling frequency of the FPGA through phase regulation and control, the bandwidth of the wideband linear frequency modulation signals generated in real time is flexible and controllable, the bandwidth is randomly adjustable, and the two-stage DDS is adopted in the signal generation process, so that the device has a simpler structure, does not use external storage resources, reduces the resource consumption and improves the reliability of the design.

Description

Frequency modulation signal generation method and device

Technical Field

The present disclosure relates to the field of communications, and in particular, to a method and apparatus for generating a frequency modulated signal.

Background

With the development of radar technology, radar signals have evolved from pulse modulation to intra-pulse modulation. The intra-pulse modulation is usually chirped, and the modulation bandwidth is increased to the gigahertz level according to the increasing demand of the prior art.

However, for the limitation of the sampling frequency of the FPGA device, the conventional method is difficult to realize wideband chirp signal generation. The implementation of the gigahertz-level chirp signal generation method becomes an important breach under the condition of limited device performance.

Accordingly, there is a need to develop a method and apparatus for generating a frequency modulated signal that addresses one or more of the problems set forth above.

Disclosure of Invention

In view of the above, in order to solve the above technical problems or part of the technical problems, an embodiment of the present invention provides a method and an apparatus for generating a fm signal.

In a first aspect, the present application provides a method for generating a frequency modulated signal, the method comprising:

determining signal parameters of a preset frequency modulation signal;

determining the number of signal interleaving units of the frequency modulation signal according to the signal parameters, and constructing a signal interleaving unit set conforming to the number of the signal interleaving units;

establishing a corresponding interleaving unit lookup table according to the signal interleaving unit set;

and obtaining the frequency modulation signal through signal conversion by using the interleaving unit lookup table.

In one possible embodiment, the signal parameters include signal bandwidth, signal transmission time width, signal chirp frequency;

the determining the number of signal interleaving units of the frequency modulation signal according to the signal parameter comprises the following steps:

setting a Field Programmable Gate Array (FPGA) sampling frequency fs corresponding to a preset frequency modulation signal;

determining the number N of signal interleaving units of the frequency modulation signal according to the FPGA sampling frequency fs and the signal bandwidth B;

in one possible implementation manner, the creating a corresponding interleaving unit lookup table according to the signal interleaving unit set includes:

acquiring initial phases and phase increment of each signal interleaving unit in a signal interleaving unit set;

and transmitting the initial phase and the phase increment corresponding to each signal interleaving unit to the FPGA, and establishing an interleaving unit lookup table in the FPGA according to the initial phase and the phase increment.

In one possible embodiment, the acquiring the initial phase and the phase increment of each signal interleaving unit in the signal interleaving unit set includes:

invoking a phase expression of the signal interleaving unit;

and determining initial phase values and phase increments of each signal interleaving unit in the signal interleaving unit set according to the phase expression.

In one possible embodiment, the phase expression of the signal interleaving unit includes:

wherein,the method is characterized in that the method is a phase expression of a signal interleaving unit, K is signal chirp frequency, N is the number of the signal interleaving units, fs is the sampling frequency of an FPGA, t is a time variable, < >>T is the signal emission time width.

In one possible implementation manner, the building, at the FPGA, an interleaving unit lookup table according to an initial phase and a phase increment includes:

acquiring level information of each signal interleaving unit in a signal interleaving unit set;

sequentially acquiring real-time phases of all levels of signal interleaving units according to the level information, and acquiring sine values and cosine values between the real-time phases and phase increments of the signal interleaving units;

establishing an interleaving unit lookup table by utilizing sine values and cosine values corresponding to each level of signal interleaving units;

the real-time phase of the adjacent next-stage signal interleaving unit in the signal interleaving unit set is the sum of the initial phase of the signal interleaving unit, the real-time phase of the previous-stage signal interleaving unit and the delay phase of the previous-stage signal interleaving unit.

In one possible implementation manner, the obtaining the frequency modulation signal through signal conversion by using the interleaving unit lookup table includes:

converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal;

and according to the level information of the signal interleaving units in the interleaving unit lookup table, splicing all levels of interleaving signals to obtain the broadband linear frequency modulation signal.

In one possible implementation manner, the converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal includes:

converting each level of signal interleaving units into an interleaving signal by using an interleaving unit lookup table, wherein the interleaving signal comprises a real part signal and an imaginary part signal;

the sine value of the signal interleaving unit in the interleaving unit lookup table is converted into a real part signal of the interleaving signal, and the cosine value is converted into an imaginary part signal of the interleaving signal unit.

In a second aspect, the present application provides a frequency modulated signal generating apparatus, the apparatus comprising:

the upper computer module is used for setting signal parameters of preset frequency modulation signals;

the set construction module is used for determining the number of signal interleaving units of the frequency modulation signal according to the signal parameters and constructing a signal interleaving unit set conforming to the number of the signal interleaving units;

the lookup table establishing module is used for establishing a corresponding interleaving unit lookup table according to the signal interleaving unit set;

and the digital-to-analog conversion module is used for obtaining the frequency modulation signal through signal conversion by utilizing the interleaving unit lookup table.

In one possible embodiment, the apparatus further comprises:

the DDS module is used for converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal;

and the signal synthesis module is used for splicing all levels of interleaving signals according to the level information of the signal interleaving units in the interleaving unit lookup table to obtain broadband linear frequency modulation signals.

Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: the method provided by the embodiment of the application realizes the generation of the multipath parallel linear frequency modulation signals by using the phase expression of the linear frequency modulation signals, and the bandwidth of the interleaved broadband linear frequency modulation signals can break through the limitation of the sampling frequency of an FPGA device through phase regulation; the broadband linear frequency modulation signal generated in real time is flexible and controllable, the bandwidth is arbitrarily adjustable, the structure is simple, external storage resources are not used, the resource consumption is reduced, and the reliability of the design is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a flow chart of a method for generating a fm signal according to an embodiment of the present application;

fig. 2 is a schematic flow chart of another frequency modulation signal generation according to an embodiment of the present application;

figure 3 is a schematic block diagram of a method for generating a fm signal according to an embodiment of the present application,

FIG. 4 is a graph of amplitude of a real signal of a FM signal according to an embodiment of the present application;

FIG. 5 is a graph of amplitude of an imaginary signal of a FM signal according to an embodiment of the present application;

FIG. 6 is a spectrum diagram of a FM signal according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a frequency modulation signal generating device according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.

The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In order to solve the technical problem of wideband linear frequency modulation signal generation under the condition of limited sampling rate in the prior art, the application provides a frequency modulation signal generation method and device.

Fig. 1 is a flow chart of a method for generating a frequency modulated signal according to an embodiment of the present application, as shown in fig. 1, where the method specifically includes:

s101, determining signal parameters of a preset frequency modulation signal;

the signal source of the linear frequency modulation signal can improve the resolution under the condition of not reducing the pulse width by using the analog echo signal generated by linear frequency modulation, and the linear frequency modulation signal is often expressed in a complex form. Before generating the chirp signal, it is necessary to select the waveform mode of the signal source as chirp and set the parameters of the signal source. The preset parameters may be a period, a signal bandwidth, a pulse width, a center frequency, a signal strength, and the like. For example, the signal source may be a signal generator.

The preset signal parameters of the frequency modulation signals are used for restraining the period, the signal bandwidth, the pulse width, the center frequency, the signal strength and the like of the linear frequency modulation digital signals, and the set parameters are not written in the FPGA codes and can be flexibly modified according to actual needs.

For example, based on an FPGA chip with a sampling frequency of 250M, the signal bandwidth is 700M, and the signal parameters b=700M, fs=250M, and t=5 μs are wideband chirp signals with a transmission time width of 5 μs;

s102, determining the number of signal interleaving units of the frequency modulation signal according to the signal parameters, and constructing a signal interleaving unit set conforming to the number of the signal interleaving units;

in the digital signal processing, signal interleaving represents processing burst errors, and the principle is that the original multi-bit data is scrambled, so that when burst errors occur, continuous multi-bit errors are avoided, and error bit data are scattered into the plurality of data, namely, 1-bit errors occur in the plurality of data, and then, single-bit errors can be easily corrected through forward error correction and other techniques, so that error-free transmission of the data is realized.

Further, signal interleaving is a process of rearranging the positions of data in a one-to-one correspondence to a data sequence, and may also be regarded as a data coding mode, where the inverse process is called deinterleaving, that is, the received data sequence is subjected to position restoration, so that the positions of the data sequence become a state before interleaving.

In this embodiment, by controlling the phase parameters of different interleaving units, wideband chirp signal generation at a low-rate sampling rate can be achieved, the number of units of signal interleaving is determined according to preset signal parameters, and then a signal interleaving set meeting the number of units is constructed, and further wideband chirp signals at a low-rate sampling rate are generated according to the constructed signal interleaving set, so that the problem that wideband chirp signals are difficult to generate due to limitation of sampling rates of an FPGA device in the prior art is solved.

S103, establishing a corresponding interleaving unit lookup table according to the signal interleaving unit set;

in this embodiment, in order to increase the signal processing speed, the signal interleaving unit is represented by a result of special calculation of the phase characteristics in the signal interleaving unit set, and a corresponding interleaving unit lookup table is created.

Typically, the exponential factor of the fm signal is complex, expressed as f (t) =ke ^st S=σ+jw. According to the Euler equation, a complex exponential signal can be divided into real and imaginary parts (e ^iθ =cos θ+isinθ), the real part contains the cosine signal, and the imaginary part is the sine signal.

Furthermore, the embodiment obtains the cosine value and the sine value according to the phase information of the signal interleaving unit, establishes a corresponding interleaving unit lookup table, and lays a foundation for further conversion generation of the frequency modulation signal.

S104, obtaining the frequency modulation signal through signal conversion by utilizing the interleaving unit lookup table.

According to the principle of Fourier series, the periodic function can be expanded into an infinite series composed of a sine function and a cosine function, and any non-simple harmonic alternating current can be decomposed into a series of simple harmonic sine and cosine alternating currents for synthesis. Conversely, the sine signal and the cosine signal can be synthesized into a series of linear frequency modulation signals formed by simple harmonic sine and cosine alternating current.

In this embodiment, the interleaving unit lookup table is used to obtain a sine signal and a cosine signal, and the two signals are integrated based on the correlation between the sine signal and the cosine signal to obtain a frequency modulation signal. The period of the linear frequency modulation signal is formed by superposing sine waves and cosine waves of the sine signal and the cosine signal.

According to the frequency modulation signal generation method provided by the embodiment of the invention, the signal parameters of the preset frequency modulation signal are determined according to the signal requirements; then determining the number of signal interleaving units of the frequency modulation signal according to the signal parameters, and constructing a signal interleaving unit set conforming to the number of the signal interleaving units; and further establishing a corresponding interleaving unit lookup table according to the signal interleaving unit set, and obtaining a frequency modulation signal through signal conversion by utilizing the interleaving unit lookup table. By adopting a signal interleaving technology, through calculating the initial phase and the phase increment of signal frequency points of each interleaving unit, each interleaving unit is generated in parallel at the existing clock rate, and generates a broadband linear frequency modulation signal with continuous phase in real time through parallel-serial conversion, so that the problem of generating the broadband linear frequency modulation signal under the condition of limited sampling rate is solved, and the bandwidth of the frequency modulation signal can be set automatically.

In an alternative aspect of the embodiment of the present invention, the signal parameters include a signal bandwidth, a signal transmission time width, and a signal chirp frequency;

in this embodiment, the attribute information of the output fm signal is determined by using the signal wideband, the signal transmission time width and the signal chirp frequency settings in the signal parameters, and in the specific implementation, other parameters or parameter combinations of the signal parameters may be flexibly adjusted according to the requirements of the fm signal.

The determining the number of signal interleaving units of the frequency modulation signal according to the signal parameter comprises the following steps:

setting a Field Programmable Gate Array (FPGA) sampling frequency fs corresponding to a preset frequency modulation signal;

determining the number N of signal interleaving units of the frequency modulation signal according to the FPGA sampling frequency fs and the signal bandwidth B;

wherein,

in this embodiment, the minimum integer satisfying the condition is used as the number N of signal interleaving units.

In an optional implementation manner of the embodiment of the present invention, the creating a corresponding interleaving unit lookup table according to the signal interleaving unit set includes:

acquiring initial phases and phase increment of each signal interleaving unit in a signal interleaving unit set;

and transmitting the initial phase and the phase increment corresponding to each signal interleaving unit to the FPGA, and establishing an interleaving unit lookup table in the FPGA according to the initial phase and the phase increment.

In the embodiment, two-stage initial phases and two-stage phase increment of each interleaving unit are calculated; quantizing the calculated parameters, namely quantizing the floating point number form of the initial phase and the phase increment into fixed point numbers, for example, using 12.715 to represent the floating point number by a 12bit integer, wherein the integer part 12 at least needs to use 4 bits, the decimal part is represented by 8 bits, 0.715 x 2 x 8= 183.04, is smaller than 256, and can be represented by 8 bits after rounding, namely, the decimal part 0.715 by 183 and the decimal part 12.715 can be represented by 12 x 2 x 8+183=3255; and issuing the quantized initial phase and phase increment fixed-point values to the FPGA through a hardware circuit interface by using upper computer software.

In an alternative aspect of the embodiment of the present invention, the obtaining the initial phase and the phase increment of each signal interleaving unit in the signal interleaving unit set includes:

invoking a phase expression of the signal interleaving unit;

the phase expression includes:

wherein,the method is characterized in that the method is a phase expression of a signal interleaving unit, K is signal chirp frequency, N is the number of the signal interleaving units, fs is the sampling frequency of an FPGA, t is a time variable, < >>T is the signal emission time width.

And determining initial phase values and phase increments of each signal interleaving unit in the signal interleaving unit set according to the phase expression.

For the ith interleaving unit, its phase expression

Wherein, N is the total number of interleaving units, fs is the sampling rate, the unit is Hz, i=0, 1,2,, N-1;

initial phase of the ith signal

First-stage phase increment of ith signal

Second stage phase increment of ith signal

Schematically:

the initial phase of the second stage DDS of the 0 th path signal is as follows:

the initial phase of the second DDS of the ith signal is as follows:

the initial phase of the second DDS of the ith signal is as follows:

the specific calculation method of the phase increment is as follows:

the phase increment of each interleaving unit of the first stage DDS is as follows:the phase increment of the DDS of the second stage of the 0 th path signal is as follows:

the phase increment of the DDS of the second stage of the 1 st path signal is as follows:

the phase increment of the second stage DDS of the ith signal is as follows:

all above calculations normalize each parameter to [0,2 pi ].

In an alternative aspect of the embodiment of the present invention, the creating, at the FPGA, an interleaving unit lookup table according to an initial phase and a phase increment includes:

acquiring level information of each signal interleaving unit in a signal interleaving unit set;

sequentially acquiring real-time phases of all levels of signal interleaving units according to the level information, and acquiring sine values and cosine values between the real-time phases and phase increments of the signal interleaving units;

establishing an interleaving unit lookup table by utilizing sine values and cosine values corresponding to each level of signal interleaving units;

the real-time phase of the adjacent next-stage signal interleaving unit in the signal interleaving unit set is the sum of the initial phase of the signal interleaving unit, the real-time phase of the previous-stage signal interleaving unit and the delay phase of the previous-stage signal interleaving unit.

In this embodiment, the output phase of the first-stage signal interleaving unit is obtained by continuously accumulating the set initial phase and the set phase increment; the output phase of the second-stage signal interleaving unit is determined by the initial phase, and when the first-stage signal interleaving unit outputs, the input of the second-stage signal interleaving unit is obtained by accumulating the output phase of the first-stage signal interleaving unit, the input initial phase of the second-stage signal interleaving unit and the output phase delay value of the first-stage signal interleaving unit.

Specifically, the initial phase and the phase increment of a first-stage signal interleaving unit in the signal interleaving unit set are accumulated to obtain a real-time phase value of the first-stage signal interleaving unit, the real-time phase of a second-stage signal interleaving unit is the real-time phase value of the second-stage signal interleaving unit, which is obtained by adding the initial phase of the second-stage signal interleaving unit to the real-time phase value output by the first-stage initial phase and the first-stage output phase delayed by one clock cycle value, and the real-time phase value of the first-stage initial phase is obtained by adding the first-stage initial phase to the real-time phase value output by the first-stage output phase and the first-stage output phase delayed by one clock cycle value, which is obtained by adding the phase delay of the first-stage initial phase and the first-stage output phase delayed by one clock cycle value, and the phase delay of the first-stage output phase is obtained by adding the first-stage output phase delay of the first-stage output phase to be obtained by one clock cycle value, and the real-time phase of the second-stage signal interleaving unit and the phase increment of the second-stage signal interleaving unit is used for calculating the sine/cosine value, and the sine value of each signal interleaving unit is obtained by such a lookup table; real and imaginary values of each interleaving unit are obtained in real time through a lookup table.

Fig. 2 is a flow chart of another method for generating a fm signal according to an embodiment of the present application, as shown in fig. 2, where the method specifically includes:

s201, converting each signal interleaving unit in an interleaving unit lookup table into a corresponding interleaving signal;

specifically, corresponding analog signals are generated according to the sine/cosine values calculated by each signal interleaving unit in the interleaving unit lookup table, and the analog signals are converted into digital signals to generate corresponding sine signals and cosine signals.

S202, splicing all levels of interleaving signals according to the level information of the signal interleaving units in the interleaving unit lookup table to obtain broadband linear frequency modulation signals.

In the embodiment, sine signals and cosine signals of each signal interleaving unit are processed according to a pre-constructed triangle function integration sum-difference formula to obtain modulated sine wave signals and cosine wave signals; and determining the generation sequence of the digital signals according to the modulated sine wave signals and cosine wave signals and the level information of the signal interleaving units in the interleaving unit lookup table so as to obtain the linear frequency modulation signals.

Specifically, the real part signal and the imaginary part signal are alternately output by the FPGA control DAC chip according to the interleaving unit numbers, so that the phase of the frequency modulation signal output in real time is continuous.

According to the other frequency modulation signal generation method provided by the embodiment of the invention, the generation of the multipath parallel linear frequency modulation signals is realized, and the bandwidth of the interleaved broadband linear frequency modulation signals can break through the limitation of the clock rate of an FPGA device through phase regulation; the broadband linear frequency modulation signal generated in real time is flexible and controllable, and the two-stage DDS module is adopted, wherein the output phase of the first-stage DDS module is obtained through phase accumulation, the phase increment of the second-stage DDS and the delay of the output phase of the first-stage DDS jointly form the input phase of the second-stage DDS, the real part signal and the imaginary part signal of each interleaving unit are obtained through the lookup table of the second-stage DDS, the structure is simpler, external storage resources are not used, the resource consumption is reduced, and the reliability of the design is improved.

In an alternative aspect of the embodiment of the present invention, the converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal includes:

converting each level of signal interleaving units into an interleaving signal by using an interleaving unit lookup table, wherein the interleaving signal comprises a real part signal and an imaginary part signal;

the sine value of the signal interleaving unit in the interleaving unit lookup table is converted into a real part signal of the interleaving signal, and the cosine value is converted into an imaginary part signal of the interleaving signal unit.

In this embodiment, the real part and the imaginary part of each interleaved signal are calculated by using a "DDS Compiler" algorithm core, the real part of the output signal is the cosine value of the second-stage "DDS Compiler" algorithm core lookup table, the imaginary part is the sine value of the "DDS Compiler" algorithm core lookup table,

when needed, the phase input quantized bit width setting of the interleaved signal is consistent with the quantized bit width of the initial phase and phase increment fixed point values.

Fig. 3 is a schematic block diagram of a method for generating a fm signal according to an embodiment of the present application, as shown in fig. 3:

the FPGA is internally mainly of a two-stage DDS structure, and the first-stage DDS (DDS 1) is continuously accumulated through the set initial phase and the set phase increment to obtain the output phase of the DDS 1; the output phase of the second stage DDS (DDS 2) is determined by the initial phase, and when the DDS1 is output, the input of the DDS2 is obtained by accumulating the output phase of the DDS1, the input phase of the DDS2 and the delay value of the output phase of the DDS 1; the sine value output by the lookup table of the DDS2 is an imaginary signal, and the cosine value output by the lookup table is a real signal; and finally obtaining the broadband linear frequency modulation signal through a parallel-serial conversion module.

As shown in fig. 4 to 6, the signal bandwidth is 700M, the real part signal and the imaginary part signal of the wideband chirp signal with the transmission time width of 5 μs are serially and alternately output by the parallel-serial conversion module, and the frequency modulation signal with continuous phase is output in real time.

Fig. 7 is a schematic structural diagram of a frequency-modulated signal generating device according to an embodiment of the present application, as shown in fig. 7, specifically including:

the upper computer module 301 is configured to set signal parameters of a preset fm signal;

the set construction module 302 is configured to determine the number of signal interleaving units of the frequency modulated signal according to the signal parameter, and construct a set of signal interleaving units that conforms to the number of signal interleaving units;

a look-up table establishing module 303, configured to establish a corresponding interleaving unit look-up table according to the signal interleaving unit set;

the digital-to-analog conversion module 304 is configured to obtain a frequency modulated signal by signal conversion using the interleaving unit lookup table.

In an alternative aspect of the embodiment of the present invention, the frequency modulation signal generating device further includes:

a DDS module 305 (not shown in the figure) for converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal;

the signal synthesis module 306 (not illustrated in the figure) is configured to splice each level of interleaved signal according to the level information of the signal interleaving unit in the interleaving unit lookup table to obtain a wideband chirp signal.

In one possible implementation manner, the upper computer module 301 is specifically configured to set a field programmable gate array FPGA sampling frequency fs corresponding to a preset fm signal; determining the number N of signal interleaving units of the frequency modulation signal according to the FPGA sampling frequency fs and the signal bandwidth B; wherein,

in one possible implementation manner, the look-up table establishing module 303 is specifically configured to obtain an initial phase and a phase increment of each signal interleaving unit in the signal interleaving unit set; and transmitting the initial phase and the phase increment corresponding to each signal interleaving unit to the FPGA, and establishing an interleaving unit lookup table in the FPGA according to the initial phase and the phase increment.

In a possible implementation manner, the lookup table establishing module 303 is further specifically configured to invoke a phase expression of the signal interleaving unit; and determining initial phase values and phase increments of each signal interleaving unit in the signal interleaving unit set according to the phase expression.

In a possible implementation manner, the lookup table establishing module 303 is further specifically configured to obtain level information of each signal interleaving unit in the signal interleaving unit set; sequentially acquiring real-time phases of all levels of signal interleaving units according to the level information, and acquiring sine values and cosine values between the real-time phases and phase increments of the signal interleaving units; establishing an interleaving unit lookup table by utilizing sine values and cosine values corresponding to each level of signal interleaving units; the real-time phase of the adjacent next-stage signal interleaving unit in the signal interleaving unit set is the sum of the initial phase of the signal interleaving unit, the real-time phase of the previous-stage signal interleaving unit and the delay phase of the previous-stage signal interleaving unit.

In one possible implementation manner, the DDS module 305 is specifically configured to convert each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal; and according to the level information of the signal interleaving units in the interleaving unit lookup table, splicing all levels of interleaving signals to obtain the broadband linear frequency modulation signal.

In a possible implementation manner, the DDS module 305 is specifically further configured to convert each level of signal interleaving units into an interleaved signal by using an interleaving unit lookup table, where the interleaved signal includes a real signal and an imaginary signal; the sine value of the signal interleaving unit in the interleaving unit lookup table is converted into a real part signal of the interleaving signal, and the cosine value is converted into an imaginary part signal of the interleaving signal unit.

The fm signal generating apparatus provided in this embodiment may be the fm signal generating apparatus shown in fig. 7, and may perform all the steps of fm signal generation shown in fig. 1-6, so as to achieve the technical effects of fm signal generation shown in fig. 1-6, and the detailed description will be omitted herein for brevity.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the respective embodiments or some parts of the embodiments.

It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method of generating a frequency modulated signal, comprising:

determining signal parameters of a preset frequency modulation signal;

determining the number of signal interleaving units of the frequency modulation signal according to the signal parameters, and constructing a signal interleaving unit set conforming to the number of the signal interleaving units;

establishing a corresponding interleaving unit lookup table according to the signal interleaving unit set;

and obtaining the frequency modulation signal through signal conversion by using the interleaving unit lookup table.

2. The method of claim 1, wherein the signal parameters include signal bandwidth, signal transmission time width, signal chirp frequency;

the determining the number of signal interleaving units of the frequency modulation signal according to the signal parameter comprises the following steps:

setting a Field Programmable Gate Array (FPGA) sampling frequency fs corresponding to a preset frequency modulation signal;

determining the number N of signal interleaving units of the frequency modulation signal according to the FPGA sampling frequency fs and the signal bandwidth B;

wherein,

3. the method of claim 1, wherein said building a corresponding interleaving unit lookup table from the set of signal interleaving units comprises:

acquiring initial phases and phase increment of each signal interleaving unit in a signal interleaving unit set;

and transmitting the initial phase and the phase increment corresponding to each signal interleaving unit to the FPGA, and establishing an interleaving unit lookup table in the FPGA according to the initial phase and the phase increment.

4. The method of claim 3, wherein the obtaining initial phases and phase increments for each signal interleaving unit in the set of signal interleaving units comprises:

invoking a phase expression of the signal interleaving unit;

and determining initial phase values and phase increments of each signal interleaving unit in the signal interleaving unit set according to the phase expression.

5. The method of claim 4, wherein the phase expression of the signal interleaving unit comprises:

wherein,the method is characterized in that the method is a phase expression of a signal interleaving unit, K is signal chirp frequency, N is the number of the signal interleaving units, fs is the sampling frequency of an FPGA, t is a time variable, < >>T is the signal emission time width.

6. The method of claim 5, wherein the creating, at the FPGA, an interleaving unit lookup table based on initial phases and phase increments, comprises:

acquiring level information of each signal interleaving unit in a signal interleaving unit set;

sequentially acquiring real-time phases of all levels of signal interleaving units according to the level information, and acquiring sine values and cosine values between the real-time phases and phase increments of the signal interleaving units;

establishing an interleaving unit lookup table by utilizing sine values and cosine values corresponding to each level of signal interleaving units;

the real-time phase of the adjacent next-stage signal interleaving unit in the signal interleaving unit set is the sum of the initial phase of the signal interleaving unit, the real-time phase of the previous-stage signal interleaving unit and the delay phase of the previous-stage signal interleaving unit.

7. The method of claim 1, wherein said converting the signals using said interleaving unit lookup table to obtain frequency modulated signals comprises:

converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal;

and according to the level information of the signal interleaving units in the interleaving unit lookup table, splicing all levels of interleaving signals to obtain the broadband linear frequency modulation signal.

8. The method of claim 7, wherein converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal, comprises:

converting each level of signal interleaving units into an interleaving signal by using an interleaving unit lookup table, wherein the interleaving signal comprises a real part signal and an imaginary part signal;

the sine value of the signal interleaving unit in the interleaving unit lookup table is converted into a real part signal of the interleaving signal, and the cosine value is converted into an imaginary part signal of the interleaving signal unit.

9. A frequency modulated signal generating apparatus, comprising:

the upper computer module is used for setting signal parameters of preset frequency modulation signals;

the set construction module is used for determining the number of signal interleaving units of the frequency modulation signal according to the signal parameters and constructing a signal interleaving unit set conforming to the number of the signal interleaving units;

the lookup table establishing module is used for establishing a corresponding interleaving unit lookup table according to the signal interleaving unit set;

and the digital-to-analog conversion module is used for obtaining the frequency modulation signal through signal conversion by utilizing the interleaving unit lookup table.

10. The apparatus as recited in claim 9, further comprising:

the DDS module is used for converting each signal interleaving unit in the interleaving unit lookup table into a corresponding interleaving signal;

and the signal synthesis module is used for splicing all levels of interleaving signals according to the level information of the signal interleaving units in the interleaving unit lookup table to obtain broadband linear frequency modulation signals.