CN117672340A - One-time programmable automatic chip system verification method, device and terminal - Google Patents
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Abstract
The invention provides a one-time programmable automatic chip system verification method, a device and a terminal, which are used for generating a closing bit information input file through an OTP memory design document of a current version, generating test data of closing bits of all modules to carry out OTP chip system verification based on the closing bit information input file when the OTP memory design document is an initial version, and determining closing bit information of the closing bits of each module which is changed based on the closing bit information input file of a previous version and the current version when the OTP memory design document is a non-initial version to obtain the test data of the closing bits of all modules to carry out OTP chip system verification. The invention can extract effective information from complex design documents, and generate a large number of repeated test cases and test platform codes according to the extracted information. And for the middle design version, the test case and the test platform code segment are generated by extracting the OTP change item in the design document, so that the test case and the test platform can be automatically generated no matter the design is the initial version or the middle change version, the system verification time of the OTP in the project is shortened, and the verification accuracy is greatly improved.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a one-time programmable automatic chip system verification method, device and terminal.
Background
The digital chip has a memory for storing key information and closing enable item for chip production and test. These important information requirements can only be written once. This type of information is called OTP (one time program) memory. The system verification of the existing chip is that OTP verification is carried out according to different released design versions, and each version has different OTP content items. Some content items are often deleted, even changed from the original location to a new location, 96 items or more. Each release version requires a one-by-one check of the change content, and then manually change the test cases and test platforms. Therefore, each design version is released, the same work is needed, time and labor are wasted, errors are easy to occur in the process of changing various programs, and the chip verification is insufficient.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a one-time programmable automatic chip system verification method, device and terminal for solving the above problems of the prior art.
To achieve the above and other related objects, the present invention provides a one-time programmable automatic chip system verification method, the method comprising: generating a corresponding closing bit information input file based on the issued OTP memory design document of the current version; wherein the closing bit information input file includes: closing bit information of closing bits of all modules in the OTP memory design document of the current version; if the current version is the initial version, generating test data of all module closing bits corresponding to the current version based on the corresponding closing bit information input file for verification of the OTP chip system; wherein the test data comprises: test cases and test platform codes; if the current version is a non-initial version, determining a changed module closing bit based on the closing bit information input file corresponding to the previous version and the current version respectively, and obtaining test data of all the module closing bits corresponding to the current version based on the closing bit information of each changed module closing bit so as to verify the chip system of the OTP.
In an embodiment of the present invention, the generating the corresponding shutdown bit information input file based on the issued current version of the OTP memory design document includes: extracting closing bit names, offset addresses and bit information of closing bits of all modules in the OTP memory design document of the current version; the closing bit name, the offset address and the bit information of each module closing bit are respectively stored as closing bit information of each module closing bit, and a closing bit information input file is generated; the closing bit information of the closing bit of each module is stored to different lines of the closing bit information input file, and two space bits are stored at intervals among closing bit names, offset addresses and bit information in the closing bit information of each module.
In one embodiment of the present invention, the extracting the closing bit names, offset addresses and bit information of all the module closing bits in the OTP memory design document of the current version includes: and respectively taking all non-empty elements in the OTP memory design document of the current version as module closing bits, extracting the name of each non-empty element as the closing bit name of the corresponding module closing bit, and respectively extracting column information and row information corresponding to each non-empty element as offset addresses and bit information of the corresponding module closing bit.
In an embodiment of the present invention, comparing the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the current version with the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the previous version, and obtaining the closing bit information of each of the closing bits of the modules which is changed includes: each row in the closing bit information input file corresponding to the current version is respectively compared with all rows in the closing bit information input file corresponding to the previous version; if the closing bit information input files corresponding to the current version and the previous version have rows with the same closing bit name and the same offset address and bit information, marking the corresponding row of the closing bit information input file of the current version as an unmodified row; if the closing bit information input files corresponding to the current version and the previous version have rows with the same closing bit name and different offset addresses and/or bit information, the corresponding row of the closing bit information input file of the current version is marked as a change row; if the closing bit information input file corresponding to the current version has the row with completely different contents in the closing bit information input file corresponding to the previous version, marking the row with completely different contents in the closing bit information input file corresponding to the current version as a newly added row; and traversing all lines of the file through marked closing bit information of the current version, acquiring closing bit information of closing bits of modules of each line marked as a changed line, and acquiring closing bit information of closing bits of modules of each line marked as a newly increased line.
In an embodiment of the present invention, the generating test data corresponding to each changed module close bit based on the changed module close bit information includes: generating a test case and a test platform code of the newly added module closing bit based on the closing bit information of the newly added module closing bit in the closing bit information of the changed module closing bit; and generating a test case of the changed module closing bit based on the closing bit information of the changed module closing bit in the closing bit information of the changed module closing bit.
In an embodiment of the present invention, updating the test data of all the module closing bits corresponding to the previous version based on the test data of each module closing bit that is changed, and obtaining the test data of all the module closing bits corresponding to the current version includes: and adding the test cases of the newly added module closing bits and the test platform codes into the test data corresponding to the previous version, and replacing the test cases of the changed module closing bits with the test cases of the corresponding module closing bits of the previous version to obtain the test data of all the module closing bits corresponding to the current version.
In an embodiment of the present invention, the method for generating test data includes: corresponding test data is generated by replacing code critical locations of the fixed code template with closure bit information corresponding to the module closure bits.
In one embodiment of the invention, the scikit-learn module in python is used to construct a genetic relationship identification model.
To achieve the above and other related objects, the present invention provides a one-time programmable automatic chip system verification system, the system comprising: the closing bit information extraction module is used for generating a corresponding closing bit information input file based on the issued OTP memory design document of the current version; wherein the closing bit information input file includes: closing bit information of closing bits of all modules in the OTP memory design document of the current version; the initial version test data generation module is connected with the closing bit information extraction module and is used for generating test data of all module closing bits corresponding to the current version based on the corresponding closing bit information input file under the condition that the current version is the initial version so as to carry out chip system verification of the OTP; wherein the test data comprises: test cases and test platform codes; and the non-initial version test data generation module is connected with the closing bit information extraction module and is used for determining a changed module closing bit based on the closing bit information input file corresponding to the previous version and the current version respectively under the condition that the current version is the non-initial version, and obtaining test data of all the closing bits of the modules corresponding to the current version based on the closing bit information of the closing bits of the modules which are changed, so as to verify a chip system of the OTP.
To achieve the above and other related objects, the present invention provides a one-time programmable automation chip system verification terminal, comprising: one or more memories and one or more processors; the one or more memories are used for storing computer programs; the one or more processors are coupled to the memory for running the computer program to perform the one-time programmable automation chip system-oriented verification method.
As described above, the invention is a one-time programmable automatic chip system verification method, device and terminal, which has the following beneficial effects: the invention generates the closing bit information input file through the OTP memory design file of the current version, generates the test data of all the closing bits of the modules of the current version to carry out OTP chip system verification based on the closing bit information input file when the current version is the initial version, and determines the closing bit information of all the closing bits of the modules which are changed based on the closing bit information input file of the previous version and the current version when the current version is the non-initial version to obtain the test data of all the closing bits of the modules of the current version to carry out OTP chip system verification. The invention can extract effective information from complex design documents, and generate a large number of repeated test cases and test platform codes according to the extracted information. And for the middle design version, the test case and the test platform code segment are generated by extracting the OTP change item in the design document, so that the test case and the test platform can be automatically generated no matter the design is the initial version or the middle change version, the system verification time of the OTP in the project is shortened, and the verification accuracy is greatly improved.
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Fig. 1 is a flow chart of a one-time programmable automatic chip system verification method according to an embodiment of the invention.
FIG. 2 is a flow chart showing a method for obtaining test data of all module off bits corresponding to a non-initial version of the present invention.
Fig. 3 is a schematic structural diagram of an otp automatic chip system verification device according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of a one-time programmable automation chip system verification terminal according to an embodiment of the invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
In the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "above," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures relative to another element or feature.
Throughout the specification, when a portion is said to be "connected" to another portion, this includes not only the case of "direct connection" but also the case of "indirect connection" with other elements interposed therebetween. In addition, when a certain component is said to be "included" in a certain section, unless otherwise stated, other components are not excluded, but it is meant that other components may be included.
The first, second, and third terms are used herein to describe various portions, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one portion, component, region, layer or section from another portion, component, region, layer or section. Thus, a first portion, component, region, layer or section discussed below could be termed a second portion, component, region, layer or section without departing from the scope of the present invention.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
The invention provides a one-time programmable automatic chip system verification method, which is characterized in that a closing bit information input file is generated through an OTP memory design file of a current version, test data of closing bits of all modules of the current version are generated based on the closing bit information input file to carry out OTP chip system verification when the current version is an initial version, and closing bit information of closing bits of all modules which are changed is determined based on the previous version and the closing bit information input file of the current version when the current version is a non-initial version, so that the test data of closing bits of all modules of the current version are obtained to carry out OTP chip system verification. The invention can extract effective information from complex design documents, and generate a large number of repeated test cases and test platform codes according to the extracted information. And for the middle design version, the test case and the test platform code segment are generated by extracting the OTP change item in the design document, so that the test case and the test platform can be automatically generated no matter the design is the initial version or the middle change version, the system verification time of the OTP in the project is shortened, and the verification accuracy is greatly improved.
The embodiments of the present invention will be described in detail below with reference to the attached drawings so that those skilled in the art to which the present invention pertains can easily implement the present invention. This invention may be embodied in many different forms and is not limited to the embodiments described herein.
Fig. 1 shows a flow chart of a one-time programmable automatic chip system verification method in an embodiment of the invention.
The method comprises the following steps:
step S1: a corresponding shutdown bit information input file is generated based on the published current version of the OTP memory design document.
In detail, the closing bit information input file includes: the shutdown bit information for all module shutdown bits in the current version of the OTP memory design document.
In one embodiment, step S1 includes:
extracting closing bit names, offset addresses and bit information of closing bits of all modules in the OTP memory design document of the current version; the OTP memory design document of the current version stores the closing bit names, offset addresses and bit information of all the closing bits of the modules corresponding to the current version.
The closing bit name, the offset address and the bit information of each module closing bit are respectively stored as closing bit information of each module closing bit, and a closing bit information input file is generated; the closing bit information of the closing bit of each module is stored to different lines of the closing bit information input file, and two space bits are stored at intervals among closing bit names, offset addresses and bit information in the closing bit information of each module. Specifically, all the extracted information is stored according to the closing bit name, the offset address and the bit information format, each row is a module closing bit, and three elements in each row are separated by a double space key.
In a specific embodiment, the extracting the closing bit name, the offset address and the bit information of all the module closing bits in the OTP memory design document of the current version includes: and respectively taking all non-empty elements in the OTP memory design document of the current version as module closing bits, extracting the name of each non-empty element as the closing bit name of the corresponding module closing bit, and respectively extracting column information and row information corresponding to each non-empty element as offset addresses and bit information of the corresponding module closing bit. Specifically, the OTP memory design document is an Excel document, and all module closing bit options in the OTP memory of the current version are stored in the Excel document; extracting offset addresses and bit information of all module closing bits in an Excel document; to realize the function of extracting offset addresses and bit information of all module closing bits in an Excel document, a library for processing the Excel is imported in a python script, and all non-empty elements in specified positions, namely pages, rows and columns, of the Excel are extracted as signal items, so that the corresponding column information is the offset addresses and the corresponding row information is the bit information.
Step S2: if the current version is the initial version, generating test data of all module closing bits corresponding to the current version based on the corresponding closing bit information input file for carrying out chip system verification of the OTP.
In detail, if the current version is the initial version and the previous version does not exist, the key bit information of all the module closing bits in the file is input based on the corresponding closing bit information, and test data of all the module closing bits corresponding to the current version are generated to perform OTP chip system verification; the test data includes: test cases and test platform code.
In one embodiment, the method for generating test data of all module closing bits corresponding to the current version based on the corresponding closing bit information input file includes: and respectively replacing key positions of the middle codes of the fixed code templates with closing bit names, offset addresses and bit information in closing bit information of all module closing bits of the closing bit information input file to respectively obtain macro definition and test platform code fragments used by corresponding module closing bit test cases, and then operating the test cases of the module closing bits to finish chip system verification of OTP under a chip system verification environment.
Step S3: if the current version is a non-initial version, determining a changed module closing bit based on the closing bit information input file corresponding to the previous version and the current version respectively, and obtaining test data of all the module closing bits corresponding to the current version based on the closing bit information of each changed module closing bit so as to verify the chip system of the OTP.
In detail, if the current version is a non-initial version, there is a previous version, the changed module closing bit is determined based on key bit information of the module closing bit in the module closing bit information input file corresponding to the previous version and the current version, and test data of all module closing bits corresponding to the current version is obtained based on closing bit information of each changed module closing bit, so as to be used for verifying the chip system of the OTP.
In one embodiment, as shown in fig. 2, step S3 includes:
step S31: comparing the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the current version with the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the previous version based on the written python program to obtain the closing bit information of each changed closing bit of the modules; wherein, the closing bit information of each module closing bit changed comprises: the closing bit information of the closing bit of each newly added module and/or the closing bit information of the closing bit of each changed module;
step S32: generating test data corresponding to the changed module closing bits based on the closing bit information of the changed module closing bits;
Step S33: and updating the test data of all the module closing bits corresponding to the previous version based on the test data of each changed module closing bit to obtain the test data of all the module closing bits corresponding to the current version, and then running the test cases of each module closing bit in a chip system verification environment to complete the chip system verification of the OTP.
In an embodiment, because the closing bit information of the closing bits of each module of each version is located in different rows of the closing bit information input file, the closing bit information of the closing bits of all modules in the closing bit information input file corresponding to the current version is compared with the closing bit information of the closing bits of all modules in the closing bit information input file corresponding to the previous version, so as to obtain the closing bit information of the closing bits of each module which is changed:
through the programmed python program, adopting a forced enumeration method, respectively comparing each row in the closing bit information input file corresponding to the current version with all rows in the closing bit information input file corresponding to the previous version;
if the closing bit information input files corresponding to the current version and the previous version have the same closing bit names and the offset addresses and the same bit information, the current version and the previous version are provided with the closing bit of the module, and the content is unchanged, the corresponding row of the closing bit information input file of the current version is marked as an unchanged row, and the corresponding row is deleted from the closing bit information input file corresponding to the previous version.
If the closing bit information input files corresponding to the current version and the previous version have rows with the same closing bit name and different offset addresses and/or bit information, the current version and the previous version are provided with the closing bit of the module, but the content changes, and the corresponding row of the closing bit information input file of the current version is marked as a changing row.
If the closing bit information input file corresponding to the current version exists a row with completely different contents of each row in the closing bit information input file corresponding to the previous version, which indicates that the closing bit of the module does not exist in the previous version and only exists in the current version, the closing bit information input file corresponding to the current version is the closing bit content which is newly added, and the row with completely different contents corresponding to the closing bit information input file corresponding to the current version is marked as the newly added row;
if the closing bit information input file corresponding to the previous version exists a row with completely different contents of each row in the closing bit information input file corresponding to the current version, which indicates that the closing bit of the module does not exist in the current version and only exists in the previous version, and the closing bit information input file corresponding to the previous version is deleted closing bit content, the row with completely different contents of the closing bit information input file corresponding to the previous version is marked as a deleted row; but the delete item does not generate test data and is therefore not considered here.
And traversing all lines of the file through marked closing bit information of the current version, acquiring closing bit information of closing bits of modules of each line marked as a changed line, and acquiring closing bit information of closing bits of modules of each line marked as a newly increased line.
It should be noted that, all rows of the marked current version of the closing bit information input file and the rows corresponding to the previous version of the closing bit information input file which are not deleted may be traversed, the changed closing bit of the module may be determined, and closing bit information of the closing bit of each module and/or closing bit information of the closing bit of each module which is changed may be obtained from the current version of the closing bit information input file.
In one embodiment, the generating test data corresponding to the changed module shutdown bit based on the shutdown bit information of the changed module shutdown bit includes:
generating a test case and a test platform code of the newly added module closing bit based on the closing bit information of the newly added module closing bit in the closing bit information of the changed module closing bit; specifically, the key positions of the middle codes of the fixed code templates are respectively replaced by closing bit names, offset addresses and bit information in closing bit information of the newly added module closing bits, and macro definitions and test platform code fragments used by test cases corresponding to the newly added closing bits of each module are respectively obtained;
Generating a test case of the changed module closing bit based on the closing bit information of the changed module closing bit in the closing bit information of the changed module closing bit; specifically, the key positions of the middle codes of the fixed code template are replaced by the closing bit names, offset addresses and bit information in the closing bit information of the changed closing bits of the modules respectively, and test cases corresponding to the closing bits of the modules which are newly added are obtained respectively.
In an embodiment, the updating the test data of all the module closing bits corresponding to the previous version based on the test data of each module closing bit that is changed, and obtaining the test data of all the module closing bits corresponding to the current version includes:
and adding the test cases of the newly added module closing bits and the test platform codes into the test data corresponding to the previous version, and replacing the test cases of the changed module closing bits with the test cases of the corresponding module closing bits of the previous version to obtain the test data of all the module closing bits corresponding to the current version.
Similar to the principles of the embodiments described above, the present invention provides a one-time programmable automated system-on-chip verification device.
Specific embodiments are provided below with reference to the accompanying drawings:
Fig. 3 shows a schematic structural diagram of a one-time programmable automatic chip system verification device in an embodiment of the invention.
The system comprises:
the closing bit information extraction module 1 is used for generating a corresponding closing bit information input file based on the issued OTP memory design document of the current version; wherein the closing bit information input file includes: closing bit information of closing bits of all modules in the OTP memory design document of the current version;
the initial version test data generation module 2 is connected with the closing bit information extraction module 1 and is used for generating test data of all module closing bits corresponding to the current version based on the corresponding closing bit information input file under the condition that the current version is the initial version so as to carry out chip system verification of the OTP; wherein the test data comprises: test cases and test platform codes;
and the non-initial version test data generation module 3 is connected with the closing bit information extraction module 1 and is used for determining a changed module closing bit based on the closing bit information input file corresponding to the previous version and the current version respectively under the condition that the current version is the non-initial version, and obtaining test data of all the module closing bits corresponding to the current version based on the closing bit information of each changed module closing bit so as to verify the chip system of the OTP.
The one-time programmable automatic chip system-oriented verification device can extract effective information from complicated design documents, and generates a large number of repeated test cases and test platform codes according to the extracted information. The OTP verification time in the chip system verification is greatly shortened. The method can also be extended to other fields of text processing and code generation.
It should be noted that, it should be understood that the division of the modules in the embodiment of the system of fig. 3 is merely a division of logic functions, and may be fully or partially integrated into a physical entity or may be physically separated. And these units may all be implemented in the form of software calls through the processing element; or can be realized in hardware; the method can also be realized in a form that a part of units are called by processing elements to be software, and the other part of units are realized in a form of hardware.
Since the implementation principle of the one-time programmable automatic chip system verification device has been described in the foregoing embodiments, a repeated description is omitted herein.
In one embodiment, the closing bit information extracting module 1 is configured to extract closing bit names, offset addresses and bit information of closing bits of all modules in the OTP memory design document of the current version; the closing bit name, the offset address and the bit information of each module closing bit are respectively stored as closing bit information of each module closing bit, and a closing bit information input file is generated; the closing bit information of the closing bit of each module is stored to different lines of the closing bit information input file, and two space bits are stored at intervals among closing bit names, offset addresses and bit information in the closing bit information of each module.
In one embodiment, the extracting the closing bit names, offset addresses, and bit information of all module closing bits in the current version of the OTP memory design document includes: and respectively taking all non-empty elements in the OTP memory design document of the current version as module closing bits, extracting the name of each non-empty element as the closing bit name of the corresponding module closing bit, and respectively extracting column information and row information corresponding to each non-empty element as offset addresses and bit information of the corresponding module closing bit.
In an embodiment, the initial version test data generating module 3 is configured to compare, based on a written python program, closing bit information of closing bits of all modules in the closing bit information input file corresponding to the current version with closing bit information of closing bits of all modules in the closing bit information input file corresponding to the previous version, and obtain closing bit information of closing bits of each module that is changed; wherein, the closing bit information of each module closing bit changed comprises: the closing bit information of the closing bit of each newly added module and/or the closing bit information of the closing bit of each changed module; generating test data corresponding to the changed module closing bits based on the closing bit information of the changed module closing bits; and updating the test data of all the module closing bits corresponding to the previous version based on the test data of each changed module closing bit to obtain the test data of all the module closing bits corresponding to the current version.
In an embodiment, comparing the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the current version with the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the previous version, and obtaining the closing bit information of each of the closing bits of the modules with the changed closing bit information includes: each row in the closing bit information input file corresponding to the current version is respectively compared with all rows in the closing bit information input file corresponding to the previous version; if the closing bit information input files corresponding to the current version and the previous version have rows with the same closing bit name and the same offset address and bit information, marking the corresponding row of the closing bit information input file of the current version as an unmodified row; if the closing bit information input files corresponding to the current version and the previous version have rows with the same closing bit name and different offset addresses and/or bit information, the corresponding row of the closing bit information input file of the current version is marked as a change row; if the closing bit information input file corresponding to the current version has the row with completely different contents in the closing bit information input file corresponding to the previous version, marking the row with completely different contents in the closing bit information input file corresponding to the current version as a newly added row; and traversing all lines of the file through marked closing bit information of the current version, acquiring closing bit information of closing bits of modules of each line marked as a changed line, and acquiring closing bit information of closing bits of modules of each line marked as a newly increased line.
In one embodiment, the generating test data corresponding to the changed module shutdown bit based on the shutdown bit information of the changed module shutdown bit includes: generating a test case and a test platform code of the newly added module closing bit based on the closing bit information of the newly added module closing bit in the closing bit information of the changed module closing bit; and generating a test case of the changed module closing bit based on the closing bit information of the changed module closing bit in the closing bit information of the changed module closing bit.
In an embodiment, the updating the test data of all the module closing bits corresponding to the previous version based on the test data of each module closing bit that is changed, and obtaining the test data of all the module closing bits corresponding to the current version includes: and adding the test cases of the newly added module closing bits and the test platform codes into the test data corresponding to the previous version, and replacing the test cases of the changed module closing bits with the test cases of the corresponding module closing bits of the previous version to obtain the test data of all the module closing bits corresponding to the current version.
In one embodiment, the manner of generating test data includes: corresponding test data is generated by replacing code critical locations of the fixed code template with closure bit information corresponding to the module closure bits.
Referring to fig. 4, an optional hardware structure schematic diagram of a one-time programmable automation chip system verification terminal 400 provided by the embodiment of the invention is shown, where the terminal 400 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, and the like. The terminal 400 includes: at least one processor 401, a memory 402, at least one network interface 404, and a user interface 404. The various components in the device are coupled together by a bus system 405. It is understood that the bus system 405 is used to enable connected communications between these components. The bus system 405 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various buses are labeled as bus systems in fig. 4.
The user interface 404 may include, among other things, a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad, or touch screen, etc.
It is to be appreciated that memory 402 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), which serves as an external cache, among others. By way of example, and not limitation, many forms of RAM are available, such as static random Access Memory (SRAM, staticRandom Access Memory), synchronous static random Access Memory (SSRAM, synchronous Static RandomAccess Memory). The memory described by embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 402 in the embodiment of the present invention is used to store various kinds of data to support the operation of the terminal 400. Examples of such data include: any executable programs for operating on the terminal 400, such as an operating system 4021 and application programs 4022; the operating system 4021 contains various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application programs 4022 may include various application programs such as a media player (MediaPlayer), a Browser (Browser), and the like for implementing various application services. The one-time programmable automation chip system verification method provided by the embodiment of the invention can be contained in the application 4022.
The method disclosed in the above embodiment of the present invention may be applied to the processor 401 or implemented by the processor 401. The processor 401 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 401 or by instructions in the form of software. The processor 401 described above may be a general purpose processor, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. Processor 401 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. The general purpose processor 401 may be a microprocessor or any conventional processor or the like. The steps of the accessory optimization method provided by the embodiment of the invention can be directly embodied as the execution completion of the hardware decoding processor or the execution completion of the hardware and software module combination execution in the decoding processor. The software modules may be located in a storage medium having memory and a processor reading information from the memory and performing the steps of the method in combination with hardware.
In an exemplary embodiment, the terminal 400 may be implemented by one or more application specific integrated circuits (ASIC, application Specific Integrated Circuit), DSPs, programmable logic devices (PLD, programmable Logic Device), complex programmable logic devices (CPLD, complex Programmable LogicDevice) for performing the aforementioned methods.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by computer program related hardware. The aforementioned computer program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
In the embodiments provided herein, the computer-readable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
In summary, the one-time programmable automatic chip system verification method, the one-time programmable automatic chip system verification device and the terminal of the invention generate the closing bit information input file through the OTP memory design file of the current version, generate test data of closing bits of all modules of the current version to perform OTP chip system verification based on the closing bit information input file when the current version is the initial version, and determine closing bit information of closing bits of all modules which are changed based on the closing bit information input file of the previous version and the current version when the current version is the non-initial version to obtain the test data of closing bits of all modules of the current version to perform OTP chip system verification. The invention can extract effective information from complex design documents, and generate a large number of repeated test cases and test platform codes according to the extracted information. And for the middle design version, the test case and the test platform code segment are generated by extracting the OTP change item in the design document, so that the test case and the test platform can be automatically generated no matter the design is the initial version or the middle change version, the system verification time of the OTP in the project is shortened, and the verification accuracy is greatly improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.
Claims (10)
1. A one-time programmable automation chip system verification method, the method comprising:
generating a corresponding closing bit information input file based on the issued OTP memory design document of the current version; wherein the closing bit information input file includes: closing bit information of closing bits of all modules in the OTP memory design document of the current version;
if the current version is the initial version, generating test data of all module closing bits corresponding to the current version based on the corresponding closing bit information input file for verification of the OTP chip system; wherein the test data comprises: test cases and test platform codes;
if the current version is a non-initial version, determining a changed module closing bit based on the closing bit information input file corresponding to the previous version and the current version respectively, and obtaining test data of all the module closing bits corresponding to the current version based on the closing bit information of each changed module closing bit so as to verify the chip system of the OTP.
2. The one time programmable automated chip system verification method of claim 1, wherein generating the corresponding shutdown bit information input file based on the issued current version of the OTP memory design document comprises:
extracting closing bit names, offset addresses and bit information of closing bits of all modules in the OTP memory design document of the current version;
the closing bit name, the offset address and the bit information of each module closing bit are respectively stored as closing bit information of each module closing bit, and a closing bit information input file is generated; the closing bit information of the closing bit of each module is stored to different lines of the closing bit information input file, and two space bits are stored at intervals among closing bit names, offset addresses and bit information in the closing bit information of each module.
3. The one time programmable automation chip system verification method of claim 2, wherein the extracting the closing bit names, offset addresses and bit information of all module closing bits in the current version of OTP memory design document comprises:
and respectively taking all non-empty elements in the OTP memory design document of the current version as module closing bits, extracting the name of each non-empty element as the closing bit name of the corresponding module closing bit, and respectively extracting column information and row information corresponding to each non-empty element as offset addresses and bit information of the corresponding module closing bit.
4. The one-time programmable automation chip system verification method according to claim 2, wherein determining the changed module closing bit based on the closing bit information input file corresponding to the previous version and the current version, and obtaining test data of all the module closing bits corresponding to the current version based on the closing bit information of each changed module closing bit comprises:
comparing the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the current version with the closing bit information of all the closing bits of the modules in the closing bit information input file corresponding to the previous version based on the written python program to obtain the closing bit information of each changed closing bit of the modules; wherein, the closing bit information of each module closing bit changed comprises: the closing bit information of the closing bit of each newly added module and/or the closing bit information of the closing bit of each changed module;
generating test data corresponding to the changed module closing bits based on the closing bit information of the changed module closing bits;
and updating the test data of all the module closing bits corresponding to the previous version based on the test data of each changed module closing bit to obtain the test data of all the module closing bits corresponding to the current version.
5. The one-time programmable automation chip system verification method of claim 3, wherein comparing the shutdown bit information of all the module shutdown bits in the shutdown bit information input file corresponding to the current version with the shutdown bit information of all the module shutdown bits in the shutdown bit information input file corresponding to the previous version, and obtaining the shutdown bit information of each module shutdown bit that is changed comprises:
each row in the closing bit information input file corresponding to the current version is respectively compared with all rows in the closing bit information input file corresponding to the previous version;
if the closing bit information input files corresponding to the current version and the previous version have rows with the same closing bit name and the same offset address and bit information, marking the corresponding row of the closing bit information input file of the current version as an unmodified row;
if the closing bit information input files corresponding to the current version and the previous version have rows with the same closing bit name and different offset addresses and/or bit information, the corresponding row of the closing bit information input file of the current version is marked as a change row;
if the closing bit information input file corresponding to the current version has the row with completely different contents in the closing bit information input file corresponding to the previous version, marking the row with completely different contents in the closing bit information input file corresponding to the current version as a newly added row;
And traversing all lines of the file through marked closing bit information of the current version, acquiring closing bit information of closing bits of modules of each line marked as a changed line, and acquiring closing bit information of closing bits of modules of each line marked as a newly increased line.
6. The one time programmable automation chip system verification method of claim 4, wherein the generating test data corresponding to the changed module shutdown bits based on the changed module shutdown bit information includes:
generating a test case and a test platform code of the newly added module closing bit based on the closing bit information of the newly added module closing bit in the closing bit information of the changed module closing bit;
and generating a test case of the changed module closing bit based on the closing bit information of the changed module closing bit in the closing bit information of the changed module closing bit.
7. The one-time programmable automation chip system verification method of claim 4, wherein the updating the test data of all the module shutdown bits corresponding to the previous version based on the changed test data of each module shutdown bit to obtain the test data of all the module shutdown bits corresponding to the current version includes:
And adding the test cases of the newly added module closing bits and the test platform codes into the test data corresponding to the previous version, and replacing the test cases of the changed module closing bits with the test cases of the corresponding module closing bits of the previous version to obtain the test data of all the module closing bits corresponding to the current version.
8. The one time programmable automated system-on-chip verification method of claim 1 or 6, wherein the means for generating test data comprises:
corresponding test data is generated by replacing code critical locations of the fixed code template with closure bit information corresponding to the module closure bits.
9. A one-time programmable automation chip system-oriented verification device, the system comprising:
the closing bit information extraction module is used for generating a corresponding closing bit information input file based on the issued OTP memory design document of the current version; wherein the closing bit information input file includes: closing bit information of closing bits of all modules in the OTP memory design document of the current version;
the initial version test data generation module is connected with the closing bit information extraction module and is used for generating test data of all module closing bits corresponding to the current version based on the corresponding closing bit information input file under the condition that the current version is the initial version so as to carry out chip system verification of the OTP; wherein the test data comprises: test cases and test platform codes;
And the non-initial version test data generation module is connected with the closing bit information extraction module and is used for determining a changed module closing bit based on the closing bit information input file corresponding to the previous version and the current version respectively under the condition that the current version is the non-initial version, and obtaining test data of all the closing bits of the modules corresponding to the current version based on the closing bit information of the closing bits of the modules which are changed, so as to verify a chip system of the OTP.
10. A one-time programmable automation chip system oriented verification terminal, comprising: one or more memories and one or more processors;
the one or more memories are used for storing computer programs;
the one or more processors being connected to the memory for running the computer program to perform the method of any one of claims 1 to 8.
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