CN117672339A - Solid state disk main control testing method and device and computer readable storage medium - Google Patents

Abstract

The invention provides a method and a device for testing master control of a solid state disk and a computer readable storage medium, wherein the method comprises the following steps: receiving a main control signal from a flash memory controller through a first interface processing module, and generating an error signal when the received main control signal is abnormal, wherein the received main control signal comprises an operation command, an address and data; writing the received data into a data cache or reading the data from the data cache according to the address and the operation command in the received main control signal; and according to the operation command in the received main control signal, carrying out data movement between the data cache and the dynamic random access memory, carrying out data movement between the dynamic random access memory and a hard disk of an external host connected to the second interface processing module, and generating an error signal when the data movement is abnormal. The invention can conveniently locate the error of the flash memory controller in the solid state disk.

Description

Solid state disk main control testing method and device and computer readable storage medium

Technical Field

The present invention relates to the field of storage devices, and in particular, to a method and apparatus for testing a master control of a solid state disk, and a computer readable storage medium.

Background

The solid state disk is a relatively new data storage medium, and mainly comprises a main control unit and a FLASH memory chip (FLASH). In the solid state disk clock, the main control unit is used for controlling the flash memory chip to perform operations such as data reading and writing, and the host computer also performs data exchange and communication with the flash memory chip through the main control unit.

When designing the main control unit of the solid state disk, the test of the main control unit is an essential link. However, when testing the main control unit, it is difficult to intuitively observe and record information such as commands, addresses, flash states, read-write data and the like that the main control unit interacts with the flash memory chip. Therefore, when the master control unit has a problem, the positioning error flow is complex.

Disclosure of Invention

The invention aims to solve the technical problem that errors are difficult to locate when a main control unit of a solid state disk is tested, and provides a main control testing method and device of the solid state disk and a computer readable storage medium.

The technical scheme for solving the technical problems is that the invention provides a method for testing the main control of a solid state disk, which comprises the following steps:

receiving a main control signal from a flash memory controller through a first interface processing module, and generating an error signal when the received main control signal is abnormal, wherein the received main control signal comprises an operation command, an address and data;

writing the received data into a data cache or reading the data from the data cache according to the address and the operation command in the received main control signal;

and according to the operation command in the received main control signal, carrying out data movement between the data cache and the dynamic random access memory, carrying out data movement between the dynamic random access memory and a hard disk of an external host connected to the second interface processing module, and generating an error signal when the data movement is abnormal.

As a further improvement of the present invention, the generating an error signal when there is an abnormality in the master control signal received by the first interface processing module includes:

in the process that data is moved to a dynamic random access memory from the data cache or is moved to the data cache from the dynamic random access memory, if a main control signal received by the first interface processing module comprises an operation command, setting a first register;

the second interface processing module transmits the state information of the first register to an external host, and resets the first register by a first reset signal from the external host, which generates an error record when reading that the first register is set, and generates a first reset signal for resetting the first register.

As a further improvement of the present invention, the operation command includes a data storage command, and the generating of the error signal when there is an abnormality in the data movement includes:

setting a second register when the data after the write-in instruction received by the first interface processing module exceeds a page space;

the second interface processing module transmits the state information of the second register to an external host, and resets the second register by a second reset signal from the external host, which generates an error record when reading that the second register is set, and generates a second reset signal for resetting the second register.

As a further improvement of the present invention, the receiving, by the first interface processing module, the master control signal from the flash memory controller includes:

when the received main control signal is an operation command, analyzing the operation command according to a preset command set, and storing the operation command which is accurately analyzed into a sorting cache module;

and when the received main control signal is an address, storing the address into the sorting cache module and the cache controller, wherein the address in the sorting cache module is used for carrying out storage space allocation.

As a further improvement of the present invention, the writing data in the master signal to a data buffer or reading data from the data buffer according to the address and the operation command in the received master signal includes:

when the operation command is a data storage command, writing the data after the data storage command into a storage space allocated in the data cache by the cache controller according to the address;

and when the operation command is a data reading command, acquiring corresponding data from the data cache according to the address.

As a further improvement of the present invention, the data transfer between the data buffer and the dynamic random access memory and between the dynamic random access memory and the hard disk of the external host connected to the second interface processing module according to the operation command in the received master signal, includes:

according to the operation command stored in the sorting buffer module, data is moved between the data buffer and the dynamic random access memory;

generating a submitting queue and a finishing queue according to the operation command stored in the sorting buffer module, and interacting with an external host through the submitting queue and the finishing queue to enable the external host to carry out data movement between a dynamic random access memory and a hard disk of the external host connected to the second interface processing module.

As a further improvement of the present invention, the method further comprises: parameter setting is carried out according to instruction setting of an external host connected to the second interface processing module, and a main control signal from the flash memory controller is processed according to the set parameter.

The invention also provides a solid state disk main control testing device, which comprises:

the first interface processing module is used for being connected with the flash memory controller and receiving a main control signal from the flash memory controller, wherein the received main control signal comprises an operation command, an address and data;

the main controller is used for distributing a storage space, a first control instruction and a second control instruction according to the operation command and the address in the main control signal;

the buffer controller is used for writing the data in the main control signal into the corresponding storage space in the data buffer according to the address in the received main control signal and the storage space allocated by the main controller;

the direct memory access controller is used for carrying out data movement between the data cache and the dynamic random access memory according to a first control instruction of the main controller;

the second control instruction is transmitted to an external host by a second interface processing module, and data is moved between the dynamic random access memory and a hard disk of the external host by the external host connected to the second interface processing module;

the main controller generates an error signal when the received main control signal is abnormal and when the data movement is abnormal.

As a further improvement of the present invention, the test device further includes:

the first register is set when the main control signal received by the first interface processing module comprises an operation command in the process that data is moved to the dynamic random access memory by the data cache or is moved to the data cache by the dynamic random access memory, and the external host generates an error record when the external host reads that the first register is set and controls the first register to reset;

and the second register is set when the data after the write instruction received by the first interface processing module exceeds one page space, and the external host generates error records when reading the second register to be set and controls the second register to be reset.

The invention also provides a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the solid state disk main control test method as described above.

The invention has the following beneficial effects: by executing the main control signal from the flash memory controller, data is stored in or read from the hard disk of the external host, and error signals are generated when abnormality occurs in the process of executing data storage or reading, so that errors of the flash memory controller in the solid state disk are conveniently located.

Drawings

FIG. 1 is a schematic diagram of a hardware platform for running a method for testing a solid state disk master control provided by an embodiment of the present invention;

FIG. 2 is a schematic flow chart of a method for testing the master control of a solid state disk according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart of generating an error signal when an abnormality exists in a master control signal received by a first interface processing module in the method for testing a master control of a solid state disk according to the embodiment of the present invention;

fig. 4 is a schematic flow chart of generating an error signal when there is an abnormality in data movement in the method for testing a solid state disk master control according to the embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The solid state disk main control testing method can be applied to main control testing of the solid state disk and can be used for positioning errors in a main control program. As shown in fig. 1, the method may operate in a flash simulator connected to the flash controller 101 (i.e. the main control of the solid state disk), where the flash simulator may simulate the flash chip to execute the command from the flash controller 101 and form a simulated solid state disk together with the flash controller. Specifically, the flash memory controller 101 is connected to an upper computer through a hard disk interface such as SATA, NVME, USB, and the upper computer sends commands for operating the solid state disk such as reading and writing LBA (Logic Block Address, logical block address) to the flash memory controller through the hard disk interface; the flash memory simulator is connected with the flash memory controller 101 through the interface the same as the NAND FLASH chip, simulates NAND FLASH chip behaviors, and can store information such as commands, addresses, flash memory states, read-write data and the like in a cache; the flash simulator is also connected to an external host 112, and parameters, states, and the like of the flash simulator can be set and read through the external host 112, so that the flash simulator is matched with the flash simulator to realize the test of the flash controller 101. In particular, the host computer connected to the flash memory controller 101 and the external host 112 connected to the flash emulator may be constituted by the same hardware device.

Specifically, the flash emulator includes a Cache controller (Cache Buffer Ctrl) 102, a first interface processing module (Interface Process) 103, a command decoding module (CMD Decoder) 104, a Data Cache (Data Cache) 105, a main Controller (CPU) 106, a sorting Cache module (Sorting Hat Buffer) 107, a Direct Memory Access Controller (DMAC) 108, a control register (EFIP Ctrl Reg) 109, a dynamic random access memory (DDR) 110, a second interface processing module (PCIE) 111, and the flash emulator is connected to the flash controller 101 through the first interface processing module 103 and connected to an external host 112 through the second interface processing module 111.

The first interface processing module 103 is configured to control a pin IO interface connected to the flash memory controller 101, and is responsible for operations such as delay and sampling of a master control signal from the flash memory controller 101, delay of an output signal, and the like; the buffer controller 102 is responsible for processing the address information sampled by the first interface processing module 103 module, distributing the address stored in the data buffer 105 to the data input by the flash memory controller 101, and controlling the address processing of the data output from the data buffer 105 to the flash memory controller 101; the data buffer 105 is responsible for temporarily storing data input to the flash emulator by the flash controller 101 or data ready to be output into the flash controller 101; the direct memory access controller 108 is responsible for data interaction between the dynamic random access memory 110 and the data cache 105; the dynamic random access memory 110 is responsible for storing data input to the flash emulator by the flash controller 101 or data ready to be output to the flash controller 101; the second interface processing module 111 is responsible for information interaction between the external host 112 and the flash memory emulator; the command decoding module 104 is responsible for processing the command information sampled by the first interface processing module 103, for example, comparing the sampled command with a pre-configured command set to parse the command meaning for the host controller 106 to control the flash memory emulator; the sorting buffer module 107 is responsible for temporarily storing the addresses and command information sampled by the first interface processing module 103 (only after the command decoding module 104 confirms that the command is correct and valid); the control register 109 configures the flash emulator to emulate different model flash by modifying the module register contents; the main controller 106 is primarily responsible for several functions: configuring the control register 109, obtaining information from the flash controller 101 such as command addresses received at runtime, by the sort cache module 107, controlling the direct memory access controller 108 to handle data in the data cache 105 to the dynamic random access memory 110, generating a task queue (the external host 112 may directly access the local cache D-MEM of the host controller 106 via the second interface processing module 111 to obtain tasks in the task queue), etc., for example, the host controller 106 may interact with the external host 112 by: the main controller 106 generates (Completion Queue), SQ (commit Queue) and stores to its own cache, and the external host 112 reads the local cache D-MEM of the main controller 106 and obtains CQ, SQ through the second interface processing module 111, thereby reading data from the dynamic random access memory 110 or writing data to the dynamic random access memory 110.

The above-mentioned buffer controller 102, the first interface processing module 103, the command decoding module 104, the data buffer 105, the main controller 106, the sorting buffer module 107, the direct memory access controller 108, the control register 109, the dynamic random access memory 110, and the second interface processing module 111 may be specifically formed by combining related hardware with software, and those skilled in the art may select appropriate hardware and write codes according to the corresponding functions to implement the corresponding functions, for example, may select an FPGA and implement the flash memory emulator in combination with the corresponding codes.

Fig. 2 is a schematic flow chart of an embodiment of a method for testing a main control of a solid state disk according to an embodiment of the present invention, where the method for testing a main control of a solid state disk includes:

step S21: the first interface processing module 103 receives a master signal from the flash memory controller 101, and generates an error signal when there is an abnormality in the received master signal, which includes an operation command, an address, and data.

The flash memory controller 101 may generate a corresponding master control signal according to a command from a host computer, and specifically, the control signal includes an operation command (for example, a data storage command, a data reading command, a data deleting command, etc.), an address, data, etc.

The first interface processing module 103 includes pins corresponding to a flash memory chip (e.g., a NAND flash memory chip), for example, ALE, CLE, WE pins, etc., and is connected to the flash memory controller 101 through these pins. The first interface processing module 103 obtains a master signal from the flash memory controller 101 through pins. In particular, the first interface processing module 103 may distinguish between addresses, operation commands, and data from the master signal according to the slave pin signal (e.g., ALE, CLE, WE).

Specifically, when the received main control signal is an operation command, the command decoding module 104 analyzes the operation command according to a preset command set, and stores the operation command which is correctly analyzed into the sorting cache module 107, and the main controller 106 can read the operation command in the sorting cache module 107 and generate a corresponding task queue according to the operation command so as to control the subsequent data transceiving operation; when the received main control signal is an address, the address is stored in the sorting cache module 107 and the cache controller 102, and after the address enters the cache controller 102, the cache controller 102 can determine that the subsequently input data stores the address in the data cache 105 according to the storage space and the address information configured in the control register 109 by the main controller 106; when the received master signal is data, the data is read by the cache controller 102.

When the first interface processing module 103 is abnormal in the process of receiving the master control signal, an error signal is generated, and the error signal can be recorded by the external host 112, so that the fault location of the master control is facilitated.

Step S22: the received data is written into the data buffer 105 or read from the data buffer 105 according to the address and the operation command in the received master signal.

Specifically, when the master signal received in step S21 is a data storage command, the master controller 106 generates a data storage task for the buffer controller 102 to execute, where the data storage task includes allocating a storage space for the received data according to the address in the sorting buffer module 107, and the buffer controller 102 executes the data storage task to store the data received by the first interface processing module 103 into the corresponding storage space of the data buffer 105. When the master signal received in step S21 is a data read command, the master controller 106 generates a data read task for the buffer controller 102 to execute, and the buffer controller 102 executes the data read task, acquires corresponding data from the data buffer 105, and sends the data to the first interface processing module 103.

Step S23: according to the operation command in the received main control signal, data movement is performed between the data buffer 105 and the dynamic random access memory 110, and data movement is performed between the dynamic random access memory 110 and the hard disk of the external host 112 connected to the second interface processing module 111, and an error signal is generated when there is an abnormality in data movement. The second interface processing module 111 may be a PCIE interface, through which the external host 112 may directly read information of the dynamic random access memory 110 in the flash emulator and a local cache (D-MEM) in the host controller 106.

Specifically, when the master signal received in step S21 is a data storage command (the master controller 106 directly reads from the sorting cache module 107), the master controller 106 generates a data storage task for the direct storage access controller 108 and the external host 112 to execute, the direct storage access controller 108 first executes the data storage task, the data stored in the data cache 105 by the cache controller 102 is stored in the dynamic random access memory 110, and then the external host 112 executes the data storage task to store the data of the dynamic random access memory 110 in the hard disk.

When the master signal received in step S21 is a data read command (the master controller 106 directly reads from the sorting cache module 107), the master controller 106 generates a data read task for the direct memory access controller 108 and the external host to execute, the external host 112 first executes the data read task, writes the corresponding data of the hard disk into the dynamic random access memory 110, the direct memory access controller 108 executes the data storage task, and stores the data of the dynamic random access memory 110 into the data cache 105.

When an abnormality occurs in the data movement between the data buffer 105 and the dynamic random access memory 110, an error signal is generated, and the error signal can be recorded by the external host 112, so that the fault location of the master is facilitated.

According to the solid state disk main control testing method, the main control signal from the flash memory controller 101 is executed to store data into the hard disk of the external host 112 or read data from the hard disk of the external host 112, and an error signal is generated when an abnormality occurs in the process of executing data storage or reading, namely, a flash memory simulator is used for simulating a flash memory chip to execute a main control command, so that errors of the flash memory controller 101 can be conveniently located.

In an embodiment of the present invention, the method for testing the master control of the solid state disk further includes: parameter setting is performed according to instruction setting of the external host 112 connected to the second interface processing module 111, and a master signal from the flash memory controller 101 is processed according to the set parameter.

The above-mentioned parameter setting step may be performed when the flash memory emulator is initialized, and it may set corresponding parameters (e.g., size of data block, etc.) according to an instruction of the external host 112 connected to the second interface processing module 111, so that the flash memory emulator may process the master control signal from the flash memory controller 101 according to the flash memory model that is expected to be emulated, thereby meeting the test requirements of different flash memory controllers.

Specifically, the main controller 106 configures the flash emulator to emulate a different model of flash by modifying the value of the control register 109. The main controller 106 of the flash emulator performs both memory allocation and data transfer by controlling the direct memory access controller 108 in accordance with the value of the control register 109.

Referring to fig. 3, in an embodiment of the present invention, in the step S21, when there is an abnormality in the master signal received by the first interface processing module, an error signal is generated, including:

step S211: according to the operation command and data from the master signal, the data is moved from the data buffer 105 to the dynamic random access memory 110 or from the dynamic random access memory 110 to the data buffer 105.

Specifically, the main controller 106 of the flash emulator controls the direct memory access controller 108 to move the data in the data cache 105 to the dynamic random access controller 110 according to the operation command in the sorting cache module 107. Each time the move operation is performed, it is determined whether the direct access controller 108 is still performing the copy operation, if the copy operation of the direct access controller 108 is not finished, the host controller 106 sets the Flash status register to a busy state (Flash busy), and then waits for the completion of the operation, the host controller 106 sets the register to an idle state (ready). Upon receipt of a command sent by flash controller 101 to read a flash status register, host controller 106 replies with the value of the status register.

Step S212: it is determined whether an operation command is included in the main control signal received by the first interface processing module 103. If the flash status register is busy, the main control signal is an operation command, step S213 is executed, otherwise step S211 is continued.

Step S213: the first register is set. The first register may be one of the control registers of the flash emulator.

Since the data buffer 105 is occupied during the process of the direct memory access controller 108 moving the data from the data buffer 105 to the dynamic random access memory 110 or from the dynamic random access memory 110 to the data buffer 105 (i.e. the flash status register is busy), if the master control signal received by the first interface processing module 103 includes an operation command, the first register is set.

Step S214: the second interface processing module 111 transmits the state information of the first register to the external host 112, and resets the first register by a first reset signal from the external host 112, and the external host 112 generates an error record when reading that the first register is set, and generates a first reset signal for resetting the first register.

The error record may specifically include information such as an error type, occurrence time, etc., so as to facilitate subsequent analysis and processing. That is, when the data buffer is occupied, the flash controller 101 should not send the operation command any more, and if the operation command is received at this time, it indicates that the operation command is erroneous.

Referring to fig. 4, in the step S23, an error signal is generated when there is an abnormality in the data movement, including:

step S231: the main control signal is received from the flash memory controller 101 through the first interface processing module 103.

Step S232: whether the data received by the first interface processing module 103 after the writing instruction exceeds a page space is determined, if yes, step S233 is executed, otherwise, step S231 is executed continuously.

Step S233: the second register is set. The second register may be another one of the control registers of the flash emulator.

Since data writing can only be performed in one PAGE (PAGE Size is typically 4k,8k,16 k) during normal operation of a write of the flash memory chip. When the write data exceeds one Page space after a write command (column+dma Length > Page Size), where Column is the address offset of the write data address in one Page space, DMA Length is the Length of the write data. At this time, the second register needs to be set.

Step S234: the second interface processing module 111 transmits the state information of the second register to the external host 112 and resets the second register by a second reset signal from the external host 112, and the external host 112 generates an error record when reading that the second register is set and generates a second reset signal for resetting the second register.

The error record may also include information such as error type, occurrence time, etc., so as to facilitate subsequent analysis and processing. That is, when the write data generated by the flash memory controller exceeds one page space, the flash memory emulator will record the error information.

The invention also provides a solid state disk main control testing device which is used for simulating the flash memory chip and assisting in carrying out the solid state disk main control test. The test device of the embodiment comprises a first interface processing module, a main controller, a cache controller, a direct memory access controller, a second interface processing module and the like.

The first interface processing module is used for being connected with the flash memory controller and receiving a main control signal from the flash memory controller, wherein the received main control signal comprises an operation command, an address and data. The main controller is used for distributing the storage space, the first control instruction and the second control instruction according to the operation command and the address in the main control signal. The buffer controller is used for writing the data in the main control signal into the corresponding storage space in the data buffer according to the address in the received main control signal and the storage space allocated by the main controller. The direct memory access controller is used for carrying out data movement between the data cache and the dynamic random access memory according to a first control instruction of the main controller. The second control command is transmitted to the external host by the second interface processing module, and data movement is carried out between the dynamic random access memory and the hard disk of the external host by the external host connected to the second interface processing module. The main controller generates an error signal when the received main control signal is abnormal and when the data movement is abnormal.

In one embodiment of the present invention, the test apparatus further includes a first register and a second register. The first register is set when a main control signal received by the first interface processing module comprises an operation command in the process that data is moved from a data cache to a dynamic random access memory or from the dynamic random access memory to the data cache, and the external host generates an error record when reading that the first register is set and controls the first register to reset; the second register is set when the data after the write instruction received by the first interface processing module exceeds one page space, and the external host generates an error record when reading that the second register is set and controls the second register to reset.

The solid state disk main control testing device in this embodiment belongs to the same concept as the solid state disk main control testing method in the corresponding embodiments in fig. 2-4, the specific implementation process is detailed in the corresponding method embodiment, and the technical features in the method embodiment are correspondingly applicable in the device embodiment, and are not repeated here.

The invention also provides a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the solid state disk main control test method as described above.

The computer readable storage medium in this embodiment belongs to the same concept as the method for testing the main control of the solid state disk in the corresponding embodiments in fig. 2-4, the specific implementation process is detailed in the corresponding method embodiment, and the technical features in the method embodiment are correspondingly applicable in the device embodiment, which is not repeated here.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional units and modules according to needs. The functional units and modules in the embodiment may be integrated in one processor, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed method and apparatus for testing the master control of a solid state disk may be implemented in other manners. For example, the solid state disk master test device embodiments described above are merely illustrative.

In addition, each functional unit in the embodiments of the present application may be integrated in one processor, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each method embodiment described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or interface switching device, recording medium, USB flash disk, removable hard disk, magnetic disk, optical disk, computer Memory, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), electrical carrier wave signals, telecommunications signals, and software distribution media, among others, capable of carrying the computer program code. It should be noted that the computer readable medium may include content that is subject to appropriate increases and decreases as required by jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is not included as electrical carrier signals and telecommunication signals.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention. Furthermore, embodiments of the invention and features of the embodiments may be combined with each other without conflict.

Claims (10)

1. The method for testing the master control of the solid state disk is characterized by comprising the following steps of:

receiving a main control signal from a flash memory controller through a first interface processing module, and generating an error signal when the received main control signal is abnormal, wherein the received main control signal comprises an operation command, an address and data;

writing the received data into a data cache or reading the data from the data cache according to the address and the operation command in the received main control signal;

and according to the operation command in the received main control signal, carrying out data movement between the data cache and the dynamic random access memory, carrying out data movement between the dynamic random access memory and a hard disk of an external host connected to the second interface processing module, and generating an error signal when the data movement is abnormal.

2. The method of claim 1, wherein generating an error signal when the master control signal received by the first interface processing module is abnormal comprises:

in the process that data is moved to a dynamic random access memory from the data cache or is moved to the data cache from the dynamic random access memory, if a main control signal received by the first interface processing module comprises an operation command, setting a first register;

the second interface processing module transmits the state information of the first register to an external host, and resets the first register by a first reset signal from the external host, which generates an error record when reading that the first register is set, and generates a first reset signal for resetting the first register.

3. The method of claim 1, wherein the operation command includes a data storage command, and the generating an error signal when there is an abnormality in data migration includes:

setting a second register when the data after the write-in instruction received by the first interface processing module exceeds a page space;

the second interface processing module transmits the state information of the second register to an external host, and resets the second register by a second reset signal from the external host, which generates an error record when reading that the second register is set, and generates a second reset signal for resetting the second register.

4. The method for testing the master control of the solid state disk according to claim 1, wherein the receiving, by the first interface processing module, the master control signal from the flash memory controller comprises:

when the received main control signal is an operation command, analyzing the operation command according to a preset command set, and storing the operation command which is accurately analyzed into a sorting cache module;

and when the received main control signal is an address, storing the address into the sorting cache module and the cache controller, wherein the address in the sorting cache module is used for carrying out storage space allocation.

5. The method of claim 4, wherein writing the data in the master control signal to a data buffer or reading the data from the data buffer according to the address and the operation command in the received master control signal, comprises:

when the operation command is a data storage command, writing the data after the data storage command into a storage space allocated in the data cache by the cache controller according to the address;

and when the operation command is a data reading command, acquiring corresponding data from the data cache according to the address.

6. The method of claim 4, wherein the performing data movement between the data buffer and the dynamic random access memory and performing data movement between the dynamic random access memory and the hard disk of the external host connected to the second interface processing module according to the operation command in the received master control signal comprises:

according to the operation command stored in the sorting buffer module, data is moved between the data buffer and the dynamic random access memory;

generating a submitting queue and a finishing queue according to the operation command stored in the sorting buffer module, and interacting with an external host through the submitting queue and the finishing queue to enable the external host to carry out data movement between a dynamic random access memory and a hard disk of the external host connected to the second interface processing module.

7. The method for testing the master control of the solid state disk according to claim 1, further comprising: parameter setting is carried out according to instruction setting of an external host connected to the second interface processing module, and a main control signal from the flash memory controller is processed according to the set parameter.

8. A solid state disk master control testing device comprises:

the first interface processing module is used for being connected with the flash memory controller and receiving a main control signal from the flash memory controller, wherein the received main control signal comprises an operation command, an address and data;

the main controller is used for distributing a storage space, a first control instruction and a second control instruction according to the operation command and the address in the main control signal;

the buffer controller is used for writing the data in the main control signal into the corresponding storage space in the data buffer according to the address in the received main control signal and the storage space allocated by the main controller;

the direct memory access controller is used for carrying out data movement between the data cache and the dynamic random access memory according to a first control instruction of the main controller;

the second control instruction is transmitted to an external host by a second interface processing module, and data is moved between the dynamic random access memory and a hard disk of the external host by the external host connected to the second interface processing module;

the main controller generates an error signal when the received main control signal is abnormal and when the data movement is abnormal.

9. The solid state disk main control testing device of claim 8, further comprising:

the first register is set when the main control signal received by the first interface processing module comprises an operation command in the process that data is moved to the dynamic random access memory by the data cache or is moved to the data cache by the dynamic random access memory, and the external host generates an error record when the external host reads that the first register is set and controls the first register to reset;

and the second register is set when the data after the write instruction received by the first interface processing module exceeds one page space, and the external host generates error records when reading the second register to be set and controls the second register to be reset.

10. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the solid state disk hosting test method according to any one of claims 1 to 7.