CN117648280A - Sharing caching method and device for multi-port switching equipment - Google Patents

Abstract

The disclosure provides a method and a device for sharing and caching multi-port switching equipment. The method is applied to a multiport switching device interface unit, the multiport switching device interface unit comprises a RAM module, a controller module and a cache bus selector module, the RAM module comprises a plurality of RAMs, and the controller module comprises a plurality of controller sub-modules. The cache bus selector module obtains configuration information for at least one controller sub-module. The cache bus selector module determines the controller sub-module in an activated state based on configuration information of at least one controller sub-module. The cache bus selector module allocates at least one of the plurality of RAMs to the controller submodule in an activated state. The cache bus selector module re-maps the allocated address of the at least one RAM, and establishes a mapping relation between the at least one RAM and the controller submodule in an activated state.

Description

Sharing caching method and device for multi-port switching equipment

Technical Field

The embodiment of the disclosure relates to the technical field of computers, in particular to a method and a device for sharing cache of multi-port switching equipment.

Background

PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) switching devices use PCIe controllers to process PCIe protocol underlying services, and when implementing a multi-port PCIe switching device, each port corresponds to one PCIe controller, and each controller is independent from each other and is used to process PCIe protocol underlying services of a corresponding port. And each controller is provided with a respective cache, and each cache is also used independently of each other.

Therefore, if the port is in the unused state, the buffer memory corresponding to the controller of the port in the unused state is in the idle state and cannot be used, so that a great amount of buffer memory resource is wasted. For example, when only the controller of the X8 port is in the use state, since the controllers of the X4, X2 and X2 are in the idle state, the caches of the corresponding controllers of the X4, X2 and X2 are also in the idle state and cannot be used, thereby causing the waste of cache resources.

Therefore, there is a need to propose a method for sharing a cache of a multi-port switch device, so as to solve at least one of the above technical problems.

Disclosure of Invention

The embodiment of the disclosure provides a method and a device for sharing and caching multi-port switching equipment.

In a first aspect, the present disclosure provides a method for sharing a cache of a multiport switching device, which is applied to a multiport switching device interface unit, where the multiport switching device interface unit includes a RAM module, a controller module, and a cache bus selector module, the RAM module includes a plurality of RAMs, and the controller module includes a plurality of controller sub-modules, including:

the cache bus selector module obtains configuration information for at least one controller sub-module;

the cache bus selector module determines a controller sub-module in an activated state according to configuration information of at least one controller sub-module;

the cache bus selector module allocates at least one of the plurality of RAMs to the controller submodule in an activated state;

the cache bus selector module re-maps the allocated address of the at least one RAM, and establishes a mapping relation between the at least one RAM and the controller submodule in an activated state.

In some alternative embodiments, the cache bus selector module assigns at least one of the plurality of RAMs to a controller submodule in an activated state, including:

the cache bus selector module allocates at least one of the plurality of RAMs to the controller submodule in an activated state based on the identification information of the at least one controller submodule in the activated state and the type of the at least one controller submodule in the activated state.

In some alternative embodiments, the cache bus selector module remaps the allocated address of the at least one RAM, and establishes a mapping relationship between the at least one RAM and the controller submodule in the activated state, including:

the cache bus selector module re-maps the address of each RAM according to the distribution quantity of the RAMs in each activated controller sub-module and the address length of each RAM, and establishes a mapping relation from at least one RAM to the activated controller sub-module.

In some alternative embodiments, the controller submodule further includes a cache slice management module, further including:

the cache slice management module divides the RAM subjected to address remapping into a plurality of storage units;

the buffer slice management module stores the data packet to different storage units according to the type of the data packet.

In some alternative embodiments, further comprising:

the cache slice management module analyzes the data type of the data in the data packet;

the cache bus selector module writes the data packet into different memory cells of the RAM according to the data type of the data in the data packet and the address of the RAM that has been address remapped.

In some alternative embodiments, further comprising:

the cache slice management module receives a read request for target data;

and the cache slice management module acquires the target data from different storage units of the RAM corresponding to the cache slice management module according to the data type of the target data.

In some alternative embodiments, the total capacity of the plurality of RAMs matches the RAM capacity required for the maximum number of channels.

In some alternative embodiments, the amount of RAM is equal to a multiple of the number of controller sub-modules.

In some alternative embodiments, the types of controller submodules include different link width types.

In a second aspect, the present disclosure provides a multi-port switching device interface unit comprising a RAM module comprising a plurality of RAMs, a controller module comprising a plurality of controller sub-modules comprising switching device ports, and a cache bus selector module, wherein,

a cache bus selector module configured to obtain configuration information for at least one controller sub-module;

a cache bus selector module further configured to determine a controller sub-module in an activated state based on configuration information of at least one controller module;

A cache bus selector module further configured to allocate at least one of the plurality of RAMs to a controller submodule in an activated state;

the cache bus selector module is further configured to remap the allocated address of the at least one RAM, and establish a mapping relationship between the at least one RAM and the controller submodule in an activated state.

The multi-port switching device sharing caching method and device provided by the embodiment of the disclosure are applied to a multi-port switching device interface unit, wherein the multi-port switching device interface unit comprises a RAM (Random Access Memory ) module, a controller module and a cache bus selector module, the RAM module comprises a plurality of RAMs, and the controller module comprises a plurality of controller sub-modules. First, the cache bus selector module obtains configuration information for at least one controller sub-module. Secondly, the cache bus selector module determines the controller sub-module in an activated state according to the configuration information of at least one controller sub-module. The cache bus selector module then allocates at least one of the plurality of RAMs to the controller submodule in an activated state. And finally, the cache bus selector module re-maps the allocated address of the at least one RAM, and establishes a mapping relation between the at least one RAM and the controller submodule in an activated state. According to the method and the device, at least one of the RAMs is distributed to the controller submodule in the activated state through the cache bus selector module, and the address of the at least one distributed RAM is remapped, namely, the cache bus selector module can flexibly distribute RAM resources according to the distribution state of the equipment port, unified management of the RAMs is achieved, and waste of cache is reduced.

Drawings

Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings. The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention. In the drawings:

FIG. 1 is a system architecture diagram of one embodiment to which a multi-port switching device shared cache method according to the present disclosure may be applied;

fig. 2 is a schematic diagram of a multiport switching device interface unit architecture in accordance with the present disclosure;

FIG. 3 is a flow chart of one embodiment of a method of sharing a cache by a multi-port switching device according to the present disclosure;

FIGS. 4-8 are schematic diagrams of RAM allocation according to the present disclosure;

fig. 9 is a schematic diagram of a multiport switching device interface unit arrangement in accordance with the present disclosure;

fig. 10 is a schematic diagram of another multiport switching device interface unit arrangement in accordance with the present disclosure.

Detailed Description

The present disclosure is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 illustrates an exemplary system architecture 100 to which embodiments of the multi-port switching device shared caching method and apparatus of the present disclosure may be applied.

As shown in fig. 1, the system architecture 100 may include a multi-port switching device interface unit 101, terminal devices 102, 103, and a server 104. The multi-port switching device interface unit 101 and the terminal devices 102 and 103 are connected in a wired or wireless manner to realize data interaction.

The multiport switching device interface unit 101 is used for data exchange between the terminal devices 102, 103 and the server 104.

In some cases, the multi-port switching device shared caching method provided by the present disclosure may be performed by the multi-port switching device interface unit 101, e.g., "acquire port configuration information for at least one of the switching device ports". The present disclosure is not limited in this regard.

The terminal devices 102 and 103 may be hardware or software. When the terminal devices 102, 103 are hardware, they may be various electronic devices with microphones and speakers, including but not limited to smartphones, tablet computers, electronic book readers, MP3 players (Moving Picture Experts Group Audio Layer III, mpeg 3), MP4 players (Moving Picture Experts Group Audio Layer IV, mpeg 4), portable and desktop computers, etc. When the terminal devices 102, 103 are software, they can be installed in the above-listed electronic devices.

The server 104 may be hardware or software. When the server 104 is hardware, it may be implemented as a distributed server cluster formed by a plurality of servers, or as a single server. When server 104 is software, it may be implemented as multiple software or software modules (e.g., to provide distributed services), or as a single software or software module. The present invention is not particularly limited herein.

It should be understood that the number of multiport switching device interface units, terminal devices and networks in fig. 1 is merely illustrative. There may be any number of multiport switching device interface units, terminal devices and networks, as desired for implementation.

The multi-port switching device sharing caching method of the present disclosure may be applied to the multi-port switching device interface unit shown in fig. 2, and before describing one embodiment of the multi-port switching device sharing caching method of the present disclosure, the following description will simply describe the multi-port switching device interface unit.

Referring to fig. 2, fig. 2 illustrates a schematic diagram 200 of a multi-port switching device interface unit of the present disclosure.

As shown in fig. 2, the multi-port switching device interface unit includes a RAM module including a plurality of RAMs, a controller module including a plurality of controller sub-modules, and a cache bus selector module.

The interface unit of the multiport switching device shown in the present disclosure may be applied to PCIe multiport switching devices, where PCIe multiport switching devices use PCIe controllers to process PCIe protocol underlying services. The PCIe controller may be the controller module shown in fig. 2, among others.

As shown in fig. 2, each controller sub-module of the controller module includes a respective physical layer, data link layer, and transaction layer, each of which functions differently for handling different transactions specified by the PCIe protocol.

The main functions of the transaction layer are responsible for sending or receiving transaction layer packets, flow control, transaction ordering and the like.

The primary functions of the data link layer are transmitting or receiving data link layer packets, link layer error detection and correction, power management, and the like.

The main role of the physical layer is to handle all packet data physical transmissions.

In a multi-port switching device interface unit, a controller module includes a plurality of controller sub-modules.

The physical layer of each controller sub-module further defines the type of the controller sub-module, and the type of each controller sub-module may be the same or different. The types of controller submodules include different link width types.

For example, the multi-port switching device interface unit as shown in fig. 2 may include 4 controller sub-modules, and the ports of the multi-port switching device may be X8 ports.

The types of the controller sub-modules can be an X8 type, an X4 type and an X2 type.

The number of channels required by the different controller sub-modules may vary according to the type of the multi-port switching device shown in fig. 2, which may include 8 channels.

The number of channels required by the controller submodule of the X8 type is 8, that is, to use the X8 port, all 8 channels need to be allocated to the controller submodule 1 for use.

The number of channels required by the X4 type controller sub-module is 4, and the number of channels required by the X2 type controller sub-module is 2, wherein the X8 type controller sub-module can be reduced to the X4 type controller sub-module and the X2 type controller sub-module for use, and the X4 type controller sub-module can be reduced to the X2 type controller sub-module for use.

For example, the multi-port switching device interface unit shown in fig. 2 is a multi-port switching device interface unit employing X8 ports and including 8 lanes.

When the port is configured to adopt the X8 mode, all 8 channels need to be allocated to the X8 controller for use, i.e. all 8 channels may be allocated to the controller sub-module 1 for use.

When the ports are configured to adopt X4 and X4 modes, the X8 port can be reduced to be used as the X4 port, 4 channels can be allocated to the X8 controller for use, and 4 channels are allocated to the X4 controller for use. I.e. 4 channels are allocated to the controller sub-module 1 for use and another 4 channels are allocated to the controller sub-module 3 for use.

When the ports are configured to employ X2, X2 modes, both the X8 controller (i.e., controller sub-module 1) and the X4 controller (i.e., controller sub-module 4) are used as X2 controllers, 2 channels may be allocated to the X8 controllers, 2 channels to the X2 controllers, 2 channels to the X4 controllers, and 2 channels to the other X2 controller. Namely, 2 channels are allocated to the controller sub-module 1 for use, 2 channels are allocated to the controller sub-module 2 for use, 2 channels are allocated to the controller sub-module 3 for use, and 2 channels are allocated to the controller sub-module 4 for use.

In addition, the ports may be configured in a plurality of modes such as X4X2, X2X4, and the like, and are not particularly limited herein.

It is understood that the types of controller submodules include different link width types. Here, the types of the controller sub-modules are an X8 type, an X4 type, and an X2 type, which are only exemplary, and the types of the controller sub-modules may also be an X16 type, an X8 type, an X4 type, and the like, which are not particularly limited herein.

The transaction layer of each controller sub-module also includes a respective cache slice management module. The module is used for managing the RAM, and a block of RAM can be divided into different storage units, and each storage unit is used for storing different types of data packets.

For example, the RAM may be divided into three sections for storing three types of data packets of a Posted (reporting transaction), non-Posted (Non-reporting transaction), and Completion (Completion packet), respectively.

The RAM module includes a plurality of RAMs. Wherein each RAM has an independent read-write interface, and the total capacity of the plurality of RAMs can be matched with the RAM capacity required by the maximum channel number.

For example, as shown in FIG. 2 for a multi-port switching device that includes 8 channels, then the total capacity of all RAMs should be greater than or equal to the capacity of the RAMs required for 8 channels, i.e., greater than or equal to the capacity of the RAMs required for the X8 controller.

The number of all RAMs may be equal to a multiple of the number of controller sub-modules. The amount of RAM may also be equal to a multiple of the number of cache slice management modules.

For example, there are 4 controller sub-modules, and correspondingly, the number of RAMs may be a multiple of 4, e.g., the number of RAMs may be 4, 8, etc.

The cache bus selector module comprises a cache bus selector for completing the mapping of each RAM of the RAM module to the cache slice management module.

With continued reference to fig. 3, fig. 3 illustrates a flowchart 300 of one embodiment of a multi-port switching device shared cache method according to the present disclosure, the multi-port switching device shared cache method illustrated in fig. 3 being applicable to the multi-port switching device interface unit illustrated in fig. 2. The process 300 includes the steps of:

in step 201, the cache bus selector module obtains configuration information for at least one controller sub-module.

The configuration information may be information indicating whether the controller submodule is configured to use the state.

It will be appreciated that the plurality of channels may be split as desired and configured for use with at least one controller sub-module.

For example, when the port is configured in X8 mode, 8 lanes may be allocated for use by one X8 type controller submodule, i.e., 8 lanes may be allocated for use by controller submodule 1 in their entirety. At this time, the controller sub-module 1 may be configured to be in a used state, and the controller sub-module 2, the controller sub-module 3, and the controller sub-module 4 may be configured to be in an unused state.

When the port is configured in the X4 mode, the X8 type controller submodule can be reduced to the X4 type controller submodule for use, 4 channels can be allocated to the controller submodule 1 for use, and the other 4 channels are allocated to the controller submodule 3 for use. At this time, the controller sub-module 1 and the controller sub-module 3 may be configured to be in a used state, and the controller sub-module 2 and the controller sub-module 4 may be configured to be in an unused state.

Here, the ports may also be configured in a plurality of modes such as X2, X4X2, X2X4, and the like, which are not particularly limited herein. After the configuration of each controller sub-module is completed, the cache bus selector module obtains configuration information for at least one controller sub-module.

Alternatively, the cache bus selector module may directly obtain the configuration information of at least one controller sub-module configured in the use state, or may obtain the configuration information of at least one controller sub-module configured in the use state and at least one controller sub-module configured in the unused state.

In step 202, the cache bus selector module determines a controller sub-module in an activated state based on configuration information of at least one controller module.

In some alternative embodiments, each controller sub-module is independent of the other, indicating that one controller sub-module is in an activated state when the controller sub-module is configured for use.

For example, when the controller sub-module 1 is configured in the active state, i.e. it indicates that the controller sub-module 1 is in the active state. When the controller sub-module 2 is configured in the inactive state, i.e. it indicates that the controller sub-module 2 is in the inactive state.

In some alternative embodiments, the cache bus selector module may determine that the controller sub-module in the activated state is based on configuration information of at least one controller sub-module, and may determine that the controller sub-module in the activated state is based on configuration information of at least one controller sub-module in the in-use state.

At step 203, the cache bus selector module allocates at least one of the plurality of RAMs to the controller submodule in an activated state.

After determining that the controller submodule belongs to the activated state, the cache bus controller module allocates at least one RAM to the controller submodule in the activated state.

In some alternative embodiments, the cache bus selector module allocates at least one of the plurality of RAMs to the controller submodule in the activated state based on the identification information of the controller submodule in the activated state and the type of the at least one controller submodule in the activated state. The identification information of the controller sub-module is used for uniquely determining the controller sub-module.

That is, the cache bus selector module reassigns the plurality of RAMs to the controller sub-module in the activated state according to the identification information of the controller sub-module and the type of the controller sub-module.

Here, the types of the controller sub-modules are different, and the required RAM capacities thereof are also different, wherein the controller sub-modules with the larger number of required channels correspond to the larger required RAM capacities.

With continued reference to fig. 4-8, fig. 4-8 are schematic diagrams of RAM allocation.

As shown in fig. 4, when the port is configured in the X8 mode, 8 channels may be all allocated to the X8 type controller submodule 1 for use, and only the controller submodule 1 is in an activated state.

Correspondingly, all the RAM of the RAM module can be allocated to the controller sub-module 1 for use.

As shown in fig. 5, when the port is configured in the X4 mode, 4 channels of the 8 channels may be allocated to the controller sub-module 1 for use, and 4 channels may be allocated to the controller sub-module 3 for use, where the controller sub-module 1 and the controller sub-module 3 are in an activated state.

Correspondingly, part of the RAM module can be distributed to the controller sub-module 1 for use, and part of the RAM is distributed to the controller sub-module 3 for use.

For example, 2 RAMs may be allocated to the controller sub-module 1 for use, and two other RAMs may be allocated to the controller sub-module 3 for use.

As shown in fig. 6, when the port is configured in the X4X2 mode, 4 channels of the 8 channels may be allocated to the controller sub-module 1 for use, 2 channels may be allocated to the controller sub-module 2 for use, and 2 channels may be allocated to the controller sub-module 3 for use, and at this time, the controller sub-module 1, the controller sub-module 2, and the controller sub-module 3 are in an activated state.

Correspondingly, 2 RAMs of the RAM module may be allocated to the controller sub-module 1 for use, 1 RAM may be allocated to the controller sub-module 2 for use, and 1 RAM may be allocated to the controller sub-module 3 for use.

As shown in fig. 7, when the port is configured in the X2X4 mode, 2 channels of the 8 channels may be allocated to the controller sub-module 1 for use, 2 channels may be allocated to the controller sub-module 2 for use, and 4 channels may be allocated to the controller sub-module 3 for use, and at this time, the controller sub-module 1, the controller sub-module 2, and the controller sub-module 3 are in an activated state.

Correspondingly, 1 RAM of the RAM module may be allocated to the controller sub-module 1 for use, 1 RAM may be allocated to the controller sub-module 2 for use, and 2 RAMs may be allocated to the controller sub-module 3 for use.

As shown in fig. 8, when the port is configured in the X2 mode, 2 channels of the 8 channels may be allocated to the controller sub-module 1 for use, 2 channels may be allocated to the controller sub-module 2 for use, 2 channels may be allocated to the controller sub-module 3 for use, and 2 channels may be allocated to the controller sub-module 4 for use, and at this time, the controller sub-module 1, the controller sub-module 2, the controller sub-module 3, and the controller sub-module 4 are in an activated state.

Correspondingly, 1 RAM of the RAM module can be allocated to the controller sub-module 1 for use, 1 RAM is allocated to the controller sub-module 2 for use, 1 RAM is allocated to the controller sub-module 3 for use, and 1 RAM is allocated to the controller sub-module 4 for use.

In step 204, the cache bus selector module remaps the allocated address of the at least one RAM, and establishes a mapping relationship between the at least one RAM and the controller submodule in an activated state.

In some alternative embodiments, the cache bus selector module re-maps the address of each RAM according to the allocation number of RAMs in each allocated controller sub-module and the address length of each RAM, and establishes a mapping relationship between at least one RAM and the allocated controller sub-module.

It is understood that each RAM is independent and has an independent read-write interface, and each RAM has its own real address, for example, the address of each RAM may be 0KB to 63KB.

Here, the address of each RAM is remapped, and the address of the RAM may be remapped according to the allocation number of the RAMs in each controller sub-module in the allocated state and the address length of each RAM to obtain a new RAM address, which may be different from the real address of the RAM.

Example one: all RAMs of the RAM module are distributed to the controller submodule 1 for use, and the address of each RAM is remapped, so that the address range of the first RAM can be 0 KB-63 KB, the address range of the second RAM can be 64 KB-127 KB, the address range of the third RAM can be 128 KB-191 KB, and the address range of the fourth RAM can be 192 KB-255 KB.

That is, for the cache slice management module of the controller sub-module 1, all the RAMs may be managed, or 4 RAMs may be treated as one RAM for processing, that is, the cache slice management module may divide the 4 RAMs subjected to address remapping as one RAM into a plurality of storage units, and then the cache slice management module stores the data packet to a different storage unit according to the type of the data packet.

For example, the cache slice management module may divide 0 KB-127 KB of RAM into one storage unit, 128 KB-191 KB of RAM into one storage unit, and 192 KB-255 KB of RAM into another storage unit.

Example two: 2 RAMs may be allocated for use by the controller sub-module 1 and two other RAMs may be allocated for use by the controller sub-module 3. The address of each RAM is remapped, the first RAM address range of the controller sub-module 1 may be 0KB to 63KB, and the second RAM address range may be 64KB to 127KB. Likewise, for controller sub-module 3, the first RAM address range of controller sub-module 3 may be 0KB to 63KB and the second RAM address range may be 64KB to 127KB.

That is, for the cache slice management module of the controller sub-module 1, two RAMs of the RAM module may be managed, or the two RAMs may be treated as one RAM for processing. The cache slice management module of the controller submodule 3 may also manage the other two RAMs of the RAM module, or may treat both RAMs as one RAM.

Similarly, the buffer slice management module of the controller submodule 1 may divide the 2 RAMs mapped with the addresses as a block RAM into a plurality of storage units, and then store the data packet into different storage units according to the type of the data packet. The buffer slice management module of the controller submodule 3 may divide the 2 RAMs mapped with the addresses as a block RAM into a plurality of storage units, and then the buffer slice management module stores the data packet into different storage units according to the type of the data packet.

For example, the cache slice management module 1 may divide 0KB to 31KB of the RAM into one memory unit, may divide 32KB to 63KB of the RAM into one memory unit, and may divide 64KB to 127KB of the RAM into another memory unit.

Example three: 2 RAMs of the RAM module may be allocated for use by the controller sub-module 1, 1 RAM is allocated for use by the controller sub-module 2, and 1 RAM is allocated for use by the controller sub-module 3. The address of each RAM is remapped, the first RAM address range of the controller sub-module 1 may be 0KB to 63KB, and the second RAM address range may be 64KB to 127KB. The RAM address range of the controller submodule 2 may be 0KB to 63KB. The RAM address range of the controller submodule 3 may be 0KB to 63KB.

That is, for the cache slice management module of the controller sub-module 1, two RAMs of the RAM module may be managed, or the two RAMs may be treated as one RAM for processing. The cache slice management modules of the controller submodule 2 and the controller submodule 3 can respectively manage one RAM of the RAM modules.

Similarly, the buffer slice management module of the controller submodule 1 may divide the 2 RAMs mapped with the addresses as a block RAM into a plurality of storage units, and then store the data packet into different storage units according to the type of the data packet. The buffer slice management modules of the controller sub-module 2 and the controller sub-module 3 may respectively divide the 1 RAM mapped with the address as a block of RAM into a plurality of storage units, and then store the data packet into different storage units according to the type of the data packet.

For example, the cache slice management module of the controller submodule 2 may divide 0KB to 15KB of RAM into one storage unit, 16KB to 31KB of RAM into one storage unit, and 32KB to 63KB of RAM into another storage unit.

Example four: 1 RAM of the RAM module may be allocated for use by controller sub-module 1, 1 RAM is allocated for use by controller sub-module 2, and 2 RAMs are allocated for use by controller sub-module 3. The first RAM address range of the controller sub-module 1 may be 0KB to 63KB, remapping the address of each RAM. The RAM address range of the controller submodule 2 may be 0KB to 63KB. The first RAM address range of the controller submodule 3 may be 0KB to 63KB and the second RAM address range may be 64KB to 127KB.

That is, for the cache slice management modules of the controller sub-module 1 and the controller sub-module 2, one RAM of the RAM modules may be managed separately, the cache slice management module of the controller sub-module 3 may manage 2 RAMs of the RAM modules, or both RAMs may be treated as one RAM.

Likewise, the controller sub-module 1 and the controller sub-module 2 may respectively divide the 1 RAM mapped with the address as a block RAM into a plurality of storage units, and then the buffer slice management module stores the data packet into different storage units according to the type of the data packet. The buffer slice management module of the controller submodule 3 may divide the 2 RAMs mapped with the addresses as a block RAM into a plurality of storage units, and then the buffer slice management module stores the data packet into different storage units according to the type of the data packet. And will not be described in detail herein.

Example five: 1 RAM of the RAM module may be allocated for use by controller sub-module 1, 1 RAM is allocated for use by controller sub-module 2, 1 RAM is allocated for use by controller sub-module 3, and 1 RAM is allocated for use by controller sub-module 4. The RAM addresses of each RAM are remapped, and the RAM address ranges of the controller sub-module 1, the controller sub-module 2, the controller sub-module 3 and the controller sub-module 4 may be 0KB to 63KB.

Similarly, the buffer slice management modules of the controller sub-module 1, the controller sub-module 2, the controller sub-module 3 and the controller sub-module 4 may divide the 1 RAM mapped by the address into a plurality of storage units, and then the buffer slice management module stores the data packet into different storage units according to the type of the data packet, which is not described herein in detail.

By dividing the RAM into a plurality of storage units for block management, the storage management of different types of data packets can be realized.

In the above example, different storage units may be used to store three types of data packets, respectively, of the post, non-post, and Completion.

In some alternative embodiments, the buffer slice management module parses the data type of the data in the data packet, and the buffer bus selector module writes the data packet to the memory unit of the RAM according to the data type of the data in the data packet and the address of the RAM that has been address remapped.

Specifically, each controller sub-module includes a data link layer, each controller sub-module can receive a data packet from the data link layer, and then parse the data packet to obtain a data type of data in the data packet, where the data type of the data in the data packet can be three types of disposition, non-disposition and Completion.

After obtaining the data type in the data packet, the cache bus selector module may write the data packet to a different memory location of the RAM based on the data type of the data and the remapped address of the RAM.

For example, the data type of the data in the data packet is a post type, which may be stored in the first storage unit of the RAM, where the address range of the first storage unit may be 0KB to 127KB, if the 0 address of the storage unit is not stored, the data packet may be stored from 0bit, and if the storage unit has already stored another data packet before, the data packet may be stored from the free address of the data packet.

In some alternative embodiments, the cache slice management module receives a read request for the target data, and the cache slice management module acquires the target data from different storage units of the RAM corresponding to the cache slice management module according to the data type of the target data.

Specifically, the buffer slice management module may receive a read request of a post module of the multi-port switching device for target data, then acquire the target data from a storage unit corresponding to the RAM of the buffer slice management module according to a data type of the target data, and then send the target data to the post module.

The multi-port switching device sharing caching method is applied to a multi-port switching device interface unit, wherein the multi-port switching device interface unit comprises a RAM module, a controller module and a cache bus selector module, the RAM module comprises a plurality of RAMs, and the controller module comprises a plurality of controller sub-modules. First, the cache bus selector module obtains configuration information for at least one controller sub-module. Secondly, the cache bus selector module determines the controller sub-module in an activated state according to the configuration information of at least one controller sub-module. The cache bus selector module then allocates at least one of the plurality of RAMs to the controller submodule in an activated state. And finally, the cache bus selector module re-maps the allocated address of the at least one RAM, and establishes a mapping relation between the at least one RAM and the controller submodule in an activated state. According to the method and the device, at least one of the RAMs is distributed to the controller submodule in the activated state through the cache bus selector module, and the address of the at least one distributed RAM is remapped, namely, the cache bus selector module can flexibly distribute RAM resources according to the distribution state of the equipment port, unified management of the RAMs is achieved, and waste of cache is reduced.

With further reference to fig. 9, as an implementation of the method shown in the above figures, the present disclosure provides an embodiment of a multiport switching device interface unit apparatus, which corresponds to the method embodiment shown in fig. 3.

The multi-port switching device interface unit shown in this embodiment includes a RAM module, a controller module, and a cache bus selector module, where the RAM module includes a plurality of RAMs, the controller module includes a plurality of controller sub-modules,

a cache bus selector module configured to obtain configuration information for at least one controller sub-module;

a cache bus selector module further configured to determine a controller sub-module in an activated state based on configuration information of at least one controller sub-module;

a cache bus selector module further configured to allocate at least one of the plurality of RAMs to a controller submodule in an activated state;

the cache bus selector module is further configured to remap the allocated address of the at least one RAM, and establish a mapping relationship between the at least one RAM and the controller submodule in an activated state.

As shown in fig. 9, the present embodiment provides a multi-port switching device shared buffer device, which is a buffer bus selector module running in an interface unit of the multi-port switching device, and the device includes an obtaining unit 901, a determining unit 902, an allocating unit 903, and an establishing unit 904.

The acquiring unit 901 is configured to acquire configuration information for at least one controller sub-module;

a determining unit 902, configured to determine, according to configuration information of at least one controller sub-module, a controller sub-module in an activated state;

an allocation unit 903 for allocating at least one of the plurality of RAMs to the controller submodule in an activated state;

and the establishing unit 904 is used for remapping the address of the at least one RAM after allocation, and establishing a mapping relation between the at least one RAM and the controller submodule in an activated state.

In some alternative embodiments, the dispensing unit 903 is further configured to: a cache bus selector module allocates at least one of a plurality of RAMs to a controller submodule in an activated state, comprising:

the cache bus selector module allocates at least one of the plurality of RAMs to the controller submodule in an activated state based on the identification information of the at least one controller submodule in the activated state and the type of the at least one controller submodule in the activated state.

In some alternative embodiments, the establishing unit 904 is further configured to: the cache bus selector module re-maps the allocated address of the at least one RAM, establishes a mapping relationship between the at least one RAM and the controller submodule in an activated state, and comprises the following steps:

The cache bus selector module re-maps the address of each RAM according to the distribution quantity of the RAMs in each activated controller sub-module and the address length of each RAM, and establishes a mapping relation from at least one RAM to the activated controller sub-module.

In some alternative embodiments, the apparatus may further comprise:

the writing unit 905 is configured to write the data packet into different storage units of the RAM according to the data type of the data in the data packet and the address of the RAM mapped by the address.

In some alternative embodiments, the total capacity of the plurality of RAMs matches the RAM capacity required for the maximum number of channels.

In some alternative embodiments, the amount of RAM is equal to a multiple of the number of controller sub-modules.

In some alternative embodiments, the controller sub-modules may be of different types including different link widths.

The embodiment provides a multi-port switching device sharing buffer device, which operates on a buffer slice management module of an interface unit of the multi-port switching device, and the device includes a dividing unit 1001 and a storage unit 1002. Wherein,

a dividing unit 1001 for dividing the RAM subjected to address remapping into a plurality of memory units;

The storage unit 1002 is configured to store the data packet to different storage units according to the type of the data packet.

In some alternative embodiments, the apparatus further comprises:

an parsing unit 1003, configured to parse a data type of data in the data packet;

in some alternative embodiments, the apparatus further comprises:

a receiving unit 1004 for receiving a read request for target data;

the obtaining unit 1005 is configured to obtain the target data from different storage units of the RAM corresponding to the cache slice management module according to the data type of the target data.

It should be noted that, the implementation details and technical effects of each unit in the shared buffer device of the multiport switching device provided in the embodiments of the present disclosure may refer to the descriptions of other embodiments in the present disclosure, which are not described herein again.

In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to implement a multi-port switching device sharing caching method as shown in the embodiment and alternative implementations of fig. 3.

Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments described in the present disclosure may be implemented by means of software, or may be implemented by means of hardware. The name of the unit does not constitute a limitation of the unit itself in some cases, and for example, the acquisition unit may also be described as "a unit for acquiring configuration information".

The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this disclosure is not limited to the specific combinations of features described above, but also covers other embodiments which may be formed by any combination of features described above or equivalents thereof without departing from the spirit of the disclosure. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).

Claims (10)

1. A multi-port switching device sharing caching method, applied to a multi-port switching device interface unit, the multi-port switching device interface unit including a RAM module, a controller module, and a cache bus selector module, the RAM module including a plurality of RAMs, the controller module including a plurality of controller sub-modules, the method comprising:

the cache bus selector module obtains configuration information for at least one controller submodule;

the cache bus selector module determines the controller submodule in an activated state according to configuration information of at least one controller submodule;

The cache bus selector module allocates at least one of the plurality of RAMs to the controller submodule in an activated state;

and the cache bus selector module re-maps the allocated address of at least one RAM, and establishes a mapping relation between the at least one RAM and the controller submodule in an activated state.

2. The method of claim 1, wherein the cache bus selector module assigns at least one of the plurality of RAMs to the controller submodule in an activated state, comprising:

the cache bus selector module allocates at least one of the plurality of RAMs to the controller sub-module in an activated state based on identification information of at least one of the controller sub-modules in the activated state and a type of at least one of the controller sub-modules in the activated state.

3. The method of claim 1, wherein the cache bus selector module re-maps the allocated address of the at least one RAM, and wherein establishing a mapping of the at least one RAM to the controller submodule in an activated state includes:

And the cache bus selector module re-maps the address of each RAM according to the distribution quantity of the RAMs in each activated controller sub-module and the address length of each RAM, and establishes a mapping relation from at least one RAM to the activated controller sub-module.

4. The method of claim 3, wherein the controller submodule further comprises a cache slice management module, the method further comprising:

the cache slice management module divides the RAM subjected to address remapping into a plurality of storage units;

and the cache slice management module stores the data packet to different storage units according to the type of the data packet.

5. The method according to claim 4, wherein the method further comprises:

the cache slice management module analyzes the data type of the data in the data packet;

the cache bus selector module writes the data packet into different storage units of the RAM according to the data type of the data in the data packet and the address of the RAM subjected to address remapping.

6. The method according to claim 4, wherein the method further comprises:

The cache slice management module receives a read request for target data;

and the cache slice management module acquires the target data from different storage units of the RAM corresponding to the cache slice management module according to the data type of the target data.

7. The method of claim 1, wherein a total capacity of a plurality of said RAMs and a RAM capacity required for a maximum number of channels are matched.

8. The method of claim 1, wherein the amount of RAM is equal to a multiple of the number of controller sub-modules.

9. The method of claim 2, wherein the types of controller submodules include different link width types.

10. A multi-port switching device interface unit comprising a RAM module, a controller module and a cache bus selector module, the RAM module comprising a plurality of RAMs, the controller module comprising a plurality of controller sub-modules, the controller sub-modules comprising switching device ports, wherein,

the cache bus selector module is configured to acquire configuration information for at least one controller submodule;

The cache bus selector module is further configured to determine the controller submodule in an activated state according to configuration information of at least the controller submodule;

the cache bus selector module is further configured to allocate at least one of the plurality of RAMs to the controller submodule in an activated state;

the cache bus selector module is further configured to remap the allocated address of at least one RAM, and establish a mapping relationship between at least one RAM and the controller submodule in an activated state.