CN117637670A - Molded electronic device - Google Patents
Molded electronic device Download PDFInfo
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- CN117637670A CN117637670A CN202310909350.9A CN202310909350A CN117637670A CN 117637670 A CN117637670 A CN 117637670A CN 202310909350 A CN202310909350 A CN 202310909350A CN 117637670 A CN117637670 A CN 117637670A
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- level difference
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- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims description 22
- -1 polyethylene terephthalate Polymers 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- XECAHXYUAAWDEL-UHFFFAOYSA-N acrylonitrile butadiene styrene Chemical compound C=CC=C.C=CC#N.C=CC1=CC=CC=C1 XECAHXYUAAWDEL-UHFFFAOYSA-N 0.000 claims description 7
- 229920000122 acrylonitrile butadiene styrene Polymers 0.000 claims description 7
- 239000004676 acrylonitrile butadiene styrene Substances 0.000 claims description 7
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 7
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 7
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 239000004593 Epoxy Substances 0.000 claims description 5
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 5
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 5
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 5
- 229920000728 polyester Polymers 0.000 claims description 5
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 5
- 229920001296 polysiloxane Polymers 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229920000515 polycarbonate Polymers 0.000 claims description 4
- 239000004417 polycarbonate Substances 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229920002635 polyurethane Polymers 0.000 claims description 3
- 239000004814 polyurethane Substances 0.000 claims description 3
- 239000004695 Polyether sulfone Substances 0.000 claims 1
- 150000002148 esters Chemical class 0.000 claims 1
- 229920006393 polyether sulfone Polymers 0.000 claims 1
- 239000011135 tin Substances 0.000 claims 1
- 238000005452 bending Methods 0.000 abstract description 6
- 230000032798 delamination Effects 0.000 description 9
- 238000003856 thermoforming Methods 0.000 description 7
- 230000005856 abnormality Effects 0.000 description 5
- 230000037303 wrinkles Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 2
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 2
- 239000005977 Ethylene Substances 0.000 description 2
- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920005644 polyethylene terephthalate glycol copolymer Polymers 0.000 description 2
- KKEYFWRCBNTPAC-UHFFFAOYSA-L terephthalate(2-) Chemical compound [O-]C(=O)C1=CC=C(C([O-])=O)C=C1 KKEYFWRCBNTPAC-UHFFFAOYSA-L 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention discloses a molded electronic device. The molded electronic device includes a flex substrate, a first circuit layer, a dielectric layer, a level difference compensation layer, and a second circuit layer. The curved substrate has a first surface. The first circuit layer is arranged on the first surface. The dielectric layer is disposed on the first circuit layer and has a first thickness. The level difference compensation layer is arranged on the first surface and connected with the dielectric layer. The step compensation layer has a second thickness. The second circuit layer is arranged on the level difference compensation layer and is electrically connected with the level difference compensation layer. The curvature radius of the bending substrate is c, the ratio of the second thickness to the first thickness is r, and the c and the r accord with the relation: r=1.5-0.02 c±15%.
Description
Technical Field
The present invention relates to an electronic device, and more particularly, to a molded electronic device having a level difference compensation layer.
Background
In an in-mold electronics (IME) device, if there is a structural level difference between stacked structures of multiple layers (such as a structural level difference between a substrate/an insulating dielectric layer/a metal wire), after a manufacturing process of thermoforming, a problem of abnormal structural interface (such as delamination or wrinkles) is easily caused at the structural level difference, thereby affecting the reliability of the molded electronic device.
Disclosure of Invention
The invention is directed to a molded electronic device that can reduce interfacial anomalies (e.g., delamination or wrinkling) by providing a level difference compensation layer, and thus has improved reliability.
According to an embodiment of the present invention, a molded electronic device includes a flex substrate, a first wiring layer, a dielectric layer, a level difference compensation layer, and a second wiring layer. The curved substrate has a first surface. The first circuit layer is arranged on the first surface. The dielectric layer is disposed on the first circuit layer and has a first thickness. The level difference compensation layer is arranged on the first surface and connected with the dielectric layer. The step compensation layer has a second thickness. The second circuit layer is arranged on the level difference compensation layer and is electrically connected with the level difference compensation layer. The curvature radius of the bending substrate is c, the ratio of the second thickness to the first thickness is r, and the c and the r accord with the relation: r=1.5-0.02 c±15%.
In the molded electronic device according to the embodiment of the invention, the first surface is convex, concave, or a combination thereof.
In the molded electronic device according to the embodiment of the invention, the interface is formed between the second circuit layer and the level difference compensation layer.
In the molded electronic device according to the embodiment of the present invention, the radius of curvature described above is less than or equal to 60 mm.
In the molded electronic device according to the embodiment of the invention, the first wiring layer, the second wiring layer, and the level difference compensation layer described above have the same material.
In the molded electronic device according to the embodiment of the present invention, the material of the step compensation layer described above includes a metal.
In the molded electronic device according to the embodiment of the present invention, the material of the above-described curved substrate includes polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene terephthalate-1, 4-cyclohexanedimethanol (Poly (ethylene terephthalateco-1,4-cylclohexylenedimethylene terephthalate), PETG), polycarbonate (PC), polyimide (PI), polymethyl methacrylate (PMMA), polyethersulfone (PES), polydimethylsiloxane (PDMS), acrylonitrile-butadiene-styrene copolymer (acrylonitrile butadiene styrene, ABS), acryl (acrylic), or a combination thereof.
In the molded electronic device according to the embodiment of the invention, the thickness of the above-described curved substrate is 0.1 mm to 5 mm.
In the molded electronic device according to the embodiment of the present invention, the young's modulus of the above-described curved substrate is 0.5GPa to 20GPa.
In the molded electronic device according to the embodiment of the invention, the materials of the first circuit layer and the second circuit layer include gold, silver, copper, aluminum, nickel, tin, an alloy thereof, or a combination thereof.
In the molded electronic device according to the embodiment of the present invention, the material of the dielectric layer described above includes acrylic (acryl), epoxy (epoxy), phenol (phenol), polyester (polyester), polyurethane (urethane), silicone (silicone), or polyimide.
In the molded electronic device according to the embodiment of the invention, the second wiring layer described above is electrically connected to the first wiring layer through the level difference compensation layer.
In the molded electronic device according to the embodiment of the invention, the second circuit layer is electrically independent from the first circuit layer.
In the molded electronic device according to the embodiment of the invention, the step compensation layer is disposed between the second circuit layer and the first circuit layer.
In the molded electronic device according to the embodiment of the invention, the above-described level difference compensation layer contacts the first surface of the curved substrate.
In the molded electronic device according to the embodiment of the invention, the second circuit layer has a first side surface and a second side surface opposite to each other. The first side surface cuts Ji Jiedian the side surfaces of the level difference compensation layer away and the second side surface cuts the side surfaces of the level difference compensation layer away from the dielectric layer.
Based on the above, in the molded electronic device according to an embodiment of the present invention, by setting the level difference compensation layer, the second thickness of the level difference compensation layer may conform to the relationship: r=1.5 to 0.02c±15% (where r is the ratio of the second thickness of the step compensating layer to the first thickness of the dielectric layer, and c is the radius of curvature of the curved substrate), so that the molded electronic device of the present embodiment can reduce the problem of abnormal interface (such as delamination or wrinkles) caused by the manufacturing process of thermoforming, and further the molded electronic device of the present embodiment can have better reliability.
Drawings
FIG. 1A is a schematic perspective view of a molded electronic device according to an embodiment of the invention;
FIG. 1B is a schematic cross-sectional view of the molded electronic device of FIG. 1A along section line A-A';
FIG. 2A is a schematic perspective view of a molded electronic device according to another embodiment of the invention;
FIG. 2B is a schematic cross-sectional view of the molded electronic device of FIG. 2A along section line B-B';
FIG. 3A is a first plot of interface stress versus second thickness of the step compensation layer in examples 1-6;
FIG. 3B is a first plot of interface stress versus second thickness of the step compensation layer in examples 7-11;
FIG. 3C is a first plot of interface stress versus second thickness of the step compensation layer in examples 12-18;
FIG. 4 is a second graph of radius of curvature and ratio of second thickness of the step compensation layer to first thickness of the dielectric layer.
Description of the reference numerals
100. 100a: molded electronic device
110: curved substrate
111: a first surface
120: first circuit layer
121: part of the
122: another part is provided with
130: dielectric layer
131. 132: side surfaces
140. 140a: level difference compensation layer
141. 142: side surfaces
150. 150a: second circuit layer
151. 151a: first part
152. 152a: second part
153: a first side surface
154: a second side surface
c: radius of curvature
IF: interface(s)
r: ratio of
T: thickness of (L)
T1: first thickness of
T2: second thickness of
X, Y, Z: direction of
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Fig. 1A shows a schematic perspective view of a molded electronic device according to an embodiment of the invention. FIG. 1B shows a schematic cross-sectional view of the molded electronic device of FIG. 1A along section line A-A'.
Referring to fig. 1A and fig. 1B, the molded electronic device 100 of the present embodiment includes a curved substrate 110, a first circuit layer 120, a dielectric layer 130, a step compensation layer 140 and a second circuit layer 150. Wherein the curved substrate 110 has a first surface 111. The first surface 111 may be convex, concave, or a combination thereof, but is not limited thereto. The bending substrate 110 may be a plastic substrate including a plastic material, but is not limited thereto. The material of the bending substrate 110 may include polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene terephthalate-1, 4-cyclohexanedimethanol (Poly (ethylene terephthalateco-1,4-cylclohexylenedimethylene terephthalate), PETG), polycarbonate (PC), polyimide (PI), polymethyl methacrylate (PMMA), polyethersulfone (PES), polydimethylsiloxane (PDMS), acrylonitrile-butadiene-styrene copolymer (acrylonitrile butadiene styrene, ABS), acryl (acrylic), or a combination thereof, but is not limited thereto.
In the present embodiment, the curved substrate 110 has a radius of curvature c, and the radius of curvature c may be, for example, 60 millimeters (mm) or less, but is not limited thereto. For example, the radius of curvature c of the curved substrate 110 may be, for example, 20, 25, 30, 35, 40, 45, 50, 55, or 60 millimeters, but is not limited thereto.
In the present embodiment, the thickness T of the curved substrate 110 may be, for example, 0.1 mm to 5 mm, but is not limited thereto. In the present embodiment, young's modulus (Young's modulus) of the bending substrate 110 may be, for example, 0.5GPa to 20GPa, but is not limited thereto.
In the present embodiment, the directions X, Y, and Z in fig. 1A and 1B are different directions, respectively. The direction X is, for example, the direction of extension of the section line A-A', and the direction Y is, for example, the normal direction of the molded electronic device 100. The direction X is substantially perpendicular to the direction Y, and the directions X and Y are substantially perpendicular to the direction Z, respectively, but are not limited thereto.
In the present embodiment, the first circuit layer 120 is disposed on the first surface 111 of the curved substrate 110. The material of the first circuit layer 120 may include gold, silver, copper, aluminum, nickel, tin, an alloy thereof, or a combination thereof, but is not limited thereto.
In the present embodiment, the dielectric layer 130 is disposed on the first circuit layer 120 to cover a portion 121 of the first circuit layer 120 and expose another portion 122 of the first circuit layer 120. The dielectric layer 130 has a side surface 131 and a side surface 132 opposite to each other. Wherein the side surface 131 is far from the level difference compensation layer 140, and the side surface 132 contacts and connects with the level difference compensation layer 140. The dielectric layer 130 has a first thickness T1. The material of the dielectric layer 130 may include acrylic (acryl), epoxy (epoxy), phenol (phenol), polyester (polyester), polyurethane (urethane), silicone (silicone), or polyimide, but is not limited thereto.
In the present embodiment, the level difference compensation layer 140 is disposed on the first surface 111 of the curved substrate 110. The level difference compensation layer 140 is disposed on the other portion 122 of the first circuit layer 120. The level difference compensation layer 140 may contact another portion 122 of the first circuit layer 120, and the level difference compensation layer 140 may overlap another portion 122 of the first circuit layer 120 in the direction Y. The level difference compensation layer 140 is disposed between the second circuit layer 150 and the first circuit layer 120. The material of the level difference compensation layer 140 may include silver, aluminum, or other suitable metals, but is not limited thereto.
In the present embodiment, the level difference compensation layer 140 has a side surface 141 and a side surface 142 opposite to each other. Wherein, the side surface 141 of the level difference compensation layer 140 can contact and connect with the side surface 132 of the dielectric layer 130, and the side surface 142 is far away from the level difference of the dielectric layer 130. The level difference compensation layer 140 has a second thickness T2.
In the present embodiment, the ratio of the second thickness T2 of the step compensating layer 140 to the first thickness T1 of the dielectric layer 130 is r, and the curvature radius c and the ratio r can satisfy the following relationship: r=1.5 to 0.02c±15%, but is not limited thereto.
In the present embodiment, the second circuit layer 150 is disposed on the dielectric layer 130 and the level difference compensation layer 140. The second circuit layer 150 includes a first portion 151 that may overlap the dielectric layer 130 in the direction Y and a second portion 152 that does not overlap the dielectric layer 130 in the direction Y. The first portion 151 may further overlap the first circuit layer 120 in the direction Y, and the second portion 152 may further overlap the level difference compensation layer 140 in the direction Y. The level difference compensation layer 140 is disposed between the second portion 152 of the second circuit layer 150 and the other portion 122 of the first circuit layer 120.
In the present embodiment, an interface IF or a seam is formed between the second circuit layer 150 and the level difference compensation layer 140. The material of the second circuit layer 150 may include gold, silver, copper, aluminum, nickel, tin, an alloy thereof, or a combination thereof, but is not limited thereto. In some embodiments, the first wiring layer 120, the second wiring layer 150, and the level difference compensation layer 140 may have the same material.
In the present embodiment, the second circuit layer 150 may be electrically connected to the level difference compensation layer 140. The second circuit layer 150 may be electrically connected to the first circuit layer 120 through the level difference compensation layer 140, so that the second circuit layer 150 and the first circuit layer 120 may transmit the same signal. In the present embodiment, the second circuit layer 150 has a first side surface 153 and a second side surface 154 opposite to each other. Wherein the first side surface 153 cuts Ji Jiedian the layer 130 away from the side surface 131 of the level difference compensation layer 140 and the second side surface 154 cuts the level difference compensation layer 140 away from the side surface 142 of the dielectric layer 130.
In this embodiment, the manufacturing method of the molded electronic device 100 may include, but is not limited to, the following steps: providing a planar substrate (or non-curved substrate) (not shown), wherein the planar substrate has a first surface 111; forming a first circuit layer 120 on the first surface 111 of the planar substrate; forming a dielectric layer 130 on the first circuit layer 120 to cover a portion 121 of the first circuit layer 120 and expose another portion 122 of the first circuit layer 120; forming a level difference compensation layer 140 on the other portion 122 of the first circuit layer 120, such that the level difference compensation layer 140 contacts the first circuit layer 120 and connects the dielectric layer 130; forming a second circuit layer 150 on the dielectric layer 130 and the level difference compensation layer 140, such that the second circuit layer 150 can overlap the first circuit layer 120 and the level difference compensation layer 140 in the direction Y, and the second circuit layer 150 can be electrically connected to the first circuit layer 120 through the level difference compensation layer 140; the thermoforming process is performed to bend the planar substrate into a curved substrate 110, and to allow the curved substrate 110 to be disposed on a mold having a curved surface (including convex, concave, or a combination thereof). Thus, the molded electronic device 100 of the present embodiment can be substantially manufactured.
Although there is a structural level difference between the stack structures of the second circuit layer 150, the dielectric layer 130 and the first circuit layer 120 in the molded electronic device 100 of the present embodiment, the present embodiment is configured by the level difference compensation layer 140, and the second thickness T2 of the level difference compensation layer 140 can conform to the relationship: r=1.5 to 0.02c±15% (where r is the ratio of the second thickness T2 of the step compensating layer 140 to the first thickness T1 of the dielectric layer 130, and c is the radius of curvature of the curved substrate 110), so that the problem of interface abnormality (such as delamination or wrinkling) at the structural step caused by the thermoforming process can be reduced, and the molded electronic device 100 of the present embodiment can have better reliability.
In addition, in some embodiments, by disposing the level difference compensation layer 140 between the second portion 152 of the second circuit layer 150 and the other portion 122 of the first circuit layer 120, the second portion 152 of the second circuit layer 150 may overlap the level difference compensation layer 140 in the direction Y, and the second side surface 154 of the second circuit layer 150 may align the level difference compensation layer 140 away from the side surface 142 of the dielectric layer 130, such that the problem of interface abnormality (such as delamination or wrinkling) caused by the thermoforming process at the structural level difference can be reduced, and thus the molded electronic device 100 having the level difference compensation layer 140 can have better reliability.
Other examples will be listed below as illustration. It should be noted that the following embodiments use the signal reference numerals and part of the content of the foregoing embodiments, where the same reference numerals are used to denote the same or similar signals, and descriptions of the same technical content are omitted. For the description of the omitted parts, reference is made to the foregoing embodiments, and the following embodiments are not repeated.
Fig. 2A shows a schematic perspective view of a molded electronic device according to another embodiment of the invention. FIG. 2B shows a schematic cross-sectional view of the molded electronic device of FIG. 2A along section line B-B'. Referring to fig. 1A, 1B, 2A and 2B, the molded electronic device 100a of the present embodiment is similar to the molded electronic device 100 in fig. 1A, but the main differences are as follows: in the molded electronic device 100a of the present embodiment, the second circuit layer 150a is not electrically connected to the first circuit layer 120.
Specifically, referring to fig. 2A and fig. 2B, in the present embodiment, the step compensating layer 140a is disposed on the first surface 111 of the curved substrate 110. The level difference compensation layer 140a may contact the first surface 111 of the curved substrate 110. The level difference compensation layer 140a overlaps the second circuit layer 150a in the direction Y, and the level difference compensation layer 140a does not overlap the other portion 122 of the first circuit layer 120 in the direction Y.
In the present embodiment, the second circuit layer 150a includes a first portion 151a that may overlap the dielectric layer 130 in the direction Y and a second portion 152a that does not overlap the dielectric layer 130 in the direction Y. The first portion 151a does not overlap the first circuit layer 120 in the direction Y, and the second portion 152a may also overlap the level difference compensation layer 140a in the direction Y. The level difference compensation layer 140a is disposed between the second portion 152a of the second circuit layer 150a and the first surface 111 of the curved substrate 110.
In the present embodiment, the second circuit layer 150a is not electrically connected to the first circuit layer 120 (that is, the second circuit layer 150a is electrically independent from the first circuit layer 120), so that the second circuit layer 150a and the first circuit layer 120 can respectively transmit different signals.
Hereinafter, the relationship (i.e., the relationship r=1.5 to 0.02c±15%) among the radius of curvature c, the first thickness T1 and the second thickness T2 defined in the molded electronic device of the above embodiment is described in detail by experimental examples, and the effect of reducing interface abnormality (e.g., delamination or wrinkles) can be obtained. However, the following experimental examples are not intended to limit the present invention.
Experimental example 1
In this experimental example, a first relation between the second thickness T2 of the step compensating layer and the interface stress S in the molded electronic device was calculated by measuring the variation of the interface stress of the molded electronic device in the different embodiments (embodiment 1 to embodiment 18), and a second relation between the radius of curvature c of the curved substrate, the first thickness T1 of the first wiring layer, and the second thickness T2 of the second wiring layer in the molded electronic device was calculated. In this experimental example, when the interfacial stress S is greater than 0.1MPa, there is a problem of interfacial abnormality (e.g., delamination, wrinkles, etc.).
In examples 1 to 18, the material of the bending substrate was 0.5 mm polycarbonate, the material of the dielectric layer was silicone resin, and the materials of the first wiring layer, the second wiring layer, and the step compensating layer were silver. The radius of curvature c of the curved substrate, the first thickness T1 of the dielectric layer, the thickness of the first wiring layer, the second thickness T2 of the step compensation layer, and the thickness of the second wiring layer used in the different embodiments are shown in table 1. The results of the interfacial stress S measured in the different examples are also shown in table 1.
TABLE 1
Then, according to the results of table 1, the relationship between the second thickness T2 of the step difference compensation layer and the corresponding interface stress S in examples 1 to 6 is plotted as a first relationship chart as shown in fig. 3A. Next, a first regression curve (broken line in fig. 3A) is drawn according to the first relationship diagram, and the equation of the first regression curve (i.e., the first relationship between the second thickness T2 of the level difference compensation layer and the interface stress S) is calculated as s= -0.0001×t2 2 -0.0032×t2+0.1029. As can be seen from the first relation, when the radius of curvature c of the curved substrate in the molded electronic device is 60mm and the first thickness T1 of the dielectric layer is 10 μm, the second thickness T2 of the step compensating layer should be at least 3 μm to avoid the interfacial stress S being greater than 0.1MPa. That is, when the radius of curvature c of the curved substrate is 60mm, the ratio r of the second thickness T2 of the step compensating layer to the first thickness T1 of the dielectric layer should be at least greater than 0.3.
According to the results of table 1, the relationship between the second thickness T2 of the step difference compensation layer and the corresponding interface stress S in examples 7 to 11 is plotted as a first relationship chart shown in fig. 3B. Next, a first regression curve (broken line in fig. 3B) is drawn according to the first relationship diagram, and the equation of the first regression curve (i.e., the first relationship between the second thickness T2 of the step compensating layer and the interface stress S) is calculated to be s=0.0006×t2 2 -0.0167 x T2+0.1894. As can be seen from the first relation, when the radius of curvature c of the curved substrate in the molded electronic device is 40mm and the first thickness T1 of the dielectric layer is 10 μm, the second thickness T2 of the level difference compensation layer should be at least 7 μm to avoidThe interfacial stress S is greater than 0.1MPa. That is, when the curvature radius c of the curved substrate is 40mm, the ratio r of the second thickness T2 of the step compensating layer to the first thickness T1 of the dielectric layer should be at least greater than 0.7.
According to the results of table 1, the relationship between the second thickness T2 of the step difference compensation layer and the corresponding interface stress S in examples 12 to 18 is plotted as a first relationship chart shown in fig. 3C. Next, a first regression curve (broken line in fig. 3C) is drawn according to the first relationship diagram, and the equation of the first regression curve (i.e., the first relationship between the second thickness T2 of the level difference compensation layer and the interface stress S) is calculated as s= -0.0004×t2 2 -0.0029×t2+0.1677. As can be seen from the first relation, when the radius of curvature c of the curved substrate in the molded electronic device is 20mm and the first thickness T1 of the dielectric layer is 10 μm, the second thickness T2 of the step compensating layer should be at least 11 μm to avoid the interfacial stress S being greater than 0.1MPa. That is, when the curvature radius c of the curved substrate is 20mm, the ratio r of the second thickness T2 of the step compensating layer to the first thickness T1 of the dielectric layer should be at least greater than 1.1.
Then, based on the above results, the relationship between the radius of curvature c and the corresponding ratio r is plotted as a second relationship chart as shown in fig. 4. Next, a second regression curve (a broken line in fig. 4) is drawn from the second relationship chart, and an equation of the second regression curve (i.e., a second relationship between the radius of curvature c and the ratio r) is calculated to be r=1.5 to 0.02c±15%. Wherein the ratio r is greater as the radius of curvature c is smaller.
Experimental example 2
In this experimental example, the relation between the radius of curvature c and the ratio r in experimental example 1 was verified to be applicable to the molded electronic devices of the other different embodiments by measuring the variation in the interfacial stress of the molded electronic devices of the different embodiments (embodiment 19 to embodiment 27).
The same materials as those of examples 1 to 18 were used in examples 19 to 27, except that the first thickness T1 of the dielectric layer and the thickness of the second wiring layer were both increased to 20 μm. The radius of curvature c of the curved substrate, the first thickness T1 of the dielectric layer, the thickness of the first wiring layer, the second thickness T2 of the step compensating layer, and the thickness of the second wiring layer used in the different embodiments are shown in table 2, and the results of the interface stress S measured in the different embodiments are also shown in table 2.
TABLE 2
From the relation r=1.5 to 0.02c±15% between the radius of curvature c and the ratio r obtained in experimental example 1, it is known that: when the radius of curvature c is 60mm and the first thickness T1 of the dielectric layer is 20 μm, the second thickness T2 of the level difference compensation layer should be at least 6 μm to avoid the interfacial stress being greater than 0.1MPa; when the curvature radius c is 40mm and the first thickness T1 of the dielectric layer is 20 mu m, the second thickness T2 of the level difference compensation layer is at least 14 mu m so as to avoid the interface stress being larger than 0.1MPa; and when the radius of curvature c is 20mm and the first thickness T1 of the dielectric layer is 20 μm, the second thickness T2 of the level difference compensation layer should be at least 22 μm to avoid the interfacial stress being greater than 0.1MPa.
From the results of table 2, it is understood that when the radius of curvature c is 60mm and the first thickness T1 of the dielectric layer is 20 μm, the use of the step compensating layer having the second thickness T2 of 6 μm, 7 to 11 μm or 12 to 15 μm can surely avoid the interfacial stress S from being greater than 0.1MPa, so that the predicted result of the relation r=1.5 to 0.02c±15% is satisfied. When the radius of curvature c is 40mm and the first thickness T1 of the dielectric layer is 20 μm, the use of the step compensating layer having the second thickness T2 of 14 μm, 15 to 17 μm or 18 to 20 μm can surely avoid the interfacial stress S from being greater than 0.1MPa, so that the predicted result of the relation r=1.5 to 0.02c±15% is satisfied. When the radius of curvature c is 20mm and the first thickness T1 of the dielectric layer is 20 μm, the use of the step compensating layer having the second thickness T2 of 22 μm, 23 to 27 μm or 28 to 30 μm can surely avoid the interfacial stress S from being greater than 0.1MPa, so that the predicted result of the relation r=1.5 to 0.02c±15% is satisfied.
Experimental example 3
In this experimental example, the relation between the radius of curvature c and the ratio r in experimental example 1 was verified to be applicable to the molded electronic devices of the other different embodiments by measuring the variation in the interfacial stress of the molded electronic devices of the different embodiments (embodiment 28 to embodiment 36).
The same materials as those of examples 1 to 18 were used in examples 28 to 36, except that the first thickness T1 of the dielectric layer and the thickness of the second wiring layer were both increased to 30 μm. The radius of curvature c of the curved substrate, the first thickness T1 of the dielectric layer, the thickness of the first wiring layer, the second thickness T2 of the step compensating layer, and the thickness of the second wiring layer used in the various embodiments are shown in table 3, and the results of the interfacial stress S measured in the various embodiments are also shown in table 3.
TABLE 3 Table 3
From the relation r=1.5 to 0.02c±15% between the radius of curvature c and the ratio r obtained in experimental example 1, it is known that: when the radius of curvature c is 60mm and the first thickness T1 of the dielectric layer is 30 μm, the second thickness T2 of the level difference compensation layer should be at least 9 μm to avoid the interfacial stress being greater than 0.1MPa; when the curvature radius c is 40mm and the first thickness T1 of the dielectric layer is 30 mu m, the second thickness T2 of the level difference compensation layer is at least 21 mu m so as to avoid the interface stress being larger than 0.1MPa; and when the radius of curvature c is 20mm and the first thickness T1 of the dielectric layer is 30 μm, the second thickness T2 of the level difference compensation layer should be at least 33 μm to avoid the interfacial stress being greater than 0.1MPa.
From the results of table 3, it is understood that when the radius of curvature c is 60mm and the first thickness T1 of the dielectric layer is 30 μm, the use of the step compensating layer having the second thickness T2 of 9 μm, 10 to 14 μm or 15 to 30 μm can surely avoid the interfacial stress S from being greater than 0.1MPa, so that the predicted result of the relation r=1.5 to 0.02c±15% is satisfied. When the radius of curvature c is 40mm and the first thickness T1 of the dielectric layer is 30 μm, the use of the step compensating layer having the second thickness T2 of 21 μm, 22 to 26 μm or 27 to 30 μm can surely avoid the interface stress S from being greater than 0.1MPa, so that the predicted result of the relation r=1.5 to 0.02c±15% is satisfied. When the radius of curvature c is 20mm and the first thickness T1 of the dielectric layer is 30 μm, the use of the step compensating layer having the second thickness T2 of 33 μm, 34 to 36 μm or 37 to 40 μm can surely avoid the interface stress S from being greater than 0.1MPa, so that the predicted result of the relation r=1.5 to 0.02c±15% is satisfied.
In summary, in the molded electronic device according to an embodiment of the invention, the step compensating layer is disposed, and the second thickness of the step compensating layer can conform to the relationship: r=1.5 to 0.02c±15% (where r is the ratio of the second thickness of the step compensating layer to the first thickness of the dielectric layer, and c is the radius of curvature of the curved substrate), so that the molded electronic device of the present embodiment can reduce the problem of abnormal interface (such as delamination or wrinkles) caused by the manufacturing process of thermoforming, and further the molded electronic device of the present embodiment can have better reliability. In addition, in some embodiments, the problem of interface abnormality (such as delamination or wrinkling) caused by the thermoforming process at the structural level difference can be reduced by providing the level difference compensation layer between the second portion of the second circuit layer and the other portion of the first circuit layer, enabling the second portion of the second circuit layer to overlap the level difference compensation layer in the direction Y, and enabling the second side surface of the second circuit layer to be aligned with the side surface of the level difference compensation layer away from the dielectric layer, so that the molded electronic device with the level difference compensation layer can have better reliability.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (16)
1. A molded electronic device, comprising:
a curved substrate having a first surface;
a first circuit layer disposed on the first surface;
the dielectric layer is arranged on the first circuit layer and has a first thickness;
the step compensating layer is arranged on the first surface and connected with the dielectric layer, wherein the step compensating layer has a second thickness; and
the second circuit layer is arranged on the level difference compensation layer and is electrically connected with the level difference compensation layer,
wherein the curvature radius of the curved substrate is c, the ratio of the second thickness to the first thickness is r, and c and r conform to the relation: r=1.5-0.02 c±15%.
2. The molded electronic device of claim 1, wherein the first surface is convex, concave, or a combination thereof.
3. The molded electronic device of claim 1, wherein an interface is provided between the second wiring layer and the level difference compensation layer.
4. The molded electronic device of claim 1, wherein the radius of curvature is less than or equal to 60 millimeters.
5. The molded electronic device of claim 1, wherein the first wiring layer, the second wiring layer, and the level difference compensation layer have the same material.
6. The molded electronic device of claim 1, wherein the material of the level difference compensation layer comprises a metal.
7. The molded electronic device of claim 1, wherein the material of the flex substrate comprises polyethylene terephthalate, polyethylene terephthalate-1, 4-cyclohexanedimethanol ester, polycarbonate, polyimide, polymethyl methacrylate, polyethersulfone, polydimethylsiloxane, acrylonitrile-butadiene-styrene copolymer, acrylic, or a combination thereof.
8. The molded electronic device of claim 1, wherein the curved substrate has a thickness of 0.1 millimeters to 5 millimeters.
9. The molded electronic device of claim 1, wherein the flex substrate has a young's modulus of 0.5GPa to 20GPa.
10. The molded electronic device of claim 1, wherein the material of the first and second circuit layers comprises gold, silver, copper, aluminum, nickel, tin, alloys thereof, or combinations thereof.
11. The molded electronic device of claim 1, wherein the material of the dielectric layer comprises acrylic, epoxy, phenol, polyester, polyurethane, silicone, or polyimide.
12. The molded electronic device of claim 1, wherein the second wiring layer is electrically connected to the first wiring layer through the level difference compensation layer.
13. The molded electronic device of claim 1, wherein the second circuit layer is electrically independent of the first circuit layer.
14. The molded electronic device of claim 1, wherein the level difference compensation layer is disposed between the second circuit layer and the first circuit layer.
15. The molded electronic device of claim 1, wherein the level difference compensation layer contacts the first surface of the curved substrate.
16. The molded electronic device of claim 1, wherein the second circuit layer has a first side surface and a second side surface opposite each other, the first side surface being aligned with a side surface of the dielectric layer remote from the level difference compensation layer, and the second side surface being aligned with a side surface of the level difference compensation layer remote from the dielectric layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202263402481P | 2022-08-31 | 2022-08-31 | |
| US63/402,481 | 2022-08-31 | ||
| TW112121748 | 2023-06-09 |
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| Publication Number | Publication Date |
|---|---|
| CN117637670A true CN117637670A (en) | 2024-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310909350.9A Pending CN117637670A (en) | 2022-08-31 | 2023-07-24 | Molded electronic device |
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| Country | Link |
|---|---|
| CN (1) | CN117637670A (en) |
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- 2023-07-24 CN CN202310909350.9A patent/CN117637670A/en active Pending
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