CN117634426B - Defect mark generation method of circuit design, electronic equipment and storage medium - Google Patents
Defect mark generation method of circuit design, electronic equipment and storage medium Download PDFInfo
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- CN117634426B CN117634426B CN202410097658.2A CN202410097658A CN117634426B CN 117634426 B CN117634426 B CN 117634426B CN 202410097658 A CN202410097658 A CN 202410097658A CN 117634426 B CN117634426 B CN 117634426B
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- 230000007547 defect Effects 0.000 title claims abstract description 124
- 238000013461 design Methods 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000004807 localization Effects 0.000 claims abstract description 4
- 238000010586 diagram Methods 0.000 claims description 43
- 238000013507 mapping Methods 0.000 claims description 2
- 238000012552 review Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000012800 visualization Methods 0.000 description 1
Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Abstract
The invention relates to the technical field of EDA, in particular to a method for generating a defect mark of a circuit design, electronic equipment and a storage medium, wherein a table file is imported into an EDA tool, a defect positioning field in each item in the table file is extracted through the EDA tool, the circuit design is subjected to defect positioning according to the defect positioning field, and a defect graphic mark is generated; wherein the generating step of the defect graphic mark of the i-th item includes: extracting defect localization field LF of ith entry i The method comprises the steps of carrying out a first treatment on the surface of the Searching LF i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i The method comprises the steps of carrying out a first treatment on the surface of the In TP i Generating a defect pattern flag, and associating the defect pattern flag with the defect flag field CF of the i-th entry i Binding is performed. The method provided by the invention improves the defect searching efficiency.
Description
Technical Field
The present invention relates to the field of EDA technologies, and in particular, to a method for generating a defect mark for a circuit design, an electronic device, and a storage medium.
Background
In the current EDA tools, the information presented in the design interface is the design data itself, such as the attribute information of the components. But cannot reveal other additional tag information. For example, in a product design flow, an important link is performed when a circuit design is reviewed, and the circuit design review ring can utilize the unique advantage of each member of a team to improve the working quality of a single individual. In general, in order to keep secret, an original file of a circuit design is not directly adopted in the process of circuit design review, but a circuit diagram mode is adopted for a reviewer to review, and each reviewer can only point out problems in the circuit diagram and form a table file by intercepting part of views in the circuit diagram or pointing out names of a certain component in the circuit diagram and the like. The hardware designer needs to look up and modify the original file of the circuit design one by one according to the table files fed back by multiple reviewers.
The above manner makes it necessary for a hardware designer to locate and view the original files of the circuit design one by one and perform corresponding modification or feedback, so that the searching efficiency is low, and therefore, a method for quickly searching for defects in the circuit design is needed.
Disclosure of Invention
Aiming at the technical problems, the invention adopts the following technical scheme: a method of generating a defect mark for a circuit design, the method comprising the steps of:
s200, a table file is obtained, wherein the table file comprises a plurality of entries, and each entry comprises a defect locating field and a defect marking field of a circuit design.
S400, importing the table file into an EDA tool, and performing defect positioning on the circuit design according to each entry in the table file to generate a defect graphic mark; wherein the generating step of the defect graphic mark of the i-th item includes:
s420, extracting the defect location field LF of the ith item i 。
S440, find LF i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i 。
S460, at TP i Generating a defect pattern flag, and associating the defect pattern flag with the defect flag field CF of the i-th entry i Binding is performed.
The present invention also provides a non-transitory computer readable storage medium having stored therein at least one instruction or at least one program loaded and executed by a processor to implement the above-described method.
Furthermore, the invention also provides an electronic device comprising a processor and the non-transitory computer readable storage medium.
The invention has at least the following beneficial effects:
the invention provides a defect mark generation method, electronic equipment and storage medium of a circuit design, which are characterized in that a table file is imported into an EDA tool, a defect positioning field in each entry in the table file is extracted through the EDA tool, the circuit design is subjected to defect positioning according to the defect positioning field, and a defect graphic mark is generated. The invention solves the problems that in the prior art, the efficiency of checking the table files one by one and manually searching the circuit design to check the table files one by one and correspondingly modify or feed back is low, and the searching efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a defect mark generating method for a circuit design according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a defect graphical marker of a circuit design in an EDA tool.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Referring to the drawings, there is shown a flow chart of a defect mark generating method of circuit design, the method comprising the steps of:
s200, a table file is obtained, wherein the table file comprises a plurality of entries, and each entry comprises a defect locating field and a defect marking field of a circuit design.
Wherein the table file is a file independent of the EDA tool. In the circuit design review link, the circuit design diagrams of different layers for review are derived from the EDA tool, and a user reviews the circuit design diagrams of different layers and edits defect problems in the circuit design diagrams of different layers into a table file.
The defect locating field is used for indicating an object with defects in the circuit design diagram. For example, the defect localization field is the name of a certain component.
The defect mark field is used for describing information such as defect content, defect type, defect grade and the like.
S400, importing the table file into an EDA tool, and performing defect positioning on the circuit design according to each entry in the table file to generate a defect graphic mark, wherein the defect graphic mark is used for visually displaying a defect mark field.
The defect graph mark is a preset special graph and is specially used for marking defects, and when a user sees the defect graph mark in circuit design, the user can know that the object marked by the defect graph has defects.
Wherein the defect graphic marks generated according to the table have the same shape.
Further, the generating step of the defect graphic mark of the i-th item includes:
s420, extracting the defect location field LF of the ith item i 。
And extracting the defect locating field in the ith item according to the field identification of the defect locating field.
As one example, a table file includes N entries, each of which is made up of a plurality of table cells in a row, the top row of each table cell defining a field type for each column. Such as defect localization fields and defect marking fields, etc.
S440, find LF i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i 。
Wherein the image in the circuit design interface visualized in the EDA tool is not a normal picture, but is the result of the visualization in EDA of the data in the database of the circuit design, which changes synchronously when the circuit design is edited. Each component in the database has own attribute information, for example, the attribute of the pin includes attribute information such as pin number, pin network name, center point coordinate of the pin, pin shape, etc., and the component includes attribute information such as name of the component, center point coordinate of the component, shape of the component, etc.
S460, at TP i Generating a defect pattern flag, and associating the defect pattern flag with the defect flag field CF of the i-th entry i Binding is performed. When the user selects or designates the defect graphic mark, the defect mark field CF is visually displayed i Is a content of (3).
As a preferred embodiment, LF in S420 i Locating field S1LF for text-like defects i S440 further includes: searching LF according to text matching i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i . Searching LF by text matching in the prior art i Methods of location in circuit design fall within the scope of the present invention. Realize S1LF according to user specification i The purpose of generating the defect graphic marks is directly positioned in the circuit design.
As a preferred embodiment, the text class locator field S1LF i Including an object name field and an object type field. The object type field allows the selection of the object type displayed in the visual interface in the EDA tool.
As a preferred embodiment, LF in S420 i Locating field S2LF for image type defects i The S2LF i For attaching a partial diagram of the circuit design. In the case that the local diagram in the table file is in a picture format, and the position in the circuit design cannot be directly matched when the position in the circuit design is located by the local diagram in the picture format, S440 further includes:
s442, obtaining a plurality of different-layer circuit design drawings derived by the EDA tool, wherein the circuit design drawings of the different layers are original files for generating the local drawings. It should be noted that, the circuit design diagram reviewed by the table file is a circuit design diagram derived from the design data of the EDA, and the coordinates in the derived circuit design diagram are the same as the coordinates of the object stored in the database, so that the local diagram is template-matched in the originally derived circuit design diagram.
And S444, performing template matching in the circuit design diagram according to the partial diagram to obtain a matched target circuit design diagram and a target position. The derived circuit design diagram has layer identification, and different layers correspond to different circuit design diagrams. When the target circuit design diagram and the target position are obtained, the S2LF can be uniquely confirmed i Is a position of (c).
The template matching is realized by convolution, and the realization principle is as follows: when the size of the circuit design diagram is W×H and the size of the local diagram is w×h, the size of the generated diagram is (W-w+1) × (H-h+1), and each pixel value in the generated diagram represents the matching degree of the circuit design diagram and the local diagram. In the prior art, other methods for obtaining the position of the partial graph in the circuit design graph through template matching fall within the protection scope of the invention.
S446, the layer identification of the target circuit design drawing is acquired, and the layer identification and the target position are used as new positioning fields.
S448, searching the positioning coordinates of the new positioning field in the circuit design, and obtaining the target position TP of the ith item in the circuit design according to the positioning coordinates i . The purpose of locating the corresponding position in the circuit design and generating the defect graphic mark according to the local diagram pointed by the user is achieved.
As a preferred embodiment, the defect graphic marking binds a layer identification of the circuit design. The layer identification allows the selection of the visually displayed circuit design of the layer in the EDA tool.
As a preferred embodiment, when the ith item includes text class locator field S1LF i And image class location field S2LF i When giving preference to S1LF i Searching, when the result is not found, according to S2LF i And searching is carried out. Specifically, in S420 LF i Includes text-based locating field S1LF i And image class location field S2LF i S440 further includes: searching LF according to text matching i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i Ending the positioning; if the positioning coordinates are not found according to the text matching, executing the following steps:
s442, obtaining a plurality of different-layer circuit design drawings derived by the EDA tool, wherein the circuit design drawings of the different layers are original files for generating the local drawings.
And S444, performing template matching in the circuit design diagram according to the partial diagram to obtain a matched target circuit design diagram and a target position.
S446, the layer identification of the target circuit design drawing is acquired, and the layer identification and the target position are used as new positioning fields.
S448, searching the positioning coordinates of the new positioning field in the circuit design, and obtaining the target position TP of the ith item in the circuit design according to the positioning coordinates i 。
As a preferred embodiment, the defect flag field further includes a defect content description field, a defect type field, and a defect level identification. The defect type field and the defect level identification can be used as classification labels respectively, and a certain type or types of defects displayed in the visual window or a certain type or multiple defect levels or a combination of the defect type and the defect level can be visually displayed in the EDA tool.
As a preferred embodiment, the defect graphic mark is further bound with a color identifier, and the color identifier and the defect level identifier have a one-to-one mapping relationship. The defect grade of the object marked by the corresponding defect graphic mark can be quickly checked through the color mark. For example, the highest defect level is marked as red, the next highest defect level is marked as orange, and so on, and the defect graphic marks of different defect levels are distinguished by colors, so that a user can quickly observe the defect level of a corresponding object, and the defect level is convenient to view.
As an example, referring to fig. 2, which shows a schematic diagram of a defect pattern mark of a circuit design in an EDA tool, the object and the defect pattern mark in fig. 1, wherein the object comprises a first pin 110, a second pin 130, and a connection line 120, wherein the defect pattern mark comprises a first defect pattern mark 210 bound to the connection line 120, and a second defect pattern mark 220 bound to the second pin 130.
The invention provides a defect mark generation method of a circuit design, which is characterized in that a table file is imported into an EDA tool, a defect positioning field in each entry in the table file is extracted through the EDA tool, the circuit design is subjected to defect positioning according to the defect positioning field, and a defect graphic mark is generated. The invention solves the problems that in the prior art, the efficiency of checking the table files one by one and manually searching the circuit design to check the table files one by one and correspondingly modify or feed back is low, and the searching efficiency is improved.
Embodiments of the present invention also provide a non-transitory computer readable storage medium that may be disposed in an electronic device to store at least one instruction or at least one program for implementing one of the methods embodiments, the at least one instruction or the at least one program being loaded and executed by the processor to implement the methods provided by the embodiments described above.
Embodiments of the present invention also provide an electronic device comprising a processor and the aforementioned non-transitory computer-readable storage medium.
Embodiments of the present invention also provide a computer program product comprising program code for causing an electronic device to carry out the steps of the method according to the various exemplary embodiments of the invention as described in the specification, when said program product is run on the electronic device.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. Those skilled in the art will also appreciate that many modifications may be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. A method for generating a defect mark for a circuit design, the method comprising the steps of:
s200, acquiring a table file, wherein the table file comprises a plurality of entries, and each entry comprises a defect positioning field and a defect marking field of a circuit design; the defect positioning field is used for indicating an object with defects in the circuit design diagram; the defect mark field is used for describing defect content, defect type and defect grade information;
s400, importing the table file into an EDA tool, and performing defect positioning on the circuit design according to each entry in the table file to generate a defect graphic mark; wherein the generating step of the defect graphic mark of the i-th item includes:
s420, extracting the defect location field LF of the ith item i ；
S440, find LF i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i ；
S460, at TP i Generating a defect pattern flag, and associating the defect pattern flag with the defect flag field CF of the i-th entry i Binding is performed.
2. The method of claim 1, wherein LF in S420 i Locating field S1LF for text-like defects i S440 further includes: searching LF according to text matching i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i 。
3. The method of claim 1, wherein LF in S420 i Locating field S2LF for image type defects i The S2LF i A partial diagram for an additional circuit design diagram;
s440 further includes:
s442, obtaining a plurality of circuit design drawings of different layers derived by an EDA tool, wherein the circuit design drawings of the different layers are original files for generating a local drawing at the same time;
s444, performing template matching in the circuit design diagram according to the local diagram to obtain a matched target circuit design diagram and a target position;
s446, acquiring a layer identifier of the target circuit design drawing, and taking the layer identifier and the target position as new positioning fields;
s448, searching the positioning coordinates of the new positioning field in the circuit design, and obtaining the target position TP of the ith item in the circuit design according to the positioning coordinates i 。
4. The method of claim 1, wherein LF in S420 i Includes text-based locating field S1LF i And image class location field S2LF i ；
S440 further comprises: searching LF according to text matching i Positioning coordinates in the circuit design, and acquiring the target position TP of the ith item in the circuit design according to the positioning coordinates i Ending the positioning; if the positioning coordinates are not found according to the text matching, executing the following steps:
s442, obtaining a plurality of circuit design drawings of different layers derived by an EDA tool, wherein the circuit design drawings of the different layers are original files for generating a local drawing at the same time;
s444, performing template matching in the circuit design diagram according to the local diagram to obtain a matched target circuit design diagram and a target position;
s446, acquiring a layer identifier of the target circuit design drawing, and taking the layer identifier and the target position as new positioning fields;
s448, searching the positioning coordinates of the new positioning field in the circuit design, and obtaining the target position TP of the ith item in the circuit design according to the positioning coordinates i 。
5. The method according to claim 2 or 4, characterized in that the text class localization field S1LF i Including an object name field and an object type field.
6. The method of claim 1, wherein the defect graphical indicia binds a layer identification of the circuit design.
7. The method of claim 1, wherein the defect flag field further comprises a defect content description field, a defect type field, and a defect level identification.
8. The method of claim 7, wherein the defect graphical indicia is further bound with a color identification having a one-to-one mapping with a defect level identification.
9. A non-transitory computer readable storage medium having stored therein at least one instruction or at least one program, wherein the at least one instruction or the at least one program is loaded and executed by a processor to implement the method of any one of claims 1-8.
10. An electronic device comprising a processor and the non-transitory computer readable storage medium of claim 9.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102930114A (en) * | 2012-11-14 | 2013-02-13 | 常州奥施特信息科技有限公司 | Visualization detection method of electronic product electronic design automation (EAD) design manufacturability |
| CN109783505A (en) * | 2019-01-25 | 2019-05-21 | 上海创景信息科技有限公司 | The method and system and medium evaluated offline are realized using visual control |
| CN110543422A (en) * | 2019-09-05 | 2019-12-06 | 中国人民解放军国防科技大学 | software package code defect data processing method, system and medium for FPR |
| US10719650B1 (en) * | 2017-12-18 | 2020-07-21 | Synopsys, Inc. | Hierarchical dynamic heat maps in full custom EDA applications |
| CN112598397A (en) * | 2020-12-30 | 2021-04-02 | 北京迪浩永辉技术有限公司 | Circuit design online evaluation method, system, medium, equipment, terminal and application |
| CN116451510A (en) * | 2023-06-16 | 2023-07-18 | 中电投工程研究检测评定中心有限公司 | Visual building quality detection method, electronic equipment and storage medium |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101227485B1 (en) * | 2005-11-25 | 2013-01-29 | 엘지전자 주식회사 | Recording mdium, Method and Apparatus for recording defect management information on the recording medium |
| US9268889B2 (en) * | 2013-12-05 | 2016-02-23 | International Business Machines Corporation | Verification of asynchronous clock domain crossings |
| US10267853B2 (en) * | 2015-12-18 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company Ltd. | System and method to diagnose integrated circuit |
-
2024
- 2024-01-24 CN CN202410097658.2A patent/CN117634426B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102930114A (en) * | 2012-11-14 | 2013-02-13 | 常州奥施特信息科技有限公司 | Visualization detection method of electronic product electronic design automation (EAD) design manufacturability |
| US10719650B1 (en) * | 2017-12-18 | 2020-07-21 | Synopsys, Inc. | Hierarchical dynamic heat maps in full custom EDA applications |
| CN109783505A (en) * | 2019-01-25 | 2019-05-21 | 上海创景信息科技有限公司 | The method and system and medium evaluated offline are realized using visual control |
| CN110543422A (en) * | 2019-09-05 | 2019-12-06 | 中国人民解放军国防科技大学 | software package code defect data processing method, system and medium for FPR |
| CN112598397A (en) * | 2020-12-30 | 2021-04-02 | 北京迪浩永辉技术有限公司 | Circuit design online evaluation method, system, medium, equipment, terminal and application |
| CN116451510A (en) * | 2023-06-16 | 2023-07-18 | 中电投工程研究检测评定中心有限公司 | Visual building quality detection method, electronic equipment and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 基于信息检索的软件缺陷定位技术研究进展;张芸;刘佳琨;夏鑫;吴明晖;颜晖;;软件学报;20200815(第08期);2432-2452 * |
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