CN117632405A

CN117632405A - Scheduling instructions using latency of processor interconnect

Info

Publication number: CN117632405A
Application number: CN202311064293.5A
Authority: CN
Inventors: S·查特吉; N·维斯瓦纳坦; K·A·克鲁斯; S·戈埃尔; A·辛格
Original assignee: Nvidia Corp
Current assignee: Nvidia Corp
Priority date: 2022-08-24
Filing date: 2023-08-22
Publication date: 2024-03-01

Abstract

The present disclosure relates to scheduling instructions using latency of processor interconnects. Apparatus, systems, and techniques for scheduling instructions in a cluster to ensure GPU-CPU alignment of the instructions. In at least one embodiment, jobs are scheduled based on constraints on job size and job placement. In at least one embodiment, a processor includes circuitry to schedule instructions to be executed by the processors based on latency of interconnects coupled to the processors.

Description

Scheduling instructions using latency of processor interconnect

Request priority

The present application claims the benefit of indian provisional application No.202211048314 entitled "shared cluster scheduling (SHARED CLUSTER SCHEDULING)" filed at month 8 and 24 of 2022, the entire contents of which are incorporated herein by reference.

Technical Field

At least one embodiment relates to a processor or computing system for assigning one or more Graphics Processing Units (GPUs) to a workload in accordance with the various novel techniques described herein. For example, at least one embodiment relates to a processor or computing device that marks one or more nodes using a scheduler to provide scheduling of jobs to be executed by one or more processors on the one or more nodes.

Background

The prior art of allocating processing resources to workloads in a group of computing devices produces inefficient results. For example, if a scheduler schedules several workloads to be executed using different compute clusters, the performance of the clusters may vary, and variations in performance may affect the scheduling of these jobs and the predictability of the scheduling (e.g., when the compute clusters will complete executing the workloads). Thus, scheduling may be improved, including allocating resources for executing the workload.

Drawings

FIG. 1 illustrates a high-level view of a scheduling environment and flow in accordance with at least one embodiment;

FIG. 2 illustrates an example diagram of a GPU node topology in a non-uniform memory access (NUMA) domain in accordance with at least one embodiment;

FIG. 3 illustrates an example diagram of scheduling jobs based on job size in accordance with at least one embodiment;

FIG. 4 illustrates an example diagram of scheduling jobs based on an unchangeable job size in accordance with at least one embodiment;

FIG. 5 is a process according to at least one embodiment;

FIG. 6 illustrates an example including a processor and modules in accordance with at least one embodiment;

FIG. 7 is a block diagram illustrating a driver and/or runtime including one or more libraries that provide one or more Application Programming Interfaces (APIs), in accordance with at least one embodiment;

FIG. 8 illustrates a distributed system in accordance with at least one embodiment;

FIG. 9 illustrates an exemplary data center in accordance with at least one embodiment;

FIG. 10 illustrates a client-server network in accordance with at least one embodiment;

FIG. 11 illustrates an example of a computer network in accordance with at least one embodiment;

FIG. 12A illustrates a networked computer system in accordance with at least one embodiment;

FIG. 12B illustrates a networked computing system in accordance with at least one embodiment;

FIG. 12C illustrates a networked computing system in accordance with at least one embodiment;

FIG. 13 illustrates one or more components of a system environment in which a service may be provided as a third party network service in accordance with at least one embodiment;

FIG. 14 illustrates a cloud computing environment in accordance with at least one embodiment;

FIG. 15 illustrates a set of functional abstraction layers provided by a cloud computing environment in accordance with at least one embodiment;

FIG. 16 illustrates a supercomputer at chip level in accordance with at least one embodiment;

FIG. 17 illustrates a supercomputer at rack module level in accordance with at least one embodiment;

FIG. 18 illustrates a supercomputer at rack level in accordance with at least one embodiment;

FIG. 19 illustrates a supercomputer at an overall system level, in accordance with at least one embodiment;

FIG. 20A illustrates inference and/or training logic in accordance with at least one embodiment;

FIG. 20B illustrates inference and/or training logic in accordance with at least one embodiment;

FIG. 21 illustrates training and deployment of a neural network in accordance with at least one embodiment;

FIG. 22 illustrates an architecture of a network system in accordance with at least one embodiment;

FIG. 23 illustrates an architecture of a network system in accordance with at least one embodiment;

FIG. 24 illustrates a control plane protocol stack in accordance with at least one embodiment;

FIG. 25 illustrates a user plane protocol stack in accordance with at least one embodiment;

fig. 26 illustrates components of a core network in accordance with at least one embodiment;

FIG. 27 illustrates components of a system supporting Network Function Virtualization (NFV) in accordance with at least one embodiment;

FIG. 28 illustrates a processing system in accordance with at least one embodiment;

FIG. 29 illustrates a computer system in accordance with at least one embodiment;

FIG. 30 illustrates a system in accordance with at least one embodiment;

FIG. 31 illustrates an exemplary integrated circuit in accordance with at least one embodiment;

FIG. 32 illustrates a computing system in accordance with at least one embodiment;

FIG. 33 illustrates an APU in accordance with at least one embodiment;

FIG. 34 illustrates a CPU in accordance with at least one embodiment;

FIG. 35 illustrates an exemplary accelerator integrated slice in accordance with at least one embodiment;

36A-36B illustrate an exemplary graphics processor in accordance with at least one embodiment;

FIG. 37A illustrates a graphics core in accordance with at least one embodiment;

FIG. 37B illustrates a GPGPU in accordance with at least one embodiment;

FIG. 38A illustrates a parallel processor in accordance with at least one embodiment;

FIG. 38B illustrates a processing cluster in accordance with at least one embodiment;

FIG. 38C illustrates a graphics multiprocessor in accordance with at least one embodiment;

FIG. 39 illustrates a software stack of a programming platform in accordance with at least one embodiment;

FIG. 40 illustrates a CUDA implementation of the software stack of FIG. 39 in accordance with at least one embodiment;

FIG. 41 illustrates a ROCm implementation of the software stack of FIG. 39 in accordance with at least one embodiment;

FIG. 42 illustrates an OpenCL implementation of the software stack of FIG. 39 according to at least one embodiment;

FIG. 43 illustrates software supported by a programming platform in accordance with at least one embodiment; and

FIG. 44 illustrates compiled code for execution on the programming platform of FIGS. 39-42 in accordance with at least one embodiment.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. It will be apparent, however, to one skilled in the art, that the present inventive concept may be practiced without one or more of these specific details.

In at least one embodiment, a Central Processing Unit (CPU) core can be allocated from the same slot as a Graphics Processing Unit (GPU) to avoid slow transfer across NUMA memory consequences. In at least one embodiment, NUMA may refer to memory access non-uniformity between a processor and main memory. In at least one embodiment, NUMA can refer to the process of configuring a processor cluster to share memory locally. In at least one embodiment, the scheduling system can include a hierarchy of NUMA domains. For example, the scheduler may allocate two GPUs in the NUMA domain or four GPUs in the slot domain. In at least one embodiment, the bare engine GPU node may include a subset of available GPUs to be allocated based at least in part on the speed of communication between GPUs. In at least one embodiment, a processor includes circuitry to schedule instructions to be executed by the processors based on latency (latency) of interconnects coupled to the processors. In at least one embodiment, latency refers to the time required to communicate information between processors of each node or latency associated with processors communicating with the same or different slots. For example, latency varies from node to node because each processor in a node may use a different bus or different shared memory to share or store information, and these buses or memories require different amounts of time to transfer or store data, which can affect the communication time between processors.

In at least one embodiment, the job scheduler in the GPU cluster includes a processor to execute an algorithm to ensure that nodes do not have jobs of different GPU sizes at any time, which ensures optimal selection of GPUs and CPU cores. In at least one embodiment, the nodes may not need to have a static, specified job size. In at least one embodiment, when the nodes execute jobs, the jobs executed by the nodes are uniform in size.

In at least one embodiment, building higher level semantics in the job scheduler may ensure GPU-CPU alignment for jobs at least by imposing constraints on job size and job placement via a GPU Affinity (Affinity) aware fitness algorithm. In at least one embodiment, the at least partially semantic-based job scheduler may ensure that an optimal set of GPUs are assigned to workloads in the shared cluster. In at least one embodiment, by adding job size constraints and slot constraints on the nodes, it is ensured that the user gets the best GPU selection. In at least one embodiment, the CPUs and GPUs assigned to a job by the scheduler are from the same NUMA slot.

The techniques presented herein are improvements over existing solutions at least because maintaining latency information for interconnects coupled to processors in a compute node may be useful to a job scheduler to avoid the substantial cost of communicating across memory domain boundaries. In at least one embodiment, the presented techniques prevent fragmentation of cluster-level computing resources based on selection of nodes, as described herein. In at least one embodiment, the presented techniques co-locate computing resources within a NUMA domain improve communication between computing resources. In at least one embodiment, the presented technique selects resources allocated for jobs within the NUMA domain, which makes the performance of all jobs scheduled by the scheduler predictable. Prior solutions arbitrarily allocate resources to a workload or mark resources for a particular task. In at least one embodiment, the presented technique has a GPU affinity aware schedule that considers co-location of processors according to a memory access domain, which would perform better in scheduling (e.g., machine learning/artificial intelligence workload). Thus, in accordance with the embodiments disclosed above, techniques for a job scheduler to ensure GPU-CPU alignment of jobs include enforcing constraints on job size and job placement through a GPU affinity aware adaptation algorithm. For further description of the present technology, examples are now provided with reference to the accompanying drawings.

In at least one embodiment, the processor executes an algorithm that dynamically marks the nodes so that the scheduler can use the labels to schedule jobs onto nodes that are optimized to execute the jobs. In at least one embodiment, to determine how to mark the nodes, an algorithm gathers data from each node, where the data includes the number of processors (e.g., GPUs) available to execute the job, the number of processors in the node that executed the most recent job, and the latency of executing the job at the node using the processors (e.g., the number of milliseconds needed to share information between processors in the node). In at least one embodiment, the algorithm then generates a table comprising the following information: the number of resources in a node (e.g., the number of GPUs, the number of CPUs), the current job size (i.e., the number of processors executing the job), and the latency for using the node. Using this table, the algorithm marks each node such that the tag reflects the job size of the node, i.e., the number of processors executing the job.

In at least one embodiment, the processor executing the algorithm marks the nodes, which allows the scheduler to schedule jobs using the tag to select the node that matches the job size and has the lowest available latency. For example, if a job requires two GPUs, the scheduler will schedule it onto the first node, which is marked as running two GPU jobs, with 2 GPUs available and with the lowest latency. This also allows for more efficient classification of jobs into nodes having the required amount of resources. In at least one embodiment, a system administrator may set the job size of a node.

In at least one embodiment, the tags are static or dynamic. In at least one embodiment, a static tag refers to an administrator setting the tag to a particular job size, such as 4 GPUs, and it cannot be changed. For example, the marked node will accept only 4 GPU-sized jobs. In at least one embodiment, dynamic labels refer to job size labels that: the job size tag may be changed if all processors have completed executing the job for the node. For example, if an 8GPU node is marked as a 2GPU job size node, and it recently completed 4 separate 2GPU size jobs, the scheduler may reset its tag when all jobs are completed, i.e., all processors are available. In at least one embodiment, the scheduler may dynamically mark nodes as nodes of different job sizes, e.g., 4GPU job sizes or 8GPU job sizes. Such dynamic marking makes the scheduling process more flexible. In at least one embodiment, a processor includes one or more circuits to schedule one or more jobs to be performed by one or more nodes based at least in part on one or more tags of the one or more nodes, wherein the one or more tags are based at least in part on latency of the one or more nodes.

FIG. 1 illustrates an example block diagram 100 of a scheduling system in accordance with at least one embodiment. In at least one embodiment, a scheduling system, as shown in FIG. 1, is executed using one or more systems, processors, or communication devices to schedule one or more instructions to be executed by one or more processors based at least in part on latency of one or more interconnects coupled to the one or more processors. In at least one embodiment, the one or more processors may include one or more circuits to select the two or more processors to execute the one or more software workflows, wherein the selecting is based at least in part on one or more communication latencies between the two or more processors. In at least one embodiment, a scheduling system may schedule instructions (or otherwise referred to as jobs, workloads, software programs, or portions thereof) to computer systems (otherwise referred to as nodes or compute nodes) based at least in part on affinity groupings of the processors of the computer systems.

In at least one embodiment, as shown in FIG. 1, a scheduling system may include a scheduler 102, a job group manager 104, a cluster 106, a workload 108, a processor 110, and a communication bus 112.

In at least one embodiment, scheduler 102, which may also be referred to as a job scheduler, workload scheduler, or task scheduler, is software executed by a processor to facilitate the distribution of workloads (e.g., artificial intelligence and machine learning workloads) across a large number of graphics processing units and utilize computing resources. In at least one embodiment, the scheduler is a code library that is executed by a processor (e.g., CPU). In at least one embodiment, the scheduler is a computer application executed by the processor to control job performance. In at least one embodiment, the jobs may include, but are not limited to, matrix multiplication, training of neural networks, network operations, graphics operations, and/or reasoning operations. In at least one embodiment, the scheduler 102 maintains two data structures: a queue for unscheduled jobs and a cache for scheduled jobs. In at least one embodiment, a processor (e.g., CPU) executes a scheduler 102, where the scheduler 102 includes a library of code, functions, or other operations to perform sequencing operations for scheduling queues and scheduling jobs to be executed by one or more processors. In at least one embodiment, the job scheduler includes a GPU affinity-related node tag that indicates the GPU size of the pod (container group) currently running on the node, and the GPU size of the pod that can be scheduled on the node.

In at least one embodiment, when the pod group/job manager 104 invokes a "pop group" function (e.g., removes or "pops" elements from the queue), the pod group at the head of the dispatch queue is returned. In at least one embodiment, cluster 106, otherwise referred to as a shared cluster, a node cluster, a GPU cluster, etc., may include one or more computers with processors (e.g., GPUs) on each node and/or server, which may be general purpose computers, dedicated server computers, server farms, server clusters, or any other suitable arrangement and/or combination. In at least one embodiment, the cluster of nodes may include multiple parallel slave nodes, such as nodes 306A-B, distributed in multiple slots. In at least one embodiment, the node cluster 106 may include multiple GPUs within respective slots.

In at least one embodiment, to support constraints, two labels are introduced for each node in a shared cluster (such as node cluster 106), as described in the following table:

in at least one embodiment, the workload 108 may include a pod of various jobs to be assigned to GPUs in a plurality of nodes within the node cluster 106. In at least one embodiment, the workload may include, but is not limited to, matrix multiplication, training of neural networks, network operations, graphical operations, and/or inference operations. In at least one embodiment, job scheduler 102 (e.g., NSV K8s scheduler) may schedule single GPU-sized pods on nodes (such as nodes 306A-B in FIG. 3) to cause affinity packets of the GPUs to execute a workload, such as workload 108. In at least one embodiment, GPU affinity may refer to the close proximity between processors. For example, GPU affinity may be considered when scheduler 102 selects processor 110 to execute a workload to achieve optimal performance.

In at least one embodiment, the processor 110 may include a central processing unit ("CPU"), a graphics processor unit ("GPU"), or other processor (including an accelerator, a Field Programmable Gate Array (FPGA), etc.). In at least one embodiment, bus 112 may be used to transfer communication signals, such as address, data, or control signals, between a processor and other components in a processing system. In at least one embodiment, bus 112 may be an interconnection coupling of one or more processors, such as processor 110.

In at least one embodiment, an example processor includes circuitry to schedule instructions to be executed by one or more processors based on latency of an interconnect coupled to the processors using the processors. In at least one embodiment, the components, methods, and/or systems described in connection with FIG. 1 are further non-exclusively shown in any of FIGS. 1-7.

FIG. 2 illustrates an example diagram 200 of a Graphics Processing Unit (GPU) topology on a non-uniform memory access (NUMA) node in accordance with at least one embodiment. In at least one embodiment, as shown in FIG. 2, a node cluster, such as node cluster 106, may include one or more nodes 206A-B, switches 214A-B, central Processing Units (CPUs) 224A-B, and Graphics Processing Units (GPUs) labeled 0, 1, 2, 3, 4, 5, 6, and 7. In at least one embodiment, nodes 206A-B are similar to node cluster 106 in FIG. 1. In at least one embodiment, switches 214A-B may be connectors between processors. In at least one embodiment, switches 214A-B may include mechanisms that allow a user to maximize Graphics Processing Unit (GPU) performance. In at least one embodiment, switches 214A-B may optimize battery life by switching between graphics processing units (such as GPUs 0-7).

In at least one embodiment, the node includes one or more GPUs. In at least one embodiment, one or more GPUs may be used to schedule jobs. Here, as shown in fig. 2, the GPUs are labeled 0, 1, 2, 3, 4, 5, 6, and 7. In at least one embodiment, GPUs 0, 1, 2, and 3 are located on one NUMA node 206A, while GPUs 4, 5, 6, and 7 are located on another NUMA node 206B. In at least one embodiment, when a 2-GPU job is submitted to a cluster (e.g., as shown in FIG. 3), the job scheduler may select any two groups of GPUs from the node. In at least one embodiment, when GPU 0 and GPU 1 are selected by the job scheduler, the GPUs may have the best network connectivity, and the performance of these GPUs will be better than if GPU 0 and GPU 4 were assigned to the job. In at least one embodiment, to ensure that the slots left (e.g., connections or ports inside the computer on the motherboard) are always optimal, a scheduler system (e.g., scheduler 102) allocates a fixed GPU size to the nodes.

In at least one embodiment, the GPU node cluster includes GPUs 0, 1, 2, 3 in a first slot 0 and GPUs 4, 5, 6, 7 in slot 1. For example, if nodes 206A-B are occupied by all GPUs running the job, then the job on GPU 0, 1, 4, 5 is complete. If the job scheduler attempts to schedule four GPU jobs on GPUs 0, 1, 4, and 5 (GPU 0 and GPU 1 on slot 0, GPU 4 and GPU 5 on slot 1), then the GPUs will communicate across the slot domain so that performance is suboptimal. In at least one embodiment, when the job scheduler selects GPUs that are all located on the same slot (e.g., 0, 1, 2, and 3, as shown in fig. 2), then the performance of the GPU will be optimal. In at least one embodiment, configuring the node based at least in part on the slot-based scheduling technique ensures that the optimal set of resources is selected at the node.

In at least one embodiment, an example processor includes circuitry to schedule instructions to be executed by one or more processors based on latency of an interconnect coupled to the processors using the processors. In at least one embodiment, the components, methods, and/or systems described in connection with FIG. 2 are further non-exclusively shown in any of FIGS. 1-7.

FIG. 3 illustrates an example diagram of selecting a GPU for a job in accordance with at least one embodiment. In at least one embodiment, as shown in FIG. 3, system 300 may include nodes 306A-B, which are similar to nodes 206A-B in FIG. 2 and nodes 406A-B in FIG. 4. In at least one embodiment, nodes 306A-B (e.g., a "working" node) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field Programmable Gate Arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read only memory), storage devices (e.g., solid state or disk drives), network input/output ("NW I/O") devices, network switches, virtual machines ("VMs"), power and cooling modules, and the like. In at least one embodiment, the nodes 306A-B may be servers having one or more of the computing resources described above.

In at least one embodiment, the job scheduler may assign job sizes to nodes, such as nodes 306A-B. In at least one embodiment, a job scheduler, such as scheduler 102 in FIG. 1, may schedule jobs to nodes based on the fitness score. In at least one embodiment, the fitness score may be designed to favor nodes labeled "static" rather than nodes labeled "dynamic" for a given job size. In at least one embodiment, a node may support job sizes based on the order of jobs in a queue.

For example, the scheduler 102 marks node 306A as dynamic and node 306B as static. In at least one embodiment, the dynamic label indicates the job size (e.g., 1, 2, 4, 8) that can be run on the node. In at least one embodiment, the static tag indicates the unalterable pod size (the number of GPUs required) that the job scheduler can schedule on the node. Here, as one example, scheduler 102 allocates resources GPU 0 and GPU 1 in slot 0 of node 306A to execute 2-GPU sized jobs, such as workload 108. In at least one embodiment, to maintain optimal efficiency, the scheduler 102 marks node 306A as dynamic to execute jobs of the same size (e.g., 2-GPU-sized jobs). As one example, if the scheduler allocates resources to a subsequent workload that includes a 4-GPU sized job, the scheduler may allocate the subsequent workload to another node, such as node 306B. In at least one embodiment, the dynamic node can only accept jobs of the same size until it becomes empty again—all jobs are completed. In at least one embodiment, dynamic tagging enables efficient use of GPU clusters, such as node cluster 106, at least because the cost of using GPU clusters is predictable and the scheduling system can guarantee a certain level of performance.

FIG. 4 illustrates an example diagram of node selection based on a fixed-size job in accordance with at least one embodiment. In at least one embodiment, as shown in FIG. 4, system 400 may include nodes 406A-B, which are similar to nodes 206A-B in FIG. 2 and nodes 306A-B in FIG. 3. In at least one embodiment, the constraints include fixed-size job instances. Jobs submitted to the system may request a number of GPUs of 1, 2, 4, or 8. For example, a job with three or five GPUs may result in fragmentation. In at least one embodiment, the number of allocated CPU cores is fixed and proportional to the number of GPUs requested. In at least one embodiment, after considering CPU usage of the system applications, the number of CPU cores per GPU is calculated based at least in part on the available cores in the same slot. In at least one embodiment, to ensure that a job does not fall on a node that has already run a different size job, a constraint may be added to the job scheduler to return a value of 0 for hosts that have already run or are targeted to run different size jobs.

As another example, as shown in fig. 4, if the scheduler marks node 406B as static to execute a job requiring 4 GPUs (e.g., a 4-GPU sized job), the scheduler may optimally allocate resources GPU 0-3 in slot 0 of node 406B to execute the subsequent workload that includes the 4-GPU sized job. In at least one embodiment, the scheduler 102 may assign a percentage of the nodes in the cluster to either static nodes or dynamic nodes. In at least one embodiment, a system administrator may assign the percentage of nodes that are configurable by the system administrator or user.

In at least one embodiment, a job scheduler (e.g., scheduler 102 in FIG. 1) can include a filter plug-in that can filter out nodes such as nodes 306A-B that have node labels related to GPU affinity that does not match the GPU size of the pod workload (such as workload 108 in FIG. 1). In at least one embodiment, GPU affinity may refer to the close proximity between processors.

In at least one embodiment, the score plug-in is modified to calculate a plurality of "slebs" based solely on GPU affinity-related constraints. In at least one embodiment, a board may be a set of one or more contiguous pages of memory set aside for a single cache by a board allocator. In at least one embodiment, the job scheduler includes a GPU affinity score plug-in to take into account nodes having GPU affinity tags set to "true" and nodes having a particular value of "static" over nodes without these values. In at least one embodiment, the GPU affinity tag indicates whether the node is capable of supporting GPU affinity. If the tag of a node is not set to true, then no GPU affinity related filters and score plug-ins will be executed for that node. In at least one embodiment, the pod scheduled on such a node does not guarantee GPU affinity. In at least one embodiment, the "static" tag is set by the cluster administrator and read only by the scheduler. In at least one embodiment, the tag is used to reserve nodes for pod of a particular GPU size.

In at least one embodiment, a job scheduler, such as scheduler 102, includes a global flag (e.g., GPU Affinity Enabled) in the scheduler configuration to enable or disable GPU affinity based on scheduling in scheduler 102.

In at least one embodiment, the GPU affinity based scheduling supports a mix of static and dynamic labels that assign label values to nodes. In at least one embodiment, a subset of nodes will have "pod_gpu_size.static" set to a fixed value by an administrator based at least in part on past job assignments. These nodes are called static nodes. In at least one embodiment, a first implementation of GPU affinity based scheduling may have the following distribution:

a) 5% of nodes reserved for 2-GPU jobs

b) 5% of nodes reserved for 4-GPU jobs

c) 10% of the nodes reserved for 8-GPU jobs (at least because 8-GPU jobs are more common and more likely to be in urgent need (standby)

d) Nodes are not reserved for 1-GPU jobs (at least because 1-GPU jobs can be accommodated by dynamic nodes and are unlikely to be urgently needed).

In at least one embodiment, the remaining nodes may have node tags set to "dynamic", where the job scheduler determines the job sizes supported by the remaining nodes based at least in part on the order of the jobs in the queue. In at least one embodiment, if no partially allocated node can accommodate a job ahead of the dispatch queue, the job may be allocated to an idle proxy node. In at least one embodiment, the node will have a "dynamic" tag (as shown in FIG. 3) set to the size of the job that has been scheduled.

In at least one embodiment, static nodes are superior to dynamic nodes in terms of fitness scores. In at least one embodiment, static nodes may be preferred over dynamic nodes by adding configurable weights to all static nodes. In at least one embodiment, jobs can only be preempted from nodes supporting the same job size. In at least one embodiment, nodes that are set to "dynamic" may not change due to preemption.

In at least one embodiment, the administrator can change the value of pod_gpu_size.static on the node to static (if needed) or restore them from static to dynamic at any time without requiring node exhaustion. In at least one embodiment, the change in the tag value will be notified to the job scheduler by a system node observer event. In at least one embodiment, the job scheduler will recheck the known value of the pod_gpu_size.static tag before scheduling the job. In at least one embodiment, if the value has changed since the adaptation calculation, the scheduling assignment may be ignored and the job re-queued for scheduling. In at least one embodiment, if the tag value changes after scheduling, or if a job of a different size is running on the node, no new jobs are scheduled on the node until all running jobs reach a termination state. In at least one embodiment, when there are no more jobs on the node that are running, jobs matching the size of the updated pod_gpu_size.static value will be scheduled.

In at least one embodiment, the value of pod_gpu_size.static is assigned to the node to be processed by a script external to the job scheduler. In at least one embodiment, scheduler 102 may include an alert when a job is urgent due to a node being unavailable for a particular job size, and may include changes to monitoring and reporting specifications.

Embodiments may include various methods for assigning tag values to nodes. In at least one embodiment, various methods for assigning tag values may affect preemption decisions, as well as fitness score computation for GPU affinity scheduling. In at least one embodiment, all nodes may have a fixed, specified job size. In at least one embodiment, the scheduler includes a processor to process past behavior of submitted jobs and determine a percentage of submitted jobs for each job size. The cluster administrator supports each job size by setting pod_gpu_size.static to specify an equal percentage of nodes.

In at least one embodiment, if the job size supported by a node is fixed, the preemption logic is updated to preempt jobs only from nodes supporting its size. In at least one embodiment, a 4-GPU job will only preempt another 4-GPU job from a node that supports 4-GPU size jobs. When no more jobs of a particular size can be preempted, the next set of GPU-sized jobs will be checked.

In at least one embodiment, the size of jobs supported on a node may be changed. In at least one embodiment, pod_gpu_size.static is set to "dynamic" for all nodes, and the job scheduler assigns jobs to nodes based at least in part on the fitness score. In at least one embodiment, the node supports job sizes based at least in part on the order of the jobs in the queue. In at least one embodiment, the value of pod_gpu_size.dynamic may change when all jobs on a node terminate (in which case pod_gpu_size.dynamic is cleared), or when jobs are scheduled on an empty node (in which case pod_gpu_size.dynamic is set to the size of the scheduled jobs), or during preemption when all jobs on a node are preempted to make room for urgent jobs of different sizes (in which case pod_gpu_size.dynamic will be set to the size of the urgent job that triggered preemption).

In at least one embodiment, if the job size supported by a node can be modified by a job scheduler, such as scheduler 102, may need to examine preemptible jobs of different sizes in addition to preempting jobs of the same size for urgent-needed jobs. In at least one embodiment, if all jobs running on a node (e.g., nodes 406A-B) are preemptible, jobs of different sizes will be preempted. In at least one embodiment, the pod_gpu_size.dynamic tag is set to the size of the urgent job that triggered the preemption. This is done to schedule other sized jobs without regard to the node in the next scheduling cycle.

In at least one embodiment, the scheduling system assigns a mix of static and dynamic tags. In at least one embodiment, the subset of nodes has a fixed, specified job size of pod_gpu_size.static, which is set by the cluster administrator based at least in part on a minimum number of estimates of each size needed to prevent an urgent need. In at least one embodiment, a 1-GPU based job is unlikely to be urgently needed, and no node may need to be set to static = 1. In at least one embodiment, the remaining nodes (except for the subset of nodes) will have a dynamic job size, where pod_gpu_size.static is set to "dynamic", and the job scheduler sets pod_gpu_size.dynamic for each node. In at least one embodiment, this is done to preserve nodes for job size and to take into account the size of jobs in the queue. In at least one embodiment, the cluster administrator may change the value of pod_gpu_size.static on the dynamic nodes from "dynamic" to a fixed job size to make them static (and vice versa, restore the static nodes to dynamic).

In at least one embodiment, the job scheduler may only be able to preempt jobs from nodes that support their size. In at least one embodiment, the scheduler performs node marking automation. In at least one embodiment, the percentage of nodes in the cluster having each tag value is set in a configurable data structure and the occupancy of the nodes having each tag value is checked periodically. In at least one embodiment, the tag is capable of reserving nodes for fixed size jobs. In at least one embodiment, the tag permits modular design and implementation to handle the urgent processing of large jobs. In at least one embodiment, to avoid the urgent need for a job of a certain size, the occupancy of nodes with each tag value is monitored periodically. In at least one embodiment, when the occupancy of a node exceeds a threshold or falls below a minimum threshold, the percentage of nodes is recalculated and labels are reassigned among the nodes. In at least one embodiment, the nodes are re-marked with updated values to keep the percentage of label distribution within the configured limits.

For example, in a shared node cluster, 5% of the nodes are assigned static labels of size 2GPU, the other 5% of the nodes are assigned static labels of size 4GPU, 10% of the nodes are assigned static labels of size 8GPU, and the remaining 80% of the nodes will be dynamic, with a threshold of plus or minus 2%. The scheduler system periodically checks the occupancy of the 2 GPU-tagged nodes and similarly checks the occupancy of the other 4 and 8 GPU-tagged nodes, when the occupancy exceeds 5%, the system reassigns the tag (e.g., increases it from 5% to 7%), and if the occupancy will be below a minimum threshold, the system may decrease the percentage of tagged nodes.

In at least one embodiment, the combination of node labels is described in the following table:

in at least one embodiment, at startup, the job scheduler will read the value of the "pod_gpu_size.static" tag for each node reported by the node observer. In at least one embodiment, if the value of the "pod_gpu_size.dynamic" tag is set, the scheduler will also read it. In at least one embodiment, the job scheduler uses the values of "pod_gpu_size.static" and "pod_gpu_size.dynamic" during the fitness calculation and preemption procedures.

In at least one embodiment, the node proxy assigns the GPU to the job based on the optimal connectivity. As another example, consider that the NUMA node structure with GPUs 0,1,2,3, 4,5,6, and 7 as shown in fig. 2 is completely free, with the job constants requiring two GPUs. The node proxy will assign the job to GPU 0 and GPU 1 with the best connectivity. When another 2-GPU job comes, it will go to 2 and 3, which is also optimal. The next job will get 4 and 5 and the next job will get 6 and 7. All 2-GPU jobs then have the best GPU assigned to them. In at least one embodiment, when a job running on a different slot (e.g., 0,1,4,5) is terminated and a 4-GPU job comes in, the node proxy in the best effort algorithm will determine if a set of best connected 4 GPUs (e.g., 0,1,2,3 or 4,5,6, 7) can be freely allocated. When a set of best-connected GPUs cannot be freely allocated, an embodiment of the job scheduler will let the node agents allocate only the available 0,1,4, 5. In at least one embodiment, the node marking method will ensure that if a 4-GPU job is running on one node, the node proxy will only schedule other 4-GPU jobs to the node. In at least one embodiment, when there is a 2-GPU job running, the node proxy will not consider scheduling a 4-GPU job. Thus, the node marking method can achieve optimal allocation of GPUs and ensure affinity scheduling of workloads in a shared cluster.

In at least one embodiment, the scheduler selects a node based on the GPU-sized job currently running on the node, in accordance with at least one embodiment. In at least one embodiment, the constraints include a mix of nodes that cannot run any GPU-sized jobs. In at least one embodiment, the node may not need to previously "specify" the job size. In at least one embodiment, the job size that a node runs when running a job is homogenous. This is done by updating the fitness score computation for each node in the job scheduler to ensure that jobs are not scheduled onto nodes that are running jobs of different GPU sizes. For example, if there is a cluster that is empty or that is not running many jobs, when a workload of a job requesting 2GPU comes in, the scheduler may select a node for the workload. Once a 2GPU job is running on the node, the scheduler will not schedule a 1GPU or 4GPU or 8GPU job in the node until the current 2GPU job is terminated. In at least one embodiment, when a job has been scheduled onto a node, the scheduler will schedule only jobs on that node that are requesting the same number of GPUs until all current jobs have terminated and the node becomes an idle node.

In at least one embodiment, to ensure that a job does not fall on a node that has already run a job of a different size, a constraint will be added to the job scheduler to return a '0' for hosts that have already run or target to run jobs of a different size. In at least one embodiment, an example processor includes circuitry to use one or more processors to schedule instructions to be executed by the processors based on latency of an interconnect coupled to the processors. In at least one embodiment, the components, methods, and/or systems described in connection with FIG. 4 will be further illustrated non-exclusively in any of FIGS. 1-7.

FIG. 5 is a flow diagram illustrating an example of a process 500 for scheduling instructions to be executed on one or more processors in accordance with at least one embodiment. In at least one embodiment, some or all of the process 400 of scheduling a system (or any other process described, or variations and/or combinations of those processes) as shown in fig. 5 may be performed using one or more systems, processors, or communication devices to schedule one or more instructions to be executed by one or more processors based at least in part on latency of one or more interconnects coupled to the one or more processors. In at least one embodiment, one or more of the operations performed as part of process 500 may be performed in various orders and combinations, including in parallel, other than those shown in fig. 4.

In at least one embodiment, a scheduler (such as scheduler 104 of fig. 1) may receive one or more instructions to be executed by one or more processors (such as processor 110 of fig. 1), such as instructions in workload 108, at 502.

In at least one embodiment, a scheduler, such as scheduler 102 in FIG. 1, may generate an fitness score for each of one or more nodes (such as nodes 306A-B in FIG. 3) including one or more processors, such as processor 110 in FIG. 1, at 504. In at least one embodiment, the scheduling system calculates fitness scores based on node health history (including but not limited to available resources, job success/failure, etc.), and uses the fitness scores in a scheduling algorithm to select candidate nodes. In at least one embodiment, the fitness score may cause the node to be marked with one or more constraints on placement of jobs of a job size and various numbers of processors (e.g., GPU-sized jobs).

In at least one embodiment, a scheduler, such as scheduler 102 in FIG. 1, may schedule one or more instructions to be executed on one or more processors (such as processor 110 in FIG. 1), such as instructions in workload 108, at 506. In at least one embodiment, the scheduler may cause a node, such as nodes 306A-B in FIG. 3, to execute one or more instructions (such as instructions in workload 108) at 508. In at least one embodiment, the scheduler 102 may include one or more processors, such as processor 110 in FIG. 1, to execute one or more instructions based on latency of an interconnect coupled to the one or more processors. In at least one embodiment, the components, methods, and/or systems described in connection with FIG. 5 are further illustrated non-exclusively in any of FIGS. 1-7.

In at least one embodiment, an exemplary processor includes circuitry to use one or more processors to schedule instructions to be executed by the processors based on latency of an interconnect coupled to the processors. In at least one embodiment, the components, methods, and/or systems described in connection with FIG. 6 are further non-exclusively shown in any of FIGS. 1-7.

FIG. 6 illustrates an example including a processor and modules in accordance with at least one embodiment. Fig. 6 illustrates an embodiment 600 including a processor 602 and modules in accordance with at least one embodiment. In at least one embodiment, the processor 602 performs one or more processes such as those described herein to order portions or programs (e.g., pod or job) in the dispatch queue based on credits associated with the portions or programs. In at least one embodiment, processor 602 performs the processes described in connection with FIGS. 1-3. In at least one embodiment, the processor 602 performs one or more processes, such as those described in connection with fig. 1-7. In at least one embodiment, the processor 602 includes one or more circuits to schedule one or more instructions to be executed by one or more processors based on latency of an interconnect coupled to the one or more processors.

In at least one embodiment, the processor 602 includes one or more processors such as those described in connection with fig. 1-7. In at least one embodiment, the processor 602 is any suitable processing unit and/or combination of processing units, such as one or more CPU, GPU, GPGPU, PPU and/or variants thereof. In at least one embodiment, the processor 602 includes or has access to a scheduling module 604, a node marking module 626, and a scheduling queue module 628. In at least one embodiment, the scheduling module 604, the node marking module 626, and the scheduling queue module 628 are distributed among a plurality of processors that communicate via buses, networks, by writing to a shared memory, and/or any suitable communication process such as those described herein.

In at least one embodiment, a module used in any implementation described herein refers to any combination of software logic, firmware logic, hardware logic, and/or circuitry configured to provide the functionality described herein unless specified otherwise or explicitly stated to the contrary from the context. In at least one embodiment, the software may be embodied as a software package, code, and/or instruction set or instructions, and "hardware" such as used by a processor, as used in any of the implementations described herein may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and/or firmware that stores instructions executed by the programmable circuitry, alone or in any combination. In at least one embodiment, the modules may be collectively or individually embodied as circuitry that forms part of a larger system, such as an Integrated Circuit (IC), a system on a chip (SoC), or the like. In at least one embodiment, the modules perform one or more processes related to any suitable processing unit and/or combination of processing units (such as one or more CPU, GPU, GPGPU, PPU and/or variants thereof).

In at least one embodiment, the processor 602 uses the scheduling module 604 to cause a software program (such as the software program 218 in FIG. 2) to execute on one or more resources, such as the nodes 206A-B. In at least one embodiment, the processor 602 executes the scheduling module 604 and processes such as those described herein by including at least instructions that cause execution of the one or more processes (e.g., by the processor 602) or are otherwise available to execute the one or more processes (e.g., by the processor 602). In at least one embodiment, the processor of scheduling module 604 is used to manage allocation of job tasks, such as selecting which resources (e.g., node cluster 106 in FIG. 1) to execute a software workload. In at least one embodiment, the processor using scheduling module 604 allocates resources for jobs in a process such as those described in connection with FIGS. 1 and 7. In at least one embodiment, the processor 602 uses the scheduling module 604 to cause the software program to execute using software program-based computing resources to schedule one or more instructions to be executed by one or more processors, such as in the embodiments described in connection with fig. 1-7.

In at least one embodiment, the processor 602 uses the node marking module 626 to generate one or more node labels of one or more computing resources (or otherwise referred to as nodes, compute nodes, etc.) to enforce constraints on job size and placement of jobs on one or more processors. In at least one embodiment, the processor 602 marks one or more nodes as static using the node marking module 626, indicating the unchangeable pod size (number of GPUs required) that the scheduler can schedule on the one or more nodes. In at least one embodiment, the processor 602 marks one or more nodes as dynamic using the dispatch queue module 628 indicating a particular job size that may be run on one or more nodes. In at least one embodiment, the processor 602 uses the node marking module 626 to configure a percentage of one or more nodes in the cluster that may be assigned each of these tag values. In at least one embodiment, the processor 602 marks one or more nodes through one or more processes (such as those described in connection with fig. 1-7) using the node marking module 626.

In at least one embodiment, the processor 602 uses the dispatch queue module 628 to perform queuing operations, including but not limited to maintaining a total number of newly added jobs (or otherwise referred to as pods, workloads, etc.) to be executed by one or more processors. In at least one embodiment, the processor 602 uses the dispatch queue module 628 to perform one or more processes such as those described herein by including at least instructions that cause execution of the one or more processes (e.g., by the processor 602) or are otherwise available to perform the one or more processes (e.g., by the processor 602). In at least one embodiment, the processor 602 uses the dispatch queue module 628 to order the jobs based at least in part on priority or as a first in first out system. In at least one embodiment, the processor 602 uses the dispatch queue module 628 to order jobs extracted from available resources and to implement dynamic marking of one or more nodes based at least in part on the job order. In at least one embodiment, the processor 602 uses the dispatch queue module 628 to order and arrange the jobs through one or more processes, such as those described in connection with FIGS. 1-7.

In at least one embodiment, the example processor 602 includes circuitry to use one or more processors to schedule one or more instructions to be executed by the one or more processors based on latency of an interconnect coupled to the one or more processors. In at least one embodiment, the components, methods, and/or systems described in connection with FIG. 6 are further non-exclusively shown in any of FIGS. 1-7.

FIG. 7 is a block diagram illustrating a driver and/or runtime including one or more libraries to provide one or more Application Programming Interfaces (APIs) in accordance with at least one embodiment. In at least one embodiment, software program 702 is a software module. In at least one embodiment, software program 702 includes one or more software modules. In at least one embodiment, one or more software modules are further described as non-exclusively in FIG. 6. In at least one embodiment, the one or more APIs 710 are a set of software instructions that, if executed, cause the one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, runtimes 704, drivers 704, and/or any other groupings of software and/or executable code described further herein. In at least one embodiment, one or more APIs 710 perform one or more computing operations in response to a call by software program 702. In at least one embodiment, software program 702 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computing operations and/or to call one or more other instruction sets to be performed, such as API 710 or API function 712. In at least one embodiment, the functionality provided by the one or more APIs 710 includes software functionality 712, such as functionality that is available to accelerate one or more portions of the software program 702 using one or more Parallel Processing Units (PPUs), such as a Graphics Processing Unit (GPU). In at least one embodiment, the software program is a compiler, further non-exclusively shown in fig. 3 and/or 5.

In at least one embodiment, API 710 is a hardware interface of one or more circuits for performing one or more computing operations. In at least one embodiment, one or more software APIs 710 described herein are implemented as one or more circuits for performing one or more of the techniques described below in connection with FIGS. 2-6. In at least one embodiment, one or more software programs 702 include instructions that, if executed, cause one or more hardware devices and/or circuits to perform one or more techniques described further below in connection with fig. 2-6.

In at least one embodiment, a software program 702, such as a user-implemented software program, utilizes one or more Application Programming Interfaces (APIs) 710 to perform various computing operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computing operation performed by a Parallel Processing Unit (PPU), such as a Graphics Processing Unit (GPU), as further described herein. In at least one embodiment, one or more APIs 710 provide a set of callable functions 712, referred to herein as APIs, API functions, and/or functions, that individually perform one or more computing operations, such as computing operations related to parallel computing. For example, in an embodiment, one or more APIs 710 provide a function 712 for causing a scheduler 716 to schedule instructions to be executed by processors based on latency of an interconnect coupled to the processors.

In at least one embodiment, one or more software programs 702 interact or otherwise communicate with one or more APIs 710 to perform one or more computing operations using one or more PPUs (such as a GPU). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more sets of computing operations that are accelerated by being executed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 710 to facilitate parallel computing using a remote or local interface.

In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 712 provided by one or more APIs 710. In at least one embodiment, the software programs 702 use a local interface when the software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to one or more APIs 710. In at least one embodiment, one or more software programs 702 are statically compiled with precompiled library 706 or uncompiled source code that includes instructions for executing one or more APIs 710. In at least one embodiment, one or more software programs 702 are dynamically compiled and linked to one or more precompiled libraries 706 comprising one or more APIs 710 using a linker.

In at least one embodiment, the software program 702 uses a remote interface when a software developer executes a software program that utilizes a library 706 that includes one or more APIs 710 or that otherwise communicates with a library 706 that includes one or more APIs 710 via a network or other remote communication medium. In at least one embodiment, one or more libraries 706 comprising one or more APIs 710 will be executed by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 706 comprising one or more APIs 710 will be executed by any other computing host that provides the one or more APIs 710 to the one or more software programs 702.

In at least one embodiment, a processor executing or using one or more software programs 702 invokes, uses, executes, or otherwise implements one or more APIs 710 to allocate and otherwise manage memory to be used by the software programs 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory to be used by one or more portions of the software programs 702 to accelerate using one or more PPUs (such as a GPU or any other accelerator or processor described further herein). These software programs 702 may be executed by one or more processors based at least in part on latency of an interconnect coupled to the one or more processors using functions 712 provided by one or more APIs 710 in an embodiment.

In at least one embodiment, API 710 is an API that facilitates parallel computing. In at least one embodiment, API 710 is any other API further described herein. In at least one embodiment, the APIs 710 are provided by the driver and/or the runtime 704. In at least one embodiment, API 710 is provided by a CUDA user mode driver. In at least one embodiment, API 710 is provided by a CUDA runtime. In at least one embodiment, the driver 704 is a data value and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 712 of the API 710 during the loading and execution of one or more portions of the software program 702. In at least one embodiment, the runtime 704 is a data value and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 712 of the API 710 during execution of the software program 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by drivers and/or runtime 704 to perform combined arithmetic operations by the one or more software programs 702 during execution by one or more PPUs, such as GPUs.

In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by the driver and/or runtime 704 to perform the combined arithmetic operations of one or more PPUs, such as a GPU. In at least one embodiment, one or more APIs 710 provide combined arithmetic operations through the driver and/or runtime 704 as described above. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by the driver and/or runtime 704 to allocate or otherwise reserve one or more blocks of memory 714 of one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 702 allocate or otherwise reserve memory blocks using one or more APIs 710 provided by the driver and/or runtime 704. In at least one embodiment, one or more APIs 710 are used to perform the combined arithmetic operations, as described below in connection with any of FIGS. 2-6.

To improve the usability of the software program 702 and/or optimize one or more portions of the software program 702 to be accelerated by one or more PPUs (such as GPUs), in one embodiment, one or more APIs 710 provide one or more API functions 712 to execute a scheduling system usable or used by one or more computing devices as described above and further below in connection with fig. 1-6. In at least one embodiment, the example block diagram 700 depicts a processor including one or more circuits for executing one or more software programs to combine two or more Application Programming Interfaces (APIs) into a single API. In at least one embodiment, the exemplary block diagram 700 depicts a system comprising one or more processors to execute one or more software programs to combine two or more Application Programming Interfaces (APIs) into a single API. In at least one embodiment, the processor uses an API to cause the scheduler to select a thread selection mechanism and/or otherwise perform the operations described herein. In at least one embodiment, exemplary block 700 illustrates an API that invokes a scheduler to cause allocation of resources.

In at least one embodiment, a processor uses an exemplary API to schedule one or more instructions to be executed by one or more processors based at least in part on latency of one or more interconnects coupled to the one or more processors. In at least one embodiment, the components, methods, and/or systems described in connection with FIG. 7 are further illustrated non-exclusively in any of FIGS. 1-6.

As will be appreciated by those of skill in the art in light of the present disclosure, certain embodiments may be capable of attaining certain advantages, including some or all of the following: the field of computing and job scheduler systems for distributing jobs in a cluster of nodes is improved. Thus, according to the embodiments disclosed above, a scheduling system may schedule instructions to be executed by processors based on the latency of the interconnect coupled to the processors.

Server and data center

The following figures illustrate exemplary web servers and data center-based systems that can be used to implement at least one embodiment.

Fig. 8 illustrates a distributed system 800 in accordance with at least one embodiment. In at least one embodiment, the distributed system 800 includes one or more client computing devices 802, 804, 808, and 808 configured to execute and operate client applications, such as a network (web) browser, proprietary client, and/or variants thereof, on one or more networks 810. In at least one embodiment, a server 812 may be communicatively coupled with remote client computing devices 802, 804, 806, and 808 via a network 810.

In at least one embodiment, server 812 may be adapted to run one or more services or software applications, such as services and applications that may manage session activity for single sign-on (SSO) access across multiple data centers. In at least one embodiment, server 812 may also provide other services, or software applications, which may include non-virtual and virtual environments. In at least one embodiment, these services may be provided to users of client computing devices 802, 804, 806, and/or 808 as web-based services or cloud services or under a software as a service (SaaS) model. In at least one embodiment, a user operating client computing devices 802, 804, 806, and/or 808 can, in turn, utilize one or more client applications to interact with server 812 to utilize services provided by these components.

In at least one embodiment, software components 818, 820, and 822 of system 800 are implemented on server 812. In at least one embodiment, one or more components of system 800 and/or services provided by such components may also be implemented by one or more of client computing devices 802, 804, 806, and/or 808. In at least one embodiment, a user operating a client computing device may then utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components may be implemented in hardware, firmware, software, or a combination thereof. It should be appreciated that a variety of different system configurations are possible, which may differ from distributed system 800. Thus, the embodiment shown in FIG. 8 is one example of a distributed system for implementing the embodiment system and is not intended to be limiting.

In at least one embodiment, client computing devices 802, 804, 806, and/or 808 can include different types of computing systems. In at least one embodiment, the client computing device may comprise a portable handheld device (e.g.,cellular phone, & lt & gt>Computing tablet, personal Digital Assistant (PDA)) or wearable device (e.g., google)Head mounted display) running software (e.g. Microsoft Windows +.>) And/or various mobile operating systems (such as iOS, windows Phone, android, blackBerry, palm OS, and/or variants thereof). In at least one embodiment, the device may support different applications, such as different internet-related applications, email, short Message Service (SMS) applications, and may use various other communication protocols. In at least one embodiment, the client computing device may also include a general purpose personal computer, e.g., including Microsoft Windows running various versionsApple/>And/or a personal computer and/or a laptop computer of a Linux operating system. In at least one embodiment, the client computing device may be running a variety of commercially available +.>Or a workstation computer resembling any of the UNIX operating systems, including but not limited to GNU/Linux operating systems such as Google Chrome OS. In at least one embodiment, the client computing devices may also include electronic devices capable of communicating over one or more networks 810, such as a thin client computer, an internet-enabled gaming system (e.g., with or without->Microsoft Xbox game console of the gesture input device), and/or a personal messaging device. Although the distributed system 800 in fig. 8 is shown with four client computing devices, any number of client computing devices may be supported. Other devices (such as devices with sensors, etc.) may interact with server 812.

In at least one embodiment, network 810 in distributed system 800 may be any type of network capable of supporting data communications using any of a variety of available protocols, including, but not limited to, TCP/IP (Transmission control protocol/Internet protocol), SNA (System network architecture), IPX (Internet packet exchange), appleTalk, and/or variants thereof. In at least one embodiment, network 810 may be a Local Area Network (LAN), an Ethernet-based network, token ring, wide area network, the Internet, a virtual network, a Virtual Private Network (VPN), an intranet, an extranet, a Public Switched Telephone Network (PSTN), an infrared network, a wireless network (e.g., in the Institute of Electrical and Electronics Engineers (IEEE) 802.11 protocol suite, a wireless network, And/or a network operating under any of the other wireless protocols), and/or any combination of these and/or other networks.

In at least one embodiment, the server 812 may be comprised of one or more general purpose computers, special purpose server computers (e.g., including a PC server),Servers, mid-range servers, mainframe computers, rack mounted servers, etc.), a server farm, a cluster of servers, or any other suitable arrangement and/or combination. At the right angleIn at least one embodiment, the server 812 may include one or more virtual machines running a virtual operating system or other computing architecture that involves virtualization. In at least one embodiment, one or more flexible pools of logical storage devices may be virtualized to maintain virtual storage devices for servers. In at least one embodiment, the virtual network may be controlled by server 812 using a software-defined network. In at least one embodiment, server 812 may be adapted to run one or more services or software applications.

In at least one embodiment, server 812 may run any operating system, as well as any commercially available server operating system. In at least one embodiment, server 812 may also run any of a variety of additional server applications and/or middle tier applications, including HTTP (HyperText transfer protocol) servers, FTP (File transfer protocol) servers, CGI (common gateway interface) servers, Servers, database servers, and/or variants thereof. In at least one embodiment, exemplary database servers include, but are not limited to, those commercially available from Oracle, microsoft, sybase, IBM (International Business machines) and/or variants thereof.

In at least one embodiment, server 812 may include one or more applications for analyzing and merging data feeds and/or event updates received from users of client computing devices 802, 804, 806, and 808. In at least one embodiment, the data feed and/or event update may include, but is not limited to, being received from one or more third party information sources and a continuous data streamFeed, & lt & gt>Updates or real-time updates, which may include real-time events related to sensor data applications, financial quoters, network performance measurement tools (e.g., network monitoring and business management applications), click stream analysis tools, car trafficBy monitoring and/or changes thereof. In at least one embodiment, server 812 can also include one or more applications for displaying data feeds and/or real-time events via one or more display devices of client computing devices 802, 804, 806, and 808.

In at least one embodiment, the distributed system 800 may also include one or more databases 814 and 816. In at least one embodiment, the database may provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 814 and 816 may reside in various locations. In at least one embodiment, one or more of databases 814 and 816 may reside on non-transitory storage media local to server 812 (and/or resident in server 812). In at least one embodiment, databases 814 and 816 may be remote from server 812 and in communication with server 812 via a network-based connection or a dedicated connection. In at least one embodiment, databases 814 and 816 may reside in a Storage Area Network (SAN). In at least one embodiment, any necessary files for performing the functions attributed to server 812 may be stored locally on server 812 and/or remotely as appropriate. In at least one embodiment, databases 814 and 816 can include relational databases, such as databases adapted to store, update, and retrieve data in response to SQL formatted commands.

Various aspects of the foregoing figures may incorporate one or more of the embodiments described with respect to fig. 1-7. For example, at least one embodiment of the foregoing figures may incorporate a processor, system, or communication device to schedule one or more instructions to be executed by one or more processors based at least in part on latency of one or more interconnects coupled to the one or more processors.

FIG. 9 illustrates an exemplary data center 900 in accordance with at least one embodiment. In at least one embodiment, data center 900 includes, but is not limited to, a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

In at least one embodiment, as shown in fig. 9, the data center infrastructure layer 910 can include a resource coordinator 912, grouped computing resources 914, and node computing resources ("node c.r.") 916 (1) -916 (N), where "N" represents any complete positive integer. In at least one embodiment, nodes c.r.916 (1) -916 (N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read only memory), storage devices (e.g., solid state drives or disk drives), network input/output ("NW I/O") devices, network switches, virtual machines ("VMs"), power modules, cooling modules, and the like. In at least one embodiment, one or more of the nodes c.r.916 (1) -916 (N) may be a server having one or more of the above-described computing resources.

In at least one embodiment, the grouped computing resources 914 may include individual groupings of nodes c.r. housed within one or more racks (not shown), or a number of racks (also not shown) housed within a data center at various geographic locations. Individual packets of node c.r. within the grouped computing resources 914 may include computing, network, memory, or storage resources of the packet that may be configured or allocated to support one or more workloads. In at least one embodiment, several nodes c.r. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

In at least one embodiment, the resource coordinator 912 can configure or otherwise control one or more nodes c.r.916 (1) -916 (N) and/or grouped computing resources 914. In at least one embodiment, the resource coordinator 912 can include a software design infrastructure ("SDI") management entity for the data center 900. In at least one embodiment, the resource coordinator 912 may include hardware, software, or some combination thereof.

In at least one embodiment, as shown in FIG. 9, the framework layer 920 includes, but is not limited to, a job scheduler 932, a configuration manager 934, a resource manager 936, and a distributed file system 938. In at least one embodiment, the framework layer 920 can include a framework of one or more applications 942 of the application layer 940 and/or software 952 of the software layer 930. In at least one embodiment, software 952 or application 942 may include Web-based services software or applications, respectively, such as those provided by Amazon Web Services, google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be, but is not limited to, a free and open source network application framework, such as Apache Spark (hereinafter "Spark") that may utilize the distributed file system 938 for extensive data processing (e.g., "big data"). In at least one embodiment, job scheduler 932 may include Spark drivers to facilitate scheduling of workloads supported by the various layers of data center 900. In at least one embodiment, the configuration manager 934 may be capable of configuring different layers, such as a software layer 930 and a framework layer 920 including Spark and a distributed file system 938 for supporting large-scale data processing. In at least one embodiment, the resource manager 936 is capable of managing cluster or group computing resources mapped to or allocated for supporting the distributed file system 938 and job scheduler 932. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 914 on the data center infrastructure layer 910. In at least one embodiment, the resource manager 936 can coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

In at least one embodiment, the software 952 included in the software layer 930 may include software used by at least a portion of the nodes C.R.916 (1) -916 (N), the distributed file system 938 of the packet computing resource 914 and/or the framework layer 920. One or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

In at least one embodiment, the one or more applications 942 included in the application layer 940 may include one or more types of applications used by at least a portion of the nodes c.r.916 (1) -916 (N), the grouped computing resources 914, and/or the distributed file system 938 of the framework layer 920. The one or more types of applications may include, but are not limited to, a CUDA application, a 5G network application, an artificial intelligence application, a data center application, and/or variants thereof.

In at least one embodiment, any of the configuration manager 934, resource manager 936, and resource coordinator 912 may implement any number and type of self-modifying actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modifying action may mitigate a data center operator of the data center 900 from making potentially bad configuration decisions and may avoid underutilized and/or poorly performing portions of the data center.

Fig. 10 illustrates a client-server network 1004 formed by a plurality of network server computers 1002 interconnected in accordance with at least one embodiment. In at least one embodiment, each network server computer 1002 stores data accessible to other network server computers 1002 and client computers 1006 and networks 1008 linked into wide area network 1004. In at least one embodiment, the configuration of the client-server network 1004 can change over time as the client computer 1006 and one or more networks 1008 connect and disconnect from the network 1004, and as one or more trunk server computers 1002 are added to the network 1004 or removed from the network 1004. In at least one embodiment, a client-server network includes client computers 1006 and network 1008 when such client computers 1006 and network 1008 are connected to network server computer 1002. In at least one embodiment, the term computer includes any device or machine capable of accepting data, applying a specified process to the data, and providing the results of the process.

In at least one embodiment, the client-server network 1004 stores information accessible to the network server computer 1002, the remote network 1008, and the client computer 1006. In at least one embodiment, the network server computer 1002 is formed of a mainframe computer, mini-computer, and/or microcomputer each having one or more processors. In at least one embodiment, the server computers 1002 are linked together by wired and/or wireless transmission media (such as conductive wires, fiber optic cables) and/or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, the client computer 1006 accesses the network server computer 1002 via a similar wired or wireless transmission medium. In at least one embodiment, the client computer 1006 can be linked into the client-server network 1004 using a modem and a standard telephone communications network. In at least one embodiment, alternative carrier systems (e.g., cable and satellite communication systems) may also be used to link into the client-server network 1004. In at least one embodiment, other proprietary or time-shared carrier systems may be used. In at least one embodiment, the network 1004 is a global information network, such as the Internet. In at least one embodiment, the network is a private intranet that uses a similar protocol to the Internet but with added security measures and limited access control. In at least one embodiment, the network 1004 is a private or semi-private network that uses proprietary communication protocols.

In at least one embodiment, the client computer 1006 is any end user computer, and may also be a mainframe, mini-computer, or mini-computer having one or more microprocessors. In at least one embodiment, a server computer 1002 may sometimes act as a client computer accessing another server computer 1002. In at least one embodiment, the remote network 1008 may be a local area network, a network added to a wide area network through a separate service provider (ISP) for the internet, or another set of computers interconnected by a wired or wireless transmission medium having a fixed or time-varying configuration. In at least one embodiment, the client computers 1006 may be linked into the network 1004 and access the network 1004, either independently or through a remote network 1008.

FIG. 11 illustrates an example 1100 of a computer network 1108 connecting one or more computing machines in accordance with at least one embodiment. In at least one embodiment, network 1108 may be any type of electrically connected set of computers, including, for example, the following networks: the internet, an intranet, a Local Area Network (LAN), a Wide Area Network (WAN), or an interconnected combination of these network types. In at least one embodiment, the connections within network 1108 may be a remote modem, ethernet (IEEE 802.3), token ring (IEEE 802.5), fiber distributed data link interface (FDDI), asynchronous Transfer Mode (ATM), or any other communication protocol. In at least one embodiment, the computing device linked to the network may be a desktop, server, portable, handheld, set-top box, personal Digital Assistant (PDA), terminal, or any other desired type or configuration. In at least one embodiment, network connected devices may vary widely in processing power, internal memory, and other performance depending on their functionality. In at least one embodiment, communications within the network and communications to or from computing devices connected to the network may be wired or wireless. In at least one embodiment, the network 1108 may comprise, at least in part, the worldwide public internet, which connects multiple users according to transmission control protocol/internet protocol (TCP/IP) specifications, typically according to a client-server model. In at least one embodiment, the client-server network is the dominant model for communication between two computers. In at least one embodiment, a client computer ("client") issues one or more commands to a server computer ("server"). In at least one embodiment, the server fulfills the client command by accessing available network resources and returning information to the client in accordance with the client command. In at least one embodiment, a client computer system and network resources residing on a network server are assigned network addresses for identification during communication between elements of a network. In at least one embodiment, the communication from the other network-connected system to the server will include the network address of the relevant server/network resource as part of the communication, such that the appropriate destination of the data/request is identified as the recipient. In at least one embodiment, when network 1108 comprises the global internet, the network address is an IP address in TCP/IP format that may at least partially route data to an email account, website, or other internet appliance residing on a server. In at least one embodiment, information and services residing on the web server may be available to the web browser of the client computer through a domain name (e.g., www.site.com) (which maps to the IP address of the web server).

In at least one embodiment, a plurality of clients 1102, 1104, and 1106 connect to network 1108 via respective communication links. In at least one embodiment, each of these clients may access network 1108 via any desired form of communication, such as via a dial-up modem connection, a cable link, a Digital Subscriber Line (DSL), a wireless or satellite link, or any other form of communication. In at least one embodiment, each client may communicate using any machine compatible with network 1108, such as a Personal Computer (PC), workstation, dedicated terminal, personal Data Assistant (PDA), or other similar device. In at least one embodiment, clients 1102, 1104, and 1106 may or may not be located in the same geographic region.

In at least one embodiment, a plurality of servers 1110, 1112, and 1114 are connected to network 1118 to serve clients in communication with network 1118. In at least one embodiment, each server is typically a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, the server includes a computer readable data storage medium such as a hard disk drive and RAM memory that stores program instructions and data. In at least one embodiment, servers 1110, 1112, 1114 run applications that respond to client commands. In at least one embodiment, server 1110 can run a web server application for responding to client requests for HTML pages, and can also run a mail server application for receiving and routing emails. In at least one embodiment, other applications may also run on server 1110, such as an FTP server or media server for streaming audio/video data to clients. In at least one embodiment, different servers may be dedicated to performing different tasks. In at least one embodiment, server 1110 can be a dedicated web server that manages website-related resources for different users, while server 1112 can be dedicated to providing electronic mail (email) management. In at least one embodiment, other servers may be dedicated to media (audio, video, etc.), file Transfer Protocol (FTP), or a combination of any two or more services that are generally available or provided over a network.

In at least one embodiment, each server may be in the same or different location as the other servers. In at least one embodiment, there may be multiple servers performing mirroring tasks for the user, thereby alleviating congestion or minimizing traffic to and from a single server. In at least one embodiment, the servers 1110, 1112, 1114 are under the control of a web hosting provider in a business that maintains and delivers third party content over the network 1118.

In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which may be referred to as a browser, requests content, such as web pages, email messages, video clips, etc., from servers 1110, 1112, 1114. In at least one embodiment, a second type (which may be referred to as a user) hires a web hosting provider to maintain network resources (such as websites) and make them available to the browser. In at least one embodiment, users contract with web hosting providers to make memory space, processor capacity, and communication bandwidth available to their desired network resources, depending on the amount of server resources that users desire to utilize.

In at least one embodiment, in order for a web hosting provider to serve both clients, the application that manages the network resources hosted by the server must be properly configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially control the application's response to browser requests and also at least partially define server resources available to a particular user.

In one embodiment, intranet server 1116 communicates with network 1108 via a communication link. In at least one embodiment, an intranet server 1116 communicates with a server manager 1118. In at least one embodiment, the server manager 1118 includes a database of application configuration parameters for use in the servers 1110, 1112, 1114. In at least one embodiment, the user modifies the database 1120 via the intranet 1116 and the server manager 1118 interacts with the servers 1110, 1112, 1114 to modify the application parameters so that they match the contents of the database. In at least one embodiment, a user logs into the intranet 1116 by connecting to the intranet 1116 via the computer 1102 and entering authentication information such as a user name and password.

In at least one embodiment, when a user wishes to log in to a new service or modify an existing service, the intranet server 1116 authenticates the user and provides the user with an interactive screen display/control panel that allows the user to access configuration parameters of a particular application. In at least one embodiment, a plurality of modifiable text boxes describing aspects of a configuration of a user's website or other network resource are presented to the user. In at least one embodiment, if a user desires to increase the memory space reserved on a server for his website, the user is provided with a field in which the user specifies the desired memory space. In at least one embodiment, in response to receiving this information, intranet server 1116 updates database 1120. In at least one embodiment, the server manager 1118 forwards this information to the appropriate server and uses the new parameters during application operation. In at least one embodiment, intranet server 1116 is configured to provide a user with access to configuration parameters of hosted network resources (e.g., web pages, emails, FTP sites, media sites, etc.) that the user has signed up with a web hosting service provider.

FIG. 12A illustrates a networked computer system 1200A in accordance with at least one embodiment. In at least one embodiment, the networked computer system 1200A includes a plurality of nodes or personal computers ("PCs") 1202, 1218, 1220. In at least one embodiment, the personal computer or node 1202 includes a processor 1214, memory 1216, a camera 1204, a microphone 1206, a mouse 1208, a speaker 1212, and a monitor 1212. In at least one embodiment, the PCs 1202, 1218, 1220 may each run one or more desktop servers, such as an internal network within a given company, or may be servers of a general purpose network that is not limited to a particular environment. In at least one embodiment, there is one server per PC node of the network, such that each PC node of the network represents a particular network server with a particular network URL address. In at least one embodiment, each server defaults to a default web page for the user of that server, which may itself include embedded URLs pointing to further sub-pages of the user on that server, or to pages on other servers or other servers on the network.

In at least one embodiment, the nodes 1202, 1218, 1220 and other nodes of the network are interconnected via medium 1222. In at least one embodiment, medium 1222 may be a communication channel such as an integrated services digital network ("ISDN"). In at least one embodiment, the various nodes of the networked computer system may be connected by a variety of communication media including a local area network ("LAN"), plain old telephone line ("POTS") (sometimes referred to as the public switched telephone network ("PSTN")), and/or variants thereof. In at least one embodiment, the various nodes of the network may also constitute computer system users interconnected via a network, such as the Internet. In at least one embodiment, each server on the network (running from a particular node of the network at a given instance) has a unique address or identity within the network, which may be specified in terms of a URL.

In at least one embodiment, a plurality of multipoint conference units ("MCUs") may thus be used to transmit data to and from various nodes or "endpoints" of the conference system. In at least one embodiment, the nodes and/or MCUs may be interconnected via ISDN links or by a local area network ("LAN") in addition to various other communication media, such as nodes connected by the internet. In at least one embodiment, the nodes of the conference system may be generally connected directly to a communication medium (such as a LAN) or through an MCU, and the conference system may include other nodes or elements, such as routers, servers, and/or variants thereof.

In at least one embodiment, the processor 1214 is a general purpose programmable processor. In at least one embodiment, the processor of the node of the networked computer system 1200A can also be a dedicated video processor. In at least one embodiment, the different peripherals and components of a node (such as those of node 1202) may be different from those of other nodes. In at least one embodiment, node 1218 and node 1220 can be configured the same as or different from node 1202. In at least one embodiment, the nodes may be implemented on any suitable computer system in addition to a PC system.

FIG. 12B illustrates a networked computer system 1200B in accordance with at least one embodiment. In at least one embodiment, system 1200B illustrates a network (such as LAN 1224) that may be used to interconnect various nodes that may communicate with each other. In at least one embodiment, attached to LAN 1224 is a plurality of nodes, such as PC nodes 1226, 1228, 1230. In at least one embodiment, the nodes may also be connected to a LAN via a web server or other device. In at least one embodiment, system 1200B includes other types of nodes or elements, including routers, servers, and nodes for at least one embodiment.

FIG. 12C illustrates a networked computer system 1200C in accordance with at least one embodiment. In at least one embodiment, system 1200C illustrates a WWW system having communications across a backbone communication network (such as internet 1232) that may be used to interconnect the various nodes of the network. In at least one embodiment, the WWW is a set of protocols that operate on top of the internet and allow a graphical interface system to operate thereon to access information through the internet. In at least one embodiment, attached to the internet 1232 in the WWW are a plurality of nodes, such as PCs 1240, 1242, 1244. In at least one embodiment, the nodes interface with other nodes of the WWW through WW HTTP servers (such as servers 1234, 1236). In at least one embodiment, the PC 1244 may be a PC that forms a node of the network 1232, and the PC 1244 itself runs its server 1236, although the PC 1244 and server 1236 are shown separately in fig. 12C for illustrative purposes.

In at least one embodiment, the WWW is a distributed type of application characterized by WWW HTTP, a protocol of the WWW that runs on top of the transmission control protocol/Internet protocol ("TCP/IP") of the Internet. In at least one embodiment, the WWW may thus be characterized by a set of protocols (i.e., HTTP) running on the internet as its "backbone".

In at least one embodiment, a web browser is an application running on a node of a network in a WWW-type compatible network system that allows a user of a particular server or node to view such information and thus allow the user to search for graphics and text-based files linked together using hypertext links embedded in documents or files available from a server on the HTTP-aware network. In at least one embodiment, when a user retrieves a given web page of a first server associated with a first node using another server on a network such as the Internet, the retrieved document may have a different hypertext link embedded therein and a local copy of the page is created locally to the retrieving user. In at least one embodiment, when the user clicks on a hypertext link, the locally stored information associated with the selected hypertext link is generally sufficient to allow the user's machine to open a connection through the Internet to a server indicated by the hypertext link.

In at least one embodiment, more than one user may be coupled to each HTTP server, for example, through a LAN (such as LAN 1238, as shown with respect to WWW HTTP server 1234). In at least one embodiment, system 1200C may also include other types of nodes or elements. In at least one embodiment, the WWW HTTP server is an application running on a machine such as a PC. In at least one embodiment, each user may be considered to have a unique "server," as shown with respect to PC 1244. In at least one embodiment, a server may be considered a server, such as WWW HTTP server 1234, that provides access to a network for a LAN or multiple nodes or multiple LANs. In at least one embodiment, there are multiple users, each with a desktop PC or node of the network, each desktop PC potentially building a server for its user. In at least one embodiment, each server is associated with a particular network address or URL that, when accessed, provides a default web page for the user. In at least one embodiment, the web page may include a further link (embedded URL) that points to a further sub-page of the user on the server, or to other servers on the network or to pages on other servers on the network.

Cloud computing and services

The following figures illustrate, but are not limited to, exemplary cloud-based systems that may be used to implement at least one embodiment.

In at least one embodiment, cloud computing is a style of computing in which dynamically extensible and often virtualized resources are provided as services over the internet. In at least one embodiment, users need not have knowledge of, expertise in, or control over their technical infrastructure, which may be referred to as "in the cloud. In at least one embodiment, cloud computing incorporates infrastructure as services, platforms as services, software as services, and other variants with common topics that rely on the internet to meet the computing needs of the user. In at least one embodiment, a Data Center (DC) in a typical cloud deployment, such as in a private cloud (e.g., an enterprise network) or a public cloud (e.g., the internet), may consist of thousands of servers (or alternatively, VMs), hundreds of ethernet, fibre channel, or fibre channel over ethernet (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, the cloud may also consist of a network services infrastructure, such as an IPsec VPN hub, firewall, load balancer, wide Area Network (WAN) optimizer, or the like. In at least one embodiment, remote subscribers may securely access cloud applications and services by connecting via a VPN tunnel (e.g., an IPsec VPN tunnel).

In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be quickly configured and released with minimal management effort or service provider interaction.

In at least one embodiment, cloud computing is characterized by on-demand self-service, where consumers can automatically unilaterally provision computing capabilities, such as server time and network storage, as needed without human interaction with each service provider. In at least one embodiment, cloud computing is characterized by extensive network access, where capabilities are available on the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by a resource pool in which the computing resources of a provider are pooled to serve multiple consumers using a multi-tenant model, in which different physical and virtual resources are dynamically signed and reallocated according to consumer demand. In at least one embodiment, there is a sense of location independence because consumers typically have no control or knowledge of the exact location of the provided resources, but may be able to specify locations at a higher level of abstraction (e.g., country, state, or data center). In at least one embodiment, examples of resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by fast resilience, where capabilities can be quickly and flexibly provisioned (in some cases automatically) to quickly shrink and quickly release to quickly zoom in. In at least one embodiment, the available supply capacity for the consumer generally appears unrestricted and may be purchased in any number at any time. In at least one embodiment, cloud computing is characterized by measured services, where the cloud system automatically controls and optimizes resource usage by utilizing metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource usage may be monitored, controlled, and reported to provide transparency to both the provider and consumer of the utilized service.

In at least one embodiment, cloud computing may be associated with various services. In at least one embodiment, cloud software as a service (SaaS) may refer to a service where the capability provided to the consumer is an application using a provider running on a cloud infrastructure. In at least one embodiment, an application may be accessed from different client devices through a thin client interface such as a web browser (e.g., web-based email). In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including network, server, operating system, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

In at least one embodiment, cloud platform as a service (PaaS) may refer to such a service: wherein the capability provided to the consumer is to deploy consumer created or acquired applications onto the cloud infrastructure, the applications being created using programming languages and tools supported by the provider. In at least one embodiment, the consumer does not manage or control an underlying cloud infrastructure including a network, server, operating system, or storage, but has control over deployed applications and possibly application hosting environment configurations.

In at least one embodiment, cloud infrastructure as a service (IaaS) may refer to such services: where the capability provided to the consumer is to provide processing, storage, networking, and other basic computing resources that the consumer can deploy and run any software that may include operating systems and applications. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure, but rather has control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

In at least one embodiment, cloud computing may be deployed in different ways. In at least one embodiment, a private cloud may refer to a cloud infrastructure that operates only for an organization. In at least one embodiment, the private cloud may be managed by an organization or a third party, and may exist either within the venue or outside the venue. In at least one embodiment, a community cloud may refer to a cloud infrastructure that is shared by several organizations and supports a particular community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). In at least one embodiment, the community cloud may be managed by an organization or a third party, and may exist either within the venue or outside the venue. In at least one embodiment, a public cloud may refer to a cloud infrastructure available to the general public or large industrial groups and owned by an organization providing cloud services. In at least one embodiment, a hybrid cloud may refer to a cloud infrastructure that is an integral part of two or more clouds (private, community, or public), which are still unique entities, but are bound together by standardized or proprietary techniques that enable data and application portability (e.g., cloud bursting for load balancing between clouds). In at least one embodiment, the cloud computing environment is service oriented, focusing on stateless, low-coupling, modularity, and semantic interoperability.

Fig. 13 illustrates one or more components of a system environment 1300 in which services can be provided as third party network services in accordance with at least one embodiment. In at least one embodiment, the third party network may be referred to as a cloud, a cloud network, a cloud computing network, and/or variants thereof. In at least one embodiment, the system environment 1300 includes one or more client computing devices 1304, 1306, and 1308, which client computing devices 1304, 1306, and 1308 can be used by users to interact with a third party network infrastructure system 1302 that provides third party network services (which can be referred to as cloud computing services). In at least one embodiment, the third party network infrastructure system 1302 can include one or more computers and/or servers.

It should be appreciated that the third party network infrastructure system 1302 depicted in fig. 13 may have other components in addition to those depicted. Further, fig. 13 depicts an embodiment of a third party network infrastructure system. In at least one embodiment, the third party network infrastructure system 1302 may have more or fewer components than depicted in fig. 13, may combine two or more components, or may have different component configurations or arrangements.

In at least one embodiment, the client computing devices 1304, 1306, and 1308 may be configured to operate a client application, such as a web browser, a proprietary client application or some other application that may be used by a user of the client computing device to interact with the third-party network infrastructure system 1302 to use services provided by the third-party network infrastructure system 1302. Although exemplary system environment 1300 is illustrated as having three client computing devices, any number of client computing devices may be supported. In at least one embodiment, other devices, such as devices with sensors, etc., may interact with the third party network infrastructure system 1302. In at least one embodiment, one or more networks 1310 may facilitate communication and data exchange between client computing devices 1304, 1306, and 1308 and third-party network infrastructure system 1302.

In at least one embodiment, the services provided by the third party network infrastructure system 1302 may include hosts of services available to users of the third party network infrastructure system on demand. In at least one embodiment, various services may also be provided including, but not limited to, online data storage and backup solutions, web-based email services, hosted office suites and document collaboration services, database management and processing, managed technical support services, and/or variations thereof. In at least one embodiment, the services provided by the third party network infrastructure system may be dynamically extended to meet the needs of its users.

In at least one embodiment, a particular instantiation of a service provided by the third party network infrastructure system 1302 may be referred to as a "service instance". In at least one embodiment, any service available to a user from a third party network service provider system via a communications network (such as the internet) is generally referred to as a "third party network service". In at least one embodiment, in a public third party network environment, the servers and systems that make up the third party network service provider system are different from the customer's own on-premise servers and systems. In at least one embodiment, a third party network service provider system may host applications, and users may order and use applications on demand via a communication network (such as the internet).

In at least one embodiment, services in a computer network third party network infrastructure may include protected computer network access to storage, hosted databases, hosted network servers, software applications, or other services provided to users by third party network providers. In at least one embodiment, the service may include password-protected access to remote storage on a third party network via the Internet. In at least one embodiment, the services can include a web service-based hosted relational database and a scripting language middleware engine for private use by networking developers. In at least one embodiment, the service may include access to an email software application hosted on a website of a third party network provider.

In at least one embodiment, the third party network infrastructure system 1302 may include a set of applications, middleware, and database service offerings that are delivered to customers in a self-service, subscription-based, elastically extensible, reliable, highly available, and secure manner. In at least one embodiment, the third party network infrastructure system 1302 may also provide "big data" related computing and analysis services. In at least one embodiment, the term "big data" is generally used to refer to a very large set of data that can be stored and manipulated by analysts and researchers to visualize, detect trends, and/or otherwise interact with the data. In at least one embodiment, big data and related applications may be hosted and/or manipulated by the infrastructure system at many levels and on different scales. In at least one embodiment, tens, hundreds, or thousands of processors linked in parallel may act on such data to present the data or simulate external forces on the data or the content represented thereby. In at least one embodiment, these data sets may relate to structured data (such as structured data organized in a database or otherwise according to a structured model) and/or unstructured data (e.g., emails, images, data blobs, web pages, complex event processing). In at least one embodiment, by utilizing the capabilities of the embodiments to relatively quickly focus more (or less) computing resources on a target, a third party network infrastructure system may be better available to perform tasks on a large data set based on demands from an enterprise, government agency, research organization, private individual, group of individuals or organizations with the same ideas, or other entity.

In at least one embodiment, the third party network infrastructure system 1302 may be adapted to automatically provide, manage and track customer subscriptions to services provided by the third party network infrastructure system 1302. In at least one embodiment, the third party network infrastructure system 1302 can provide third party network services via different deployment models. In at least one embodiment, services may be provided under a public third party network model, where the third party network infrastructure system 1302 is owned by an organization selling third party network services and makes the services available to the general public or to different business enterprises. In at least one embodiment, the services may be provided under a private third party network model in which the third party network infrastructure system 1302 operates only for a single organization and may provide services for one or more entities within the organization. In at least one embodiment, third party network services may also be provided under a community third party network model, where the third party network infrastructure system 1302 and the services provided by the third party network infrastructure system 1302 are shared by several organizations in the relevant community. In at least one embodiment, the third party network services may also be provided under a hybrid third party network model, which is a combination of two or more different models.

In at least one embodiment, the services provided by the third party network infrastructure system 1302 may include one or more services provided under a software as a service (SaaS) class, a platform as a service (PaaS) class, an infrastructure as a service (IaaS) class, or other service classes including hybrid services. In at least one embodiment, a customer via a subscription order may subscribe to one or more services provided by the third party network infrastructure system 1302. In at least one embodiment, the third party network infrastructure system 1302 then performs processing to provide services in the customer's subscription order.

In at least one embodiment, the services provided by the third party network infrastructure system 1302 may include, but are not limited to, application services, platform services, and infrastructure services. In at least one embodiment, the application services may be provided by a third party network infrastructure system via a SaaS platform. In at least one embodiment, the SaaS platform may be configured to provide third party web services belonging to the SaaS class. In at least one embodiment, the SaaS platform may provide the ability to build and deliver a set of on-demand applications on an integrated development and deployment platform. In at least one embodiment, the SaaS platform may manage and control the underlying software and infrastructure for providing the SaaS services. In at least one embodiment, the client may utilize an application executing on a third party network infrastructure system by utilizing services provided by the SaaS platform. In at least one embodiment, the client may obtain the application service without requiring the client to purchase a separate license and support. In at least one embodiment, a variety of different SaaS services may be provided. In at least one embodiment, examples include, but are not limited to, services that provide solutions for sales performance management, enterprise integration, and business flexibility for large organizations.

In at least one embodiment, the platform services may be provided by the third party network infrastructure system 1302 via a PaaS platform. In at least one embodiment, the PaaS platform can be configured to provide third party web services belonging to the PaaS class. In at least one embodiment, examples of platform services may include, but are not limited to, services that enable an organization to merge existing applications on a shared common architecture, and the ability to build new applications that utilize shared services provided by the platform. In at least one embodiment, the PaaS platform can manage and control the underlying software and infrastructure for providing PaaS services. In at least one embodiment, the customer may obtain PaaS services provided by the third party network infrastructure system 1302 without the customer purchasing separate licenses and support.

In at least one embodiment, by utilizing the services provided by the PaaS platform, the customer can employ programming languages and tools supported by the third party network infrastructure system and also control the deployed services. In at least one embodiment, the platform services provided by the third party network infrastructure system may include database third party network services, middleware third party network services, and third party network services. In at least one embodiment, the database third party network services may support a shared service deployment model that enables an organization to aggregate database resources and provide databases, i.e., services, to clients in the form of a database third party network. In at least one embodiment, in a third party network infrastructure system, middleware third party network services may provide a platform for customers to develop and deploy different business applications, and third party network services may provide a platform for customers to deploy applications.

In at least one embodiment, various infrastructure services may be provided by the IaaS platform in the third party network infrastructure system. In at least one embodiment, the infrastructure services facilitate management and control of underlying computing resources (such as storage, networks, and other underlying computing resources) by clients that utilize services provided by the SaaS platform and PaaS platform.

In at least one embodiment, the third party network infrastructure system 1302 can also include infrastructure resources 1330 for providing resources for providing various services to customers of the third party network infrastructure system. In at least one embodiment, infrastructure resources 1330 can include a combination of pre-integration and optimization of hardware (such as servers, storage, and networking resources) for executing services and other resources provided by PaaS platforms and SaaS platforms.

In at least one embodiment, resources in the third party network infrastructure system 1302 may be shared by multiple users and dynamically reallocated as desired. In at least one embodiment, resources can be allocated to users in different time zones. In at least one embodiment, the third party network infrastructure system 1302 can enable a first group of users in a first time zone to utilize resources of the third party network infrastructure system for a specified number of hours and then enable the same resources to be reassigned to another group of users located in a different time zone, thereby maximizing resource utilization.

In at least one embodiment, a plurality of internal sharing services 1332 that are shared by different components or modules of the third party network infrastructure system 1302 may be provided for enabling services to be provided by the third party network infrastructure system 1302. In at least one embodiment, these internal sharing services may include, but are not limited to, security and identity services, integration services, enterprise library services, enterprise manager services, virus scanning and whitelisting services, high availability, backup and restore services, services for enabling third party network support, email services, notification services, file transfer services, and/or variants thereof.

In at least one embodiment, the third party network infrastructure system 1302 can provide comprehensive management of third party network services (e.g., saaS, paaS, and IaaS services) in the third party network infrastructure system. In at least one embodiment, the third party network management functions may include the ability to provision, manage, and track subscriptions of customers received by the third party network infrastructure system 1302, and/or variations thereof.

In at least one embodiment, as shown in FIG. 13, third party network management functions may be provided by one or more modules, such as an order management module 1320, an order orchestration module 1322, an order provisioning module 1324, an order management and monitoring module 1326, and an identity management module 1328. In at least one embodiment, these modules may include or be provided using one or more computers and/or servers, which may be general purpose computers, special purpose server computers, server farms, clusters of servers, or any other suitable arrangement and/or combination.

In at least one embodiment, at step 1334, a customer using a client device (such as client computing device 1304, 1306, or 1308) may interact with third party network infrastructure system 1302 by requesting one or more services provided by third party network infrastructure system 1302 and placing an order for a subscription to one or more services provided by third party network infrastructure system 1302. In at least one embodiment, the customer may access a third party network User Interface (UI), such as third party network UI 1312, third party network UI 1314, and/or third party network UI 1316, and place the order via these UIs. In at least one embodiment, the order information received by the third party network infrastructure system 1302 in response to the customer placing the order may include information identifying the customer and one or more services provided by the third party network infrastructure system 1302 to which the customer wants to subscribe.

In at least one embodiment, at step 1336, the order information received from the customer may be stored in order database 1318. In at least one embodiment, if this is a new order, a new record may be created for the order. In at least one embodiment, the order database 1318 may be one of several databases operated by the third party network infrastructure system 1318 and in conjunction with other system elements.

In at least one embodiment, at step 1338, the order information may be forwarded to an order management module 1320, which may be configured to perform billing and accounting functions related to the order, such as validating the order, and, upon validation, to order an order.

In at least one embodiment, at step 1340, information about the order may be transferred to the order orchestration module 1322, the order orchestration module 1322 configured to orchestrate the provision of services and resources for the order placed by the customer. In at least one embodiment, the order orchestration module 1322 may provision using the services of the order provisioning module 1324. In at least one embodiment, the order orchestration module 1322 enables the business processes associated with each order to be managed, and applies business logic to determine whether an order should continue to be served.

In at least one embodiment, at step 1342, the order orchestration module 1322 sends a request to the order provisioning module 1324 to allocate resources and configure the resources needed to fulfill the subscription order when a new subscription order is received. In at least one embodiment, the order provisioning module 1324 enables resource allocation for services subscribed to by a customer. In at least one embodiment, the order provisioning module 1324 provides a level of abstraction between the third party network service provided by the third party network infrastructure system 1300 and the physical implementation layer for provisioning resources for providing the requested service. In at least one embodiment, this enables the order orchestration module 1322 to be isolated from implementation details, such as whether services and resources are actually provisioned in real-time, or pre-provisioned and allocated/assigned only upon request.

In at least one embodiment, once the services and resources are provisioned, a notification may be sent to the subscribing client indicating that the requested service is now ready for use, step 1344. In at least one embodiment, information (e.g., a link) may be sent to the customer that enables the customer to begin using the requested service.

In at least one embodiment, the orders to which the customer subscribes may be managed and tracked by the order management and monitoring module 1326 at step 1346. In at least one embodiment, the order management and monitoring module 1326 may be configured to collect usage statistics regarding customer usage of subscription services. In at least one embodiment, statistics may be collected for the amount of memory used, the amount of data transmitted, the number of users, and the amount of system power-up and system power-down time and/or changes thereof.

In at least one embodiment, the third party network infrastructure system 1300 can include an identity management module 1328, the identity management module 1328 configured to provide identity services, such as access management and authorization services in the third party network infrastructure system 1300. In at least one embodiment, the identity management module 1328 can control information about customers desiring to utilize services provided by the third party network infrastructure system 1302. In at least one embodiment, such information may include information authenticating the identity of such clients and information describing which actions those clients are authorized to perform with respect to various system resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, the identity management module 1328 may also include managing descriptive information about each customer and how and by whom the descriptive information may be accessed and modified.

FIG. 14 illustrates a cloud computing environment 1402 in accordance with at least one embodiment. In at least one embodiment, cloud computing environment 1402 includes one or more computer systems/servers 1404 with which computing devices such as Personal Digital Assistant (PDA) or cellular telephone 1406A, desktop computer 1406B, laptop computer 1406C, and/or automobile computer system 1406N communicate. In at least one embodiment, this allows infrastructure, platforms, and/or software to be provided as a service from cloud computing environment 1402, so that each client is not required to maintain such resources individually. It should be appreciated that the types of computing devices 1406A-N shown in fig. 14 are intended to be illustrative only, and that cloud computing environment 1402 may communicate with any type of computerized device over any type of network and/or network/addressable connection (e.g., using a web browser).

In at least one embodiment, computer system/server 1404, which can be represented as a cloud computing node, can operate with many other general purpose or special purpose computing system environments or configurations. In at least one embodiment, examples of computing systems, environments, and/or configurations that may be suitable for use with computer system/server 1404 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and/or variations thereof.

In at least one embodiment, the computer system/server 1404 can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. In at least one embodiment, the exemplary computer system/server 1404 can be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices that are linked through a communications network. In at least one embodiment, in a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

FIG. 15 illustrates a set of functional abstraction layers provided by cloud computing environment 1402 (FIG. 14) in accordance with at least one embodiment. It should be understood in advance that the components, layers, and functions shown in fig. 15 are intended to be illustrative only, and that the components, layers, and functions may vary.

In at least one embodiment, the hardware and software layer 1502 includes hardware and software components. In at least one embodiment, examples of hardware components include a mainframe, servers based on various RISC (reduced instruction set computer) architectures, various computing systems, supercomputers, storage devices, networks, networking components, and/or variations thereof. In at least one embodiment, the software components include web application server software, various database software, and/or variations thereof.

In at least one embodiment, virtualization layer 1504 provides an abstraction layer from which the following exemplary virtual entities may be provided: virtual servers, virtual storage, virtual networks (including virtual private networks), virtual applications, virtual clients, and/or variants thereof.

In at least one embodiment, the management layer 1506 provides various functions. In at least one embodiment, resource provisioning provides dynamic acquisition of computing resources and other resources for executing tasks within a cloud computing environment. In at least one embodiment, metering (metering) provides usage tracking when resources are utilized within a cloud computing environment, as well as billing or invoices for consumption of those resources. In at least one embodiment, the resource may include an application software license. In at least one embodiment, security provides authentication for users and tasks, as well as protection of data and other resources. In at least one embodiment, the user interface provides access to the cloud computing environment for both users and system administrators. In at least one embodiment, service level management provides cloud computing resource allocation and management such that a desired service level is met. In at least one embodiment, service Level Agreement (SLA) management provides for pre-deployment and acquisition of cloud computing resources, which are anticipated to be in future demand for the cloud computing resources according to the SLA.

In at least one embodiment, the workload layer 1508 provides functionality that utilizes a cloud computing environment. In at least one embodiment, the workloads and functions that may be provided from this layer include: map and navigation, software development and management, educational services, data analysis and processing, transaction processing, and service delivery.

Super computing

The following figures illustrate, but are not limited to, exemplary supercomputer-based systems that may be utilized to implement at least one embodiment.

In at least one embodiment, a supercomputer may refer to a hardware system exhibiting significant parallelism and including at least one chip, wherein chips in the system are interconnected by a network and placed in a hierarchically organized enclosure. In at least one embodiment, a large hardware system that fills a machine room with racks is one particular example of a supercomputer, each rack including a number of boards/rack modules, each board/rack module including a number of chips all interconnected by a scalable network. In at least one embodiment, a single rack of such a large hardware system is another example of a supercomputer. In at least one embodiment, a single chip exhibiting significant parallelism and including several hardware components may also be considered a supercomputer, as the amount of hardware that may be incorporated into a single chip may also increase as feature sizes may decrease.

FIG. 16 illustrates a chip-scale supercomputer in accordance with at least one embodiment. In at least one embodiment, the main computation is performed within a finite state machine (1604), referred to as a thread unit, inside an FPGA or ASIC chip. In at least one embodiment, a task and synchronization network (1602) is connected to the finite state machine and is used to dispatch threads and perform operations in the correct order. In at least one embodiment, a memory network (1606, 1610) is used to access an on-chip cache hierarchy (1608, 1612) of a multi-level partition. In at least one embodiment, the off-chip memory is accessed using a memory controller (1616) and an off-chip memory network (1614). In at least one embodiment, the I/O controller (1618) is used to communicate across chips when the design is not suitable for a single logic chip.

FIG. 17 illustrates a supercomputer at rack module level in accordance with at least one embodiment. In at least one embodiment, within the rack module, there are a plurality of FPGA or ASIC chips (1702) connected to one or more DRAM units (1704) that make up the main accelerator memory. In at least one embodiment, each FPGA/ASIC chip is connected to its neighboring FPGA/ASIC chip with differential high-speed signaling (1706) using a wide bus on board. In at least one embodiment, each FPGA/ASIC chip is also connected to at least one high-speed serial communications cable.

FIG. 18 illustrates a rack-level supercomputer in accordance with at least one embodiment. FIG. 19 illustrates an overall system level supercomputer in accordance with at least one embodiment. In at least one embodiment, referring to fig. 18 and 19, a scalable, possibly incomplete hypercube network is implemented using high-speed serial or copper cables (1802, 1902) between rack modules in the rack and across the entire system of racks. In at least one embodiment, one of the accelerator's FPGA/ASIC chips is connected to the host system through a PCI-Express connection (1904). In at least one embodiment, the host system includes a host microprocessor (1908) on which the software portion of the application runs and memory comprised of one or more host memory DRAM cells (1906) that are consistent with memory on the accelerator. In at least one embodiment, the host system may be a separate module on one of the racks, or may be integrated with one of the modules of the supercomputer. In at least one embodiment, the loop topology of the cube connections provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a small group of FPGA/ASIC chips on a rack module may act as a single hypercube node such that the total number of external links per group is increased compared to a single chip. In at least one embodiment, the group includes chips A, B, C and D on a rack module with an internal wide differential bus connecting A, B, C and D in a ring organization. In at least one embodiment, there are 12 serial communication cables connecting the rack module to the outside world. In at least one embodiment, the chip A on the rack module is connected to the serial communication cable 0, 1, 2. In at least one embodiment, chip B is connected to cables 3, 4, 5. In at least one embodiment, chip C is connected to 6, 7, 8. In at least one embodiment, the chip D is connected to 9, 10, 11. In at least one embodiment, the entire set { A, B, C, D } comprising the rack modules may form a hypercube node within a supercomputer system, with up to 212 = 4096 rack modules (16384 FPGA/ASIC chips). In at least one embodiment, in order for chip A to send messages out on link 4 of group { A, B, C, D }, the messages must first be routed to chip B using an on-board differential wide bus connection. In at least one embodiment, messages arriving on link 4 at group { A, B, C, D } destined for chip A (i.e., arriving at B) must also be routed first to the correct destination chip (A) inside group { A, B, C, D }. In at least one embodiment, other sizes of parallel supercomputer systems may also be implemented.

Artificial intelligence

The following figures illustrate exemplary artificial intelligence-based systems that may be used to implement at least one embodiment.

Fig. 20A illustrates inference and/or training logic 2015 for performing inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 2015 are provided below in connection with fig. 20A and/or 20B.

In at least one embodiment, the inference and/or training logic 2015 can include, but is not limited to, code and/or data storage 2001 for storing forward and/or output weights and/or input/output data, and/or other parameters for configuring neurons or layers of a neural network that is trained and/or used for inference in aspects of one or more embodiments. In at least one embodiment, training logic 2015 may include or be coupled to code and/or data store 2001 to store graphics code or other software to control timing and/or sequencing, wherein loading weights and/or other parameter information is used to configure logic, including integer and/or floating point units (collectively referred to as Arithmetic Logic Units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and/or data store 2001 stores weight parameters and/or input/output data for each layer of a neural network that is trained or used in connection with one or more embodiments during forward propagation of the input/output data and/or weight parameters during training and/or reasoning using aspects of one or more embodiments. In at least one embodiment, any portion of code and/or data storage 2001 may be included with other on-chip or off-chip data storage devices, including the processor's L1, L2, or L3 cache memory or system memory.

In at least one embodiment, any portion of code and/or data storage 2001 may be internal or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, the code and/or data storage 2001 may be cache memory, dynamic random-access memory ("DRAM"), static random-access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage device. In at least one embodiment, the choice of whether code and/or data storage 2001 is internal or external to the processor, for example, or includes DRAM, SRAM, flash, or some other storage type, may depend on the latency requirements of the training and/or reasoning function being performed, the batch size of the data used in the reasoning and/or training of the neural network, or some combination of these factors, relative to the available storage off-chip.

In at least one embodiment, the inference and/or training logic 2015 can include, but is not limited to: code and/or data store 2005 to store inverse and/or output weights and/or input/output data corresponding to neurons or layers of a neural network that are trained and/or used for reasoning in aspects of one or more embodiments. In at least one embodiment, the code and/or data store 2005 stores weight parameters and/or input/output data for each layer of a neural network that is trained or used in connection with one or more embodiments during back propagation of the input/output data and/or weight parameters during training and/or reasoning using aspects of the one or more embodiments. In at least one embodiment, training logic 2015 may include or be coupled to code and/or data store 2005 to store graph code or other software to control timing and/or sequencing, where weights and/or other parameter information are to be loaded to configure logic, including integer and/or floating point units (collectively referred to as Arithmetic Logic Units (ALUs)).

In at least one embodiment, code (such as graph code) causes the architecture based on the neural network to which such code corresponds to load weight or other parameter information into the processor ALU. In at least one embodiment, any portion of code and/or data store 2005 can be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and/or data storage 2005 may be internal or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, the code and/or data storage 2005 can be cache memory, DRAM, SRAM, nonvolatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and/or data storage 2005 is internal or external to the processor, for example, or includes DRAM, SRAM, flash, or some other storage type, may depend on the latency requirements of the training and/or reasoning function being performed relative to the available storage off-chip, the batch size of the data used in the reasoning and/or training of the neural network, or some combination of these factors.

In at least one embodiment, code and/or data store 2001 and code and/or data store 2005 can be separate storage structures. In at least one embodiment, code and/or data store 2001 and code and/or data store 2005 can be a combined storage structure. In at least one embodiment, code and/or data store 2001 and code and/or data store 2005 can be partially combined and partially separated. In at least one embodiment, code and/or data store 2001 and any portion of code and/or data store 2005 can be included with other on-chip or off-chip data stores (including processor L1, L2, or L3 caches or system memory).

In at least one embodiment, the inference and/or training logic 2015 can include, but is not limited to, one or more arithmetic logic units ("ALUs") 2010, including integer and/or floating point units, for performing logical and/or mathematical operations based at least in part on or indicated by training and/or inference code (e.g., graphics code), the results of which can result in activations (e.g., output values from layers or neurons within a neural network) stored in an activation store 2020 that is a function of input/output and/or weight parameter data stored in code and/or data store 2001 and/or code and/or data store 2005. In at least one embodiment, the activations stored in the activation store 2020 are generated according to linear algebra performed by the ALU 2010 and/or matrix-based mathematics in response to executing instructions or other code, wherein the weight values stored in the code and/or data store 2005 and/or data store 2001 are used as operands along with other values (such as bias values, gradient information, momentum values, or other parameters or super parameters), any or all of which may be stored in the code and/or data store 2005 or the code and/or data store 2001 or another storage on-chip or off-chip.

In at least one embodiment, one or more ALUs 2010 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 2010 may be external to the processor or other hardware logic device or circuit (e.g., coprocessor) in which they are used. In at least one embodiment, ALU 2010 may be included or otherwise within an ALU library accessible to an execution unit of a processor that is within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, code and/or data store 2001, code and/or data store 2005, and activation store 2020 may share a processor or other hardware logic device or circuitry, while in another embodiment they may be in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of the activation store 2020 may be included with other on-chip or off-chip data stores including the processor's L1, L2, or L3 cache or system memory. In addition, the inference and/or training code can be stored with other code that can be accessed by a processor or other hardware logic or circuitry and that can be obtained and/or processed using the processor's acquisition, decoding, scheduling, execution, retirement (retirement), and/or other logic circuitry.

In at least one embodiment, the activation store 2020 may be cache memory, DRAM, SRAM, nonvolatile memory (e.g., flash memory) or other storage. In at least one embodiment, the activation store 2020 may be wholly or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation store 2020 is internal or external to the processor, in at least one embodiment, or includes DRAM, SRAM, flash, or some other storage type, may depend on the latency requirements of the training and/or reasoning function being performed, the batch size of the data used in the reasoning and/or training of the neural network, or some combination of these factors, relative to the available storage off-chip.

In at least one embodiment, the inference and/or training logic 2015 shown in FIG. 20A can be used in conjunction with an application specific integrated circuit ("ASIC"), such as from GoogleProcessing unit from Graphcore ^TM Is an reasoning processing unit (IPU) of (E) or +.>(e.g., "Lake create") processor. In at least one embodiment, the inference and/or training logic 2015 shown in FIG. 20A can be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware (e.g., field programmable gate array ("FPGA")).

Fig. 20B illustrates inference and/or training logic 2015 in accordance with at least one embodiment. In at least one embodiment, the inference and/or training logic 2015 can include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in connection with weight values or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, the inference and/or training logic 2015 shown in FIG. 20B can be combined with an Application Specific Integrated Circuit (ASIC) (e.g., from GoogleProcessing unit from Graphcore ^TM Is an reasoning processing unit (IPU) of (E) or +.>(e.g., "Lake Crest ") processor. In at least one embodiment, the inference and/or training logic 2015 shown in fig. 20B can be used in conjunction with Central Processing Unit (CPU) hardware, graphics Processing Unit (GPU) hardware, or other hardware, such as a Field Programmable Gate Array (FPGA). In at least one embodiment, the inference and/or training logic 2015 includes, but is not limited to, code and/or data stores 2001 and code and/or data stores 2005, which can be used to store code (e.g., graph code), weight values, and/or other information, including bias values, gradient information, momentum values, and/or other parameter or hyper-parameter information. In at least one embodiment illustrated in fig. 20B, each of code and/or data store 2001 and code and/or data store 2005 is associated with dedicated computing resources (e.g., computing hardware 2002 and computing hardware 2006), respectively. In at least one embodiment, each of the computing hardware 2002 and 2006 includes one or more ALUs that perform mathematical functions (such as linear algebraic functions) on only the information stored in the code and/or data store 2001 and the code and/or data store 2005, respectively, the results of which are stored in the activation store 2020.

In at least one embodiment, each code and/or data store 2001 and 2005 and corresponding computing hardware 2002 and 2006, respectively, corresponds to a different layer of the neural network such that the resulting activation from one storage/computing pair 2001/2002 of the code and/or data store 2001 and computing hardware 2002 is provided as input to the next storage/computing pair 2005/2006 of the code and/or data store 2005 and computing hardware 2006 to mirror the conceptual organization of the neural network. In at least one embodiment, each of the storage/computation pairs 2001/2002 and 2005/2006 may correspond to more than one neural network layer. In at least one embodiment, additional storage/computation pairs (not shown) after or in parallel with storage/computation pairs 2001/2002 and 2005/2006 can be included in inference and/or training logic 2015.

FIG. 21 illustrates training and deployment of a deep neural network in accordance with at least one embodiment. In at least one embodiment, the training data set 2102 is used to train the untrained neural network 2106. In at least one embodiment, the training frame 2104 is a PyTorch frame, while in other embodiments, the training frame 2104 is TensorFlow, boost, caffe, microsoft Cognitive Toolkit/CNTK, MXNet, chainer, keras, deeplearning4j or other training frame. In at least one embodiment, the training framework 2104 trains the untrained neural network 2106 and enables it to be trained using the processing resources described herein to generate a trained neural network 2108. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

In at least one embodiment, the untrained neural network 2106 is trained using supervised learning, wherein the training data set 2102 comprises inputs paired with desired outputs for the inputs, or wherein the training data set 2102 comprises inputs having known outputs, and the outputs of the neural network 2106 are manually ranked. In at least one embodiment, the untrained neural network 2106 is trained in a supervised manner and the inputs from the training data set 2102 are processed and the resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, the error is then counter-propagated through the untrained neural network 2106. In at least one embodiment, the training framework 2104 adjusts weights that control the untrained neural network 2106. In at least one embodiment, the training framework 2104 includes a tool for monitoring how well the untrained neural network 2106 converges toward a model (such as the trained neural network 2108) adapted to generate a correct answer (such as the result 2114) based on input data (such as the new data set 2112). In at least one embodiment, the training framework 2104 repeatedly trains the untrained neural network 2106 while adjusting weights using an impairment function and an adjustment algorithm (such as a random gradient descent) to refine the output of the untrained neural network 2106. In at least one embodiment, the training framework 2104 trains the untrained neural network 2106 until the untrained neural network 2106 achieves a desired accuracy. In at least one embodiment, the trained neural network 2108 can then be deployed to implement any number of machine learning operations.

In at least one embodiment, the untrained neural network 2106 is trained using unsupervised learning, where the untrained neural network 2106 attempts to train itself using untagged data. In at least one embodiment, the unsupervised learning training data set 2102 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 2106 can learn the groupings within the training data set 2102 and can determine how the individual inputs relate to the untrained data set 2102. In at least one embodiment, unsupervised training may be used to generate an ad hoc map in trained neural network 2108 that is capable of performing operations useful in reducing the dimensions of new data set 2112. In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which allows identification of data points in the new data set 2112 that deviate from the normal pattern of the new data set 2112.

In at least one embodiment, semi-supervised learning, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 2102, may be used. In at least one embodiment, the training framework 2104 can be used to perform incremental learning, such as by a transfer learning technique. In at least one embodiment, incremental learning enables the trained neural network 2108 to adapt to the new data set 2112 without forgetting knowledge injected into the trained neural network 2108 during initial training.

5G network

The following figures illustrate exemplary 5G network-based systems that may be used to implement at least one embodiment.

Fig. 22 illustrates an architecture of a system 2200 of a network in accordance with at least one embodiment. In at least one embodiment, system 2200 is shown to include User Equipment (UE) 2202 and UE 2204. In at least one embodiment, the UEs 2202 and 2204 are shown as smart phones (e.g., handheld touch screen mobile computing devices connectable to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as a Personal Digital Assistant (PDA), pager, laptop computer, desktop computer, wireless handheld device, or any computing device that includes a wireless communication interface.

In at least one embodiment, any of the UEs 2202 and 2204 may comprise an internet of things (IoT) UE that may include a network access layer designed for low power IoT applications that utilize ephemeral UE connections. In at least one embodiment, the IoT UE may utilize technologies such as for exchanging data with MTC servers or devices via Public Land Mobile Networks (PLMNs), proximity-based services (ProSe) or device-to-device (D2D) communications, sensor networks, or IoT networks, such as machine-to-machine (M2M) or Machine Type Communications (MTC). In at least one embodiment, the M2M or MTC data exchange may be a machine initiated data exchange. In at least one embodiment, the IoT network describes interconnected IoT UEs that may include uniquely identifiable embedded computing devices (within the internet infrastructure) with short-lived connections. In at least one embodiment, ioT UEs may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate connection of IoT networks.

In at least one embodiment, the UE 2202 and the UE 2204 may be configured to connect (e.g., communicatively couple) with a Radio Access Network (RAN) 2216. In at least one embodiment, the RAN 2216 may be, for example, an evolved Universal Mobile Telecommunications System (UMTS) terrestrial radio access network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN. In at least one embodiment, the UE 2202 and the UE 2204 utilize connections 2212 and 2214, respectively, each of which includes a physical communication interface or layer. In at least one embodiment, connections 2212 and 2214 are shown as air interfaces for implementing communicative coupling and may be consistent with cellular communication protocols, such as global system for mobile communications (GSM) protocols, code Division Multiple Access (CDMA) network protocols, push-to-talk (PTT) protocols, push-to-cellular (POC) protocols, universal Mobile Telecommunications System (UMTS) protocols, 3GPP Long Term Evolution (LTE) protocols, fifth generation (5G) protocols, new Radio (NR) protocols, and variations thereof.

In at least one embodiment, the UEs 2202 and 2204 may also exchange communication data directly via the ProSe interface 2206. In at least one embodiment, proSe interface 2206 may alternatively be referred to as a side link interface comprising one or more logical channels including, but not limited to, a physical side link control channel (PSCCH), a physical side link shared channel (PSSCH), a physical side link discovery channel (PSDCH), and a physical side link broadcast channel (PSBCH).

In at least one embodiment, UE 2204 is shown configured to access an Access Point (AP) 2210 via connection 2208. In at least one embodiment, the connection 2208 may comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, where the AP 2210 would include wireless fidelityAnd a router. In at least one embodiment, the AP 2210 is shown connected to the internet and not to the core network of the wireless system.

In at least one embodiment, RAN 2216 can include one or more access nodes that enable connections 2212 and 2214. In at least one embodiment, these Access Nodes (ANs) may be referred to as Base Stations (BS), nodebs, evolved nodebs (enbs), next generation nodebs (gnbs), RAN nodes, etc., and may include ground stations (e.g., terrestrial access points) or satellite stations that provide coverage within a geographic area (e.g., cell). In at least one embodiment, the RAN 2216 may include one or more RAN nodes (e.g., macro RAN node 2218) for providing macro cells and one or more RAN nodes (e.g., low Power (LP) RAN node 2220) for providing femto cells or pico cells (e.g., cells having a smaller coverage area, smaller user capacity, or higher bandwidth than macro cells).

In at least one embodiment, either of the RAN nodes 2218 and 2220 may terminate the air interface protocol and may be the first point of contact for the UEs 2202 and 2204. In at least one embodiment, either of the RAN nodes 2218 and 2220 may implement various logical functions of the RAN 2216 including, but not limited to, radio Network Controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management, and data packet scheduling and mobility management.

In at least one embodiment, the UE 2202 and the UE 2204 may be configured to communicate with each other or any of the RAN node 2218 and RAN node 2220 over a multicarrier communication channel using Orthogonal Frequency Division Multiplexing (OFDM) communication signals in accordance with various communication techniques such as, but not limited to, orthogonal Frequency Division Multiple Access (OFDMA) communication techniques (e.g., for downlink communications) or single carrier frequency division multiple access (SC-FDMA) communication techniques (e.g., for uplink and ProSe or side link communications), and/or variants thereof. In at least one embodiment, the OFDM signal may include a plurality of orthogonal subcarriers.

In at least one embodiment, a downlink resource grid may be used for downlink transmissions from either of the RAN nodes 2218 and 2220 to the UEs 2202 and 2204, while uplink transmissions may utilize similar techniques. In at least one embodiment, the grid may be a time-frequency grid, referred to as a resource grid or a time-frequency resource grid, which is a physical resource in the downlink in each time slot. In at least one embodiment, such a time-frequency planar representation is a common practice of OFDM systems, which makes it intuitive for radio resource allocation. In at least one embodiment, each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one slot in a radio frame. In at least one embodiment, the smallest time-frequency unit in the resource grid is denoted as a resource element. In at least one embodiment, each resource grid includes a plurality of resource blocks that describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block includes a set of resource elements. In at least one embodiment, in the frequency domain, this may represent the minimum number of resources that can currently be allocated. In at least one embodiment, there are several different physical downlink channels transmitted using such resource blocks.

In at least one embodiment, a Physical Downlink Shared Channel (PDSCH) may carry user data and higher layer signaling to UEs 2202 and 2204. In at least one embodiment, a Physical Downlink Control Channel (PDCCH) may carry information on a transport format and resource allocation related to a PDSCH channel, and the like. In at least one embodiment, it may also inform UEs 2202 and 2204 of transport format, resource allocation, and HARQ (hybrid automatic repeat request) information related to the uplink shared channel. In at least one embodiment, in general, downlink scheduling (allocation of control and shared channel resource blocks to UEs 2202 within a cell) may be performed at either of RAN nodes 2218 and 2220 based on channel quality information fed back from either of UEs 2202 and 2204. In at least one embodiment, the downlink resource allocation information may be transmitted on a PDCCH for (e.g., allocated to) each of the UEs 2202 and 2204.

In at least one embodiment, the PDCCH may transmit control information using Control Channel Elements (CCEs). In at least one embodiment, the PDCCH complex-valued symbols may first be organized into quadruples before being mapped to resource elements, which may then be permuted using a sub-block interleaver for rate matching. In at least one embodiment, each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements referred to as Resource Element Groups (REGs). In at least one embodiment, four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to each REG. In at least one embodiment, the PDCCH may be transmitted using one or more CCEs depending on a size of Downlink Control Information (DCI) and channel conditions. In at least one embodiment, there may be four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, l=1, 2, 4, or 8).

In at least one embodiment, an Enhanced Physical Downlink Control Channel (EPDCCH) using PDSCH resources may be used for control information transmission. In at least one embodiment, the EPDCCH may be transmitted using one or more Enhanced Control Channel Elements (ECCEs). In at least one embodiment, each ECCE may correspond to nine sets of four physical resource elements referred to as Enhanced Resource Element Groups (EREGs). In at least one embodiment, ECCEs may have other numbers of EREGs in some cases.

In at least one embodiment, RAN 2216 is shown communicatively coupled to a Core Network (CN) 2238 via an S1 interface 2222. In at least one embodiment, the CN 2238 may be an Evolved Packet Core (EPC) network, a NextGen Packet Core (NPC) network, or some other type of CN. In at least one embodiment, S1 interface 2222 is split into two parts: an S1-U interface 2226 that carries traffic data between RAN nodes 2218 and 2220 and a serving gateway (S-GW) 2230; and an S1-Mobility Management Entity (MME) interface 2224, which is a signaling interface between RAN nodes 2218 and 2220 and MME 2228.

In at least one embodiment, the CN 2238 includes an MME 2228, an S-GW 2230, a Packet Data Network (PDN) gateway (P-GW) 2234, and a Home Subscriber Server (HSS) 2232. In at least one embodiment, the MME 2228 may be similar in function to the control plane of a conventional serving General Packet Radio Service (GPRS) support node (SGSN). In at least one embodiment, the MME 2228 may manage mobility aspects in access, such as gateway selection and tracking area list management. In at least one embodiment, the HSS2232 may include a database for network users that includes subscription-related information for supporting network entities to handle communication sessions. In at least one embodiment, the CN 2238 may include one or more HSS2232, depending on the number of mobile users, the capacity of the device, the organization of the network, and so on. In at least one embodiment, the HSS2232 may provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependencies, and the like.

In at least one embodiment, the S-GW 2230 may terminate the S1 interface 2222 towards the RAN 2216 and route data packets between the RAN 2216 and the CN 2238. In at least one embodiment, the S-GW 2230 may be a local mobility anchor for inter-RAN node handover and may also provide an anchor for inter-3 GPP mobility. In at least one embodiment, other responsibilities may include lawful interception, charging, and some policy enforcement.

In at least one embodiment, the P-GW 2234 may terminate the SGi interface towards the PDN. In at least one embodiment, the P-GW 2234 may route data packets between the EPC network 2238 and an external network, such as a network that includes an application server 2240 (or referred to as an Application Function (AF)), via an Internet Protocol (IP) interface 2242. In at least one embodiment, the application server 2240 may be an element that provides applications using IP bearer resources using a core network (e.g., UMTS Packet Service (PS) domain, LTE PS data service, etc.). In at least one embodiment, P-GW 2234 is shown communicatively coupled to application server 2240 via IP communication interface 2242. In at least one embodiment, the application server 2240 may also be configured to support one or more communication services (e.g., voice over internet protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) of the UEs 2202 and 2204 via the CN 2238.

In at least one embodiment, the P-GW 2234 may also be a node for policy enforcement and charging data collection. In at least one embodiment, the policy and charging enforcement function (PCRF) 2236 is a policy and charging control element of the CN 2238. In at least one embodiment, in a non-roaming scenario, a single PCRF may be present in a Home Public Land Mobile Network (HPLMN) associated with an internet protocol connectivity access network (IP-CAN) session of a UE. In at least one embodiment, in a roaming scenario with local traffic breakthrough, there may be two PCRFs associated with the IP-CAN session of the UE: a home PCRF (H-PCRF) within the HPLMN and a visited PCRF (V-PCRF) within the Visited Public Land Mobile Network (VPLMN). In at least one embodiment, PCRF 2236 can be communicatively coupled to application server 2240 via P-GW 2234. In at least one embodiment, the application server 2240 may signal the PCRF 2236 to indicate the new service flow and select the appropriate quality of service (QoS) and charging parameters. In at least one embodiment, PCRF 2236 may supply this rule to a Policy and Charging Enforcement Function (PCEF) (not shown) of the QoS Class (QCI) with the appropriate Traffic Flow Template (TFT) and identifier, which begins QoS and charging specified by application server 2240.

Fig. 23 illustrates an architecture of a system 2300 of a network in accordance with some embodiments. In at least one embodiment, the system 2300 is shown to include a UE 2302, a 5G access node or RAN node (shown as (R) AN node 2308), a user plane function (shown as UPF 2304), a data network (DN 2306), which may be, for example, AN operator service, AN internet access or third party service, and a 5G core network (5 GC) (shown as CN 2310).

In at least one embodiment, the CN 2310 includes an authentication server function (AUSF 2314); core access and mobility management functions (AMF 2312); session management function (SMF 2318); network exposure function (NEF 2316); policy control function (PCF 2322); a Network Function (NF) repository function (NRF 2320); unified data management (UDM 2324); and an application function (AF 2326). In at least one embodiment, the CN 2310 may also include other elements not shown, such as structured data storage network functions (SDSFs), unstructured data storage network functions (UDSFs), and variations thereof.

In at least one embodiment, UPF 2304 may serve as an anchor point for intra-RAT and inter-RAT mobility, an external PDU session point interconnected to DN 2306, and a branching point to support multi-homing PDU sessions. In at least one embodiment, the UPF 2304 may also perform packet routing and forwarding, packet inspection, user plane portion enforcing policy rules, lawful intercept packets (UP collection); traffic usage reporting, performing QoS processing (e.g., packet filtering, gating, UL/DL rate execution) for the user plane, performing uplink traffic verification (e.g., SDF to QoS flow mapping), transport level packet marking in uplink and downlink, and downlink packet buffering and downlink data notification triggering. In at least one embodiment, the UPF 2304 may include an uplink classifier for supporting routing traffic flows to a data network. In at least one embodiment, DN 2306 may represent various network operator services, internet access, or third party services.

In at least one embodiment, the AUSF 2314 may store data for authentication of the UE 2302 and process authentication related functions. In at least one embodiment, the AUSF 2314 may facilitate a common authentication framework for various access types.

In at least one embodiment, the AMF 2312 may be responsible for registration management (e.g., for registering the UE 2302, etc.), connection management, reachability management, mobility management, and lawful interception of AMF related events, as well as access authentication and authorization. In at least one embodiment, the AMF 2312 may provide for the transmission of SM messages for the SMF 2318 and act as a transparent proxy for routing SM messages. In at least one embodiment, the AMF 2312 may also provide for transmission of Short Message Service (SMS) messages between the UE 2302 and an SMS function (SMSF) (not shown in fig. 23). In at least one embodiment, the AMF 2312 may act as a secure anchor function (SEA), which may include interactions with the AUSF 2314 and the UE 2302 and receiving intermediate keys established as a result of the UE 2302 authentication procedure. In at least one embodiment, in the case of USIM-based authentication, the AMF 2312 may retrieve the security material from the AUSF 2314. In at least one embodiment, the AMF 2312 may also include a Security Context Management (SCM) function that receives a key from the SEA that it uses to derive access network specific keys. Furthermore, in at least one embodiment, the AMF 2312 may be a termination point of the RAN CP interface (N2 reference point), a termination point of NAS (NI) signaling, and perform NAS ciphering and integrity protection.

In at least one embodiment, the AMF 2312 may also support NAS signaling with the UE 2302 over an N3 interworking function (IWF) interface. In at least one embodiment, the N3IWF may be used to provide access to untrusted entities. In at least one embodiment, the N3IWF may be the termination point of the N2 and N3 interfaces of the control plane and user plane, respectively, and thus, the N2 signaling from the SMF and AMF may be handled for PDU sessions and QoS, encapsulating/decapsulating packets of IPSec and N3 tunnels, marking the N3 user plane packets in the uplink, and enforcing QoS corresponding to the N3 packet marking taking into account QoS requirements associated with such marking received over N2. In at least one embodiment, the N3IWF may also relay uplink and downlink control plane NAS (NI) signaling between the UE 2302 and the AMF 2312, and relay uplink and downlink user plane packets between the UE 2302 and the UPF 2304. In at least one embodiment, the N3IWF also provides a mechanism for IPsec tunnel establishment with UE 2302.

In at least one embodiment, the SMF 2318 may be responsible for session management (e.g., session establishment, modification, and release, including tunnel maintenance between UPF and AN nodes); UE IP address assignment and management (including optional authorization); selection and control of the UP function; configuring traffic steering at the UPF to route traffic to an appropriate destination; terminating the interface towards the policy control function; policy enforcement and QoS control section; lawful interception (for SM events and interfaces to LI systems); termination of SM portion of NAS message; downlink data notification; AN initiator of AN specific SM information, which is sent to the AN over N2 via AMF; the SSC pattern of the session is determined. In at least one embodiment, the SMF 2318 may include the following roaming functions: processing the local implementation to apply QoS SLAB (VPLMN); a charging data collection and charging interface (VPLMN); lawful interception (for SM events in VPLMN and interfacing to LI system); interaction with the external DN is supported to transmit signaling for PDU session authorization/authentication by the external DN.

In at least one embodiment, the NEF 2316 may provide means for securely exposing services and capabilities provided by 3GPP network functions for third parties, internal exposure/re-exposure, application functions (e.g., AF 2326), edge computing or fog computing systems, and the like. In at least one embodiment, the NEF 2316 may authenticate, authorize, and/or throttle AF. In at least one embodiment, NEF 2316 may also convert information exchanged with AF 2326 and information exchanged with internal network functions. In at least one embodiment, the NEF 2316 may translate between AF service identifiers and internal 5GC information. In at least one embodiment, the NEF 2316 may also receive information from other Network Functions (NFs) based on the exposed capabilities of the other network functions. In at least one embodiment, this information may be stored as structured data at NEF 2316, or at data store NF using a standardized interface. In at least one embodiment, the stored information may then be re-exposed to other NFs and AFs by the NEF 2316, and/or used for other purposes, such as analysis.

In at least one embodiment, NRF 2320 may support service discovery functionality, receive NF discovery requests from NF instances, and provide NF instances with information of discovered NF instances. In at least one embodiment, NRF 2320 also maintains information of available NF instances and services supported thereby.

In at least one embodiment, PCF 2322 may provide policy rules to control plane functions to implement them, and may also support a unified policy framework to manage network behavior. In at least one embodiment, PCF 2322 may also implement a front-end (FE) for accessing subscription information related to policy decisions in the UDR of UDM 2324.

In at least one embodiment, the UDM 2324 may process subscription related information to support network entities in handling communication sessions, and may store subscription data for the UE 2302. In at least one embodiment, UDM 2324 may include two parts, an application FE and a User Data Repository (UDR). In at least one embodiment, the UDM may include a UDM FE responsible for handling credentials, location management, subscription management, and the like. In at least one embodiment, several different front ends may serve the same user in different transactions. In at least one embodiment, the UDM-FE accesses sub-subscription information stored in the UDR and performs authentication credential processing; user identification processing; access authorization; registration/mobility management; subscription management. In at least one embodiment, the UDR may interact with PCF 2322. In at least one embodiment, UDM 2324 may also support SMS management, where SMS-FEs implement similar application logic as previously described.

In at least one embodiment, the AF 2326 may provide application impact on traffic routing, access to Network Capability Exposure (NCE), and interaction with policy frameworks for policy control. In at least one embodiment, NCE may be a mechanism that allows 5GC and AF 2326 to provide information to each other via NEF 2316, which NEF 2316 may be used for edge computing implementations. In at least one embodiment, network operators and third party services may be hosted near the attachment access point of the UE 2302 to enable efficient service delivery with reduced end-to-end latency and load on the transport network. In at least one embodiment, for edge computing implementations, the 5GC may select a UPF 2304 close to the UE 2302 and perform traffic steering from the UPF 2304 to the DN 2306 via the N6 interface. In at least one embodiment, this may be based on UE subscription data, UE location, and information provided by AF 2326. In at least one embodiment, AF 2326 may affect UPF (re) selection and traffic routing. In at least one embodiment, based on the operator deployment, the network operator may allow the AF 2326 to interact directly with the associated NF when the AF 2326 is considered a trusted entity.

In at least one embodiment, the CN 2310 may include an SMSF that may be responsible for SMS subscription checking and authentication and relay SM messages to/from the UE 2302 to/from other entities, such as SMS-GMSC/IWMSC/SMS router. In at least one embodiment, SMS may also interact with AMF 2312 and UDM 2324 for notification procedures that UE 2302 is available for SMS delivery (e.g., setting a UE unreachable flag and notifying UDM 2324 when UE 2302 is available for SMS).

In at least one embodiment, the system 2300 may include the following service-based interfaces: namf: service-based interfaces presented by the AMF; nsmf: a service-based interface presented by the SMF; nnef: a service-based interface exhibited by the NEF; npcf: a service-based interface exhibited by the PCF; nudm: a service-based interface presented by the UDM; naf: service-based interfaces revealed by AF; nnrf: service-based interfaces presented by NRF; nausf: an AUSF exposed service-based interface.

In at least one embodiment, the system 2300 may include the following reference points: n1: a reference point between the UE and the AMF; n2: (R) a reference point between AN and AMF; and N3: (R) a reference point between AN and UPF; n4: a reference point between SMF and UPF; and N6: reference points between UPF and data network. In at least one embodiment, there may be more reference points and/or service-based interfaces between NF services in the NF, however, these interfaces and reference points have been omitted for clarity. In at least one embodiment, the NS reference point may be between the PCF and the AF; the N7 reference point may be between the PCF and the SMF; the N11 reference point is between AMF and SMF, etc. In at least one embodiment, the CN 2310 may include an Nx interface, which is an inter-CN interface between the MME and the AMF 2312, in order to enable interworking between the CN 2310 and the CN 7221.

In at least one embodiment, the system 2300 may include a plurality of RAN nodes (such as (R) AN nodes 2308), wherein AN Xn interface is defined between two or more (R) AN nodes 2308 (e.g., gnbs) connected to the 5gc 410, between a (R) AN node 2308 (e.g., gNB) connected to the CN 2310 and AN eNB (e.g., macro RAN node), and/or between two enbs connected to the CN 2310.

In at least one embodiment, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, an Xn-U may provide for the non-guaranteed delivery of user plane PDUs and support/provide data forwarding and flow control functions. In at least one embodiment, the Xn-C may provide management and error handling functions, functions to manage the Xn-C interface; mobility support for UEs 2302 in a CONNECTED mode (e.g., CM-CONNECTED) includes functionality to manage UE mobility for a CONNECTED mode between one or more (R) AN nodes 2308. In at least one embodiment, mobility support may include a context transfer from AN old (source) service (R) AN node 2308 to a new (target) service (R) AN node 2308; and controlling a user plane tunnel between the old (source) serving (R) AN node 2308 to the new (target) serving (R) AN node 2308.

In at least one embodiment, the protocol stack of the Xn-U may include a transport network layer built on top of an Internet Protocol (IP) transport layer and a GTP-U layer on top of UDP and/or one or more IP layers for carrying user plane PDUs. In at least one embodiment, the Xn-C protocol stack may include an application layer signaling protocol, referred to as Xn application protocol (Xn-AP), and a transport network layer built upon the SCTP layer. In at least one embodiment, the SCTP layer may be on top of the IP layer. In at least one embodiment, the SCTP layer provides guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transport is used to deliver signaling PDUs. In at least one embodiment, the Xn-U protocol stack and/or the Xn-C protocol stack may be the same or similar to the user plane and/or control plane protocol stacks shown and described herein.

Fig. 24 is an illustration of a control plane protocol stack in accordance with some embodiments. In at least one embodiment, the control plane 2400 is shown as a communication protocol stack between the UE 2202 (or alternatively, the UE 2204), the RAN 2216, and the MME 2228.

In at least one embodiment, PHY layer 2402 may transmit or receive information used by MAC layer 2404 over one or more air interfaces. In at least one embodiment, PHY layer 2402 may also perform link adaptation or Adaptive Modulation and Coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers (e.g., RRC layer 2410). In at least one embodiment, PHY layer 2402 may further perform error detection for the transport channel, forward Error Correction (FEC) encoding/decoding of the transport channel, modulation/demodulation of the physical channel, interleaving, rate matching, mapping to the physical channel, and multiple-input multiple-output (MIMO) antenna processing.

In at least one embodiment, the MAC layer 2404 may perform mapping between logical channels and transport channels, multiplexing MAC Service Data Units (SDUs) from one or more logical channels onto Transport Blocks (TBs) to be delivered to the PHY via the transport channels, demultiplexing MAC SDUs from Transport Blocks (TBs) delivered from the PHY via the transport channels onto one or more logical channels, multiplexing MAC SDUs onto TBs, scheduling information reporting, error correction by hybrid automatic repeat request (HARD), and logical channel prioritization.

In at least one embodiment, the RLC layer 2406 may operate in a variety of modes of operation, including: transparent Mode (TM), unacknowledged Mode (UM), and Acknowledged Mode (AM). In at least one embodiment, the RLC layer 2406 may perform transmission of upper layer Protocol Data Units (PDUs), error correction by automatic repeat request (ARQ) for AM data transmission, and concatenation, segmentation, and reassembly of RLC SDUs for UM and AM data transmission. In at least one embodiment, the RLC layer 2406 may also perform re-segmentation of RLC data PDUs for AM data transmissions, reorder RLC data PDUs for UM and AM data transmissions, detect duplicate data for UM and AM data transmissions, discard RLC SDUs for UM and AM data transmissions, detect protocol errors for AM data transmissions, and perform RLC re-establishment.

In at least one embodiment, the PDCP layer 2408 may perform header compression and decompression of IP data, maintain PDCP Sequence Numbers (SNs), perform in-sequence delivery of higher layer PDUs when reconstructing lower layers, eliminate duplication of lower layer SDUs when reconstructing lower layers for radio bearers mapped on RLC AM, encrypt and decrypt control plane data, integrity protect and integrity verify control plane data, discard data based on control timers, and perform security operations (e.g., encrypt, decrypt, integrity protect, integrity verify, etc.).

In at least one embodiment, the primary services and functions of the RRC layer 2410 may include broadcasting of system information (e.g., included in a Master Information Block (MIB) or System Information Block (SIB) related to a non-access stratum (NAS)), broadcasting of system information related to an Access Stratum (AS), paging, establishment, maintenance, and release of RRC connections between a UE and an E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance, and release of point-to-point radio bearers, security functions including key management, inter-Radio Access Technology (RAT) mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, the MIB and SIB may include one or more Information Elements (IEs), each of which may include a separate data field or data structure.

In at least one embodiment, the UE 2202 and the RAN 2216 may utilize a Uu interface (e.g., an LTE-Uu interface) to exchange control plane data via a protocol stack including a PHY layer 2402, a MAC layer 2404, an RLC layer 2406, a PDCP layer 2408, and an RRC layer 2410.

In at least one embodiment, the non-access stratum (NAS) protocol (NAS protocol 2412) forms the highest layer of the control plane between the UE 2202 and the MME 2228. In at least one embodiment, NAS protocol 2412 supports mobility and session management procedures for UE 2202 to establish and maintain an IP connection between UE 2202 and P-GW 2234.

In at least one embodiment, the Si application protocol (Si-AP) layer (Si-AP layer 2424) may support the functionality of the Si interface and include basic procedures (EPs). In at least one embodiment, the EP is an interworking unit between the RAN 2216 and the CN 2228. In at least one embodiment, the S1-AP layer service may include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including, but not limited to: E-UTRAN radio access bearer (E-RAB) management, UE capability indication, mobility, NAS signaling, RAN Information Management (RIM), and configuration transfer.

In at least one embodiment, a Stream Control Transmission Protocol (SCTP) layer (alternatively referred to as a stream control transmission protocol/internet protocol (SCTP/IP) layer) (SCTP layer 2420) may ensure reliable delivery of signaling messages between RAN 2216 and MME 2228 based in part on the IP protocols supported by IP layer 2418. In at least one embodiment, the L2 layer 2416 and the L1 layer 2414 may refer to communication links (e.g., wired or wireless) used by the RAN node and MME to exchange information.

In at least one embodiment, the RAN 2216 and the one or more MMEs 2228 may utilize the S1-MME interface to exchange control plane data via a protocol stack including an L1 layer 2414, an L2 layer 2416, an IP layer 2418, an SCTP layer 2420, and a Si-AP layer 2422.

Fig. 25 is an illustration of a user plane protocol stack in accordance with at least one embodiment. In at least one embodiment, the user plane 2500 is illustrated as a communication protocol stack between the UE 2202, the RAN 2216, the S-GW 2230, and the P-GW 2234. In at least one embodiment, the user plane 2500 may utilize the same protocol layers as the control plane 2400. In at least one embodiment, for example, the UE 2202 and the RAN 2216 may utilize a Uu interface (e.g., an LTE-Uu interface) to exchange user plane data via a protocol stack including a PHY layer 2402, a MAC layer 2404, an RLC layer 2406, a PDCP layer 2408.

In at least one embodiment, a General Packet Radio Service (GPRS) tunneling protocol (GTP-U) layer (GTP-U layer 2504) for the user plane may be used to carry user data within the GPRS core network and between the radio access network and the core network. In at least one embodiment, the user data transmitted may be packets in any of, for example, IPv4, IPv6, or PPP formats. In at least one embodiment, the UDP and IP security (UDP/IP) layer (UDP/IP layer 2502) may provide a checksum of data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication of selected data streams. In at least one embodiment, RAN 2216 and S-GW 2230 may utilize an S1-U interface to exchange user plane data via a protocol stack comprising L1 layer 2414, L2 layer 2416, UDP/IP layer 2502, and GTP-U layer 2504. In at least one embodiment, the S-GW 2230 and the P-GW 2234 may utilize an S5/S8a interface to exchange user plane data via a protocol stack that includes an L1 layer 2414, an L2 layer 2416, a UDP/IP layer 2502, and a GTP-U layer 2504. In at least one embodiment, as discussed above with respect to fig. 24, the NAS protocol supports mobility and session management procedures for the UE 2202 to establish and maintain an IP connection between the UE 2202 and the P-GW 2234.

Fig. 26 illustrates a component 2600 of a core network in accordance with at least one embodiment. In at least one embodiment, the components of the CN 2238 may be implemented in one physical node or in a separate physical node that includes components for reading and executing instructions from a machine-readable medium or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, network Function Virtualization (NFV) is used to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). In at least one embodiment, a logical instantiation of CN 2238 can be referred to as network slice 2602 (e.g., network slice 2602 is shown as including HSS2232, MME 2228, and S-GW 2230). In at least one embodiment, a logical instantiation of a portion of CN 2238 may be referred to as network sub-slice 2604 (e.g., network sub-slice 2604 is shown as including P-GW 2234 and PCRF 2236).

In at least one embodiment, the NFV architecture and infrastructure can be used to virtualize one or more network functions on physical resources including industry standard server hardware, storage hardware, or a combination of switches, which can alternatively be performed by dedicated hardware. In at least one embodiment, the NFV system may be used to perform virtual or reconfigurable implementations of one or more EPC components/functions.

Fig. 27 is a block diagram illustrating components of a system 2700 for supporting Network Function Virtualization (NFV) in accordance with at least one embodiment. In at least one embodiment, system 2700 is shown to include a virtualized infrastructure manager (shown as VIM 2702), a network function virtualized infrastructure (shown as NFVI 2704), a VNF manager (shown as VNFM 2706), a virtualized network function (shown as VNF 2708), an element manager (shown as EM 2710), an NFV coordinator (shown as NFVO 2712), and a network manager (shown as NM 2714).

In at least one embodiment, VIM 2702 manages the resources of NFVI 2704. In at least one embodiment, NFVI 2704 may include physical or virtual resources and applications (including hypervisors) for executing system 2700. In at least one embodiment, VIM 2702 can utilize NFVI 2704 to manage lifecycles of virtual resources (e.g., creation, maintenance, and tear down of Virtual Machines (VMs) associated with one or more physical resources), track VM instances, track performance, failures and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

In at least one embodiment, the VNFM 2706 may manage the VNF 2708. In at least one embodiment, the VNF 2708 may be used to perform EPC components/functions. In at least one embodiment, the VNFM 2706 may manage the life cycle of the VNF 2708 and track performance, faults, and security of the virtual aspects of the VNF 2708. In at least one embodiment, EM 2710 may track performance, faults, and security in the functioning of VNF 2708. In at least one embodiment, tracking data from VNFM 2706 and EM 2710 may include, for example, performance Measurement (PM) data used by VIM 2702 or NFVI 2704. In at least one embodiment, both VNFM 2706 and EM 2710 may scale up/down the number of VNFs of system 2700.

In at least one embodiment, NFVO 2712 can coordinate, authorize, release, and occupy resources of NFVI 2704 in order to provide requested services (e.g., to perform EPC functions, components, or slices). In at least one embodiment, NM 2714 may provide end user function packages responsible for managing networks, which may include network elements with VNFs, non-virtualized network functions, or both (management of VNFs may occur via EM 2710).

Computer-based system

The following figures set forth, but are not limited to, exemplary computer-based systems that can be used to implement at least one embodiment.

Fig. 28 illustrates a processing system 2800 in accordance with at least one embodiment. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808, and may be a single processor desktop system, a multiprocessor workstation system, or a server system with a large number of processors 2802 or processor cores 2807. In at least one embodiment, processing system 2800 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for mobile, handheld, or embedded devices.

In at least one embodiment, processing system 2800 can be included or incorporated in a server-based gaming platform, including a game console, a mobile game console, a handheld game console, or an online game console. In at least one embodiment, processing system 2800 is a mobile phone, smart phone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 2800 can further include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device.

In at least one embodiment, processing system 2800 is a television or set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

In at least one embodiment, the one or more processors 2802 each include one or more processor cores 2807 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2807 is configured to process a particular instruction set 2809. In at least one embodiment, the instruction set 2809 may facilitate Complex Instruction Set Computing (CISC), reduced Instruction Set Computing (RISC), or computing by Very Long Instruction Words (VLIW). In at least one embodiment, multiple processor cores 2807 may each process a different instruction set 2809, which instruction set 2809 may include instructions that help simulate other instruction sets. In at least one embodiment, the processor core 2807 may also include other processing devices, such as a Digital Signal Processor (DSP).

In at least one embodiment, processor 2802 includes a cache memory (cache) 2804. In at least one embodiment, processor 2802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among the various components of processor 2802. In at least one embodiment, the processor 2802 also uses an external cache (e.g., a level three (L3) cache or Last Level Cache (LLC)) (not shown), which may share this logic between the processor cores 2807 using known cache coherency techniques. In at least one embodiment, a register file 2806 is additionally included in processor 2802, and processor 2802 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2806 may include general purpose registers or other registers.

In at least one embodiment, one or more processors 2802 are coupled with one or more interface buses 2810 to transmit communication signals, such as address, data, or control signals, between the processors 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus, in one embodiment. In at least one embodiment, interface bus 2810 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, memory controller 2816 facilitates communication between the memory devices and other components of processing system 2800, while Platform Controller Hub (PCH) 2830 provides connectivity to input/output (I/O) devices through a local I/O bus.

In at least one embodiment, memory device 2820 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or have suitable capabilities to function as a processor memory. In at least one embodiment, a storage device 2820 may be used as a system memory for processing system 2800 to store data 2822 and instructions 2821 for use when one or more processors 2802 execute applications or processes. In at least one embodiment, the memory controller 2816 is also coupled with an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 of the processors 2802 to perform graphics and media operations. In at least one embodiment, a display device 2811 can be connected to the processor 2802. In at least one embodiment, the display device 2811 can include one or more of internal display devices, such as external display devices connected at a mobile electronic device or portable computer device or through a display interface (e.g., display port (DisplayPort), etc.). In at least one embodiment, the display device 2811 may comprise a Head Mounted Display (HMD), such as a stereoscopic display device used in a Virtual Reality (VR) application or an Augmented Reality (AR) application.

In at least one embodiment, the platform controller hub 2830 enables peripheral devices to connect to the storage device 2820 and the processor 2802 through a high speed I/O bus. In at least one embodiment, the I/O peripherals include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, a data storage 2824 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage 2824 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, touch sensor 2825 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2826 may be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2828 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2834 may enable network connections to wired networks. In at least one embodiment, a high performance network controller (not shown) is coupled with interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high definition audio controller. In at least one embodiment, processing system 2800 includes an optional legacy (legacy) I/O controller 2840 for coupling legacy (e.g., personal System 2 (PS/2)) devices to processing system 2800. In at least one embodiment, the platform controller hub 2830 may also be connected to one or more Universal Serial Bus (USB) controllers 2842, which connect input devices such as a keyboard and mouse 2843 combination, a camera 2844, or other USB input devices.

In at least one embodiment, the memory controller 2816 and the platform controller hub 2830 instances may be integrated into a discrete external graphics processor, such as external graphics processor 2812. In at least one embodiment, the platform controller hub 2830 and/or the memory controller 2816 may be external to the one or more processors 2802. For example, in at least one embodiment, processing system 2800 may include an external memory controller 2816 and a platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset in communication with processor 2802.

FIG. 29 illustrates a computer system 2900 in accordance with at least one embodiment. In at least one embodiment, the computer system 2900 may be a system with interconnected devices and components, an SOC, or some combination. In at least one embodiment, the computer system 2900 is formed by a processor 2902, which processor 2902 may include execution units for executing instructions. In at least one embodiment, computer system 2900 may include, but is not limited to, components such as a processor 2902 that employs execution units including logic to perform algorithms for process data. In at least one embodiment, computer system 2900 may include a processor, such as that available from Intel corporation of Santa Clara, calif. (Intel Corporation of Santa Clara, california) Processor family, xeonTM, +.>XScaleTM and/or StrongARMTM, < >>Core ^TM Or->Nervana ^TM Microprocessors, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 2900 may execute a version of the WINDOWS operating system available from microsoft corporation of redmond, washi.e., microsoft Corporation of Redmond, although other operating systems (e.g., UNIX and Linux), embedded software, and/or graphical user interfaces may be used.

In at least one embodiment, the computer system 2900 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, internet protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a SoC, a network computer ("NetPC"), a set-top box, a hub, a wide area network ("WAN") switch, or any other system that may execute one or more instructions in accordance with at least one embodiment.

In at least one embodiment, the computer system 2900 may include, but is not limited to, a processor 2902, which processor 2902 may include, but is not limited to, one or more execution units 2908, which may be configured to execute a compute unified device architecture ("CUDA")Developed by nvidia corporation of santa clara, california). In at least one embodiment, the CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, the computer system 2900 is a single processor desktop or server system. In at least one embodiment, a computer system2900 may be a multiprocessor system. In at least one embodiment, the processor 2902 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, the processor 2902 may be coupled to a processor bus 2910, which processor bus 2910 may transmit data signals between the processor 2902 and other components in the computer system 2900.

In at least one embodiment, the processor 2902 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 2904. In at least one embodiment, the processor 2902 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to the processor 2902. In at least one embodiment, the processor 2902 may include a combination of internal and external caches. In at least one embodiment, register file 2906 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

In at least one embodiment, an execution unit 2908, including but not limited to logic to perform integer and floating point operations, is also located in the processor 2902. The processor 2902 may also include microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 2908 may include logic to process packaged instruction set 2909. In at least one embodiment, by including the packaged instruction set 2909 in the instruction set of the general purpose processor 2902, and associated circuitry to execute instructions, the packaged data in the general purpose processor 2902 may be used to perform operations used by many multimedia applications. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which may not require the transmission of smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

In at least one embodiment, execution unit 2908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 2900 may include, but is not limited to, memory 2920. In at least one embodiment, memory 2920 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 2920 may store instructions 2919 and/or data 2921 represented by data signals that may be executed by processor 2902.

In at least one embodiment, a system logic chip may be coupled to processor bus 2910 and memory 2920. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 2916, and the processor 2902 may communicate with the MCH 2916 via a processor bus 2910. In at least one embodiment, MCH 2916 may provide a high bandwidth memory path 2918 to memory 2920 for instruction and data storage as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2916 may initiate data signals between processor 2902, memory 2920, and other components in computer system 2900, and bridge data signals between processor bus 2910, memory 2920, and system I/O2922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 2916 may be coupled to memory 2920 through a high bandwidth memory path 2918, and graphics/video card 2912 may be coupled to MCH 2916 through an accelerated graphics port (Accelerated Graphics Port) ("AGP") interconnect 2914.

In at least one embodiment, computer system 2900 may use system I/O2922 as a proprietary hub interface bus to couple MCH 2916 to an I/O controller hub ("ICH") 2930. In at least one embodiment, the ICH 2930 may provide a direct connection to certain I/O devices through a local I/O bus. In at least one embodiment, the local I/O bus may include, but is not limited to, a high speed I/O bus for connecting peripheral devices to memory 2920, the chipset, and processor 2902. Examples may include, but are not limited to, an audio controller 2929, a firmware hub ("Flash BIOS") 2928, a wireless transceiver 2926, a data store 2924, a conventional I/O controller 2923 and keyboard interface including user input 2925, a serial expansion port 2977 (e.g., USB), and a network controller 2934. Data storage 2924 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment, FIG. 29 illustrates a system including interconnected hardware devices or "chips". In at least one embodiment, fig. 29 may illustrate an exemplary SoC. In at least one embodiment, the devices shown in fig. 29 may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2900 are interconnected using a computing quick link (CXL) interconnect.

Fig. 30 illustrates a system 3000 in accordance with at least one embodiment. In at least one embodiment, system 3000 is an electronic device that utilizes processor 3010. In at least one embodiment, system 3000 may be, for example, but not limited to, a notebook computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

In at least one embodiment, system 3000 may include a processor 3010 communicatively coupled to any suitable number or variety of components, peripheral devices, modules, or devices. In at least one embodiment, the processor 3010 uses bus or interface coupling, such as I ² C bus, system management bus ("SMBus"), low Pin Count (LPC) bus A serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a USB (version 1, 2, 3), or a universal asynchronous receiver/transmitter ("UART") bus. In at least one embodiment, FIG. 30 illustrates a system that includes interconnected hardware devices or "chips". In at least one embodiment, fig. 30 may illustrate an exemplary SoC. In at least one embodiment, the devices shown in FIG. 30 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of fig. 30 are interconnected using a computing fast link (CXL) interconnect line.

In at least one embodiment, fig. 30 may include a display 3024, a touch screen 3025, a touch pad 3030, a near field communication unit ("NFC") 3045, a sensor hub 3040, a thermal sensor 3046, a fast chipset ("EC") 3035, a trusted platform module ("TPM") 3038, a BIOS/firmware/Flash ("BIOS, FW Flash") 3022, a DSP 3060, a solid state disk ("SSD") or hard disk drive ("HDD") 3020, a wireless local area network unit ("WLAN") 3050, a bluetooth unit 3052, a wireless wide area network unit ("WWAN") 3056, a Global Positioning System (GPS) 3055, a camera ("USB 3.0 camera") 3054 (e.g., a USB 3.0 camera), or a low power double data rate ("LPDDR") memory unit ("LPDDR 3") 3015 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to the processor 3010 via the components discussed above. In at least one embodiment, an accelerometer 3041, an ambient light sensor ("ALS") 3042, a compass 3043, and a gyroscope 3044 may be communicatively coupled to the sensor hub 3040. In at least one embodiment, the thermal sensor 3039, the fan 3037, the keyboard 3046, and the touch pad 3030 can be communicatively coupled to the EC 3035. In at least one embodiment, a speaker 3063, an earphone 3064, and a microphone ("mic") 3065 may be communicatively coupled to an audio unit ("audio codec and class D amplifier") 3064, which in turn may be communicatively coupled to the DSP 3060. In at least one embodiment, audio unit 3064 may include, for example, but not limited to, an audio encoder/decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 3057 can be communicatively coupled to the WWAN unit 3056. In at least one embodiment, components such as WLAN unit 3050 and bluetooth unit 3052 and WWAN unit 3056 may be implemented as Next Generation Form Factor (NGFF).

Fig. 31 illustrates an example integrated circuit 3100 in accordance with at least one embodiment. In at least one embodiment, the example integrated circuit 3100 is a SoC that can be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 3100 includes one or more application processors 3105 (e.g., CPUs), at least one graphics processor 3110, and may additionally include image processor 3115 and/or video processor 3120, any of which may be modular IP cores. In at least one embodiment, integrated circuit 3100 includes peripheral or bus logic comprising USB controller 3125, UART controller 3130, SPI/SDIO controller 3135, and I ² S/I ² C controller 3140. In at least one embodiment, the integrated circuit 3100 can include a display device 3145 coupled to one or more of a high-definition multimedia interface (HDMI) controller 3150 and a Mobile Industrial Processor Interface (MIPI) display interface 3155. In at least one embodiment, storage may be provided by flash subsystem 3160, including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via the memory controller 3165 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits further include an embedded security engine 3170.

Fig. 32 illustrates a computing system 3200 in accordance with at least one embodiment. In at least one embodiment, the computing system 3200 includes a processing subsystem 3201 having one or more processors 3202 and a system memory 3204 that communicate via an interconnection path that may include a memory hub 3205. In at least one embodiment, the memory hub 3205 may be a separate component within the chipset component or may be integrated within one or more processors 3202. In at least one embodiment, the memory hub 3205 is coupled to the I/O subsystem 3211 by a communication link 3206. In at least one embodiment, the I/O subsystem 3211 includes an I/O hub 3207, which may enable the computing system 3200 to receive input from one or more input devices 3208. In at least one embodiment, the I/O hub 3207 may enable a display controller, which is included in the one or more processors 3202, for providing output to the one or more display devices 3210A. In at least one embodiment, the one or more display devices 3210A coupled to the I/O hub 3207 may include a local, internal, or embedded display device.

In at least one embodiment, the processing subsystem 3201 includes one or more parallel processors 3212 coupled to a memory hub 3205 via a bus or other communication link 3213. In at least one embodiment, the communication link 3213 may be one of a number of standards-based communication link technologies or protocols, such as, but not limited to PCIe, or may be a communication interface or communication fabric for the vendor. In at least one embodiment, one or more parallel processors 3212 form a computationally intensive parallel or vector processing system that may include a large number of processing cores and/or processing clusters, such as Multiple Integrated Core (MIC) processors. In at least one embodiment, one or more parallel processors 3212 form a graphics processing subsystem that may output pixels to one of one or more display devices 3210A coupled via an I/O hub 3207. In at least one embodiment, the one or more parallel processors 3212 may also include a display controller and a display interface (not shown) to enable direct connection to the one or more display devices 3210B.

In at least one embodiment, the system memory unit 3214 may be connected to the I/O hub 3207 to provide a storage mechanism for the computing system 3200. In at least one embodiment, the I/O switch 3216 may be used to provide an interface mechanism to enable connections between the I/O hub 3207 and other components, such as network adapter 3218 and/or wireless network adapter 3219, which may be integrated into a platform, and various other devices that may be added by one or more additional devices 3220. In at least one embodiment, the network adapter 3218 may be an ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 3219 may include one or more of Wi-Fi, bluetooth, NFC, or other network devices including one or more radios.

In at least one embodiment, the computing system 3200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and/or variations thereof, as well as to the I/O hub 3207. In at least one embodiment, the communication paths interconnecting the various components in FIG. 32 may be implemented using any suitable protocol, such as PCI (peripheral component interconnect) based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and/or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

In at least one embodiment, the one or more parallel processors 3212 include circuitry optimized for graphics and video processing (e.g., including video output circuitry) and constitute a Graphics Processing Unit (GPU). In at least one embodiment, one or more of the parallel processors 3212 includes circuitry optimized for general purpose processing. In at least one embodiment, components of computing system 3200 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more of the parallel processor 3212, the memory hub 3205, the processor 3202, and the I/O hub 3207 may be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, components of computing system 3200 may be integrated into a single package to form a System In Package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 3200 may be integrated into a multi-chip module (MCM) that may be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, the I/O subsystem 3211 and display device 3210B are omitted from the computing system 3200.

Processing system

The following figures illustrate exemplary processing systems that may be used to implement at least one embodiment.

FIG. 33 illustrates an acceleration processing unit ("APU") 3300 in accordance with at least one embodiment. In at least one embodiment, APU 3300 is developed by AMD corporation of Santa Clara, calif. In at least one embodiment, the APU 3300 can be configured to execute an application, such as a CUDA program. In at least one embodiment, APU 3300 includes, but is not limited to, a core complex 3310, a graphics complex 3340, a fabric 3360, an I/O interface 3370, a memory controller 3380, a display controller 3392, and a multimedia engine 3394. In at least one embodiment, APU 3300 can comprise any combination of, but is not limited to, any number of core complexes 3310, any number of graphics complexes 3340, any number of display controllers 3392, and any number of multimedia engines 3394. For purposes of illustration, a number of instances of a similar object are denoted herein by reference numerals, where the reference numerals identify the object and the numerals in brackets identify the desired instance.

In at least one embodiment, core complex 3310 is a CPU, graphics complex 3340 is a GPU, and APU 3300 is a processing unit that is not limited to 3310 and 3340 being integrated onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 3310, while other tasks may be assigned to graphics complex 3340. In at least one embodiment, the core complex 3310 is configured to execute main control software, such as an operating system, associated with the APU 3300. In at least one embodiment, the core complex 3310 is the main processor of the APU 3300 that controls and coordinates the operation of the other processors. In at least one embodiment, core complex 3310 issues commands that control the operation of graphics complex 3340. In at least one embodiment, core complex 3310 may be configured to execute host executable code derived from CUDA source code and graphics complex 3340 may be configured to execute device executable code derived from CUDA source code.

In at least one embodiment, core complex 3310 includes, but is not limited to, cores 3320 (1) -3320 (4) and an L3 cache 3330. In at least one embodiment, core complex 3310 may include, but is not limited to, any combination of any number of cores 3320 and any number and type of caches. In at least one embodiment, core 3320 is configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 3320 is a CPU core.

In at least one embodiment, each core 3320 includes, but is not limited to, a fetch/decode unit 3322, an integer execution engine 3324, a floating point execution engine 3326, and an L2 cache 3328. In at least one embodiment, the fetch/decode unit 3322 fetches instructions, decodes the instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 3324 and the floating point execution engine 3326. In at least one embodiment, the fetch/decode unit 3322 may dispatch one micro instruction to the integer execution engine 3324 and another micro instruction to the floating point execution engine 3326 simultaneously. In at least one embodiment, integer execution engine 3324 performs operations not limited to integer and memory operations. In at least one embodiment, the floating point engine 3326 performs operations not limited to floating point and vector operations. In at least one embodiment, the fetch-decode unit 3322 assigns micro-instructions to a single execution engine that replaces both the integer execution engine 3324 and the floating point execution engine 3326.

In at least one embodiment, each core 3320 (i) may access an L2 cache 3328 (i) included in the core 3320 (i), where i is an integer representing a particular instance of the core 3320. In at least one embodiment, each core 3320 included in core complex 3310 (j) is connected to other cores 3320 included in core complex 3310 (j) via an L3 cache 3330 (j) included in core complex 3310 (j), where j is an integer representing a particular instance of core complex 3310. In at least one embodiment, the core 3320 included in the core complex 3310 (j) may access all L3 caches 3330 (j) included in the core complex 3310 (j), where j is an integer representing a particular instance of the core complex 3310. In at least one embodiment, the L3 cache 3330 may include, but is not limited to, any number of slices.

In at least one embodiment, the graphics complex 3340 may be configured to perform computing operations in a highly parallel manner. In at least one embodiment, the graphics complex 3340 is configured to perform graphics pipeline operations such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering images to a display. In at least one embodiment, the graphics complex 3340 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 3340 is configured to perform graphics-related operations and graphics-independent operations.

In at least one embodiment, the graphics complex 3340 includes, but is not limited to, any number of computing units 3350 and L2 caches 3342. In at least one embodiment, the computing units 3350 share an L2 cache 3342. In at least one embodiment, the L2 cache 3342 is partitioned. In at least one embodiment, the graphics complex 3340 includes, but is not limited to, any number of computing units 3350 and any number (including zero) and type of caches. In at least one embodiment, the graphics complex 3340 includes, but is not limited to, any number of specialized graphics hardware.

In at least one embodiment, each computing unit 3350 includes, but is not limited to, any number of SIMD units 3352 and shared memory 3354. In at least one embodiment, each SIMD unit 3352 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 3350 may execute any number of thread blocks, but each thread block executes on a single compute unit 3350. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, the workgroup is a thread block. In at least one embodiment, each SIMD unit 3352 executes a different thread bundle (warp). In at least one embodiment, the thread bundle is a set of threads (e.g., 16 threads), where each thread in the thread bundle belongs to a single thread block and is configured to process different sets of data based on a single instruction set. In at least one embodiment, prediction (prediction) may be used to disable one or more threads in a thread bundle. In at least one embodiment, the channel is a thread. In at least one embodiment, the work items are threads. In at least one embodiment, the wavefront is a thread bundle. In at least one embodiment, the different wave fronts in the thread blocks can be synchronized together and communicated via shared memory 3354.

In at least one embodiment, the architecture 3360 is a system interconnect that facilitates data and control transfer across the core complex 3310, the graphics complex 3340, the I/O interface 3370, the memory controller 3380, the display controller 3392, and the multimedia engine 3394. In at least one embodiment, the APU 3300 can include, in addition to, or in lieu of, the structure 3360, any number and type of system interconnections, such structure 3360 facilitating the transfer of data and control across any number and type of directly or indirectly linked components that can be internal or external to the APU 3300. In at least one embodiment, I/O interface 3370 represents any number and type of I/O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, gigabit Ethernet ("GBE"), USB, and the like). In at least one embodiment, various types of peripheral devices are coupled to I/O interface 3370. In at least one embodiment, peripheral devices coupled to I/O interface 3370 may include, but are not limited to, a keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, and the like.

In at least one embodiment, the display controller AMD92 displays images on one or more display devices, such as a Liquid Crystal Display (LCD) device. In at least one embodiment, the multimedia engine 3394 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, the memory controller 3380 facilitates data transfer between the APU 3300 and the unified system memory 3390. In at least one embodiment, core complex 3310 and graphics complex 3340 share unified system memory 3390.

In at least one embodiment, the APU 3300 implements a variety of memory subsystems including, but not limited to, any number and type of memory controllers 3380 and memory devices (e.g., shared memory 3354) that may be dedicated to one component or shared among multiple components. And (3) an assembly. In at least one embodiment, APU 3300 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3428, L3 cache 3330, and L2 cache 3342), each of which may be component private or shared among any number of components (e.g., core 3320, core complex 3310, SIMD unit 3352, computing unit 3350, and graphics complex 3340).

Fig. 34 shows a CPU 3400 according to at least one embodiment. In at least one embodiment, CPU 3400 is developed by AMD corporation of Santa Clara, calif. In at least one embodiment, the CPU 3400 may be configured to execute an application program. In at least one embodiment, the CPU 3400 is configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 3400 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 3400 may be configured to execute host executable code derived from CUDA source code, and the external GPU may be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 3400 includes, but is not limited to, any number of core complexes 3410, fabric 3460, I/O interfaces 3470, and memory controllers 3480.

In at least one embodiment, core complex 3410 includes, but is not limited to, cores 3420 (1) -3420 (4) and L3 cache 3430. In at least one embodiment, core complex 3410 may include, but is not limited to, any number of cores 3420 and any combination of any number and type of caches. In at least one embodiment, core 3420 is configured to execute instructions of a particular ISA. In at least one embodiment, each core 3420 is a CPU core.

In at least one embodiment, each core 3420 includes, but is not limited to, a fetch/decode unit 3422, an integer execution engine 3424, a floating point execution engine 3426, and an L2 cache 3428. In at least one embodiment, the fetch/decode unit 3422 fetches instructions, decodes the instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 3424 and the floating point execution engine 3426. In at least one embodiment, the fetch/decode unit 3422 may dispatch one micro instruction to the integer execution engine 3424 and another micro instruction to the floating point execution engine 3426 simultaneously. In at least one embodiment, the integer execution engine 3424 performs operations that are not limited to integer and memory operations. In at least one embodiment, the floating point engine 3426 performs operations that are not limited to floating point and vector operations. In at least one embodiment, the fetch-decode unit 3422 assigns the microinstructions to a single execution engine that replaces both the integer execution engine 3424 and the floating point execution engine 3426.

In at least one embodiment, each core 3420 (i) can access an L2 cache 3428 (i) included in the core 3420 (i), where i is an integer representing a particular instance of the core 3420. In at least one embodiment, each core 3420 included in core complex 3410 (j) is connected to other cores 3420 in core complex 3410 (j) via an L3 cache 3430 (j) included in core complex 3410 (j), where j is an integer representing a particular instance of core complex 3410. In at least one embodiment, the cores 3420 included in the core complex 3410 (j) may access all L3 caches 3430 (j) included in the core complex 3410 (j), where j is an integer representing a particular instance of the core complex 3410. In at least one embodiment, the L3 cache 3430 may include, but is not limited to, any number of slices.

In at least one embodiment, fabric 3460 is a system interconnect that facilitates data and control transfer across core complexes 3410 (1) -3410 (N) (where N is an integer greater than zero), I/O interface 3470, and memory controller 3480. In at least one embodiment, the CPU 3400 may also include, but is not limited to, any number and type of system interconnects in addition to the structure 3460 or in lieu of the structure 3460, the structure 3460 facilitating data and control transfer across any number and type of directly or indirectly linked components that may be internal or external to the CPU 3400. In at least one embodiment, I/O interface 3470 represents any number and type of I/O interfaces (e.g., PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interface 3470. In at least one embodiment, the peripheral devices coupled to the I/O interface 3470 can include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

In at least one embodiment, the memory controller 3480 facilitates data transfer between the CPU 3400 and the system memory 3490. In at least one embodiment, core complex 3410 and graphics complex 3440 share system memory 3490. In at least one embodiment, the CPU 3400 implements a memory subsystem including, but not limited to, any number and type of memory controllers 3480 and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, the CPU 3400 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., an L2 cache 3428 and an L3 cache 3430), each of which may be component private or shared among any number of components (e.g., core 3420 and core complex 3410).

FIG. 35 illustrates an exemplary accelerator integrated slice 3590 in accordance with at least one embodiment. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of a plurality of graphics processing engines of a plurality of graphics acceleration modules. The graphics processing engines may each include a separate GPU. Alternatively, the graphics processing engine may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., video encoder/decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engine may be a respective GPU integrated on a generic package, line card, or chip.

The application effective address space 3582 within the system memory 3514 stores process elements 3583. In one embodiment, the process element 3583 is stored in response to a GPU call 3581 from an application 3580 executing on the processor 3507. The process element 3583 includes the processing state of the corresponding application 3580. The Work Descriptor (WD) 3584 included in the process element 3583 may be a single job requested by an application or may include a pointer to a job queue. In at least one embodiment, WD 3584 is a pointer to a job request queue in application effective address space 3582.

The graphics acceleration module 3546 and/or individual graphics processing engines can be shared by all or a portion of the processes in the system. In at least one embodiment, an infrastructure for establishing processing states and sending WD 3584 to graphics acceleration module 3546 to begin jobs in a virtualized environment may be included.

In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 3546 or an individual graphics processing engine. Since the graphics acceleration module 3546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition and the operating system initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 3546 is assigned.

In operation, the WD obtain unit 3591 in the accelerator integrated slice 3590 obtains a next WD 3584, including an indication of work to be done by one or more graphics processing engines of the graphics acceleration module 3546. Data from WD 3584 may be stored in registers 3545 for use by Memory Management Unit (MMU) 3539, interrupt management circuit 3547, and/or context management circuit 3548, as shown. For example, one embodiment of the MMU 3539 includes segment/page roaming circuitry for accessing segment/page tables 3586 within the OS virtual address space 3585. The interrupt management circuit 3547 may process interrupt events (INT) 3592 received from the graphics acceleration module 3546. When performing the graphics operation, the effective address 3593 generated by the graphics processing engine is translated into a real address by the MMU 3539.

In one embodiment, the same register set 3545 is replicated for each graphics processing engine and/or graphics acceleration module 3546 and may be initialized by a hypervisor or operating system. Each of these replicated registers may be included in accelerator integrated slice 3590. An exemplary register that may be initialized by the hypervisor is shown in Table 1.

TABLE 1 registers for hypervisor initialization

1	Slice control register
		2	Real Address (RA) planned processing region pointer
3	Authorization mask override register
		4	Interrupt vector table input offset
5	Interrupt vector table entry restriction
		6	Status register
7	Logical partition ID
		8	Real Address (RA) hypervisor accelerator utilization record pointer
9	Storage description register

An exemplary register that may be initialized by the operating system is shown in Table 2.

TABLE 2 operating System initialization registers

In one embodiment, each WD 3584 is specific to a particular graphics acceleration module 3546 and/or a particular graphics processing engine. It includes all the information that the graphics processing engine needs to do the job or work, or it may be a pointer to a memory location where the application program establishes a command queue for the work to be done.

36A-36B illustrate an exemplary graphics processor in accordance with at least one embodiment herein. In at least one embodiment, any of the exemplary graphics processors may be manufactured using one or more IP cores. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores. In at least one embodiment, an exemplary graphics processor is used within a SoC.

Fig. 36A illustrates an exemplary graphics processor 3610 of an SoC integrated circuit, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Fig. 36B illustrates an additional exemplary graphics processor 3640 of an SoC integrated circuit, which can be fabricated using one or more IP cores in accordance with at least one embodiment. In at least one embodiment, graphics processor 3610 of FIG. 36A is a low power graphics processor core. In at least one embodiment, graphics processor 3640 of FIG. 36B is a higher performance graphics processor core. In at least one embodiment, each graphics processor 3610, 3640 may be a variation of graphics processor 1210 of FIG. 12.

In at least one embodiment, graphics processor 3610 includes vertex processor 3605 and one or more fragment processors 3615A-3615N (e.g., 3615A, 3615B, 3615C, 3615D-3615N-1 and 3615N). In at least one embodiment, graphics processor 3610 may execute different shader programs via separate logic such that vertex processor 3605 is optimized to perform operations for vertex shader programs, while one or more fragment processors 3615A-3615N perform fragment (e.g., pixel) shading operations for fragment or pixel or shader programs. In at least one embodiment, vertex processor 3605 performs the vertex processing stages of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processors 3615A-3615N use primitives and vertex data generated by vertex processor 3605 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 3615A-3615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in Direct 3 DAPI.

In at least one embodiment, graphics processor 3610 additionally includes one or more MMUs 3620A-3620B, caches 3625A-3625B, and circuit interconnects 3630A-3630B.

In at least one embodiment, one or more MMUs 3620A-3620B provide a mapping of virtual to physical addresses for graphics processor 3610, including for vertex processor 3605 and/or fragment processors 3615A-3615N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more caches 3625A-3625B. In at least one embodiment, one or more of the MMUs 3620A-3620B can be synchronized with other MMUs within the system, including one or more of the MMUs associated with one or more of the application processors 1205, image processors 1215, and/or video processors 1220 of FIG. 12, such that each of the processors 1205-1220 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3630A-3630B enable graphics processor 3610 to connect with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

In at least one embodiment, graphics processor 3640 includes one or more MMUs 3620A-3620B, caches 3625A-3625B, and circuit interconnects 3630A-3630B of graphics processor 3610 of FIG. 36A. In at least one embodiment, graphics processor 3640 includes one or more shader cores 3655A-3655N (e.g., 3655A, 3655B, 3655C, 3655D, 3655E, 3655F, through 3655N-1, and 3655N) that provide a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, the plurality of shader cores may vary. In at least one embodiment, the graphics processor 3640 includes an inter-core task manager 3645 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3655A-3655N and a partitioning unit 3658 to accelerate tile-based rendering partitioning operations, where rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize use of internal caches.

Fig. 37A illustrates a graphics core 3700 in accordance with at least one embodiment. In at least one embodiment, graphics core 3700 may be included within graphics processor 3110 of fig. 31. In at least one embodiment, graphics core 3700 can be unified shader cores 3655A-3655N in FIG. 36B. In at least one embodiment, graphics core 3700 includes shared instruction cache 3702, texture unit 3718, and cache/shared memory 3720, which are common to execution resources within graphics core 3700. In at least one embodiment, graphics core 3700 may include multiple slices (slices) 3701A-3701N or partitions of each core, and a graphics processor may include multiple instances of graphics core 3700. Slices 3701A-3701N may include support logic including local instruction caches 3704A-3704N, thread schedulers 3706A-3706N, thread dispatchers 3708A-3708N, and a set of registers 3710A-3710N. In at least one embodiment, slices 3701A-3701N may include a set of Additional Functional Units (AFUs) 3712A-3712N, floating Point Units (FPUs) 3714A-3714N, integer Arithmetic Logic Units (ALUs) 3716A-3716N, address Calculation Units (ACUs) 3713A-3713N, double Precision Floating Point Units (DPFPUs) 3715A-3715N, and Matrix Processing Units (MPUs) 3717A-3717N.

In one embodiment, the FPUs 3714A-3714N may perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 3715A-3715N may perform double-precision (64-bit) floating-point operations. In at least one embodiment, ALUs 3716A-3716N may perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision, and may be configured for mixed precision operations. In at least one embodiment, MPUs 3717A-3717N may also be configured for mixed precision matrix operations, including half-precision floating point operations and 8-bit integer operations. In at least one embodiment, MPUs 3717A-3717N can perform various matrix operations to accelerate the CUDA program, including enabling support for accelerated generic matrix-to-matrix multiplication (GEMM). In at least one embodiment, AFUs 3712A-3712N can perform additional logical operations that are not supported by floating point numbers or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

Fig. 37B illustrates a General Purpose Graphics Processing Unit (GPGPU) 3730 in at least one embodiment. In at least one embodiment, GPGPU 3730 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 3730 may be configured to enable highly parallel computing operations to be performed by a GPU array. In at least one embodiment, GPGPU 3730 can be directly linked to other instances of GPGPU 3730 to create a multi-GPU cluster to increase execution time for the CUDA program. In at least one embodiment, GPGPU 3730 includes a host interface 3732 to enable connections to a host processor. In at least one embodiment, host interface 3732 is a PCIe interface. In at least one embodiment, host interface 3732 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, GPGPU 3730 receives commands from a host processor and dispatches execution threads associated with those commands to a set of compute clusters 3736A-3736H using global scheduler 3734. In at least one embodiment, compute clusters 3736A-3736H share cache memory 3738. In at least one embodiment, cache memory 3738 may be used as a higher level cache for cache memory within computing clusters 3736A-3736H.

In at least one embodiment, GPGPU 3730 includes memories 3744A-3744B coupled to computing clusters 3736A-3736H via a set of memory controllers 3742A-3742B. In at least one embodiment, memories 3744A-3744B may include various types of memory devices including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory.

In at least one embodiment, the compute clusters 3736A-3736H each include a set of graphics cores, such as graphics core 3700 of FIG. 37A, which may include multiple types of integer and floating point logic units, and may perform compute operations with various accuracies, including computations suitable for association with a CUDA program. For example, in at least one embodiment, at least a subset of the floating point units in each of the compute clusters 3736A-3736H may be configured to perform 16-bit or 32-bit floating point operations, while a subset of the different floating point units may be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU 3730 may be configured to operate as a compute cluster. In at least one embodiment, the computing clusters 3736A-3736H may implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3730 communicate through host interface 3732. In at least one embodiment, GPGPU 3730 includes an I/O hub 3739 that couples GPGPU 3730 to GPU link 3740 so that it can be directly connected to other instances of GPGPU 3730. In at least one embodiment, GPU link 3740 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 3730. In at least one embodiment, GPU link 3740 is coupled with a high speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3730 reside in separate data processing systems and communicate via a network device accessible via host interface 3732. In at least one embodiment, GPU link 3740 may be configured to be capable of connecting to a host processor, in addition to or in lieu of host interface 3732. In at least one embodiment, GPGPU 3730 can be configured to execute a CUDA program.

Fig. 38A illustrates a parallel processor 3800 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 3800 can be implemented using one or more integrated circuit devices, such as a programmable processor, an Application Specific Integrated Circuit (ASIC), or an FPGA.

In at least one embodiment, the parallel processor 3800 includes a parallel processing unit 3802. In at least one embodiment, the parallel processing unit 3802 includes an I/O unit 3804 that enables communication with other devices, including other instances of the parallel processing unit 3802. In at least one embodiment, the I/O unit 3804 may be directly connected to other devices. In at least one embodiment, the I/O unit 3804 connects with other devices using a hub or switch interface (e.g., the memory hub 1305). In at least one embodiment, the connection between the memory hub 1305 and the I/O unit 3804 forms a communication link. In at least one embodiment, the I/O unit 3804 is connected to the host interface 3806 and the memory crossbar 3816, wherein the host interface 3806 receives commands for performing processing operations and the memory crossbar 3816 receives commands for performing memory operations.

In at least one embodiment, when the host interface 3806 receives command buffers via the I/O unit 3804, the host interface 3806 can direct work operations to execute those commands to the front end 3808. In at least one embodiment, the front end 3808 is coupled to a scheduler 3810, the scheduler 3810 being configured to assign commands or other work items to the processing array 3812. In at least one embodiment, scheduler 3810 ensures that processing array 3812 is properly configured and in an active state prior to assigning tasks to processing arrays 3812 in processing array 3812. In at least one embodiment, scheduler 3810 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 3810 may be configured to perform complex scheduling and work allocation operations at coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on the processing array 3812. In at least one embodiment, host software may prove a workload for scheduling on processing array 3812 by one of a plurality of graphics processing doorbell. In at least one embodiment, the workload may then be automatically distributed on the processing array 3812 by scheduler 3810 logic within a microcontroller that includes the scheduler 3810.

In at least one embodiment, processing array 3812 may include up to "N" processing clusters (e.g., clusters 3814A, clusters 3814B through 3814N). In at least one embodiment, each cluster 3814A-3814N of the processing array 3812 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 3810 may assign work to clusters 3814A-3814N of the processing array 3812 using various scheduling and/or work assignment algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be dynamically processed by scheduler 3810 or may be aided in part by compiler logic during compilation of program logic configured to be executed by processing array 3812. In at least one embodiment, different clusters 3814A-3814N of processing array 3812 may be allocated for processing different types of programs or for performing different types of computations.

In at least one embodiment, processing array 3812 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3812 is configured to perform general parallel computing operations. For example, in at least one embodiment, processing array 3812 may include logic to perform processing tasks including filtering video and/or audio data, performing modeling operations, including physical operations, and performing data transformations.

In at least one embodiment, processing array 3812 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 3812 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 3812 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 3802 may transfer data from the system memory for processing via the I/O unit 3804. In at least one embodiment, during processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 3822) during processing and then written back to system memory.

In at least one embodiment, when the parallel processing unit 3802 is used to perform graphics processing, the scheduler 3810 may be configured to divide the processing workload into approximately equal sized tasks to better allocate graphics processing operations to the multiple clusters 3814A-3814N of the processing array 3812. In at least one embodiment, portions of processing array 3812 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 3814A-3814N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 3814A-3814N for further processing.

In at least one embodiment, the processing array 3812 can receive processing tasks to be performed via a scheduler 3810, the scheduler 3810 receiving commands defining the processing tasks from the front end 3808. In at least one embodiment, the processing tasks may include an index of data to be processed, which may include, for example, surface (patch) data, raw data, vertex data, and/or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program is to be executed). In at least one embodiment, the scheduler 3810 may be configured to obtain an index corresponding to a task or may receive an index from the front end 3808. In at least one embodiment, the front end 3808 can be configured to ensure that the processing array 3812 is configured to a valid state prior to launching a workload specified by an incoming command buffer (e.g., batch-buffer, push buffer, etc.).

In at least one embodiment, each of the one or more instances of the parallel processing unit 3802 may be coupled with a parallel processor memory 3822. In at least one embodiment, parallel processor memory 3822 may be accessed via memory crossbar 3816, which memory crossbar 3816 may receive memory requests from processing array 3812 and I/O unit 3804. In at least one embodiment, the parallel processor memory 3822 is accessible to the memory crossbar 3816 via the memory interface 3818. In at least one embodiment, memory interface 3818 may include a plurality of partition units (e.g., partition unit 3820A, partition unit 3820B to partition unit 3820N), which may each be coupled to a portion of parallel processor memory 3822 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 3820A-3820N are configured to be equal to the number of memory units such that a first partition unit 3820A has a corresponding first memory unit 3824A, a second partition unit 3820B has a corresponding memory unit 3824B, and an nth partition unit 3820N has a corresponding nth memory unit 3824N. In at least one embodiment, the number of partitioning units 3820A-3820N may not be equal to the number of memory devices.

In at least one embodiment, memory cells 3824A-3824N may include various types of memory devices including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory. In at least one embodiment, memory cells 3824A-3824N may also include 3D stacked memory, including but not limited to High Bandwidth Memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory units 3824A-3824N, allowing partition units 3820A-3820N to write portions of each rendering target in parallel to efficiently use the available bandwidth of parallel processor memory 3822. In at least one embodiment, local instances of parallel processor memory 3822 may be eliminated to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

In at least one embodiment, any of clusters 3814A-3814N of processing array 3812 may process data to be written to any of memory cells 3824A-3824N within parallel processor memory 3822. In at least one embodiment, the memory crossbar 3816 may be configured to transmit the output of each cluster 3814A-3814N to any partition unit 3820A-3820N or another cluster 3814A-3814N, and the clusters 3814A-3814N may perform other processing operations on the output. In at least one embodiment, each cluster 3814A-3814N may communicate with a memory interface 3818 through a memory crossbar 3816 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 3816 has a connection to memory interface 3818 to communicate with I/O unit 3804 and a connection to a local instance of parallel processor memory 3822 to enable processing units within different processing clusters 3814A-3814N to communicate with system memory or other memory that is not local to parallel processing unit 3802. In at least one embodiment, memory crossbar 3816 may use virtual channels to split traffic between clusters 3814A-3814N and partition units 3820A-3820N.

In at least one embodiment, multiple instances of the parallel processing unit 3802 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 3802 may be configured to interoperate, even though the different instances have different numbers of processing cores, different numbers of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 3802 may include a higher precision floating point unit relative to other instances. In at least one embodiment, a system incorporating one or more instances of the parallel processing unit 3802 or the parallel processor 3800 may be implemented in a variety of configurations and form factors, including, but not limited to, a desktop, laptop or handheld personal computer, a server, a workstation, a gaming machine, and/or an embedded system.

Fig. 38B illustrates a processing cluster 3894 in accordance with at least one embodiment. In at least one embodiment, the processing clusters 3894 are included within parallel processing units. In at least one embodiment, the processing cluster 3894 is one of the processing clusters 3814A-3814N of FIG. 38. In at least one embodiment, the processing clusters 3894 may be configured to execute a number of threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single Instruction Multithreading (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 3894.

In at least one embodiment, the operation of the processing clusters 3894 may be controlled by a pipeline manager 3832 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 3832 receives instructions from the scheduler 38310 of FIG. 38, and manages execution of these instructions through the graphics multiprocessor 3834 and/or texture unit 3836. In at least one embodiment, graphics multiprocessor 3834 is an illustrative example of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within processing cluster 3894. In at least one embodiment, one or more instances of a graphics multiprocessor 3834 may be included within the processing cluster 3894. In at least one embodiment, graphics multiprocessor 3834 may process data, and data crossbar 3840 may be used to distribute the processed data to one of a number of possible purposes, including other shader units. In at least one embodiment, the pipeline manager 3832 may facilitate distribution of the processed data by specifying a destination of the processed data to be distributed via the data crossbar 3840.

In at least one embodiment, each graphics multiprocessor 3834 within the processing cluster 3894 may include the same set of function execution logic (e.g., arithmetic logic units, load Store Units (LSUs), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined fashion, where a new instruction may be issued before a previous instruction completes. In at least one embodiment, the function execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, boolean operations, shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

In at least one embodiment, instructions transferred to the processing clusters 3894 constitute threads. In at least one embodiment, the set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes programs on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within the graphics multiprocessor 3834. In at least one embodiment, the thread group may include fewer threads than the plurality of processing engines within the graphics multiprocessor 3834. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the plurality of processing engines within the graphics multiprocessor 3834. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 3834, processing may be performed in successive clock cycles. In at least one embodiment, multiple thread groups may be concurrently executing on the graphics multiprocessor 3834.

In at least one embodiment, graphics multiprocessor 3834 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 3834 may discard internal caches and use cache memory (e.g., L1 cache 3848) within processing cluster 3894. In at least one embodiment, each graphics multiprocessor 3834 may also access an L2 cache within partition units (e.g., partition units 3820A-3820N of FIG. 38A), which are shared among all processing clusters 3894 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3834 may also access off-chip global memory, which may include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to the parallel processing unit 3802 may be used as global memory. In at least one embodiment, processing clusters 3894 include multiple instances of graphics multiprocessor 3834, which may share common instructions and data that may be stored in L1 cache 3848.

In at least one embodiment, each processing cluster 3894 can include an MMU 3845 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 3845 may reside within memory interface 3818 of fig. 38. In at least one embodiment, the MMU 3845 includes a set of Page Table Entries (PTEs) for mapping virtual addresses to physical addresses of tiles (talking about more information about tiles) and optionally to cache line indexes. In at least one embodiment, the MMU 3845 may include an address translation look-aside buffer (TLB) or may reside in the graphics multiprocessor 3834 or in the L1 cache 3848 or in the processing cluster 3894. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or miss.

In at least one embodiment, the processing clusters 3834 may be configured such that each graphics multiprocessor 3834 is coupled to a texture unit 3836 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 3834, and fetched from an L2 cache, local parallel processor memory, or system memory, as desired. In at least one embodiment, each graphics multiprocessor 3834 outputs processed tasks to a data crossbar 3840 to provide the processed tasks to another processing cluster 3894 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 3816. In at least one embodiment, a pre-raster operations unit (preROP) 3842 is configured to receive data from graphics multiprocessor 3834, direct the data to an ROP unit, which may be located with the partition units described herein (e.g., partition units 3820A-3820N of FIG. 38). In at least one embodiment, the PreROP 3842 unit may perform optimization for color blending, organize pixel color data, and perform address translation.

Fig. 38C illustrates a graphics multiprocessor 3896 in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor 3896 is graphics multiprocessor 3834 of fig. 38B. In at least one embodiment, graphics multiprocessor 3896 is coupled with a pipeline manager 3832 of processing clusters 3834. In at least one embodiment, graphics multiprocessor 3896 has an execution pipeline including, but not limited to, an instruction cache 3852, an instruction unit 3854, an address mapping unit 3856, a register file 3858, one or more GPGPU cores 3862, and one or more LSUs 3866.GPGPU core 3862 and LSU 3866 are coupled with cache memory 3872 and shared memory 3870 via memory and cache interconnect 3868.

In at least one embodiment, the instruction cache 3832 receives a stream of instructions to be executed from the pipeline manager 3832. In at least one embodiment, instructions are cached in instruction cache 3852 and dispatched for execution by instruction unit 3854. In one embodiment, the instruction unit 3854 may dispatch instructions as a thread group (e.g., a thread bundle), each thread of the thread group being assigned to a different execution unit within the GPGPU core 3862. In at least one embodiment, an instruction may access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 3856 may be used to translate addresses in a unified address space into different memory addresses that may be accessed by LSU 3866.

In at least one embodiment, register file 3858 provides a set of registers for functional units of graphics multiprocessor 3896. In at least one embodiment, register file 3858 provides temporary storage for operands of a datapath connected to functional units of graphics multiprocessor 3896 (e.g., GPGPU core 3862, LSU 3866). In at least one embodiment, register file 3858 is divided among each functional unit such that a dedicated portion of register file 3858 is allocated for each functional unit. In at least one embodiment, register file 3858 is divided among different thread groups being executed by graphics multiprocessor 3896.

In at least one embodiment, the GPGPU cores 3862 may each include an FPU and/or ALU for executing instructions of the graphics multiprocessor 3896. GPGPU cores 3862 may be similar in architecture or may differ in architecture. In at least one embodiment, the first portion of the GPGPU core 3862 includes a single precision FPU and integer ALUs, while the second portion of the GPGPU core includes a dual precision FPU. In at least one embodiment, the FPU may implement IEEE for floating point algorithms

754-2008 standard or enable variable precision floating point algorithms. In at least one embodiment, graphics multiprocessor 3896 may additionally include one or more fixed function or special function units to perform particular functions, such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores 3862 may also include fixed or special function logic.

In at least one embodiment, the GPGPU core 3862 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, GPGPU core 3862 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for a GPGPU core may be generated by a shader compiler at compile time, or automatically when executing programs written and compiled for Single Program Multiple Data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

In at least one embodiment, memory and cache interconnect 3868 is an interconnect network that connects each functional unit of graphics multiprocessor 3896 to register file 3858 and shared memory 3870. In at least one embodiment, memory and cache interconnect 3868 is a crossbar interconnect that allows LSU 3866 to implement load and store operations between shared memory 3870 and register file 3858. In at least one embodiment, register file 3858 may operate at the same frequency as GPGPU core 3862, such that the latency of data transfer between GPGPU core 3862 and register file 3858 is very low. In at least one embodiment, shared memory 3870 may be used to enable communication between threads executing on functional units within graphics multiprocessor 3896. In at least one embodiment, cache memory 3872 may be used, for example, as a data cache to cache texture data communicated between functional units and texture units 3836. In at least one embodiment, shared memory 3870 may also be used as a program managed cache. In at least one embodiment, threads executing on GPGPU core 3862 may also programmatically store data in shared memory in addition to automatically cached data stored in cache memory 3872.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various General Purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor/core via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core through an internal processor bus/interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPUs are connected, the processor cores may distribute work to the GPUs in the form of command/instruction sequences that the WD includes. In at least one embodiment, the GPU then uses dedicated circuitry/logic to efficiently process these commands/instructions.

General purpose computing

The following figures set forth, but are not limited to, exemplary software configurations for implementing at least one embodiment in a general purpose computing.

FIG. 39 illustrates a software stack of a programming platform in accordance with at least one embodiment. In at least one embodiment, the programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer may access a programming platform through libraries, compiler directives, and/or extensions to a programming language. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, radeon open computing platform ("ROCm"), openCL (OpenCL developed by Khronos group) ^TM ) SYCL or Intel One APIs.

In at least one embodiment, the software stack 3900 of the programming platform provides an execution environment for applications 3901. In at least one embodiment, the application 3901 may comprise any computer software capable of being launched on the software stack 3900. In at least one embodiment, applications 3901 may include, but are not limited to, artificial intelligence ("AI")/machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI") or data center workloads.

In at least one embodiment, the application 3901 and the software stack 3900 run on hardware 3907. In at least one embodiment, hardware 3907 may include one or more GPU, CPU, FPGA, AI engines and/or other types of computing devices that support a programming platform. In at least one embodiment, using CUDA, for example, software stack 3900 may be vendor specific and compatible only with devices from a particular vendor. In at least one embodiment, such as in employing OpenCL, software stack 3900 may be used with devices from different vendors. In at least one embodiment, hardware 3907 includes a host connected to one or more devices that are accessible via Application Programming Interface (API) calls to perform computing tasks. In at least one embodiment, as compared to a host within hardware 3907, it may include, but is not limited to, a CPU (but may also include a computing device) and its memory, and devices within hardware 3907 may include, but are not limited to, a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

In at least one embodiment, the software stack 3900 of the programming platform includes, but is not limited to, a plurality of libraries 3903, runtime 3905, and device kernel drivers 3906. In at least one embodiment, each of the libraries 3903 may include data and programming code that may be used by a computer program and utilized during software development. In at least one embodiment, library 3903 may include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documents, assistance data, and/or message templates. In at least one embodiment, library 3903 comprises functions optimized for execution on one or more types of devices. In at least one embodiment, library 3903 may include, but is not limited to, functions for performing mathematical, deep learning, and/or other types of operations on a device. In at least one embodiment, the library 4003 is associated with a corresponding API 4002, and the API 4002 can include one or more APIs that expose functions implemented in the library 4003.

In at least one embodiment, the application 3901 is written as source code that is compiled into executable code, as discussed in more detail below in connection with FIG. 44. In at least one embodiment, the executable code of the application 3901 may run at least in part on the execution environment provided by the software stack 3900. In at least one embodiment, code that needs to run on the device (as compared to the host) can be obtained during execution of application 3901. In this case, in at least one embodiment, runtime 3905 may be invoked to load and launch the necessary code on the device. In at least one embodiment, the runtime 3905 can comprise any technically feasible runtime system capable of supporting execution of the application 3901.

In at least one embodiment, the runtime 3905 is implemented as one or more runtime libraries associated with a corresponding API (which is shown as API 3904). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling and/or synchronization, and the like. In at least one embodiment, the memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory and transferring data between host memory and device memory. In at least one embodiment, executing the control functions may include, but is not limited to, a function that starts a function on the device (sometimes referred to as a "kernel" when the function is a global function that is callable from the host), and a function that sets attribute values in a buffer maintained by the runtime library for a given function to be executed on the device.

In at least one embodiment, the runtime libraries and corresponding APIs 3904 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number) of APIs may expose a low-level set of functions for fine-grained control of a device, while another (or any number) of APIs may expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API may be built on top of a low-level API. In at least one embodiment, the one or more runtime APIs may be language-specific APIs that are layered on top of the language-independent runtime APIs.

In at least one embodiment, the device kernel driver 3906 is configured to facilitate communication with an underlying device. In at least one embodiment, the device kernel driver 3906 may provide low-level functions on which APIs such as API 3904 and/or other software depend. In at least one embodiment, the device kernel driver 3906 may be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 3906 may compile non-hardware specific parallel thread execution ("PTX") IR code at runtime into binary code (cache compiled binary code) for a particular target device, sometimes referred to as "final" code. In at least one embodiment, this may allow the final code to run on the target device, which may not exist when the source code is initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled offline into binary code without requiring the device kernel driver 3906 to compile IR code at runtime.

FIG. 40 illustrates a CUDA implementation of the software stack 3900 of FIG. 39 in accordance with at least one embodiment. In at least one embodiment, CUDA software stack 4000, on which application 4001 can be launched, includes CUDA library 4003, CUDA runtime 4005, CUDA driver 4007 and device kernel driver 4008. In at least one embodiment, CUDA software stack 4000 executes on hardware 4009, which hardware 4009 may comprise a CUDA-enabled GPU developed by NVIDIA corporation of santa clara, california.

In at least one embodiment, the application 4001, the CUDA runtime 4005, and the device kernel driver 4008 can perform similar functions as the application 3901, the runtime 3905, and the device kernel driver 3906, respectively, which are described above in connection with fig. 39. In at least one embodiment, the CUDA driver 4007 comprises a library (libcuda. So) that implements the CUDA driver API 4006. In at least one embodiment, similar to CUDA runtime API 4004 implemented by CUDA runtime library (cudart), CUDA driver API 4006 can expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and/or graphics interoperability, and the like. In at least one embodiment, the CUDA driver API 4006 differs from the CUDA runtime API 4004 in that the CUDA runtime API 4004 simplifies device code management by providing implicit initialization, context (similar to a process) management, and module (similar to a dynamically loaded library) management. In contrast to the high-level CUDA runtime API 4004, in at least one embodiment, the CUDA driver API 4006 is a low-level API that provides finer granularity control of devices, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 4006 can expose functions for context management that are not exposed by the CUDA runtime API 4004. In at least one embodiment, the CUDA driver API 4006 is also language independent and supports, for example, openCL in addition to the CUDA runtime API 4004. Further, in at least one embodiment, the development library, including CUDA runtime 4005, can be considered separate from the driver components, including user-mode CUDA driver 4007 and kernel-mode device driver 4008 (also sometimes referred to as a "display" driver).

In at least one embodiment, CUDA library 4003 may include, but is not limited to, a math library, a deep learning library, a parallel algorithm library, and/or a signal/image/video processing library, which may be utilized by a parallel computing application (e.g., application 4001). In at least one embodiment, CUDA library 4003 can comprise a mathematical library, such as a cuBLAS library, which is an implementation of a basic linear algebra subroutine ("BLAS") for performing linear algebra operations; a curfft library for computing a fast fourier transform ("FFT"), a curnd library for generating random numbers, and the like. In at least one embodiment, CUDA library 4003 may include deep learning libraries, such as cuDNN libraries for primitives of deep neural networks and the TensorRT platform for high performance deep learning reasoning, among others.

Fig. 41 illustrates a ROCm implementation of the software stack 3900 of fig. 39 in accordance with at least one embodiment. In at least one embodiment, the ROCm software stack 4100 on which the application 4101 can be launched includes a language runtime 4103, a system runtime 4105,thunk 4107,ROCm kernel driver 4108 and a device kernel driver 4109. In at least one embodiment, the ROCm software stack 4100 executes on hardware 4109, the hardware 4109 can include a ROCm enabled GPU developed by AMD corporation of santa clara, california.

In at least one embodiment, the application 4101 can perform similar functions as the application 3901 discussed above in connection with FIG. 39. In addition, in at least one embodiment, language runtime 4103 and system runtime 4105 can perform similar functions as runtime 3905 discussed above in connection with FIG. 39. In at least one embodiment, the language runtime 4103 differs from the system runtime 4105 in that the system runtime 4105 is a language independent runtime that implements the ROCr system runtime API 4104 and utilizes a heterogeneous system architecture ("HAS") runtime API. In at least one embodiment, the HAS runtime API is a thin user mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, execution control through architecture dispatch kernels, error handling, system and agent information, and runtime initialization and shutdown, among others. In at least one embodiment, the language runtime 4103 is an implementation of the language specific runtime API 4102 that is layered above the ROCr system runtime API 4104, as compared to the system runtime 4105. In at least one embodiment, the language runtime APIs may include, but are not limited to, a portable heterogeneous computing interface ("HIP") language runtime API, a heterogeneous computing compiler ("HCC") language runtime API or an OpenCL API, or the like. In particular, the HIP language is an extension of the C++ programming language, having functionally similar versions of the CUDA mechanism, and in at least one embodiment, the HIP language runtime APIs include similar functions as the CUDA runtime APIs 4004 discussed above in connection with FIG. 40, such as functions for memory management, execution control, device management, error handling, synchronization, and the like.

In at least one embodiment, the thread (ROCt) 4107 is an interface that can be used to interact with the underlying ROCm driver 4108. In at least one embodiment, the ROCm driver 4108 is a ROCk driver that is a combination of an amdpu driver and HAS kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for a GPU developed by AMD that performs similar functions as the device kernel driver 3906 discussed above in connection with FIG. 39. In at least one embodiment, the HAS kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

In at least one embodiment, various libraries (not shown) can be included in the ROCm software stack 4100 above the language runtime 4103 and provide similar functionality to the CUDA library 4003 discussed above in connection with fig. 40. In at least one embodiment, the various libraries may include, but are not limited to, mathematical, deep learning, and/or other libraries, such as hipBLAS libraries that implement functions similar to CUDA cuBLAS, rocFFT libraries similar to CUDA cuFFT used to calculate FFTs, and the like.

Fig. 42 illustrates an OpenCL implementation of the software stack 3900 of fig. 39 in accordance with at least one embodiment. In at least one embodiment, the OpenCL software stack 4200 on which the application 4201 can be launched includes an OpenCL framework 4205, an OpenCL runtime 4206, and a driver 4207. In at least one embodiment, the OpenCL software stack 4200 executes on hardware 4009 that is not vendor specific. In at least one embodiment, since devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

In at least one embodiment, the application 4201, the opencl runtime 4206, the device kernel driver 4207, and the hardware 4208 may perform similar functions as the application 3901, the runtime 3905, the device kernel driver 3906, and the hardware 3907, respectively, discussed above in connection with fig. 39. In at least one embodiment, the application 4201 also includes an OpenCL kernel 4202 having code to be executed on the device.

In at least one embodiment, openCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 4203 and runtime API 4205. In at least one embodiment, the runtime API 4205 uses contexts to manage execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context that the runtime API 4205 can use to manage the device's command queue, program objects and kernel objects, shared memory objects, and the like. In at least one embodiment, the platform API 4203 discloses functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer from and to devices, among other things. In addition, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

In at least one embodiment, the compiler 4204 is also included in the OpenCL framework 4205. In at least one embodiment, the source code may be compiled offline prior to executing the application or online during execution of the application. In contrast to CUDA and ROCm, the OpenCL application in at least one embodiment may be compiled online by compiler 4204, with compiler 4204 included to represent any number of compilers that may be used to compile source code and/or IR code (e.g., standard portable intermediate representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, the OpenCL application may be compiled offline prior to execution of such application.

FIG. 43 illustrates software supported by a programming platform in accordance with at least one embodiment. In at least one embodiment, the programming platform 4304 is configured to support various programming models 4303, middleware and/or libraries 4302, and frameworks 4301 upon which the application 4300 may depend. In at least one embodiment, the application 4300 can be an AI/ML application implemented using, for example, a deep learning framework (in at least one embodiment, MXNet, pyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL") "and/or NVIDIA developer data loader library (" DALI ") CUDA library to provide accelerated computing on underlying hardware.

In at least one embodiment, the programming platform 4304 may be one of the CUDA, ROCm, or OpenCL platforms described above in connection with fig. 40, 41, and 42, respectively. In at least one embodiment, the programming platform 4304 supports a plurality of programming models 4303, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, the programming model 4303 may expose features of the underlying hardware in order to improve performance. In at least one embodiment, the programming model 4303 may include, but is not limited to CUDA, HIP, openCL, c++ accelerated massive parallelism ("c++ AMP"), open multiprocessing ("OpenMP"), open accelerator ("OpenACC"), and/or Vulcan computing (Vulcan computer).

In at least one embodiment, the library and/or middleware 4302 provides an abstract implementation of the programming model 4304. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications in addition to those available from the programming platform 4304. In at least one embodiment, the libraries and/or middleware 4302 may include, but are not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. Additionally, in at least one embodiment, the library and/or middleware 4302 may include NCCL and ROCm communication Convergence ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and/or eigen libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

In at least one embodiment, the application framework 4301 is dependent on libraries and/or middleware 4302. In at least one embodiment, each application framework 4301 is a software framework for implementing a standard structure for application software. In at least one embodiment, the AI/ML application can be implemented using a framework (such as a Caffe, caffe2, tensorFlow, keras, pyTorch or MxNet deep learning framework).

FIG. 44 illustrates compiled code to be executed on one of the programming platforms of FIGS. 39-42 in accordance with at least one embodiment. In at least one embodiment, compiler 4401 receives source code 4400, which includes both host code as well as device code. In at least one embodiment, compiler 4401 is configured to convert source code 4400 into host executable code 4402 for execution on a host and device executable code 4403 for execution on a device. In at least one embodiment, the source code 4400 may be compiled offline prior to executing the application or online during execution of the application.

In at least one embodiment, the source code 4400 may include code in any programming language supported by the compiler 4401, such as c++, C, fortran, and the like. In at least one embodiment, source code 4400 may be included in a single-source (single-source) file having a mix of host code and device code, and where the location of the device code is indicated. In at least one embodiment, the single source file may be a. Cu file including CUDA code or a. HIP. Cpp file including HIP code. Alternatively, in at least one embodiment, the source code 4400 may include multiple source code files instead of a single source file in which the host code and device code are separate.

In at least one embodiment, compiler 4401 is configured to compile source code 4400 into host executable code 4402 for execution on a host and device executable code 4403 for execution on a device. In at least one embodiment, compiler 4401 performs operations including parsing source code 4400 into Abstract System Trees (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code 4400 includes a single source file, compiler 4401 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 4403 and host executable code 4402, respectively, and link device executable code 4403 and host executable code 4402 together in a single file, as discussed in more detail below with respect to fig. 33.

In at least one embodiment, the host executable code 4402 and the device executable code 4403 may be in any suitable format, such as binary code and/or IR code. In the case of CUDA, in at least one embodiment, host executable code 4402 may include native object code, while device executable code 4403 may include code represented in the middle of PTX. In at least one embodiment, in the case of ROCm, both the host executable 4402 and the device executable 4403 may include target binary code.

Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative arrangements, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative arrangements, and equivalents falling within the spirit and scope of the disclosure as defined by the appended claims.

The use of the terms "a" and "an" and "the" and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (meaning "including, but not limited to,") unless otherwise noted. The term "connected" (referring to physical connection when unmodified) should be interpreted as partially or wholly included, attached to, or connected together, even with some intervention. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, unless indicated otherwise or contradicted by context, the use of the term "set" (e.g., "set of items") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless indicated otherwise or contradicted by context, the term "subset" of a respective set does not necessarily denote an appropriate subset of the corresponding set, but the subset and the corresponding set may be equal.

At least one embodiment of the present disclosure may be described in view of the following clauses:

clause 1. A processor, comprising: one or more circuits to schedule one or more instructions to be executed by one or more processors based at least in part on latency of one or more interconnects coupled to the one or more processors.

Clause 2, the processor of clause 1, wherein the one or more circuits are to schedule the one or more instructions based at least in part on a first node tag indicating a maximum number of the one or more processors to execute the one or more instructions and a second node tag indicating an unalterable number of the one or more processors to execute the one or more instructions.

Clause 3, the processor of any of the above clauses, wherein the latency of the one or more interconnects is based at least in part on a proximity of the one or more processors within a non-uniform memory access (NUMA) domain.

Clause 4. The processor of any of the preceding clauses, wherein the one or more circuits are to schedule the one or more instructions based at least in part on a constraint on a number of processors used to execute the one or more instructions.

Clause 5 the processor of any of the preceding clauses, wherein the one or more circuits are to schedule the one or more instructions based at least in part on constraints on placement of instructions executed by a number of processors.

Clause 6, the processor of any of the preceding clauses, wherein the one or more circuits are to schedule the one or more instructions based at least in part on dynamic marking of one or more nodes comprising the one or more processors.

Clause 7, the processor of any of the above clauses, wherein the one or more circuits are to schedule subsequent one or more instructions based at least in part on a second latency equal to the latency of the one or more interconnects coupled to the one or more processors.

Clause 8, a system comprising:

one or more processors to schedule one or more instructions to be executed by the one or more processors based at least in part on a latency of one or more interconnects coupled to the one or more processors.

Clause 9 the system of clause 8, wherein the one or more processors are configured to schedule the one or more instructions based at least in part on a first node tag indicating a dynamic number of processors for executing the instructions and a second node tag indicating an unalterable number of processors for executing the instructions.

Clause 10 the system of any of the preceding clauses, wherein the latency of the one or more interconnects is based at least in part on a proximity of one processor executing the one or more instructions to another processor executing the one or more instructions.

Clause 11 the system of any of the preceding clauses, wherein the latency of the one or more interconnects is based at least in part on a slot domain.

Clause 12 the system according to any of the preceding clauses, wherein the dynamic label of the processor changes based at least in part on completion of all instructions being executed by the plurality of processors on the node.

Clause 13 the system of any of the preceding clauses, wherein the one or more processors are to schedule the second one or more instructions to be executed by the second one or more processors based at least in part on an equivalent latency of the latency of one or more interconnects coupled to the one or more processors.

Clause 14. The system of any of the preceding clauses, wherein the percentage of one or more nodes assigned the first node label and the second node label is configurable.

Clause 15, a method comprising:

one or more instructions to be executed by one or more processors are scheduled based at least in part on latency of one or more interconnects coupled to the one or more processors.

Clause 16, the method of any of the preceding clauses, wherein scheduling the one or more instructions is based at least in part on a node tag of one or more nodes comprising the one or more processors executing the one or more instructions.

Clause 17, the method of any of the preceding clauses, wherein the latency of the one or more interconnects is based at least in part on a proximity of one processor executing the one or more instructions to another processor executing the one or more instructions.

Clause 18 the method of any of the preceding clauses, wherein scheduling the one or more instructions is based at least in part on a constraint on a number of processors used to execute the one or more instructions.

Clause 19 the method of any of the preceding clauses, further comprising:

the one or more instructions are executed based at least in part on the latency of one or more interconnects coupled to the one or more processors.

Clause 20. The method according to any of the preceding clauses, further comprising:

generating an fitness score for a node comprising the one or more processors, the fitness score indicating a different value than a number of processors executing the one or more instructions; and

a second one or more instructions to be executed by a different number of the one or more processors than the number of processors executing the one or more instructions are scheduled.

Unless otherwise explicitly indicated or clearly contradicted by context, a connective language such as a phrase in the form of "at least one of a, B and C" or "at least one of a, B and C" is understood in the context to be generally used to denote an item, term, etc., which may be a or B or C, or any non-empty subset of the a and B and C sets. For example, in the illustrative example of a set having three members, the conjoin phrases "at least one of a, B, and C" and "at least one of a, B, and C" refer to any of the following sets: { A }, { B }, { C }, { A, B }, { A, C }, { B, C }, { A, B, C }. Thus, such connection language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. In addition, unless otherwise indicated herein or otherwise clearly contradicted by context, the term "plurality" refers to a state of plural (e.g., the term "plurality of items" refers to a plurality of items). In at least one embodiment, the number of items in the plurality of items is at least two, but may be more if explicitly indicated or indicated by context. Furthermore, unless otherwise indicated or clear from context, the phrase "based on" means "based at least in part on" rather than "based only on".

The operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, processes such as those described herein (or variations and/or combinations thereof) are performed under control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that are jointly executed on one or more processors via hardware or a combination thereof. In at least one embodiment, the code is stored on a computer readable storage medium in the form of a computer program that, in at least one embodiment, includes a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., propagated transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) that, when executed by one or more processors of a computer system (i.e., as a result of being executed), cause the computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all code, but the plurality of non-transitory computer-readable storage media collectively store all code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors, in at least one embodiment, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of the instructions.

Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such computer system is configured with suitable hardware and/or software that enables the operations to be performed. Further, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system, comprising a plurality of devices operating in different manners, such that the distributed computer system performs the operations described herein, and such that a single device does not perform all of the operations.

The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in particular examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

Unless specifically stated otherwise, it is appreciated that throughout the description, terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical quantities (e.g., electronic) within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices.

In a similar manner, the term "processor" may refer to any device or portion of memory that processes electronic data from registers and/or memory and converts the electronic data into other electronic data that may be stored in the registers and/or memory. As a non-limiting example, a "processor" may be a CPU or GPU. A "computing platform" may include one or more processors. As used herein, in at least one embodiment, a "software" process may include software and/or hardware entities, such as tasks, threads, and intelligent agents, that perform work over time. Also, each process may refer to multiple processes to execute instructions sequentially or in parallel, either continuously or intermittently. The terms "system" and "method" are used interchangeably herein as long as the system can embody one or more methods, and the methods can be considered as systems.

In at least one embodiment, the arithmetic logic unit is a set of combinational logic circuits that accept one or more inputs to produce a result. In at least one embodiment, the processor uses arithmetic logic units to implement mathematical operations such as addition, subtraction, or multiplication. In at least one embodiment, the arithmetic logic unit is used to implement logical operations, such as logical AND/OR. In at least one embodiment, the arithmetic logic unit is stateless and is made of physical switching components such as semiconductor transistors arranged to form logic gates. In at least one embodiment, the arithmetic logic unit may operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, the arithmetic logic unit may be configured as an asynchronous logic circuit whose internal state is not maintained in the associated register set. In at least one embodiment, the processor uses an arithmetic logic unit to combine operands stored in one or more registers of the processor and produce an output that can be stored by the processor in another register or memory location.

In at least one embodiment, as a result of processing an instruction retrieved by the processor, the processor presents one or more inputs or operands to the arithmetic logic unit such that the arithmetic logic unit generates a result based at least in part on the instruction code provided to the inputs of the arithmetic logic unit. In at least one embodiment, the instruction code provided by the processor to the ALU is based at least in part on instructions executed by the processor. In at least one embodiment, combinational logic in the ALU processes the inputs and produces outputs that are placed on a bus within the processor. In at least one embodiment, the processor selects a target register, memory location, output device, or output storage location on the output bus to clock the processor so that the results produced by the ALU are sent to the desired location.

In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, computer system or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data may be accomplished in a variety of ways, such as by receiving data that is a parameter of a function call or call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data may be implemented by transmitting the data as input or output parameters for a function call, parameters for an application programming interface, or an interprocess communication mechanism.

While the above discussion sets forth example implementations of the technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of the present disclosure. Furthermore, while specific assignments of responsibilities are defined above for purposes of discussion, various functions and responsibilities may be assigned and divided in different ways depending on the circumstances.

Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A processor, comprising:

one or more circuits to schedule one or more instructions to be executed by one or more processors based at least in part on latency of one or more interconnects coupled to the one or more processors.

2. The processor of claim 1, wherein the one or more circuits are to schedule the one or more instructions based at least in part on a first node tag indicating a maximum number of the one or more processors to execute the one or more instructions and a second node tag indicating an unchangeable number of the one or more processors to execute the one or more instructions.

3. The processor of claim 1, wherein the latency of the one or more interconnects is based at least in part on a proximity of the one or more processors within a non-uniform memory access (NUMA) domain.

4. The processor of claim 1, wherein the one or more circuits are to schedule the one or more instructions based at least in part on a constraint on a number of processors used to execute the one or more instructions.

5. The processor of claim 1, wherein the one or more circuits are to schedule the one or more instructions based at least in part on constraints on placement of instructions executed by a number of processors.

6. The processor of claim 1, wherein the one or more circuits are to schedule the one or more instructions based at least in part on dynamic marking of one or more nodes comprising the one or more processors.

7. The processor of claim 1, wherein the one or more circuits are to schedule subsequent one or more instructions based at least in part on a second latency equal to the latency of the one or more interconnects coupled to the one or more processors.

8. A system, comprising:

9. The system of claim 8, wherein the one or more processors are to schedule the one or more instructions based at least in part on a first node tag indicating a dynamic number of processors to execute instructions and a second node tag indicating an unchangeable number of processors to execute the instructions.

10. The system of claim 8, wherein the latency of the one or more interconnects is based at least in part on a proximity of one processor executing the one or more instructions to another processor executing the one or more instructions.

11. The system of claim 8, wherein the latency of the one or more interconnects is based at least in part on a slot domain.

12. The system of claim 8, wherein the dynamic label of a processor changes based at least in part on completion of all instructions being executed by a plurality of processors on a node.

13. The system of claim 8, wherein the one or more processors are to schedule a second one or more instructions to be executed by a second one or more processors based at least in part on an equivalent latency of the latency of one or more interconnects coupled to the one or more processors.

14. The system of claim 9, wherein a percentage of one or more nodes assigned the first node label and the second node label is configurable.

15. A method, comprising:

16. The method of claim 15, wherein scheduling the one or more instructions is based at least in part on a node tag of one or more nodes comprising the one or more processors executing the one or more instructions.

17. The method of claim 15, wherein the latency of the one or more interconnects is based at least in part on a proximity of one processor executing the one or more instructions to another processor executing the one or more instructions.

18. The method of claim 15, wherein scheduling the one or more instructions is based at least in part on a constraint on a number of processors used to execute the one or more instructions.

19. The method of claim 15, further comprising:

20. The method of claim 15, further comprising: