CN117558307B - Threshold voltage adjusting method, device and equipment of memory chip and storage medium - Google Patents
Threshold voltage adjusting method, device and equipment of memory chip and storage medium Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
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Abstract
The invention relates to the technical field of voltage regulation and discloses a threshold voltage regulation method, device, equipment and storage medium of a storage chip.
Description
Technical Field
The present invention relates to the field of voltage regulation technologies, and in particular, to a method, an apparatus, a device, and a storage medium for regulating threshold voltage of a memory chip.
Background
The threshold voltage of the memory chip refers to the voltage threshold in the memory chip that identifies logic "1" and "0", the threshold voltage is generally defined as the gate voltage of the transistor, when the gate voltage is higher than this voltage, the transistor is considered to be in an "on" state, and the output is considered to be logic "1"; when the gate voltage is below this voltage, the transistor is considered to be in an "off" state and the output is considered to be a logic "0".
When the memory chip is used for reading and writing the memory content, a series of gate voltage signals are required to be output to transmit the reading and writing operation, so that the reading and writing operation of the memory content is modified, the gate voltage signals are required to be judged through the threshold voltage and are converted into high level or low level, and the information transmission is realized.
In the process of the memory chip, the threshold voltage is generally in a fixed state, so that when the gate voltage signal of the memory chip changes along with the aging of the device and other reasons, the threshold voltage cannot be adjusted correspondingly in time, thereby causing errors in the memory content.
Disclosure of Invention
The invention aims to provide a threshold voltage adjusting method, device and equipment of a memory chip and a memory medium, and aims to solve the problem that the threshold voltage of the memory chip in the prior art is in a fixed state and cannot be adjusted in time aiming at the change of the gate voltage, so that memory errors are caused.
The present invention is achieved in that, in a first aspect, the present invention provides a threshold voltage adjustment method for a memory chip, including:
collecting gate voltage signals, compiling standards and compiling results of a storage chip at all moments, recording the gate voltage signals, the compiling standards and the compiling results corresponding to the same moment as a signal compiling behavior, and constructing all the signal compiling behaviors into a signal compiling sequence according to a time sequence;
feature extraction of compiling discrete parameters is carried out on each signal compiling behavior of the signal compiling sequence, and the compiling discrete parameters are arranged to obtain a compiling discrete sequence of the signal compiling sequence; wherein the coding discrete parameter is used for describing the distance between the grid voltage signal and the coding standard in the signal coding behavior;
dividing each compiling discrete parameter corresponding to different compiling results into a first parameter set and a second parameter set, and calculating theoretical characteristics of compiling standards according to the first parameter set and the second parameter set to obtain theoretical compiling standards; the theoretical compiling standard can enable the difference between average parameters of compiling discrete parameters in the first parameter set and the second parameter set to be the minimum value on the premise of keeping the compiling result of the signal compiling sequence unchanged;
detecting storage errors of the storage chip, and distinguishing each signal compiling behavior of the signal compiling sequence into an error compiling behavior and a correct compiling behavior according to a detection result;
performing verification calculation on the error compiling behavior according to the theoretical compiling standard to judge whether the theoretical compiling standard can correct the error compiling behavior, if so, determining the theoretical compiling standard as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard;
if the error compiling behavior cannot be corrected, generating a plurality of preliminary compiling standards based on the theoretical compiling standard, respectively performing verification calculation on whether the error compiling behavior can be corrected for each preliminary compiling standard, determining the preliminary compiling standard which is closest to the theoretical compiling standard and can correct the error compiling behavior as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard.
Preferably, the step of collecting the gate voltage signal, the compiling standard and the compiling result of the memory chip at each moment, recording the gate voltage signal, the compiling standard and the compiling result corresponding to the same moment as a signal compiling behavior, and constructing each signal compiling behavior into a signal compiling sequence according to a time sequence includes:
constructing a moment coordinate axis; the moment coordinate axes are provided with moment coordinate points which are sequentially arranged;
continuously collecting the grid voltage signals, the compiling standards and the compiling results of the storage chip, and combining the grid voltage signals, the compiling standards and the compiling results corresponding to the same moment into the signal compiling behavior;
and setting the signal compiling behavior on a time coordinate point corresponding to the time coordinate axis according to the time corresponding to the signal compiling behavior.
Preferably, the step of extracting features of compiling discrete parameters for each signal compiling behavior of the signal compiling sequence and arranging the compiling discrete parameters to obtain a compiling discrete sequence of the signal compiling sequence comprises:
performing difference value calculation on the grid voltage signals of the signal compiling behaviors and the compiling standard to obtain compiling difference values of the signal compiling behaviors;
summarizing the compiling difference values into discrete reference sets, calculating the ratio relation among the compiling difference values through the discrete reference sets, and generating discrete scales of the compiling difference values according to the calculated ratio relation among the compiling difference values;
according to the compiling result of each signal compiling behavior, a positive sign or a negative sign is given to the corresponding discrete scale so as to generate compiling discrete parameters of the signal compiling behavior;
and arranging the compiling discrete parameters to obtain the compiling discrete sequence.
Preferably, the step of dividing each of the compiling discrete parameters corresponding to different compiling results into a first parameter set and a second parameter set, and calculating theoretical features of a compiling standard according to the first parameter set and the second parameter set to obtain the theoretical compiling standard includes:
dividing the coding discrete parameters with the forward marks into a first parameter set, and recording the average parameters of all the coding discrete parameters in the first parameter set as first average parameters;
dividing the coding discrete parameters with the negative marks into a second parameter set, and recording the average parameters of all the coding discrete parameters in the second parameter set as second average parameters;
generating a plurality of prediction standards adjacent to the existing compiling standard by using the depth search algorithm with the compiling standard in the existing compiling discrete sequence as a benchmark, calculating differences of the first average parameter and the second average parameter corresponding to each prediction standard, and recording each calculated difference as each prediction discrete difference;
and performing contrast analysis on each predicted discrete difference, and taking the prediction standard corresponding to the predicted discrete difference with the minimum value as a theoretical compiling standard according to the result of the contrast analysis.
Preferably, the step of detecting a storage error of the storage chip and distinguishing each signal compiling behavior of the signal compiling sequence into an erroneous compiling behavior and a correct compiling behavior according to a result of the detection includes:
a detection storage area is planned in the storage chip in advance and used for backing up storage contents, and the corresponding relation between the storage contents and the signal compiling behavior is recorded;
and checking the storage contents in the storage chip according to the storage contents in the detection storage area at intervals of preset time to obtain a checking result, marking error storage contents and correct storage contents in the storage contents according to the checking result, taking signal compiling behaviors corresponding to the error storage contents as error compiling behaviors, and taking signal compiling behaviors corresponding to the correct storage contents as correct compiling behaviors.
In a second aspect, the present invention provides a threshold voltage adjusting apparatus of a memory chip, comprising:
the data acquisition module is used for acquiring gate voltage signals, compiling standards and compiling results of the memory chip at all moments, recording the mutually corresponding gate voltage signals, compiling standards and compiling results as primary signal compiling behaviors, and constructing all the signal compiling behaviors into a signal compiling sequence according to time sequences;
the data processing module is used for extracting the characteristics of the compiling discrete parameters of each signal compiling behavior of the signal compiling sequence and arranging the compiling discrete parameters of each signal compiling behavior of the signal compiling sequence to obtain the compiling discrete sequence of the signal compiling sequence; wherein the coding discrete parameter is used for describing the distance between the grid voltage signal and the coding standard in the signal coding behavior;
the data calculation module is used for calculating theoretical characteristics of the compiling standard based on the compiling discrete sequence so as to acquire the theoretical compiling standard; the theoretical compiling standard can enable the sum of compiling discrete parameters in the compiling discrete sequence to be minimum on the premise of keeping the compiling result of the signal compiling sequence unchanged;
the error detection module is used for detecting storage errors of the storage chip and distinguishing each signal compiling behavior of the signal compiling sequence into an error compiling behavior and a correct compiling behavior according to a detection result;
the first verification module is used for performing verification calculation on the error compiling behavior according to the theoretical compiling standard so as to judge whether the theoretical compiling standard can correct the error compiling behavior, if so, determining the theoretical compiling standard as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard;
and the second verification module is used for generating a plurality of preparation compiling standards by taking the theoretical compiling standard as a reference when the error compiling behavior cannot be corrected, respectively performing verification calculation on whether the error compiling behavior can be corrected for each preparation compiling standard, determining the preparation compiling standard which is closest to the theoretical compiling standard and can correct the error compiling behavior as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard.
In a third aspect, the present invention provides a threshold voltage adjustment device for a memory chip, comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor implementing a threshold voltage adjustment method for a memory chip according to any one of the first aspects when executing the computer program.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform a threshold voltage adjustment method of a memory chip as set forth in any one of the first aspects.
The invention provides a threshold voltage adjusting method of a memory chip, which has the following beneficial effects:
according to the invention, the signal compiling sequence consisting of the signal compiling behaviors at all times is obtained by collecting the gate voltage signals, the compiling standards and the compiling results of the memory chip at all times, the compiling discrete sequence consisting of the compiling discrete parameters is obtained based on the extracting characteristics of the signal compiling sequence, the theoretical compiling standards are generated by analyzing the compiling discrete sequence, and the theoretical compiling standards are regulated according to the existing error compiling behaviors of the memory chip, so that the final compiling standards are obtained, the threshold voltage can correct the error compiling behaviors and can adapt to the signal current situation of the memory chip, and the problems that the threshold voltage of the memory chip is in a fixed state, and the memory error is caused because the change of the gate voltage cannot be regulated timely in the prior art are solved.
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FIG. 1 is a schematic diagram showing steps of a threshold voltage adjustment method for a memory chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a threshold voltage adjusting device of a memory chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The same or similar reference numerals in the drawings of the present embodiment correspond to the same or similar components; in the description of the present invention, it should be understood that, if there is an azimuth or positional relationship indicated by terms such as "upper", "lower", "left", "right", etc., based on the azimuth or positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus terms describing the positional relationship in the drawings are merely illustrative and should not be construed as limiting the present invention, and specific meanings of the terms described above may be understood by those of ordinary skill in the art according to specific circumstances.
The implementation of the present invention will be described in detail below with reference to specific embodiments.
Referring to fig. 1 and 2, a preferred embodiment of the present invention is provided.
In a first aspect, the present invention provides a threshold voltage adjustment method for a memory chip, including:
s1: collecting gate voltage signals, compiling standards and compiling results of a storage chip at all moments, recording the gate voltage signals, the compiling standards and the compiling results corresponding to the same moment as a signal compiling behavior, and constructing all the signal compiling behaviors into a signal compiling sequence according to a time sequence;
s2: feature extraction of compiling discrete parameters is carried out on each signal compiling behavior of the signal compiling sequence, and the compiling discrete parameters are arranged to obtain a compiling discrete sequence of the signal compiling sequence; wherein the coding discrete parameter is used for describing the distance between the grid voltage signal and the coding standard in the signal coding behavior;
s3: dividing each compiling discrete parameter corresponding to different compiling results into a first parameter set and a second parameter set, and calculating theoretical characteristics of compiling standards according to the first parameter set and the second parameter set to obtain theoretical compiling standards; the theoretical compiling standard can enable the difference between average parameters of compiling discrete parameters in the first parameter set and the second parameter set to be the minimum value on the premise of keeping the compiling result of the signal compiling sequence unchanged;
s4: detecting storage errors of the storage chip, and distinguishing each signal compiling behavior of the signal compiling sequence into an error compiling behavior and a correct compiling behavior according to a detection result;
s5: performing verification calculation on the error compiling behavior according to the theoretical compiling standard to judge whether the theoretical compiling standard can correct the error compiling behavior, if so, determining the theoretical compiling standard as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard;
s6: if the error compiling behavior cannot be corrected, generating a plurality of preliminary compiling standards based on the theoretical compiling standard, respectively performing verification calculation on whether the error compiling behavior can be corrected for each preliminary compiling standard, determining the preliminary compiling standard which is closest to the theoretical compiling standard and can correct the error compiling behavior as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard.
Specifically, the threshold voltage refers to a voltage threshold value for determining a logic level in a digital circuit or a memory chip, in which the threshold voltage is used to distinguish between a high level and a low level signal, and is considered to be a high level when the voltage exceeds the threshold voltage; when the voltage is below the threshold voltage, it is considered to be low.
It can be understood that the memory chip needs to read and write the memory content, and in the process of reading and writing, each gate voltage signal needs to be judged according to the threshold voltage to determine whether the gate voltage signal corresponds to a high level or a low level.
More specifically, the level of the threshold voltage should be consistent with the signal strength of the gate voltage signal, so that the gate voltage signals corresponding to the high level and the gate voltage signals corresponding to the low level are kept at a proper distance from the threshold voltage, thereby maximally avoiding the occurrence of the erroneous judgment phenomenon.
Therefore, the invention continuously collects and records the grid voltage signals, the compiling standards and the compiling results which occur at each moment in the memory chip, and records the grid voltage signals, the compiling standards and the compiling results which correspond to the same moment as a signal compiling behavior; the method comprises the steps of determining a gate voltage signal, wherein the gate voltage signal is used for outputting information, a compiling standard is threshold voltage for the gate voltage signal, judging the gate voltage signal according to the compiling standard, identifying whether the gate voltage signal is output in a high level or a low level, and obtaining information output by combining a plurality of gate voltage signals through combining the plurality of gate voltage signals.
More specifically, each signal compiling behavior is constructed as a signal compiling sequence according to a time sequence, each signal compiling behavior in the signal compiling sequence represents a logic level and a corresponding evaluation criterion and basis, that is, the compiling criterion in the signal compiling behavior corresponding to the threshold voltage, and the setting of the threshold voltage determines the accuracy of the signal compiling sequence.
More specifically, feature extraction of compiling discrete parameters is performed on each signal compiling behavior of the signal compiling behavior, the compiling discrete parameters are used for describing a distance between a gate voltage signal and a compiling standard in the signal compiling behavior, it is to be noted that in the signal compiling behavior, the gate voltage signal is identified as a high-level signal or a low-level signal, the compiling discrete parameters of the high-level signal and the low-level signal have different directions in orientation, the values have consistency, the compiling standard is used for judging the high-level signal and the low-level signal, and the distance between the values of the high-level signal and the low-level signal and the compiling standard is the content of the compiling discrete parameter expression.
More specifically, the compiling discrete parameters are arranged to obtain a compiling discrete sequence of the signal compiling sequence, and theoretical characteristics of the compiling standard are calculated based on the compiling discrete sequence to obtain the theoretical compiling standard, wherein the theoretical compiling standard can enable a difference of average parameters of the compiling discrete parameters corresponding to different compiling results in the compiling discrete sequence to be a minimum value on the premise that the compiling results of the signal compiling sequence are kept unchanged.
More specifically, coding discrete parameters with high coding results are divided into a first parameter set, coding discrete parameters with low coding results are divided into a second parameter set, average parameters of coding discrete parameters in the first parameter set and the second parameter set represent average differences between a high-level signal and a low-level signal and coding standards, when the coding standards deviate to the high level or the low level, the differences between the average parameters of the first parameter set and the average parameters of the second parameter set become larger, when the differences between the average parameters of the first parameter set and the second parameter set are the minimum, the coding standards are represented to be at the middle positions of grid voltage signals corresponding to the two coding results, and at the moment, the corresponding coding standards are theoretical coding standards.
More specifically, the theoretical compiling criterion calculated through the above steps may be used as a criterion for threshold voltage adjustment, however, it should be noted that there may be erroneous signal compiling behavior in the signal compiling sequence, and thus the theoretical compiling criterion needs to be adjusted so that the new adjusted criterion can correct the erroneous signal compiling behavior.
More specifically, detecting a storage error of the storage chip, and distinguishing each signal compiling behavior of the signal compiling sequence into an error compiling behavior and a correct compiling behavior according to a detection result; verifying and calculating the error compiling behavior according to the theoretical compiling standard to judge whether the theoretical compiling standard can correct the error compiling behavior, if so, determining the theoretical compiling standard as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard; if not, generating a plurality of preparation compiling standards by taking the theoretical compiling standard as a benchmark, respectively carrying out verification calculation on whether error compiling behaviors can be corrected on each preparation compiling standard, determining the preparation compiling standard which is closest to the theoretical compiling standard and can correct the error compiling behaviors as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard.
It will be appreciated that by the steps described above, the theoretical compilation criteria are adjusted to obtain the final compilation criteria that can correct for erroneous compilation behavior to adjust the threshold voltage.
The invention provides a threshold voltage adjusting method of a memory chip, which has the following beneficial effects:
according to the invention, the signal compiling sequence consisting of the signal compiling behaviors at all times is obtained by collecting the gate voltage signals, the compiling standards and the compiling results of the memory chip at all times, the compiling discrete sequence consisting of the compiling discrete parameters is obtained based on the extracting characteristics of the signal compiling sequence, the theoretical compiling standards are generated by analyzing the compiling discrete sequence, and the theoretical compiling standards are regulated according to the existing error compiling behaviors of the memory chip, so that the final compiling standards are obtained, the threshold voltage can correct the error compiling behaviors and can adapt to the signal current situation of the memory chip, and the problems that the threshold voltage of the memory chip is in a fixed state, and the memory error is caused because the change of the gate voltage cannot be regulated timely in the prior art are solved.
Preferably, the step of collecting the gate voltage signal, the compiling standard and the compiling result of the memory chip at each moment, recording the gate voltage signal, the compiling standard and the compiling result corresponding to the same moment as a signal compiling behavior, and constructing each signal compiling behavior into a signal compiling sequence according to a time sequence includes:
s11: constructing a moment coordinate axis; the moment coordinate axes are provided with moment coordinate points which are sequentially arranged;
s12: continuously collecting the grid voltage signals, the compiling standards and the compiling results of the storage chip, and combining the grid voltage signals, the compiling standards and the compiling results corresponding to the same moment into the signal compiling behavior;
s13: and setting the signal compiling behavior on a time coordinate point corresponding to the time coordinate axis according to the time corresponding to the signal compiling behavior.
Specifically, a time coordinate axis is established to record gate voltage signals, compiling standards and compiling results of the memory chip at different moments, and by constructing the time coordinate axis, the working state of the memory chip can be recorded in a time axis mode, the time coordinate axis is provided with time coordinate points which are sequentially arranged, the recording of the working state of the memory chip can be ensured to be carried out according to time sequence, and a time logic sequence is provided for subsequent analysis.
More specifically, the gate voltage signal, the compiling standard and the compiling result of the memory chip are continuously collected, and the gate voltage signal, the compiling standard and the compiling result corresponding to the same moment are combined into the signal compiling behavior.
More specifically, setting the signal compiling behavior on a time coordinate point corresponding to a time coordinate axis according to a time corresponding to the signal compiling behavior; the acquired signal compiling behavior is corresponding to the corresponding time coordinate point and is arranged at the corresponding position on the time coordinate axis, so that the working states of the memory chip at different time can be clearly mapped to the time coordinate axis; by setting the signal compiling behavior on the moment coordinate point corresponding to the moment coordinate axis, the change of the working state of the memory chip along with time can be intuitively displayed, and an intuitive time clue is provided for subsequent analysis and calibration.
Preferably, the step of extracting features of compiling discrete parameters for each signal compiling behavior of the signal compiling sequence and arranging the compiling discrete parameters to obtain a compiling discrete sequence of the signal compiling sequence comprises:
s21: performing difference value calculation on the grid voltage signals of the signal compiling behaviors and the compiling standard to obtain compiling difference values of the signal compiling behaviors;
s22: summarizing the compiling difference values into discrete reference sets, calculating the ratio relation among the compiling difference values through the discrete reference sets, and generating discrete scales of the compiling difference values according to the calculated ratio relation among the compiling difference values;
s23: according to the compiling result of each signal compiling behavior, a positive sign or a negative sign is given to the corresponding discrete scale so as to generate compiling discrete parameters of the signal compiling behavior;
s24: and arranging the compiling discrete parameters to obtain the compiling discrete sequence.
Specifically, the discrete parameters are compiled to express the distance between the gate voltage signal and the compiling standard, and it should be noted that the distance is used for calculating the average parameter in the subsequent process, that is, the distance expressed by the discrete parameters is calculated and analyzed mutually, rather than obtaining a specific value, so that a new scale can be constructed according to the distance in the compiling behavior of each signal, and the scale is taken as the value of the discrete parameters.
More specifically, the gate voltage signal of each signal compiling behavior and the compiling standard are subjected to difference value calculation to obtain compiling difference values of each signal compiling behavior, each compiling difference value is summarized into a discrete reference set, the calculating of the ratio relation between each compiling difference value is carried out through the discrete reference set, and the discrete scale of each compiling difference value is generated according to the ratio relation between each compiling difference value obtained through calculation.
More specifically, a positive sign or a negative sign is given to the corresponding discrete scale according to the compiling result of each signal compiling behavior to generate compiling discrete parameters of the signal compiling behavior, each compiling discrete parameter is arranged to obtain a compiling discrete sequence, and compiling states of the memory chip at different moments can be intuitively presented by arranging the compiling discrete parameters, so that a more intuitive visual mode is provided for subsequent analysis and calibration.
Preferably, the step of dividing each of the compiling discrete parameters corresponding to different compiling results into a first parameter set and a second parameter set, and calculating theoretical features of a compiling standard according to the first parameter set and the second parameter set to obtain the theoretical compiling standard includes:
s31: dividing the coding discrete parameters with the forward marks into a first parameter set, and recording the average parameters of all the coding discrete parameters in the first parameter set as first average parameters;
s32: dividing the coding discrete parameters with the negative marks into a second parameter set, and recording the average parameters of all the coding discrete parameters in the second parameter set as second average parameters;
s33: generating a plurality of prediction standards adjacent to the existing compiling standard by using the depth search algorithm with the compiling standard in the existing compiling discrete sequence as a benchmark, calculating differences of the first average parameter and the second average parameter corresponding to each prediction standard, and recording each calculated difference as each prediction discrete difference;
s34: and performing contrast analysis on each predicted discrete difference, and taking the prediction standard corresponding to the predicted discrete difference with the minimum value as a theoretical compiling standard according to the result of the contrast analysis.
Specifically, the positive sign and the negative sign respectively correspond to two different compiling results of high level and low level, a first parameter set and a second parameter set are constructed according to the positive sign and the negative sign of compiling discrete parameters, and a first average parameter and a second average parameter are calculated, so that an average difference value between a grid voltage signal with the compiling results of high level and low level and a compiling standard is obtained.
More specifically, with the compiling standard in the existing compiling discrete sequence as a reference, generating a plurality of prediction standards adjacent to the existing compiling standard through a depth search algorithm, calculating differences between a first average parameter and a second average parameter corresponding to each prediction standard, and recording each calculated difference as each prediction discrete difference.
It should be noted that, the Depth-First Search (DFS) is an algorithm for graph or tree traversal, which starts from a starting node, searches forward along a path until the deepest node is reached, and then backtracks and searches for other nodes that are not accessed. This process will recursively proceed until all nodes are accessed.
In the above steps, a depth search algorithm is used to generate several prediction standards adjacent to the existing compilation standard, in particular: taking the existing compiling standard as a starting node, continuously selecting adjacent nodes as a predictive compiling standard based on the starting node, calculating the difference value between a first average parameter and a second average parameter under the condition of corresponding to the predictive compiling standard, taking the difference value as a predictive discrete difference of the predictive compiling standard, and taking the predictive standard corresponding to the predictive discrete difference with the minimum value as a theoretical compiling standard through the comparative analysis of each predictive discrete difference.
Preferably, the step of detecting a storage error of the storage chip and distinguishing each signal compiling behavior of the signal compiling sequence into an erroneous compiling behavior and a correct compiling behavior according to a result of the detection includes:
s41: a detection storage area is planned in the storage chip in advance and used for backing up storage contents, and the corresponding relation between the storage contents and the signal compiling behavior is recorded;
s42: and checking the storage contents in the storage chip according to the storage contents in the detection storage area at intervals of preset time to obtain a checking result, marking error storage contents and correct storage contents in the storage contents according to the checking result, taking signal compiling behaviors corresponding to the error storage contents as error compiling behaviors, and taking signal compiling behaviors corresponding to the correct storage contents as correct compiling behaviors.
Specifically, a detection storage area is planned in the storage chip, and is used for backing up the storage content, and recording the corresponding relation between the storage content and the signal compiling behavior for subsequent verification and analysis.
More specifically, the stored contents in the memory chip are checked at predetermined intervals according to the stored contents in the detection memory area to obtain a check result, error stored contents and correct stored contents are marked in the stored contents according to the check result, signal compiling behaviors corresponding to the error stored contents are used as error compiling behaviors, and signal compiling behaviors corresponding to the correct stored contents are used as correct compiling behaviors; the aim of this step is to check the content in the memory chip regularly, find out the condition that the memory content is not in conformity with the backup content, mark these wrong memory content, according to the marking result, can regard the corresponding signal compiling behavior as wrong compiling behavior, and regard the signal compiling behavior of the correct memory content as correct compiling behavior. Therefore, the reasons can be found out from the error compiling behavior and the correct compiling behavior, and the performance of the memory chip can be further analyzed and optimized.
Referring to fig. 2, in a second aspect, the present invention provides a threshold voltage adjusting apparatus of a memory chip, comprising:
the data acquisition module is used for acquiring gate voltage signals, compiling standards and compiling results of the memory chip at all moments, recording the mutually corresponding gate voltage signals, compiling standards and compiling results as primary signal compiling behaviors, and constructing all the signal compiling behaviors into a signal compiling sequence according to time sequences;
the data processing module is used for extracting the characteristics of the compiling discrete parameters of each signal compiling behavior of the signal compiling sequence and arranging the compiling discrete parameters of each signal compiling behavior of the signal compiling sequence to obtain the compiling discrete sequence of the signal compiling sequence; wherein the coding discrete parameter is used for describing the distance between the grid voltage signal and the coding standard in the signal coding behavior;
the data calculation module is used for calculating theoretical characteristics of the compiling standard based on the compiling discrete sequence so as to acquire the theoretical compiling standard; the theoretical compiling standard can enable the sum of compiling discrete parameters in the compiling discrete sequence to be minimum on the premise of keeping the compiling result of the signal compiling sequence unchanged;
the error detection module is used for detecting storage errors of the storage chip and distinguishing each signal compiling behavior of the signal compiling sequence into an error compiling behavior and a correct compiling behavior according to a detection result;
the first verification module is used for performing verification calculation on the error compiling behavior according to the theoretical compiling standard so as to judge whether the theoretical compiling standard can correct the error compiling behavior, if so, determining the theoretical compiling standard as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard;
and the second verification module is used for generating a plurality of preparation compiling standards by taking the theoretical compiling standard as a reference when the error compiling behavior cannot be corrected, respectively performing verification calculation on whether the error compiling behavior can be corrected for each preparation compiling standard, determining the preparation compiling standard which is closest to the theoretical compiling standard and can correct the error compiling behavior as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard.
In this embodiment, for specific implementation of each module in the above embodiment of the apparatus, please refer to the description in the above embodiment of the method, and no further description is given here.
In a third aspect, the present invention provides a threshold voltage adjustment device for a memory chip, comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor implementing the threshold voltage adjustment method for the memory chip according to any one of the first aspects when executing the computer program.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform a threshold voltage adjustment method of a memory chip as set forth in any one of the first aspects.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (8)
1. A threshold voltage adjustment method of a memory chip, comprising:
collecting gate voltage signals, compiling standards and compiling results of a storage chip at all moments, recording the gate voltage signals, the compiling standards and the compiling results corresponding to the same moment as a signal compiling behavior, and constructing all the signal compiling behaviors into a signal compiling sequence according to a time sequence;
feature extraction of compiling discrete parameters is carried out on each signal compiling behavior of the signal compiling sequence, and the compiling discrete parameters are arranged to obtain a compiling discrete sequence of the signal compiling sequence; wherein the coding discrete parameter is used for describing the distance between the grid voltage signal and the coding standard in the signal coding behavior;
dividing each compiling discrete parameter corresponding to different compiling results into a first parameter set and a second parameter set, and calculating theoretical characteristics of compiling standards according to the first parameter set and the second parameter set to obtain theoretical compiling standards; the theoretical compiling standard can enable the difference between average parameters of compiling discrete parameters in the first parameter set and the second parameter set to be the minimum value on the premise of keeping the compiling result of the signal compiling sequence unchanged;
detecting storage errors of the storage chip, and distinguishing each signal compiling behavior of the signal compiling sequence into an error compiling behavior and a correct compiling behavior according to a detection result;
performing verification calculation on the error compiling behavior according to the theoretical compiling standard to judge whether the theoretical compiling standard can correct the error compiling behavior, if so, determining the theoretical compiling standard as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard;
if the error compiling behavior cannot be corrected, generating a plurality of preliminary compiling standards based on the theoretical compiling standard, respectively performing verification calculation on whether the error compiling behavior can be corrected for each preliminary compiling standard, determining the preliminary compiling standard which is closest to the theoretical compiling standard and can correct the error compiling behavior as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard.
2. The method for adjusting threshold voltage of a memory chip according to claim 1, wherein the steps of collecting gate voltage signals, compiling criteria and compiling results of the memory chip at respective times, recording the gate voltage signals, compiling criteria and compiling results corresponding to the same time as a signal compiling behavior, and constructing each of the signal compiling behaviors as a signal compiling sequence according to a time sequence comprise:
constructing a moment coordinate axis; the moment coordinate axes are provided with moment coordinate points which are sequentially arranged;
continuously collecting the grid voltage signals, the compiling standards and the compiling results of the storage chip, and combining the grid voltage signals, the compiling standards and the compiling results corresponding to the same moment into the signal compiling behavior;
and setting the signal compiling behavior on a time coordinate point corresponding to the time coordinate axis according to the time corresponding to the signal compiling behavior.
3. The method for adjusting threshold voltage of a memory chip according to claim 1, wherein the steps of extracting features of coding discrete parameters for each signal coding behavior of the signal coding sequence and arranging the coding discrete parameters to obtain a coding discrete sequence of the signal coding sequence comprise:
performing difference value calculation on the grid voltage signals of the signal compiling behaviors and the compiling standard to obtain compiling difference values of the signal compiling behaviors;
summarizing the compiling difference values into discrete reference sets, calculating the ratio relation among the compiling difference values through the discrete reference sets, and generating discrete scales of the compiling difference values according to the calculated ratio relation among the compiling difference values;
according to the compiling result of each signal compiling behavior, a positive sign or a negative sign is given to the corresponding discrete scale so as to generate compiling discrete parameters of the signal compiling behavior;
and arranging the compiling discrete parameters to obtain the compiling discrete sequence.
4. The method for adjusting threshold voltage of a memory chip according to claim 3, wherein the step of dividing each of the compiled discrete parameters corresponding to different compiling results into a first parameter set and a second parameter set, and calculating theoretical characteristics of compiling criteria based on the first parameter set and the second parameter set to obtain the theoretical compiling criteria comprises:
dividing the coding discrete parameters with the forward marks into a first parameter set, and recording the average parameters of all the coding discrete parameters in the first parameter set as first average parameters;
dividing the coding discrete parameters with the negative marks into a second parameter set, and recording the average parameters of all the coding discrete parameters in the second parameter set as second average parameters;
generating a plurality of prediction standards adjacent to the existing compiling standard by using the depth search algorithm with the compiling standard in the existing compiling discrete sequence as a benchmark, calculating differences of the first average parameter and the second average parameter corresponding to each prediction standard, and recording each calculated difference as each prediction discrete difference;
and performing contrast analysis on each predicted discrete difference, and taking the prediction standard corresponding to the predicted discrete difference with the minimum value as a theoretical compiling standard according to the result of the contrast analysis.
5. The method for adjusting threshold voltage of a memory chip according to claim 1, wherein the step of detecting a memory error of the memory chip and distinguishing each signal coding behavior of the signal coding sequence into an erroneous coding behavior and a correct coding behavior according to a result of the detection comprises:
a detection storage area is planned in the storage chip in advance and used for backing up storage contents, and the corresponding relation between the storage contents and the signal compiling behavior is recorded;
and checking the storage contents in the storage chip according to the storage contents in the detection storage area at intervals of preset time to obtain a checking result, marking error storage contents and correct storage contents in the storage contents according to the checking result, taking signal compiling behaviors corresponding to the error storage contents as error compiling behaviors, and taking signal compiling behaviors corresponding to the correct storage contents as correct compiling behaviors.
6. A threshold voltage adjusting apparatus of a memory chip, comprising:
the data acquisition module is used for acquiring gate voltage signals, compiling standards and compiling results of the memory chip at all moments, recording the mutually corresponding gate voltage signals, compiling standards and compiling results as primary signal compiling behaviors, and constructing all the signal compiling behaviors into a signal compiling sequence according to time sequences;
the data processing module is used for extracting the characteristics of the compiling discrete parameters of each signal compiling behavior of the signal compiling sequence and arranging the compiling discrete parameters of each signal compiling behavior of the signal compiling sequence to obtain the compiling discrete sequence of the signal compiling sequence; wherein the coding discrete parameter is used for describing the distance between the grid voltage signal and the coding standard in the signal coding behavior;
the data calculation module is used for calculating theoretical characteristics of the compiling standard based on the compiling discrete sequence so as to acquire the theoretical compiling standard; the theoretical compiling standard can enable the sum of compiling discrete parameters in the compiling discrete sequence to be minimum on the premise of keeping the compiling result of the signal compiling sequence unchanged;
the error detection module is used for detecting storage errors of the storage chip and distinguishing each signal compiling behavior of the signal compiling sequence into an error compiling behavior and a correct compiling behavior according to a detection result;
the first verification module is used for performing verification calculation on the error compiling behavior according to the theoretical compiling standard so as to judge whether the theoretical compiling standard can correct the error compiling behavior, if so, determining the theoretical compiling standard as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard;
and the second verification module is used for generating a plurality of preparation compiling standards by taking the theoretical compiling standard as a reference when the error compiling behavior cannot be corrected, respectively performing verification calculation on whether the error compiling behavior can be corrected for each preparation compiling standard, determining the preparation compiling standard which is closest to the theoretical compiling standard and can correct the error compiling behavior as a final compiling standard, and adjusting the threshold voltage according to the final compiling standard.
7. A threshold voltage adjustment device for a memory chip comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that the processor implements a threshold voltage adjustment method for a memory chip according to any one of claims 1 to 5 when executing the computer program.
8. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when being executed by a processor, causes the processor to perform a threshold voltage adjustment method of a memory chip according to any of claims 1-5.
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| CA2240584A1 (en) * | 1998-06-12 | 1999-12-12 | Ibm Canada Limited - Ibm Canada Limitee | Compile-time data dependency verification |
| CN101601094A (en) * | 2006-10-30 | 2009-12-09 | 爱诺彼得技术有限责任公司 | Use the method for a plurality of thresholding reading cells |
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