CN117540669A - Method and device for processing structured data of digital circuit - Google Patents
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Abstract
The present disclosure relates to a structured data processing method and apparatus for a digital circuit. The method comprises the following steps: acquiring initial structured data to be processed, wherein the structured data comprises initial intensity data and initial signal data; extracting the initial signal data from the initial structured data through a first logical operation; calculating a digital circuit based on the initial signal data to generate target signal data; performing data filling on the target signal data through a second logic operation to generate target structured data; and performing subsequent digital circuit calculation based on the target structured data. The structured data processing method and the structured data processing device for the digital circuit can realize extraction and backfilling of data through logic operation in the calculation process of the digital circuit, avoid the condition of resource waste and low efficiency caused by cyclic single data access in the prior art, and improve the overall calculation efficiency.
Description
Technical Field
The present disclosure relates to the field of digital circuits, and in particular, to a method and apparatus for processing structured data of a digital circuit.
Background
In the calculation of the digital circuit, a large number of digital signals need to be calculated and simulated, and for signals with voltage intensity (strngth), the strngth voltage intensity value and the signal value (0, 1, x, z) need to be processed together in the simulation process, so that the influence on the performance of the simulation is relatively large due to the storage data structure and the data access speed of the signals.
Currently, a more widely used access structure is a storage manner based on CHAR. The CHAR data structure stores the emulated signal as shown in fig. 1, which structure can store one signal with one CHAR, i.e. 8 bits. Wherein the high and low intensity voltage values each have 7 intensity steps, the voltage intensity data can be represented by three bit combinations (1, 2,3,4,5,6, 7), and the signal data contains 4 values, which can be represented by two bit combinations (0, 1, x, z).
In the prior art, during simulation calculation, the data content to be simulated is extracted from the CHAR by a cyclic reading mode, and one binary data bit in the CHAR is read each time, and then the voltage strength signal is read first, and then the signal data is read.
In the simulation calculation process of the digital circuit, the use ratio of the intensity data is lower, the use ratio of the signal data is higher, and the voltage intensity data needs to be read first and then the signal data needs to be read when the signal data is read each time because of the problem of the storage structure of CHAR. In the circuit simulation process, the access frequency to the bottom data is very high, and a large amount of useless voltage intensity data needs to be taken out each time in a single data sequential cyclic access mode, so that a large amount of system resources are wasted in the useless data, and the overall calculation simulation performance is affected.
Therefore, a new method and apparatus for structured data processing of digital circuits is needed.
The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
In view of this, the present application provides a method and an apparatus for processing structured data of a digital circuit, which can implement extraction and backfilling of data through logic operation in the calculation process of the digital circuit, so as to avoid resource waste and low efficiency caused by cyclic single data access in the prior art, and improve overall calculation efficiency.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.
According to an aspect of the present application, there is provided a structured data processing method of a digital circuit, the method comprising: acquiring initial structured data to be processed, wherein the structured data comprises initial intensity data and initial signal data; extracting the initial signal data from the initial structured data through a first logical operation; calculating a digital circuit based on the initial signal data to generate target signal data; performing data filling on the target signal data through a second logic operation to generate target structured data; and performing subsequent digital circuit calculation based on the target structured data.
In an exemplary embodiment of the present application, further comprising: acquiring input signal data of a digital circuit; and storing the input signal data according to a preset structure to generate the initial structured data.
In an exemplary embodiment of the present application, storing the input signal data according to a preset structure to generate the initial structured data includes: acquiring data processing parameters of an operating system; acquiring the data length of the input signal data; determining a data structure according to the data processing parameters and the data length; generating the initial structured data from the data structure and the input signal data.
In an exemplary embodiment of the present application, extracting the initial signal data from the initial structured data through a first logical operation includes: initializing the initial structured data; performing the first logical operation on the initial structured data; and extracting the initial signal data from the result of the first logical operation.
In an exemplary embodiment of the present application, performing a first logical operation on the initial structured data includes: performing mask removal operation on the initial structured data to generate a first operation result; performing multiple shifting operations on the first operation result to generate a second operation result; and carrying out mask value-taking operation on the second operation result.
In an exemplary embodiment of the present application, the calculating of the digital circuit based on the initial signal data generates target signal data, including: and calculating the digital circuit in parallel based on the initial signal data to generate the target signal data.
In an exemplary embodiment of the present application, the data-stuffing the target signal data by a second logical operation to generate target structured data includes: acquiring a target array generated in advance; performing the second logical operation on the target signal data based on the target array; and generating the target structured data according to the result of the second logical operation.
In an exemplary embodiment of the present application, before obtaining the target array generated in advance, the method further includes: and generating the target array according to the data structure of the initial structured data.
In an exemplary embodiment of the present application, performing the second logical operation on the target signal data based on the target array includes: performing mask removal operation on the target signal data to generate a third operation result; and carrying out logical OR operation on the third operation result and the target data.
In one exemplary embodiment of the present application, performing subsequent digital circuit calculations based on the target structured data includes: generating target intensity data from the initial intensity data during computation of the digital circuit; updating the target structured data by the target intensity data; and generating a digital circuit calculation result based on the target structured data.
According to an aspect of the present application, there is provided a structured data processing apparatus for a digital circuit, the apparatus comprising: the data module is used for acquiring initial structured data to be processed, wherein the structured data comprises initial strength data and initial signal data; the first logic module is used for extracting the initial signal data from the initial structural data through first logic operation; the target module is used for calculating a digital circuit based on the initial signal data and generating target signal data; the second logic module is used for performing data filling on the target signal data through a second logic operation to generate target structured data; and the calculation module is used for carrying out subsequent digital circuit calculation based on the target structured data.
According to an aspect of the present application, there is provided an electronic device including: one or more processors; a storage means for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the methods as described above.
According to an aspect of the present application, a computer-readable medium is presented, on which a computer program is stored, which program, when being executed by a processor, implements a method as described above.
According to the method and the device for processing the structured data of the digital circuit, the initial structured data to be processed is obtained, and the structured data comprises initial intensity data and initial signal data; extracting the initial signal data from the initial structured data through a first logical operation; calculating a digital circuit based on the initial signal data to generate target signal data; performing data filling on the target signal data through a second logic operation to generate target structured data; based on the mode of carrying out subsequent digital circuit calculation on the target structured data, the extraction and backfilling of the data can be realized through logic operation in the digital circuit calculation process, the condition of resource waste and low efficiency caused by cyclic single data access in the prior art is avoided, and the overall calculation efficiency is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. The drawings described below are only some embodiments of the present application and other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a CHAR data structure storage emulation signal.
Fig. 2 is a flow chart illustrating a method of structured data processing for a digital circuit according to another exemplary embodiment.
FIG. 3 is a schematic diagram of a VALTYPE_LOGIC4 memory array in a method for processing structured data of a digital circuit according to an exemplary embodiment.
FIG. 4 is a schematic diagram of a VALTYPE_LOGIC8 memory array in a method for processing structured data of a digital circuit according to an exemplary embodiment.
FIG. 5 is a diagram illustrating a memory arrangement of VALTYPE_LOGIC64 in a method for processing structured data of a digital circuit according to an exemplary embodiment.
Fig. 6 is a schematic diagram illustrating a valtype_logic memory arrangement in a method for processing structured data of a digital circuit according to an exemplary embodiment.
Fig. 7 is a flow chart illustrating a method of structured data processing for a digital circuit according to another exemplary embodiment.
Fig. 8 is a schematic diagram illustrating a method of structured data processing for a digital circuit according to another exemplary embodiment.
Fig. 9 is a flow chart illustrating a method of structured data processing for a digital circuit according to another exemplary embodiment.
Fig. 10 is a schematic diagram illustrating a method of structured data processing for a digital circuit according to another exemplary embodiment.
FIG. 11 is a block diagram of a structured data processing arrangement of digital circuitry, according to an exemplary embodiment.
Fig. 12 is a block diagram of an electronic device, according to an example embodiment.
Fig. 13 is a block diagram of a computer-readable medium shown according to an example embodiment.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present application concept. As used herein, the term "and/or" includes any one of the associated listed items and all combinations of one or more.
Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments, and that the modules or flows in the drawings are not necessarily required to practice the present application, and therefore, should not be taken to limit the scope of the present application.
Fig. 2 is a flow chart illustrating a method of structured data processing for a digital circuit according to an exemplary embodiment. The method 20 for processing structured data of a digital circuit at least comprises steps S202 to S208.
As shown in fig. 2, in S202, initial structured data to be processed is acquired, where the structured data includes initial intensity data and initial signal data.
In one embodiment, further comprising: acquiring input signal data of a digital circuit; and storing the input signal data according to a preset structure to generate the initial structured data.
More specifically, data processing parameters of the operating system may be obtained; acquiring the data length of the input signal data; determining a data structure according to the data processing parameters and the data length; generating the initial structured data from the data structure and the input signal data.
The processing parameters of the operating system may be, for example, the number of bits calculated by the operating system, which may typically be 32 bits, 64 bits, or other bits. In the embodiment of the present application, a 64-bit operating system is taken as an example for illustration, and it can be understood that the technical solution of the present application may also be applied to computing systems with other bits. The number of operating system bits depends on the instruction set architecture, and if the instruction set supports 64-bit data operations, then 64-bit registers (e.g., RAX) are used in writing the operating system.
The signal length of the input signal may be the bit number occupied by the 2-ary signal of the input signal, and in this application, different signal lengths correspond to different data structures.
As shown in fig. 3 to fig. 6, when the number of bits of the operating system is 64, that is, the system alignment mode (alignment) is 64 bits, according to the data length of the upper layer resolution of the functional simulation to be processed, the data structure of the present application may include four kinds of following:
type 1 (valtype_logic 4): for storing data of less than 5 bits of the input signal;
type 2 (valtype_logic 8): for storing data of less than 9 bits of the input signal;
type 3 (valtype_logic 64): for storing data of less than 65 bits of the input signal;
type 4 (vlatiype_logic_pointer): for storing data with an input signal greater than 64 bits.
In the embodiment of the present application, the above-mentioned type classification principle is: the data occupies less storage space and is convenient for parallelization access.
It should be noted that, during the simulation of the data circuit, the New Value (New Value) of the data calculated by the current simulation step and the old Value (Value) of the data stored previously are arranged adjacently from low to high in the memory. If the data length is less than 4,8, 64 or greater than 64 but not a multiple of 64, the existence of the spare portion (underfill) can take any value during the data access process.
The partition type 4 is mainly used for storing the extracted data or the data to be filled by using an array aiming at a large number larger than 64 bits.
It will be appreciated that if the alignment of the system is 32 bits, the data structure and algorithm may be adapted accordingly to the above criteria.
In S204, the initial signal data is extracted from the initial structured data by a first logical operation. The initial structured data may be initialized, for example; performing the first logical operation on the initial structured data; and extracting the initial signal data from the result of the first logical operation.
The content of "extracting the initial signal data from the initial structured data through the first logical operation" will be described in detail in the corresponding embodiment of fig. 7.
In S206, the digital circuit is calculated based on the initial signal data, and target signal data is generated. The calculation of the digital circuit may be performed in parallel based on the initial signal data, generating the target signal data.
In the actual simulation process, initial signal data can be extracted through first logic operation, simulation calculation of a digital circuit is carried out on the initial signal data, in the simulation iteration process, the result of the current iteration process is stored in a new value of a data structure, the value of the new value is compared with the value of the value, and when the value of the new value is different from the value of the value, the value of the new value is replaced by the value of the value. When the two are the same, the replacement is not needed, and the next iterative calculation can be directly carried out.
In S208, the target signal data is data-padded to generate target structured data through a second logical operation. A target array generated in advance can be obtained; performing the second logical operation on the target signal data based on the target array; and generating the target structured data according to the result of the second logical operation.
The content of "data-stuffing the target signal data by the second logic operation to generate the target structured data" will be described in detail in the corresponding embodiment of fig. 9.
In S210, a subsequent digital circuit calculation is performed based on the target structured data. Generating target intensity data from the initial intensity data during computation of the digital circuit; updating the target structured data by the target intensity data; and generating a digital circuit calculation result based on the target structured data.
In the simulation calculation of the data circuit, the intensity data can also be calculated in the middle process, and of course, the intensity data can also be not calculated in the simulation, and whether the intensity data needs to be calculated or not is determined according to the simulation conditions.
When the intensity data also participates in the simulation, the intensity data is updated to the target structured data and output as the simulation result.
According to the method for processing the structured data of the digital circuit, the initial structured data to be processed is obtained, wherein the structured data comprises initial intensity data and initial signal data; extracting the initial signal data from the initial structured data through a first logical operation; calculating a digital circuit based on the initial signal data to generate target signal data; performing data filling on the target signal data through a second logic operation to generate target structured data; based on the mode of carrying out subsequent digital circuit calculation on the target structured data, the extraction and backfilling of the data can be realized through logic operation in the digital circuit calculation process, the condition of resource waste and low efficiency caused by cyclic single data access in the prior art is avoided, and the overall calculation efficiency is improved.
It should be clearly understood that this application describes how to make and use particular examples, but the principles of this application are not limited to any details of these examples. Rather, these principles can be applied to many other embodiments based on the teachings of the present disclosure.
Fig. 7 is a flow chart illustrating a method of structured data processing for a digital circuit according to another exemplary embodiment. The flow 70 shown in fig. 7 is a detailed description of S204 "extract the initial signal data from the initial structured data by the first logical operation" in the flow shown in fig. 2.
As shown in fig. 7, in S702, the initial structured data is initialized.
In S704, the first logical operation is performed on the initial structured data. For example, mask removal operation may be performed on the initial structured data to generate a first operation result; performing multiple shifting operations on the first operation result to generate a second operation result; and carrying out mask value-taking operation on the second operation result.
In S706, the initial signal data is extracted from the result of the first logical operation.
In one specific application, the first LOGIC operation is described in detail with respect to the type VALTYPE_LOGIC8, assuming that the initial structured data length is 8 bits, the 8-bit signal data can be fetched by 3 left shift operations, 3 bit OR operations, and 2 mask operations.
A schematic diagram of the fetched data is shown in fig. 8, and the corresponding pseudo code is as follows:
and (5) storing a data current pointer by using the// p8 Char.
The// example does not include an x/z signal state.
Uint64_t tmp=0; operation of// initialization
01:u_char data_char＝0；
02:tmp= (p 8 char) &0x0101010101010101; removal of the strength value by the first mask
03:tmp|=tmp > >7; first shift//
04:tmp|=tmp > >14; second shift
05 data_char= (tmp|tmp > > 28) &0xFF; the third shift, and the second mask value.
Fig. 9 is a flow chart illustrating a method of structured data processing for a digital circuit according to another exemplary embodiment. The process 90 shown in fig. 9 is a detailed description of "data-stuffing the target signal data with the second logical operation to generate the target structured data" in the process S208 shown in fig. 2.
As shown in fig. 9, in S902, the target array is generated according to the data structure of the initial structured data.
In S904, a target array generated in advance is acquired.
In S906, the second logical operation is performed on the target signal data based on the target array. For example, mask removal operation may be performed on the target signal data to generate a third operation result; and carrying out logical OR operation on the third operation result and the target data.
In S908, the target structured data is generated according to the result of the second logical operation.
As shown in fig. 10, the range that can be expressed for one number of 8-bit lengths (char) is 0 to 255. If the numbers in the range are filled with the last bit of each of the 64-bit length (8 char) numbers and the rest of the bits are all filled with 0 s, it can be proved that the numbers 0 to 255 and the 64-bit length number (8 char divided by the rest of the last bit are filled with 0 s) are in one-to-one correspondence. A look-up table of such correspondence can thus be pre-established, filling 8 signal values at a time into the data bits. Different target arrays may be established for char of different lengths.
In one embodiment, illustrated by way of example with the VALTYPE_LOGIC8 type, assume that the data length is 8 bits, the pseudo code is as follows:
a predetermined array// 0xFCFCFCFCFCFCFC corresponding to 8 bits of length (char) of/(char 2long_table [255]
The// example does not include an x/z signal state.
00:*p8char＝(*p8char&0xFCFCFCFCFCFCFCFC)|
char2long_table[data_char]。
According to the structured data processing method of the digital circuit, in the calculation process of the digital circuit, the extraction and backfilling of data can be realized through logic operation, the situations of resource waste and low efficiency caused by cyclic single data access in the prior art are avoided, and the overall calculation efficiency is improved. The simulation running efficiency is greatly improved by combining parallel access data, and the complexity is reduced from O (n) to O (n/8) especially for a large number of operations.
Those skilled in the art will appreciate that all or part of the steps implementing the above described embodiments are implemented as a computer program executed by a CPU. When executed by a CPU, performs the functions defined by the above methods provided herein. The program may be stored in a computer readable storage medium, which may be a read-only memory, a magnetic disk or an optical disk, etc.
Furthermore, it should be noted that the above-described figures are merely illustrative of the processes involved in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.
The following are device embodiments of the present application, which may be used to perform method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.
FIG. 11 is a block diagram of a structured data processing arrangement of digital circuitry, according to an exemplary embodiment. As shown in fig. 11, the structured data processing apparatus 110 of the digital circuit includes: the data module 1102, the first logic module 1104, the target module 1106, the second logic module 1108, the calculation module 1110, and the structured data processing apparatus 110 of digital circuits may further include: a structural module 1112.
The data module 1102 is configured to obtain initial structured data to be processed, where the structured data includes initial intensity data and initial signal data;
the first logic module 1104 is configured to extract the initial signal data from the initial structured data through a first logic operation; the first logic module 1104 is further configured to initialize the initial structured data; performing the first logical operation on the initial structured data; and extracting the initial signal data from the result of the first logical operation.
The target module 1106 is configured to perform calculation of a digital circuit based on the initial signal data, and generate target signal data; the target module 1106 is further configured to perform computation of the digital circuit in parallel based on the initial signal data, and generate the target signal data.
The second logic module 1108 is configured to perform data filling on the target signal data through a second logic operation to generate target structured data; the second logic module 1108 is further configured to obtain a pre-generated target array; performing the second logical operation on the target signal data based on the target array; and generating the target structured data according to the result of the second logical operation.
The calculation module 1110 is configured to perform subsequent digital circuit calculations based on the target structured data. The calculation module 1110 is further configured to generate target intensity data from the initial intensity data during calculation of the digital circuit; updating the target structured data by the target intensity data; and generating a digital circuit calculation result based on the target structured data.
The structure module 1112 is configured to obtain input signal data of the digital circuit; and storing the input signal data according to a preset structure to generate the initial structured data. The structure module 1012 is further used to obtain data processing parameters of the operating system; acquiring the data length of the input signal data; determining a data structure according to the data processing parameters and the data length; generating the initial structured data from the data structure and the input signal data.
According to the structured data processing device of the digital circuit, initial structured data to be processed is obtained, wherein the structured data comprises initial intensity data and initial signal data; extracting the initial signal data from the initial structured data through a first logical operation; calculating a digital circuit based on the initial signal data to generate target signal data; performing data filling on the target signal data through a second logic operation to generate target structured data; based on the mode of carrying out subsequent digital circuit calculation on the target structured data, the extraction and backfilling of the data can be realized through logic operation in the digital circuit calculation process, the condition of resource waste and low efficiency caused by cyclic single data access in the prior art is avoided, and the overall calculation efficiency is improved.
Fig. 12 is a block diagram of an electronic device, according to an example embodiment.
An electronic device 1200 according to this embodiment of the present application is described below with reference to fig. 12. The electronic device 1200 shown in fig. 12 is merely an example, and should not be construed as limiting the functionality and scope of use of the embodiments herein.
As shown in fig. 12, the electronic device 1200 is in the form of a general purpose computing device. Components of electronic device 1200 may include, but are not limited to: at least one processing unit 1210, at least one memory unit 1220, a bus 1230 connecting the different system components (including memory unit 1220 and processing unit 1210), a display unit 1240, and the like.
Wherein the storage unit stores program code that is executable by the processing unit 1210 such that the processing unit 1210 performs steps described in the present specification according to various exemplary embodiments of the present application. For example, the processing unit 1210 may perform the steps as shown in fig. 2, 7, 9.
The memory unit 1220 may include readable media in the form of volatile memory units, such as Random Access Memory (RAM) 12201 and/or cache memory 12202, and may further include Read Only Memory (ROM) 12203.
The storage unit 1220 may also include a program/utility 12204 having a set (at least one) of program modules 12205, such program modules 12205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
Bus 1230 may be a local bus representing one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or using any of a variety of bus architectures.
The electronic device 1200 may also communicate with one or more external devices 1200' (e.g., keyboard, pointing device, bluetooth device, etc.), devices that enable a user to interact with the electronic device 1200, and/or any devices (e.g., routers, modems, etc.) that the electronic device 1200 can communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 1250. Also, the electronic device 1200 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the internet through the network adapter 1260. The network adapter 1260 may communicate with other modules of the electronic device 1200 over the bus 1230. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 1200, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, as shown in fig. 13, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a server, or a network device, etc.) to perform the above-described method according to the embodiments of the present application.
The software product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable storage medium may also be any readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
The computer-readable medium carries one or more programs, which when executed by one of the devices, cause the computer-readable medium to perform the functions of: acquiring initial structured data to be processed, wherein the structured data comprises initial intensity data and initial signal data; extracting the initial signal data from the initial structured data through a first logical operation; calculating a digital circuit based on the initial signal data to generate target signal data; performing data filling on the target signal data through a second logic operation to generate target structured data; and performing subsequent digital circuit calculation based on the target structured data. The computer readable medium also implements the following functions: acquiring input signal data of a digital circuit; and storing the input signal data according to a preset structure to generate the initial structured data.
Those skilled in the art will appreciate that the modules may be distributed throughout several devices as described in the embodiments, and that corresponding variations may be implemented in one or more devices that are unique to the embodiments. The modules of the above embodiments may be combined into one module, or may be further split into a plurality of sub-modules.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or in combination with the necessary hardware. Thus, the technical solutions according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and include several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the methods according to the embodiments of the present application.
Exemplary embodiments of the present application are specifically illustrated and described above. It is to be understood that this application is not limited to the details of construction, arrangement or method of implementation described herein; on the contrary, the application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (11)
1. A method of structured data processing for a digital circuit, comprising:
acquiring initial structured data to be processed, wherein the structured data comprises initial intensity data and initial signal data;
extracting the initial signal data from the initial structured data through a first logical operation;
calculating a digital circuit based on the initial signal data to generate target signal data;
performing data filling on the target signal data through a second logic operation to generate target structured data;
and performing subsequent digital circuit calculation based on the target structured data.
2. The method as recited in claim 1, further comprising:
acquiring input signal data of a digital circuit;
and storing the input signal data according to a preset structure to generate the initial structured data.
3. The method of claim 2, wherein storing the input signal data in a preset structure to generate the initial structured data comprises:
acquiring data processing parameters of an operating system;
acquiring the data length of the input signal data;
determining a data structure according to the data processing parameters and the data length;
generating the initial structured data from the data structure and the input signal data.
4. The method of claim 1, wherein extracting the initial signal data from the initial structured data by a first logical operation comprises:
performing the first logical operation on the initial structured data;
and extracting the initial signal data from the result of the first logical operation.
5. The method of claim 4, wherein performing a first logical operation on the initially structured data comprises:
performing mask removal operation on the initial structured data to generate a first operation result;
performing multiple shifting operations on the first operation result to generate a second operation result;
and carrying out mask value-taking operation on the second operation result.
6. The method of claim 1, wherein performing computation of a digital circuit based on the initial signal data to generate target signal data comprises:
and calculating the digital circuit in parallel based on the initial signal data to generate the target signal data.
7. The method of claim 1, wherein data populating the target signal data with a second logical operation to generate target structured data comprises:
acquiring a target array generated in advance;
performing the second logical operation on the target signal data based on the target array;
and generating the target structured data according to the result of the second logical operation.
8. The method of claim 7, further comprising, prior to obtaining the pre-generated target array:
and generating the target array according to the data structure of the initial structured data.
9. The method of claim 7, wherein performing the second logical operation on the target signal data based on the target array comprises:
performing mask removal operation on the target signal data to generate a third operation result;
and carrying out logical OR operation on the third operation result and the target data.
10. The method of claim 1, wherein performing subsequent digital circuit calculations based on the target structured data comprises:
generating target intensity data from the initial intensity data during computation of the digital circuit;
updating the target structured data by the target intensity data;
and generating a digital circuit calculation result based on the target structured data.
11. A structured data processing apparatus for a digital circuit, comprising:
the data module is used for acquiring initial structured data to be processed, wherein the structured data comprises initial strength data and initial signal data;
the first logic module is used for extracting the initial signal data from the initial structural data through first logic operation;
the target module is used for calculating a digital circuit based on the initial signal data and generating target signal data;
the second logic module is used for performing data filling on the target signal data through a second logic operation to generate target structured data;
and the calculation module is used for carrying out subsequent digital circuit calculation based on the target structured data.
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