CN117494638A - Verification method and verification platform for chip functions, electronic equipment and storage medium - Google Patents

Verification method and verification platform for chip functions, electronic equipment and storage medium Download PDF

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Publication number
CN117494638A
CN117494638A CN202311493099.9A CN202311493099A CN117494638A CN 117494638 A CN117494638 A CN 117494638A CN 202311493099 A CN202311493099 A CN 202311493099A CN 117494638 A CN117494638 A CN 117494638A
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expected
output result
chip
verification
actual
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请求不公布姓名
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Moore Thread Intelligence Technology Shanghai Co ltd
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Moore Thread Intelligence Technology Shanghai Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

Abstract

The disclosure relates to the technical field of integrated circuits, and provides a chip function verification method, a verification platform, electronic equipment and a storage medium, wherein the method comprises the following steps: inputting an excitation signal into a chip to be tested, wherein the chip to be tested is in a code form in a verification platform; receiving an actual output result of the chip to be tested; detecting the type of the expected output result corresponding to the excitation signal, wherein the verification modes corresponding to the expected output results of different types are different; and verifying the expected output result and the actual output result according to a verification mode corresponding to the expected output result, and determining whether the chip to be tested is normal in function. The verification method for the chip function of the embodiment of the disclosure can verify according to the verification mode corresponding to the detected type of the expected output result, realizes automatic adjustment of the verification mode according to specific excitation, can improve the flexibility of verification of the chip function, and can also improve the recognition accuracy of simulation errors by using the corresponding verification mode.

Description

Verification method and verification platform for chip functions, electronic equipment and storage medium
Technical Field
The disclosure relates to the technical field of integrated circuits, and in particular relates to a chip function verification method, a verification platform, electronic equipment and a storage medium.
Background
In the development process of the chip, simulation and verification are very important links, wherein the verification part of the core inputs an excitation signal into the chip to be tested before the chip is put into the chip, and whether the chip meets the requirement is judged according to whether the actual output of the chip to be tested is consistent with the expected output, which is a serious problem in the simulation and verification process. Since the verified object, i.e. the chip, may have multiple output formats, the requirements for the mechanisms of chip simulation and verification are also increasing. The existing chip simulation and verification mechanism is single, cannot well adapt to verification requirements under different output formats, and even can cause misjudgment of simulation errors, so that the defects of poor flexibility and reduction of recognition accuracy of the simulation errors exist.
Therefore, how to improve the flexibility of the verification of the chip function and improve the recognition accuracy of the simulation error becomes a problem to be solved in the art.
Disclosure of Invention
In view of this, the present disclosure proposes a method, a platform, an electronic device, and a storage medium for verifying a chip function, where different verification methods are set for different types of expected output results, so that verification can be performed according to verification methods corresponding to the types of detected expected output results during verification, automatic adjustment of the verification methods according to specific excitation is implemented, flexibility of verification of the chip function can be improved, and recognition accuracy of simulation errors can also be improved by using corresponding verification methods.
According to an aspect of the present disclosure, there is provided a method for verifying a chip function, the method being applied to a platform for verifying a chip function, the method including: inputting an excitation signal into a chip to be tested, wherein the chip to be tested is in a code form in the verification platform; receiving an actual output result of the chip to be tested; detecting the type of the expected output result corresponding to the excitation signal, wherein verification modes corresponding to the expected output results of different types are different; and verifying the expected output result and the actual output result according to a verification mode corresponding to the expected output result, and determining whether the function of the chip to be tested is normal.
In one possible implementation, the types of expected output results include a first type and a second type, the first type of expected output results including an expected raw data file and an expected image, the second type of expected output results including an expected raw data file.
In one possible implementation, when detecting that the type of the expected output result is the first type and the expected image is not present, the method further includes: and generating the expected image according to the expected original data file.
In one possible implementation manner, when the type of the expected output result is the first type or the second type, the verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, and determining whether the chip to be tested functions normally includes: detecting whether the actual output result comprises an actual original data file; when the actual output result comprises the actual original data file, comparing the actual original data file with the expected original data file; and when the comparison is successful, determining that the chip to be tested is normal in function.
In one possible implementation manner, when the type of the expected output result is the first type or the second type, the verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, to determine whether the chip to be tested functions normally, further includes: and when the actual output result does not comprise the actual original data file, determining that the chip to be tested is abnormal in function, and outputting a signal indicating simulation errors.
In one possible implementation manner, the verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, to determine whether the chip to be tested functions normally, further includes: determining that the chip to be tested is abnormal in function when the comparison of the actual original data file and the expected original data file fails and the type of the expected output result is the second type; and generating and outputting a first comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when the actual original data file and the expected original data file are compared.
In one possible implementation manner, the verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, to determine whether the chip to be tested functions normally, further includes: when the actual original data file and the expected original data file are failed to be compared and the type of the expected output result is the first type, comparing an actual image with the expected image; and when the actual image and the expected image are successfully compared, determining that the chip to be tested is normal in function.
In one possible implementation manner, the verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, to determine whether the chip to be tested functions normally, further includes: determining that the chip to be tested is abnormal in function when the comparison between the actual image and the expected image fails; and generating and outputting a first comparison text file and a second comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual original data file and the expected original data file, and the second comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual image and the expected image.
According to another aspect of the present disclosure, there is provided a verification platform for chip functions, including: the input module is used for inputting an excitation signal into a chip to be tested, and the chip to be tested is in a code form in the verification platform; the receiving module is used for receiving the actual output result of the chip to be tested; the detection module is used for detecting the type of the expected output result corresponding to the excitation signal, and verification modes corresponding to the expected output results of different types are different; and the verification module is used for verifying the expected output result and the actual output result according to a verification mode corresponding to the expected output result and determining whether the function of the chip to be tested is normal.
In one possible implementation, the types of expected output results include a first type and a second type, the first type of expected output results including an expected raw data file and an expected image, the second type of expected output results including an expected raw data file.
In one possible implementation, the verification platform further includes: and the generation module is used for generating the expected image according to the expected original data file.
In one possible implementation manner, when the type of the expected output result is the first type or the second type, the verification module is specifically configured to: detecting whether the actual output result comprises an actual original data file; when the actual output result comprises the actual original data file, comparing the actual original data file with the expected original data file; and when the comparison is successful, determining that the chip to be tested is normal in function.
In one possible implementation manner, when the type of the expected output result is the first type or the second type, the verification module is specifically configured to: and when the actual output result does not comprise the actual original data file, determining that the chip to be tested is abnormal in function, and outputting a signal indicating simulation errors.
In one possible implementation manner, the verification module is specifically configured to: determining that the chip to be tested is abnormal in function when the comparison of the actual original data file and the expected original data file fails and the type of the expected output result is the second type; and generating and outputting a first comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when the actual original data file and the expected original data file are compared.
In one possible implementation manner, the verification module is specifically configured to: when the actual original data file and the expected original data file are failed to be compared and the type of the expected output result is the first type, comparing an actual image with the expected image; and when the actual image and the expected image are successfully compared, determining that the chip to be tested is normal in function.
In one possible implementation manner, the verification module is specifically configured to: determining that the chip to be tested is abnormal in function when the comparison between the actual image and the expected image fails; and generating and outputting a first comparison text file and a second comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual original data file and the expected original data file, and the second comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual image and the expected image.
According to another aspect of the present disclosure, there is provided an electronic device including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.
According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the above-described method.
According to another aspect of the present disclosure, there is provided a computer program product comprising a computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.
According to the chip function verification method, an excitation signal is input into a chip to be verified, the chip to be verified is in a code form in a verification platform, and an actual output result of the chip to be verified is received, so that a verified object is obtained; the method comprises the steps of detecting the type of an expected output result corresponding to an excitation signal, wherein verification modes corresponding to different types of expected output results are different, so that the verification mode corresponding to the expected output result is obtained and used as a verification mode for chip function verification; and verifying the expected output result and the actual output result according to the verification mode corresponding to the expected output result, and determining whether the chip to be tested is normal or not, thereby completing the verification of the chip function in the selected verification mode corresponding to the expected output result. Because different verification modes are set for different types of expected output results, verification can be performed according to the verification mode corresponding to the type of the detected expected output results during verification, automatic adjustment of the verification mode according to specific excitation is realized, the flexibility of verification of the chip function can be improved, and the recognition accuracy of simulation errors can also be improved by using the corresponding verification mode.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 illustrates an exemplary application scenario of a verification method of a chip function according to an embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a flow of a verification method of chip functions according to an embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of a verification manner corresponding to an expected output result according to an embodiment of the present disclosure.
Fig. 4 shows a schematic diagram of the structure of a verification platform of chip functions according to an embodiment of the present disclosure.
Fig. 5 shows a block diagram of an electronic device 1900 according to an embodiment of the disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
In the development process of the chip, simulation and verification are very important links, wherein the verification part of the core inputs an excitation signal into the chip to be tested before the chip is put into the chip, and whether the chip meets the requirement is judged according to whether the actual output of the chip to be tested is consistent with the expected output, which is a serious problem in the simulation and verification process.
There may be multiple output formats for the verified object, i.e., the chip. Taking the verified object as an example of a graphics processor (graphics processing unit, GPU), the expected output is typically in two cases, one including only the expected raw data file (bin file) and the other including both the expected raw data file and the expected image. The expected original data file may include all data information that the chip to be tested can output when receiving the excitation signal, and it may be considered that the expected original data file includes both useful data and useless data, and the expected image includes only useful data. However, the existing mechanisms for simulating and verifying chips are only used for the scenario where the expected output only includes the expected original data file, or only used for the scenario where the expected output includes both the expected original data file and the expected image, and cannot be flexibly switched between the two scenarios, so that the flexibility is poor. And the expected original data file can adopt a plurality of storage formats, when judging whether the actual output of the chip is consistent with the expected output, the actual original data file in the actual output is required to be compared with the expected original data file, and if the storage formats of the actual original data file and the expected original data file are inconsistent, even if the data contents contained in the actual original data file and the expected original data file are consistent, the simulation error is misjudged. And if the useful data in the data contents contained in the two are consistent, the useless data are inconsistent, and the simulation error is misjudged.
In summary, the mechanisms of chip simulation and verification in the prior art have the disadvantages of poor flexibility and reduced recognition accuracy of simulation errors.
In view of this, the present disclosure proposes a method, a platform, an electronic device, and a storage medium for verifying a chip function, where different verification methods are set for different types of expected output results, so that verification can be performed according to verification methods corresponding to the types of detected expected output results during verification, automatic adjustment of the verification methods according to specific excitation is implemented, flexibility of verification of the chip function can be improved, and recognition accuracy of simulation errors can also be improved by using corresponding verification methods.
Fig. 1 illustrates an exemplary application scenario of a verification method of a chip function according to an embodiment of the present disclosure.
As shown in fig. 1, the application scenario may be a scenario in which the function of the chip is verified before the chip is put into a chip (i.e., before the chip of the hardware is manufactured). The application scene can comprise a verification platform (hereinafter referred to as verification platform) of the chip function and a chip to be tested in the verification platform, wherein the chip to be tested is in a code form in the verification platform. Before starting verification, the excitation signal and the expected output result are respectively imported into a verification platform. Examples of expected output results may be found in the related description below.
The verification platform performs the verification method of the chip function of the embodiment of the present disclosure, and outputs an excitation signal to an interface (not shown) of the chip to be tested and the verification platform. The chip to be tested simulates the function of the real chip according to the excitation signal, and outputs an actual output result to the verification platform, wherein the actual output result may only comprise an actual original data file or comprise an actual original data file and an actual image.
And the verification platform verifies the expected output result and the actual output result, so that whether the chip to be tested is normal in function or not can be determined. When the chip to be tested is abnormal in function and has simulation errors, text files (including a first comparison text file and/or a second comparison text file which are described below) for recording the simulation errors can be generated so as to prompt a user.
The user can adjust the chip to be tested in the verification platform to correct the abnormal chip function, and then throw the chip after the chip to be tested has normal function, so that the loss caused by the abnormal function after the chip is thrown is reduced.
It should be understood by those skilled in the art that the actual output result may further include more data, as long as the chip to be tested can output data according to the excitation signal, and the embodiment of the present disclosure does not limit the content of the data included in the actual output result.
Fig. 2 shows a schematic diagram of a flow of a verification method of chip functions according to an embodiment of the present disclosure.
As shown in fig. 2, in one possible implementation manner, the present disclosure provides a method for verifying a chip function, where the method is applied to a platform for verifying a chip function, and the method includes:
s21, inputting an excitation signal into a chip to be tested, wherein the chip to be tested is in a code form in a verification platform;
step S22, receiving an actual output result of the chip to be tested;
step S23, detecting the type of the expected output result corresponding to the excitation signal, wherein the verification modes corresponding to the expected output results of different types are different;
and step S24, verifying the expected output result and the actual output result according to a verification mode corresponding to the expected output result, and determining whether the chip to be tested is normal in function.
For example, the excitation signal may be preset by the user. When the user wants to start the verification of the chip function, the verification platform can be controlled to execute step S21 to input the excitation signal into the chip to be tested. The chip to be tested is in a code form in the verification platform. The excitation signal can be input to the chip to be tested through the interface of the chip to be tested and the verification platform. The chip to be tested responds to the excitation signal and outputs a response result (namely an actual output result) to the interface of the chip to be tested and the verification platform. For the verification platform, step S22 is executed, and the actual output result of the chip to be tested is received.
Because the function of the chip to be tested is known, the expected output result of the chip to be tested after the excitation signal is input into the chip to be tested can be determined before the excitation signal is input into the chip to be tested. The expected output result refers to an output result in response to the excitation signal when the chip to be tested is not abnormal, and the expected output result corresponds to the excitation signal. The expected output results can be classified in advance according to the data content included in the expected output results which may occur when different excitation signals are input into the chip to be tested. The verification means corresponding to the different types of expected output results may be different.
In one possible implementation, the types of expected output results include a first type of expected output results including an expected raw data file and an expected image and a second type of expected output results including an expected raw data file.
For example, for a chip with image processing capability, such as a graphics processor, the expected output result may include the expected raw data file and the expected image, or may include only the expected raw data file. In this regard, the expected output results including the expected raw data file and the expected image may be set to a first type and the expected output results including the expected raw data file may be set to a second type.
It will be appreciated that the chip to be tested may also be another type of chip, and the expected output result may include more data content than the expected original data file and the expected image, so more types may be set for the expected output result, as long as the type of the expected output result covers the possible output result of the code of the chip, and the embodiment of the present disclosure is not limited to the type of chip to be tested, the number of specific types of the expected output result, and the specific data content included in the expected output result corresponding to each type.
In this case, performing step S23 may detect the type of expected output result corresponding to the excitation signal. Further, a type identifier no_png_flag indicating the type of the expected output result may be set, and different types may be distinguished by different values, for example, when the type of the expected output result corresponding to the excitation signal is detected to be the first type, the type identifier no_png_flag may be updated to 0; when the type of the expected output result corresponding to the excitation signal is detected to be the second type, the type identifier no_png_flag may be updated to 1. It should be understood by those skilled in the art that the type identifier may be set to other values, or may be set to other objects other than values, so long as the type identifiers corresponding to different types are different, and the embodiment of the disclosure does not limit whether to set the type identifier or not and the specific setting manner of the type identifier.
The steps S22 and S23 may be completed before the step S24 is performed, and the sequence of performing the steps S22 and S23 is not limited in the embodiments of the present disclosure.
Thereafter, step S24 is executed, where the expected output result and the actual output result are verified according to the verification manner (which may be determined according to the type of the expected output result or the type identifier) corresponding to the expected output result, so as to determine whether the chip to be tested functions normally. The verification manner may be preset, and an exemplary verification manner may be referred to further description of step S24, which is described later, and the present disclosure is not limited to what verification manner is specifically adopted, as long as it can determine whether the chip to be tested is normal.
According to the chip function verification method, an excitation signal is input into a chip to be verified, the chip to be verified is in a code form in a verification platform, and an actual output result of the chip to be verified is received, so that a verified object is obtained; the method comprises the steps of detecting the type of an expected output result corresponding to an excitation signal, wherein verification modes corresponding to different types of expected output results are different, so that the verification mode corresponding to the expected output result is obtained and used as a verification mode for chip function verification; and verifying the expected output result and the actual output result according to the verification mode corresponding to the expected output result, and determining whether the chip to be tested is normal or not, thereby completing the verification of the chip function in the selected verification mode corresponding to the expected output result. Because different verification modes are set for different types of expected output results, verification can be performed according to the verification mode corresponding to the type of the detected expected output results during verification, automatic adjustment of the verification mode according to specific excitation is realized, the flexibility of verification of the chip function can be improved, and the recognition accuracy of simulation errors can also be improved by using the corresponding verification mode.
The above-mentioned expected output results may be of two types, the first type and the second type each including an expected raw data file, the first type additionally including an expected image. The expected original data file may be obtained from the excitation signal, and the specific obtaining manner may be implemented based on the prior art, which is not described herein. However, the expected images are not generated simultaneously when the expected original data files are obtained by adopting the prior art, and if the expected images are obtained by manual processing, the labor cost is excessive and the error rate is high.
In one possible implementation, when detecting that the type of expected output result is the first type and that there is no expected image, the method further includes:
an expected image is generated from the expected raw data file.
For example, the expected raw data file may include all data information that the chip under test is capable of outputting upon receipt of the stimulus signal, that is, the expected raw data file also includes data information that may generate the expected image. Thus, the verification platform may automatically generate the expected image from the expected raw data file for use in performing step S24.
The desired image may be in jpg format, png format, etc., and embodiments of the present disclosure are not limited to the particular storage format of the desired image generated. Exemplary ways in which the desired image may be used may be seen from the further description of step S24 below.
It should be understood by those skilled in the art that the above manner of obtaining the expected image is merely an example, and if the excitation signal includes enough information, the expected image may also be obtained by analyzing the excitation signal, so long as the expected image can be generated according to the existing information, and the embodiment of the present disclosure is not limited to a specific manner of generating the expected image.
In this way, the expected image can be automatically generated when the type of the expected output result is detected to be the first type and the expected image is not present, thereby reducing the labor cost.
An exemplary verification scheme corresponding to the expected output result is described below. Fig. 3 shows a schematic diagram of a verification manner corresponding to an expected output result according to an embodiment of the present disclosure. The general part of the verification scheme corresponding to different types of expected output results is described herein with reference to fig. 3.
As shown in fig. 3, in one possible implementation, when the type of the expected output result is the first type or the second type, step S24 includes:
Detecting whether an actual output result comprises an actual original data file;
when the actual output result comprises an actual original data file, comparing the actual original data file with an expected original data file;
and when the comparison is successful, determining that the chip to be tested is normal in function.
For example, as can be seen from the above description, a false positive is likely to occur when the actual raw data file and the expected raw data file fail to be aligned. That is, if the comparison between the actual original data file and the expected original data file is successful, there is no misjudgment, and it can be directly determined that the chip to be tested is normal.
Therefore, whether the type of the expected output result is the first type or the second type, when step S24 is executed, it may be detected whether the actual output result includes the actual original data file, when the actual output result includes the actual original data file, the actual original data file and the expected original data file are compared, and when the comparison is successful, it is determined that the chip functions normally. Wherein, when the two comparison parts are consistent, the comparison is considered to be successful, and when the two comparison parts are inconsistent, the comparison is considered to be failed. Further, a status identifier status indicating the verification status may be set, and different verification statuses may be distinguished by different values, where the verification platform may enable status identifier status=0 when the actual original data file and the expected original data file are successfully compared. The embodiments of the present disclosure are not limited as to whether to set the state identifier or not, and the specific numerical value of the state identifier.
In this way, the chip to be tested can be quickly determined to be normal in function.
As shown in fig. 3, in one possible implementation, when the type of the expected output result is the first type or the second type, step S24 further includes:
and when the actual output result does not comprise the actual original data file, determining that the chip to be tested is abnormal in function, and outputting a signal indicating simulation errors.
For example, when an abnormality occurs in the chip under test, the actual raw data file may not be generated normally, or the actual raw data file is generated but not output to the verification platform normally. The actual output result does not include the actual raw data file at this time.
Therefore, whether the type of the expected output result is the first type or the second type, when step S24 is performed, it may be determined that the chip to be tested is abnormal in function when the actual output result does not include the actual original data file, and when the status flag status indicating the verification status is set, the verification platform may cause the status flag status=1 and directly output a signal indicating the simulation error. The signal may indicate that the simulation has an error only, or may further indicate specific error information, for example, that the actual output result does not include the actual original data file to generate an error, or may further indicate that the actual output result does not include the actual original data file to generate an identifier corresponding to the simulation error when identifiers corresponding to different possible simulation errors are stored in advance, or the like. The embodiment of the present disclosure does not limit a specific setting manner of the signal indicating the simulation error, which is output when the actual output result does not include the actual original data file.
By the method, the functional abnormality of the chip to be tested can be rapidly determined, the fact that the simulation error is generated can be reported by outputting the information indicating the simulation error, and the method is convenient for processing the simulation error.
The following describes the distinguishing part of the verification manner corresponding to different types of expected output results with reference to fig. 3.
As shown in fig. 3, in one possible implementation, step S24 further includes:
determining that the chip to be tested is abnormal in function when the comparison of the actual original data file and the expected original data file fails and the type of the expected output result is the second type;
and generating and outputting a first comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the number of times of errors when comparing the actual original data file with the expected original data file.
For example, further, when the actual raw data file and the expected raw data file fail to be aligned (the two aligned parties are not identical), if a status identifier status indicating the verification status is set, the verification platform may make the status identifier status=3. At this time, whether the chip to be tested is normal or not can be further determined according to the type of the expected output result.
When the type of the expected output result is the second type (i.e. the type identifier no_png_flag is 1), the expected output result does not include the expected image, so that the abnormal function of the chip to be tested can be directly determined after the comparison between the actual original data file and the expected original data file fails.
A first comparison text file may be generated that records one or more of the location at which the error occurred during the comparison (i.e., the two compared parties were inconsistent), the value at that location, and the number of errors occurred. A first threshold may be preset, and when the number of errors reaches the first threshold, the comparison is stopped and the first comparison text file is output. The first comparison text file may be set to record all locations where errors occur and the values at that location to obtain more specific error information. Since the first error may be a cause of other errors occurring later, only the position where the error occurs for the first time and the value at the position may be recorded to reduce the size of the first comparison text file and avoid erroneous repeated recording.
It will be appreciated that the first comparison text file may also include more information, as long as the error is related to when the actual original data file is compared with the expected original data file, and the specific content recorded in the first comparison text file is not limited by the embodiments of the present disclosure.
In this way, verification of the expected output result and the actual output result of the second type can be completed.
As shown in fig. 3, in one possible implementation, step S24 further includes:
when the comparison of the actual original data file and the expected original data file fails and the type of the expected output result is the first type, comparing the actual image with the expected image;
and when the actual image and the expected image are successfully compared, determining that the chip to be tested is normal in function.
Referring to the related description above, when the actual original data file and the expected original data file fail to be aligned (the two sides of the alignment are not identical), erroneous judgment may be caused. Since the expected output result of the first type (i.e., the type identifier no_png_flag is 0) further includes an expected image, and the received actual output result also includes an actual image, whether the chip to be tested functions normally can be further determined by comparing the expected image with the actual image. The preset image comparison script can be called to perform comparison. If the comparison is successful (both parties of the comparison agree), the representation may be due to different formats of the actual raw data file and the intended raw data file, or due to different useless data in the actual raw data file and the intended raw data file. That is, when the actual raw data file and the expected raw data file fail to be compared and the type of the expected output result is the first type, the actual image and the expected image are compared; and when the actual image and the expected image are successfully compared, determining that the chip to be tested is normal in function.
By the method, the misjudgment result can be calibrated when misjudgment occurs, and the accuracy of verification of the chip function is ensured.
As shown in fig. 3, in one possible implementation, step S24 further includes:
determining abnormal functions of the chip to be tested when the comparison of the actual image and the expected image fails;
and generating and outputting a first comparison text file and a second comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual original data file with the expected original data file, and the second comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual image with the expected image.
For example, when it is further determined whether the chip function to be tested is normal by comparing the expected image with the actual image, if the comparison fails (the two comparison parties are inconsistent), it means that the useful data in the actual original data file and the expected original data file are inconsistent, so that the chip function is indeed abnormal. At this time, a first comparison text file and a second comparison text file may be generated, where examples of the first comparison text file may be referred to above as related description, and the second comparison text file may be one or more of a location, a numerical value, and a number of times that an error occurs when the actual image and the expected image are compared (i.e., the two compared parties are inconsistent). A second threshold may be preset, and when the number of errors reaches the second threshold, the comparison is stopped and the second comparison text file is output. The second comparison text file may be set to record all locations where errors occur and the values at that location to obtain more specific error information. Since the first error may be the cause of other errors that occur later, only the location where the error occurred for the first time and the value at that location may be recorded to reduce the size of the second comparison text file and avoid erroneous repeated recordings.
It will be appreciated that the second comparison text file may further include more information, as long as the information is related to errors occurring during image comparison, for example, errors caused by different image sizes, or errors caused by the same image size but different pixels, etc., may also be recorded, and the embodiment of the present disclosure does not limit the specific content recorded by the second comparison text file.
In this way, the recorded simulation error information is more comprehensive.
The verification method for the chip function of the embodiment of the disclosure not only can automatically adapt to the verification mode for verification according to the expected output result of the chip to be tested, reduces the requirement on the excitation signal, facilitates the expansion and reuse of the excitation signal, but also reduces the probability of false alarm of simulation errors and improves the verification efficiency. When confirming that the chip to be tested is abnormal in function, if comparison is performed, a text file with errors in recording comparison can be automatically generated and used for indicating error information, so that problem analysis and positioning are facilitated.
The present disclosure also provides a verification platform of chip functions, and fig. 4 is a schematic diagram illustrating a structure of the verification platform of chip functions according to an embodiment of the present disclosure.
As shown in fig. 4, in one possible implementation, the verification platform of the chip function includes:
the input module 41 is used for inputting an excitation signal into a chip to be tested, and the chip to be tested is in a code form in the verification platform;
a receiving module 42, configured to receive an actual output result of the chip to be tested;
the detection module 43 is configured to detect types of expected output results corresponding to the excitation signals, where verification manners corresponding to different types of expected output results are different;
and the verification module 44 is configured to verify the expected output result and the actual output result according to a verification manner corresponding to the expected output result, and determine whether the chip to be tested functions normally.
In one possible implementation, the types of expected output results include a first type and a second type, the first type of expected output results including an expected raw data file and an expected image, the second type of expected output results including an expected raw data file.
In one possible implementation, the verification platform further includes:
and the generation module is used for generating the expected image according to the expected original data file.
In one possible implementation manner, when the type of the expected output result is the first type or the second type, the verification module is specifically configured to:
detecting whether the actual output result comprises an actual original data file;
when the actual output result comprises the actual original data file, comparing the actual original data file with the expected original data file;
and when the comparison is successful, determining that the chip to be tested is normal in function.
In one possible implementation manner, when the type of the expected output result is the first type or the second type, the verification module is specifically configured to:
and when the actual output result does not comprise the actual original data file, determining that the chip to be tested is abnormal in function, and outputting a signal indicating simulation errors.
In one possible implementation manner, the verification module is specifically configured to:
determining that the chip to be tested is abnormal in function when the comparison of the actual original data file and the expected original data file fails and the type of the expected output result is the second type;
and generating and outputting a first comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when the actual original data file and the expected original data file are compared.
In one possible implementation manner, the verification module is specifically configured to:
when the actual original data file and the expected original data file are failed to be compared and the type of the expected output result is the first type, comparing an actual image with the expected image;
and when the actual image and the expected image are successfully compared, determining that the chip to be tested is normal in function.
In one possible implementation manner, the verification module is specifically configured to:
determining that the chip to be tested is abnormal in function when the comparison between the actual image and the expected image fails;
and generating and outputting a first comparison text file and a second comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual original data file and the expected original data file, and the second comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual image and the expected image.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.
The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.
The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.
Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.
Fig. 5 shows a block diagram of an electronic device 1900 according to an embodiment of the disclosure. For example, electronic device 1900 may be provided as a server or terminal device. Referring to FIG. 5, electronic device 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.
The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output interface 1958 (I/O interface). The electronic device 1900 may operate an operating system based on a memory 1932, such as Windows Server TM ，Mac OS X TM ，Unix TM ,Linux TM ，FreeBSD TM Or the like.
In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of electronic device 1900 to perform the methods described above.
The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.
The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.
The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.
Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (11)

1. A method for verifying a chip function, the method being applied to a verification platform for the chip function, the method comprising:
inputting an excitation signal into a chip to be tested, wherein the chip to be tested is in a code form in the verification platform;
receiving an actual output result of the chip to be tested;
detecting the type of the expected output result corresponding to the excitation signal, wherein verification modes corresponding to the expected output results of different types are different;
and verifying the expected output result and the actual output result according to a verification mode corresponding to the expected output result, and determining whether the function of the chip to be tested is normal.
2. The method of claim 1, wherein the types of expected output results comprise a first type and a second type, the first type of expected output results comprising expected raw data files and expected images, the second type of expected output results comprising expected raw data files.
3. The method of claim 2, wherein upon detecting that the type of expected output result is the first type and that the expected image is absent, the method further comprises:
and generating the expected image according to the expected original data file.
4. A method according to claim 2 or 3, wherein when the type of the expected output result is the first type or the second type, the verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, and determining whether the chip to be tested functions normally includes:
detecting whether the actual output result comprises an actual original data file;
when the actual output result comprises the actual original data file, comparing the actual original data file with the expected original data file;
And when the comparison is successful, determining that the chip to be tested is normal in function.
5. The method of claim 4, wherein when the type of the expected output result is the first type or the second type, the verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, and determining whether the chip to be tested functions normally further comprises:
and when the actual output result does not comprise the actual original data file, determining that the chip to be tested is abnormal in function, and outputting a signal indicating simulation errors.
6. The method of claim 4, wherein verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, and determining whether the chip to be tested is normal further comprises:
determining that the chip to be tested is abnormal in function when the comparison of the actual original data file and the expected original data file fails and the type of the expected output result is the second type;
and generating and outputting a first comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when the actual original data file and the expected original data file are compared.
7. The method of claim 4, wherein verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, and determining whether the chip to be tested is normal further comprises:
when the actual original data file and the expected original data file are failed to be compared and the type of the expected output result is the first type, comparing an actual image with the expected image;
and when the actual image and the expected image are successfully compared, determining that the chip to be tested is normal in function.
8. The method of claim 7, wherein verifying the expected output result and the actual output result according to the verification manner corresponding to the expected output result, and determining whether the chip to be tested is normal further comprises:
determining that the chip to be tested is abnormal in function when the comparison between the actual image and the expected image fails;
and generating and outputting a first comparison text file and a second comparison text file, wherein the first comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual original data file and the expected original data file, and the second comparison text file is used for recording one or more of the position, the numerical value and the frequency of errors when comparing the actual image and the expected image.
9. A verification platform for chip functions, comprising:
the input module is used for inputting an excitation signal into a chip to be tested, and the chip to be tested is in a code form in the verification platform;
the receiving module is used for receiving the actual output result of the chip to be tested;
the detection module is used for detecting the type of the expected output result corresponding to the excitation signal, and verification modes corresponding to the expected output results of different types are different;
and the verification module is used for verifying the expected output result and the actual output result according to a verification mode corresponding to the expected output result and determining whether the function of the chip to be tested is normal.
10. An electronic device, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to implement the method of any one of claims 1 to 8 when executing the instructions stored by the memory.
11. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 8.
CN202311493099.9A 2023-11-09 2023-11-09 Verification method and verification platform for chip functions, electronic equipment and storage medium Pending CN117494638A (en)

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