CN117493026B

CN117493026B - Multi-host and multi-computing quick link memory device system and application device thereof

Info

Publication number: CN117493026B
Application number: CN202311862782.5A
Authority: CN
Inventors: 谢志勇; 李仁刚; 张闯; 王敏
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-03-22
Anticipated expiration: 2043-12-29
Also published as: CN117493026A

Abstract

The embodiment of the invention provides a multi-host and multi-computing quick link memory device system and application equipment thereof, relating to the technical field of computer systems and storage; the method comprises the steps of responding to a memory allocation request, determining target quick link memory equipment according to selection heat, generating a configuration instruction, and accessing the target quick link memory equipment into a host according to the configuration instruction; responding to the access of the target quick link memory device, and acquiring and calculating the device parameter information of the quick link memory device; determining an address space according to the equipment parameter information; distributing a target memory slice based on the memory demand of the memory distribution request, updating memory management information based on the host identity and the target memory slice, and generating a memory distribution success message; reading a memory allocation success message, and starting an address space corresponding to a target memory chip; calculating a fast link memory device based on the address space management target; the invention can ensure the safe use of the computing quick link memory among multiple hosts.

Description

Multi-host and multi-computing quick link memory device system and application device thereof

Technical Field

The present invention relates to the field of computer systems and storage technologies, and in particular, to a multi-host and multi-computing fast link memory device system, an electronic device, and a computer storage medium.

Background

Compute Express Link (CXL, compute fast link) is a completely new interconnect technology standard for processors, memory extensions and accelerators and it maintains consistency between CPU (central processing unit) memory space and connected device memory. As current CXL3.0 can support multiple hosts sharing the same CXL memory device, but a reliable and secure management method for multiple hosts sharing the CXL memory is still lacking.

Disclosure of Invention

In view of the above, embodiments of the present invention have been developed to provide a multi-host and multi-computing fast link memory device system, an electronic device, and a computer storage medium that overcome, or at least partially solve, the above problems.

In order to solve the above-mentioned problems, in a first aspect of the present invention, an embodiment of the present invention discloses a system of multiple hosts and multiple computing fast link memory devices, where any computing fast link memory device in the system is connected to multiple hosts through a data center manager, where the computing fast link memory device forms multiple memory slices based on preset size slices, where a single memory slice of any computing fast link memory device is allocated to one host for use at the same time, where the host is provided with a host identity, and the computing fast link memory device stores memory management information, where the memory management information records a correspondence between the memory slice and the multiple hosts;

The host responds to a memory allocation request, determines the selection heat of any computing quick link memory device, determines a target computing quick link memory device from any computing quick link memory device according to the selection heat, and generates a configuration instruction, wherein the configuration instruction corresponds to the target computing quick link memory device; sending a configuration instruction to a data center manager;

the data center manager accesses the target computing quick link memory device to the host according to the configuration instruction;

the host responds to the access of the target computing quick link memory device to acquire the device parameter information of the computing quick link memory device;

the host determines an address space according to the equipment parameter information;

the host sends the memory allocation request to the target computing quick link memory device;

the target computing quick link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates the memory management information based on the host identity and the target memory slice, and generates a memory allocation success message;

the host reads the memory allocation success message and starts the address space corresponding to the target memory chip;

The host manages the target computing fast link memory device based on the address space.

Optionally, the system further comprises:

the host responds to a memory access request and determines an access address of the memory access request;

the host judges whether the access address belongs to a target memory slice of the target computing quick link memory device or not, and determines the validity of the access address;

the host performs access control based on the validity of the access address.

Optionally, the step of performing access control based on the validity of the access address includes:

generating access exception information when the access address belongs to the target computing fast link memory device and does not correspond to the target memory slice; the access anomaly information characterizes that the target computing quick link memory device is not authorized to be accessed;

and when the access address corresponds to the target memory chip, sending the memory access request to the target computing quick link memory device so as to access the target computing quick link memory device.

Optionally, the system further comprises:

the host responds to a memory release request and determines an address space corresponding to the target memory chip;

The host sends the address space corresponding to the target memory chip to the target computing quick link memory device;

and the target computing quick link memory device releases the target memory chip to generate release success information.

Optionally, the system further comprises:

and the host updates the memory management information according to the release success information, and determines that the allocation state corresponding to the target memory chip is an allocable state.

Optionally, the system further comprises:

and the host sets the address space corresponding to the target memory chip to be in a forbidden state based on the release success information.

Optionally, the step of determining the selection heat of the any computing fast link memory device in response to the memory allocation request, and determining the target computing fast link memory device from the any computing fast link memory device according to the selection heat includes:

receiving unallocated memory information and access delay information of the computing fast link memory device provided by the data center manager in response to a memory allocation request;

screening the computing quick link memory devices provided by the data center manager according to the unallocated memory information and the access delay information to generate a first computing quick link memory device set, wherein the computing quick link memory devices in the first computing quick link memory device set meet the unallocated memory information and the access delay information;

And determining target computing quick link memory equipment from the first computing quick link memory equipment set according to the selection heat.

Optionally, the step of screening the computing fast link memory devices provided by the data center manager according to the unallocated memory information and the access latency information, and generating the first computing fast link memory device set includes:

screening the computing quick link memory devices provided by the data center manager according to the unallocated memory information to generate a second computing quick link memory device set, wherein the computing quick link memory devices in the second computing quick link memory device set meet the unallocated memory information;

and screening the second computing quick link memory device set according to the access delay information to generate the first computing quick link memory device set.

Optionally, the step of determining the target computing fast link memory device from the first set of computing fast link memory devices according to the selection hotness includes:

calculating a selection heat value of the computing quick link memory device in the first computing quick link memory device set based on a selection heat calculation formula;

Sorting the computing fast link memory devices in the first set of computing fast link memory devices based on the descending order of the selection hotness values;

determining the computing fast link memory device of the first bit as the target computing fast link memory device.

Optionally, the selection heat calculation formula is:

unallocated memory size for a fast link memory device to be calculated, +.>Request memory size for memory allocation request, +.>Calculating a maximum access latency in a set of fast link memory devices for the first computing; />The access delay of the quick link memory device to be calculated is determined; />Is a preset influencing factor.

Optionally, the step of determining the target computing fast link memory device from the first set of computing fast link memory devices according to the selection hotness further includes:

and determining the memory utilization rate according to the unallocated memory, wherein the memory utilization rate is the ratio of the size of the allocated memory to the total size of the memory of the quick link memory device.

Determining the preset influence factor according to the memory utilization rate, wherein the preset influence factor formula is as follows:

。

optionally, the system comprises:

the host sends a configuration request to the data center manager to acquire equipment information of a computing quick link bus;

the host establishes a directed graph according to the equipment information;

and the host determines and calculates access delay information of the quick link memory device according to the directed graph.

Optionally, the host device has a first key, the target computing fast link memory device has a second public key, and the system further comprises:

the host generates a re-encryption key according to the first key and the second public key;

the host sends the re-encryption key to the target computing fast link memory device.

Optionally, the host device further has a first public key, and the system further comprises:

the host responds to the request for sending the information, and encrypts the first key by adopting the first public key to generate a key ciphertext;

the host packages the key ciphertext and the ciphertext information to generate first encryption information;

the host sends the first encryption information to the target computing quick link memory device;

The target computing fast link memory device decrypts the first encryption information based on the re-encryption key.

Optionally, the system further comprises:

the host receives second encryption information sent by the target computing quick link memory device;

the host decrypts the second encryption information based on the first key.

Optionally, the system further comprises:

the host initializes the first public key and the first secret key.

Optionally, the system further comprises:

the computing quick link memory device receives the memory allocation request;

the computing quick link memory device performs memory allocation based on the memory allocation request, updates the memory management information based on the host identity, and generates a memory allocation success message;

the computing fast link memory device sends the memory allocation success message to the host.

Optionally, the system further comprises:

when the computing quick link memory device receives a host access request, checking a target access memory of the host access request;

the computing quick link memory device determines whether the target access memory belongs to a host corresponding to the host access request according to the memory management information;

The computing quick link memory device responds to the host access request when the target access memory belongs to the host corresponding to the host access request;

and the computing quick link memory device refuses the host access request when the target access memory is not in the host corresponding to the host access request.

In a second aspect of the present invention, an embodiment of the present invention discloses an electronic device including a processor, a memory, and a computer program stored on the memory and capable of running on the processor, the computer program implementing a multi-host and multi-compute fast link memory device system as described above when executed by the processor.

In a third aspect of the invention, embodiments of the invention disclose a computer readable storage medium having stored thereon a computer program which when executed by a processor implements a multi-host and multi-compute fast link memory device system as described above.

The embodiment of the invention has the following advantages:

according to the embodiment of the invention, the host responds to a memory allocation request, the selection heat of any computing quick link memory device is determined, and a target computing quick link memory device is determined from any computing quick link memory device according to the selection heat, so that a configuration instruction is generated, and the configuration instruction corresponds to the target computing quick link memory device; sending a configuration instruction to a data center manager; the data center manager accesses the target computing quick link memory device to the host according to the configuration instruction; the host responds to the access of the target computing quick link memory device to acquire the device parameter information of the computing quick link memory device; the host determines an address space according to the equipment parameter information; the host sends the memory allocation request to the target computing quick link memory device; the target computing quick link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates the memory management information based on the host identity and the target memory slice, and generates a memory allocation success message; the host reads the memory allocation success message and starts the address space corresponding to the target memory chip; the host manages the target computing fast link memory device based on the address space; by setting the secure access mechanism based on the device information of the computing quick link memory device and the memory address of the host device, the forwarding request of the target computing quick link memory device based on the host is processed, so that the secure and orderly use of the computing quick link memory between the hosts can be ensured.

Drawings

FIG. 1 is a flowchart illustrating steps performed by an embodiment of a multi-host and multi-computing fast link memory device system according to the present invention;

FIG. 2 is a schematic diagram illustrating interaction between a host device and a computing fast link memory device in accordance with an embodiment of the present invention;

FIG. 3 is a schematic diagram of a multi-host and multi-computing fast link memory device system according to an embodiment of the present invention;

fig. 4 is a block diagram of an electronic device according to an embodiment of the present invention;

fig. 5 is a block diagram of a storage medium according to an embodiment of the present invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Referring to fig. 1, a flowchart illustrating the execution steps of an embodiment of a system of multiple hosts and multiple computing quick link memory devices according to the present invention is shown, where any computing quick link memory device in the system is connected to multiple hosts through a data center manager, where any computing quick link memory device forms multiple memory slices based on preset size slices, where a single memory slice of any computing quick link memory device is allocated to one host for use at the same time, where the host is provided with a host identity, and the computing quick link memory device stores memory management information, where the memory management information records a correspondence relationship between the memory slices and the multiple hosts.

In embodiments of the present invention, a host device may be coupled to at least one computing fast link memory device. The computing fast link memory device is the CXL memory device. A computing fast link memory device is schematically connected to a host device, and referring to fig. 2, one CXL memory device may provide a plurality of CXL ports, and each CXL memory device's port is connected to a host through a CXL Fabric (switch), and the CXL memory device acts as a logical memory device for the host device and exposes the memory capacity of the entire device. Multiple hosts can access the CXL memory device as needed. As can be seen with reference to fig. 3 for a single CXL memory device, the CXL memory device includes the following CXL interface unit, address mapping unit, access permission unit, memory controller, DRAM (memory), communication unit, memory management unit, and usage monitoring and alerting unit. The CXL address mapping unit converts the memory address into a physical address of the DRAM, and the access permission unit verifies the validity of the access. The memory controller provides memory error checking, management, isolation, and other functions. The communication unit is responsible for managing the communication of the network. The memory management unit mainly stores memory management information and is responsible for managing the proxy re-encryption key, the private key of the device and the public key of the host, and the memory management information records the host ID (identity) of the host of each memory. The utilization rate monitoring and alarming unit is used for monitoring the utilization rate of the memory and displaying the utilization rate of the memory of the current equipment, and alarming is carried out to prompt a manager to increase the memory when the utilization rate of a certain CXL memory in the system exceeds 85%, so that the system performance is prevented from being reduced due to the lack of the system memory. The memory management information of the CXL memory device is represented by a tuple, where each member of the tuple records a host ID corresponding to the piece of memory space, and each piece of memory has a size that can be used for performing a device, such as 1G (byte), according to the requirement. After the CXL memory device is powered on, the device can initialize, and the memory management information array can be emptied.

The multi-host and multi-computing fast link memory device system may specifically perform the following steps:

step 101, the host responds to a memory allocation request, determines the selection heat of any computing quick link memory device, determines a target computing quick link memory device from any computing quick link memory device according to the selection heat, and generates a configuration instruction, wherein the configuration instruction corresponds to the target computing quick link memory device; sending a configuration instruction to a data center manager;

when a host is powered up or a new CXL memory device is connected to the CXL Fabric network, an access signal of the quick link memory device such as a CXL hot plug signal can be calculated. Device information for computing the fast link memory device may be obtained in response to an access signal for computing the fast link memory device. The device information includes, but is not limited to, device-related information such as a device model number, a memory size, and the like, and the device information may be stored in the CXL device information table. As in Linux (operation) systems, each CXL memory device can be used as a NUMA (memory) node without a CPU (central processing unit), and the related information can be recorded in a pg_data_t (structure) structure, and simultaneously in a node linked list pgdat_litst (structure). And determining the selection heat of each computing quick link memory device, determining target computing quick link memory devices from all computing quick link memory devices according to the selection heat, and generating configuration instructions. Wherein the configuration instruction corresponds to the target computing quick link memory device

The generated transmit configuration instructions may then be sent to a data center manager.

Step 102, the data center manager accesses the target computing quick link memory device to the host according to the configuration instruction;

after sending the configuration instruction to the data center manager and receiving the configuration instruction, the data center manager can access the target computing quick link memory device to the host based on the configuration instruction, so that the host can call the computing quick link memory device for use later.

Step 103, the host responds to the access of the target computing quick link memory device to acquire the device parameter information of the computing quick link memory device;

when the target calculates the access host of the quick link memory device, the device parameter information of the quick link memory device can be obtained.

Step 104, the host determines an address space according to the equipment information;

the host determines an address space according to the device parameter information, and the host can be distributed to the computing quick link memory device for use through the address space.

Step 105, the host sends the memory allocation request to the target computing fast link memory device;

The host may send a memory allocation request to the target computing fast link memory device in response to the memory allocation request to perform memory allocation management in the target computing fast link memory device.

Step 106, the target computing quick link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates the memory management information based on the host identity and the target memory slice, and generates a memory allocation success message;

the target computing quick link memory device can allocate a target memory chip based on the memory requirement size of the memory allocation request, the size of the target memory chip is not smaller than the memory requirement size of the memory allocation request, and based on the host identity and the target memory chip, the memory management information is updated, and a memory allocation success message is generated.

Step 107, the host reads the memory allocation success message and enables the address space corresponding to the target memory chip.

The host device reads the memory allocation success message, enables the address space, and enables the address space corresponding to the target memory chip, so that the address space can be used by the virtual machine deployed on the host device.

At step 108, the host manages the target computing fast link memory device based on the address space.

The host can manage the target computing quick link memory device based on the address space, writing or releasing operations in the address space, and the like.

To sum up, for example, when the host device finds that a new virtual machine needs to apply for allocating the CXL memory, the target CXL memory device and its node ID are determined first, and then a request is sent to the target CXL memory device through the management network, where the request information includes the ID of the host and the size of the requested memory. And the target CXL memory device allocates enough memory according to the request, updates CXL memory management information, stores the ID of the host to which the newly allocated memory chip belongs, and finally sends an allocation success message to the host, wherein the message comprises the allocated memory position. After receiving the message, the host informs the Linux kernel memory management unit, firstly sets the state of the memory in the corresponding range as enable, then utilizes a numa_alloc_onode () function to allocate the memory on the designated node, namely allocates the memory on the target CXL memory device, and finally takes the memory as all or a part of the memory of the virtual machine.

In an alternative embodiment of the invention, the system further comprises: the host responds to a memory access request and determines an access address of the memory access request; the host judges whether the access address belongs to a target memory slice of the target computing quick link memory device or not, and determines the validity of the access address; the host performs access control based on the validity of the access address.

In the embodiment of the invention, when the target computing quick link memory device is required to be accessed, an access address of the memory access request can be determined in response to the memory access request, then whether the access address belongs to a target memory slice of the target computing quick link memory device is judged, and the validity of the access address is determined; the host performs access control based on the validity of the access address, and controls whether the memory access request is allowed.

In an alternative embodiment of the invention, the system further comprises: the step of performing access control based on the validity of the access address includes: generating access exception information when the access address belongs to the target computing fast link memory device and does not correspond to the target memory slice; the access anomaly information characterizes that the target computing quick link memory device is not authorized to be accessed; and when the access address corresponds to the target memory chip, sending the memory access request to the target computing quick link memory device so as to access the target computing quick link memory device.

When a virtual machine application on the host device accesses the CXL device memory, the host device responds to the memory access request, determines an access address of the memory access request, and generates access abnormality information when the access address does not belong to an address space. When the access address belongs to the address space, a memory access request can be sent to the target computing quick link memory device so as to access the target computing quick link memory device to acquire data. Specifically, the memory access request may be forwarded to the CXL memory device, and when the CXL memory device receives the access request, the access permission unit checks whether the range memory has been allocated, and if the memory address has been allocated, returns the data normally, and if the memory address has not been allocated, returns a memory access failure. The host generates memory access exception and is processed by the exception handler.

In an alternative embodiment of the invention, the system further comprises: the host responds to a memory release request and determines an address space corresponding to the target memory chip; the host sends the address space corresponding to the target memory chip to the target computing quick link memory device; the target computing quick link memory device is further configured to release the target memory chip, and generate release success information.

When the host device needs to release the memory of the target CXL device (e.g., the virtual machine stops running), a memory release request is sent to the target CXL device via the management network, and the message includes the location and size of the memory to be released. After receiving the message, the target CXL memory device modifies the memory management information, clears the host ID of the corresponding memory slice, and then replies that the host releases the memory successfully. After receiving the release success message, the host computer sets the memory state of the range of the corresponding address space to a disabled state.

In an alternative embodiment of the invention, the system further comprises: and the host updates the memory management information according to the release success information, and determines that the allocation state corresponding to the target memory chip is an allocable state.

After the release is successful, the memory management information can be updated according to the release success information, and the allocation state corresponding to the target memory chip is determined to be the allocatable state, so that the target memory chip can be allocated to other hosts again for use.

In an alternative embodiment of the invention, the system further comprises: and the host sets the address space corresponding to the target memory chip to be in a forbidden state based on the release success information.

And after the corresponding memory is released, the address space corresponding to the target memory chip is set to be in a disabled state, so that the host is prevented from processing the address space corresponding to the target memory chip, and data loss is prevented.

In an optional embodiment of the invention, the step of determining the selection heat of the any computing fast link memory device in response to the memory allocation request, and determining the target computing fast link memory device from the any computing fast link memory device according to the selection heat includes: responding to a memory allocation request, and receiving unallocated memory information and access delay information of the computing quick link memory device provided by the data center manager; and screening the computing quick link memory devices provided by the data center manager according to the unallocated memory information and the access delay information to generate a first computing quick link memory device set, wherein the computing quick link memory devices in the first computing quick link memory device set meet the unallocated memory information and the access delay information.

When the memory allocation is performed, the host computer stores the device information of the CXL memory device, so that the host computer sends the selection information to the CXL memory device through the management network, and can respond to the memory allocation request to receive the unallocated memory information and the access delay information of the computing quick link memory device provided by the data center manager; screening the computing quick link memory devices provided by the data center manager according to the unallocated memory information and the access delay information to generate a first computing quick link memory device set, wherein the computing quick link memory devices in the first computing quick link memory device set meet the unallocated memory information and the access delay information; and determining the target computing quick link memory device from the first computing quick link memory device set according to the selection heat. Thus, the selection of the target computing fast link memory device can be performed according to the idle condition.

Further, the step of screening the computing fast link memory devices provided by the data center manager according to the unallocated memory information and the access delay information, and generating the first computing fast link memory device set includes: screening the computing quick link memory devices provided by the data center manager according to the unallocated memory information to generate a second computing quick link memory device set, wherein the computing quick link memory devices in the second computing quick link memory device set meet the unallocated memory information; and screening the second computing quick link memory device set according to the access delay information to generate the first computing quick link memory device set.

Further, the step of determining the target computing fast link memory device from the first computing fast link memory device set according to the selection hotness includes: calculating a selection heat value of the computing quick link memory device in the first computing quick link memory device set based on a selection heat calculation formula; sorting the computing fast link memory devices in the first set of computing fast link memory devices based on the descending order of the selection hotness values; determining the computing fast link memory device of the first bit as the target computing fast link memory device.

The heat data corresponding to the time delay parameter and the residual memory information can be calculated according to a preset heat calculation formula, then the calculation quick link memory devices are ordered based on the size of the heat data, and the calculation quick link memory device with the first position, namely the calculation quick link memory device with the largest heat data, is used as the target calculation quick link memory device. The heat calculation formula may be:

unallocated memory size for a fast link memory device to be calculated, +.>Request memory size for memory allocation request, +. >Calculating a maximum access latency in a set of fast link memory devices for the first computing; />The access delay of the quick link memory device to be calculated is determined; />Is a preset influencing factor.

In an optional embodiment of the invention, the step of determining the target computing fast link memory device according to the selection hotness from the first computing fast link memory device set further includes: and determining the memory utilization rate according to the unallocated memory, wherein the memory utilization rate is the ratio of the size of the allocated memory to the total size of the memory of the quick link memory device.

Specifically, the step of determining the target computing fast link memory device from the first computing fast link memory device set according to the selection hotness further includes:

。

in addition, before calculating the heat data, the memory occupancy rate can be determined according to the remaining memory information, and whether the memory occupancy rate is too high or not can be determined. When the memory occupancy rate is smaller than a preset use threshold, that is, the computing fast link memory device can be used as a candidate, a heat-based computing formula can be executed in response to the memory occupancy rate being smaller than the preset use threshold, and further screening can be performed in the step of computing heat data according to the time delay parameter and the residual memory information.

In addition, in response to the memory occupancy rate being not less than a preset usage threshold, the heat data is determined to be zero.

When the memory occupancy rate is not less than the preset usage threshold, that is, the usage rate of the computing fast link memory device is high, the computing fast link memory device is not suitable as a candidate, and the heat data can be determined to be zero so that the computing fast link memory device is at the lowest heat.

In an alternative embodiment of the invention, the system comprises: the host sends a configuration request to the data center manager to acquire equipment information of a computing quick link bus; the host establishes a directed graph according to the equipment information; and the host determines and calculates access delay information of the quick link memory device according to the directed graph.

In the embodiment of the invention, the host can acquire the equipment information of the computing quick link bus by sending a configuration request to the data center manager; establishing a directed graph according to the equipment information; and determining and calculating access delay information of the quick link memory device according to the directed graph. Specifically, a directed graph can be built by sending a command to a CXL Switch of a CXL Fabric (management) network through a management network, and acquiring information such as configuration, ports, port connections and the like of the command. And taking the signal delay as an edge weight, and calculating the access delay from the host to each CXL memory device.

In an alternative embodiment of the invention, the system further comprises: the host initializes a first public key and a first secret key.

The host device may initialize the public and private keys using a PKI (Public Key Infrastructure ) system and save its own private key inside the device. The public key of the host device is the first public key, and the private key of the host device is the first private key.

In addition, the CXL memory device can also initialize public and private keys using a PKI (public key infrastructure) system. The public key of the CXL memory device is the second public key, and the private key of the CXL memory device is the second private key.

In an alternative embodiment of the invention, the system further comprises: the host generates a re-encryption key according to the first key and the second public key; the host sends the re-encryption key to the target computing fast link memory device.

The host selects one or more CXL memory devices as candidate application memory devices, acquires a second public key of the CXL memory device from the PKI system, generates one or more proxy re-encryption keys by using the second public key of the CXL memory device and a first private key of the host device, and then sends the proxy re-encryption keys to the corresponding CXL memory devices; the CXL memory device records the proxy re-encryption key and the corresponding host ID; the CXL memory device then obtains the public key of the host from the PKI system and records the first public key of the host and the corresponding host ID internally by the CXL memory device.

In an alternative embodiment of the invention, the system further comprises: the host responds to the request for sending the information, and encrypts the first key by adopting the first public key to generate a key ciphertext; the host packages the key ciphertext and the ciphertext information to generate first encryption information; the host sends the first encryption information to the target computing quick link memory device;

When a host sends data to a target CXL memory device, firstly randomly generating an AES/DES key, then encrypting by using an AES or DES algorithm, encrypting the key by adopting a public key of the host, and then packaging a data ciphertext and a key ciphertext according to a specified format; and finally, sending the message to the target CXL memory device through the management network. Because the data is encrypted by adopting the host public key, only the equipment with the host private key or the proxy re-encryption key can decrypt, and the equipment without the proxy re-encryption key and the host cannot decrypt, thereby ensuring the safety of the data sent by the host. After receiving the ciphertext, the target CXL memory device uses the proxy re-encryption key to convert the ciphertext, uses the private key of the target CXL memory device to decrypt the symmetric key ciphertext, and then uses the symmetric key to decrypt the data ciphertext. The host computer sends data by using the proxy re-encryption technology can allow a plurality of devices with proxy re-encryption keys to simultaneously receive the messages, so that the point-to-point sending data is prevented from occupying the management bus bandwidth, and the safety of the data is ensured.

In an alternative embodiment of the invention, the system further comprises: the host receives second encryption information sent by the target computing quick link memory device; the host decrypts the second encryption information based on the first key.

CXL memory devices send data to hosts, which fall into two categories: one is a broadcast, where data is received by all devices on the management network, and the transmission is performed in plaintext; the other is to send data to a certain host, in this case, an AES/DES key is first randomly generated, then encrypted using AES or DES algorithm, then the key is encrypted with the public key of the target host, and then the data ciphertext and the key ciphertext are packaged according to the specified format; and finally, sending the data to the target host through the management network. After receiving the data, the target host decrypts the key ciphertext by using the private key of the target host, and then decrypts the data ciphertext by using the key. When CXL memory equipment sends data to a host, a symmetrical and asymmetrical encryption algorithm is combined, and the data communication safety is effectively ensured.

The embodiment of the invention also can comprise a computing quick link memory management method, which relates to a multi-host and multi-computing quick link memory device architecture, wherein any computing quick link memory device supports sharing of a plurality of hosts, the computing quick link memory device is managed according to fragments with preset sizes, the memory fragments of the computing quick link memory device are distributed to one host at most for use in the same time, the hosts are corresponding to host identity marks, the computing quick link memory device stores memory management information, and the memory management information records the corresponding relation between the memory fragments and the plurality of hosts; the host is used for responding to the memory allocation request, determining the target computing quick link memory device according to the selection heat, and generating a configuration instruction, wherein the configuration instruction corresponds to the target computing quick link memory device; sending a configuration instruction to a data center manager, wherein the data center manager is used for accessing target computing quick link memory equipment to the host; responding to the access of the target computing quick link memory device, and acquiring the device information of the computing quick link memory device; determining an address space according to the device information, wherein the address space is used for being distributed to the computing quick link memory device for use; the sending of the memory allocation request may refer to the above embodiment for implementation of the above process, which is not described herein. The method is applied to computing the quick link memory device. The method for managing the computing quick link memory specifically comprises the following steps:

Step S1, the computing quick link memory device receives the memory allocation request;

in the embodiment of the invention, the computing quick link memory device is the target computing quick link memory device for processing the request. The memory allocation request sent by the host device can be received, and the allocation task on the physical memory of the host device can be triggered.

Step S2, the computing quick link memory device performs memory allocation based on the memory allocation request, updates the memory management information based on the host identity, and generates a memory allocation success message;

the memory allocation request can be used for performing memory allocation based on the memory allocation request, determining a memory disk corresponding to the memory allocation request, recording the memory disk and the host identity in an array corresponding to the own memory management information, so as to update the memory management information and generate a memory allocation success message. And then generating a memory allocation success message and feeding back the memory allocation success message to the host equipment.

Step S3, the computing quick link memory device sends the memory allocation success message to the host device; the host is further configured to read the memory allocation success message, and enable an address space corresponding to the target memory chip.

A memory allocation success message may be sent to the host device to enable the host device to use the computing flash to link the memory allocated in the memory device. The host device may read the memory allocation success message, determine that the memory allocation was successful, enable the address space corresponding to the target memory chip, and calculate the fast link memory device based on the address space management target, in response to various processing requirements.

In an alternative embodiment of the invention, the system further comprises: when the computing quick link memory device receives a host access request, checking a target access memory of the host access request; the computing quick link memory device determines whether the target access memory belongs to a host corresponding to the host access request according to the memory management information; the computing quick link memory device responds to the host access request when the target access memory belongs to the host corresponding to the host access request; and the computing quick link memory device refuses the host access request when the target access memory is not in the host corresponding to the host access request.

The computing quick link memory device establishes a secure access mechanism with the host device to prevent errors when the host accesses and improve the security of using the computing quick link memory device.

The embodiment of the invention can comprise a computing quick link memory management method, which relates to a multi-host and multi-computing quick link memory device architecture, wherein any computing quick link memory device supports sharing of a plurality of hosts, the computing quick link memory device is managed according to fragments with preset sizes, memory fragments of the computing quick link memory device are distributed to one host at most for use in the same time, the hosts correspond to host identity marks, the computing quick link memory device stores memory management information, and the memory management information records the corresponding relation between the memory fragments and the plurality of hosts; the method comprises the following steps:

the host responds to the memory allocation request, determines the target computing quick link memory device according to the selection heat, and generates a configuration instruction, wherein the configuration instruction corresponds to the target computing quick link memory device;

the host sends a configuration instruction to a data center manager, and the data center manager is used for accessing the target computing quick link memory device to the host;

the host responds to the access of the target computing quick link memory device to acquire the device information of the computing quick link memory device;

Determining an address space according to the device information, wherein the address space is used for being distributed to the computing quick link memory device for use;

the host sends the memory allocation request to the computing quick link memory device;

the computing quick link memory device receives the memory allocation request;

the computing fast link memory device sends the memory allocation success message to the host device

And the host reads the memory allocation success message and starts the address space corresponding to the target memory chip.

Optionally, the method further comprises:

and managing the target computing quick link memory device based on the address space.

Optionally, the method further comprises:

responding to a memory access request, and determining an access address of the memory access request;

judging whether the access address belongs to a target memory chip of the target computing quick link memory device or not, and determining the validity of the access address;

And performing access control based on the validity of the access address.

Optionally, the method further comprises:

responding to a memory release request, and determining an address space corresponding to the target memory chip;

and sending the address space corresponding to the target memory chip to the target computing quick link memory device, wherein the target computing quick link memory device is also used for releasing the target memory chip and generating release success information.

Optionally, the method further comprises:

and updating the memory management information according to the release success information, and determining the allocation state corresponding to the target memory chip as an allocable state.

Optionally, the method further comprises:

and setting the address space corresponding to the target memory chip to be in a forbidden state based on the release success information.

Optionally, the step of determining the target computing fast link memory device according to the selection heat in response to the memory allocation request includes:

Optionally, the selection heat calculation formula is:

unallocated memory size for a fast link memory device to be calculated, +. >Request memory size for memory allocation request, +.>Calculating a maximum access latency in a set of fast link memory devices for the first computing; />The access delay of the quick link memory device to be calculated is determined; />Is a preset influencing factor.

。

optionally, the method comprises:

sending a configuration request to the data center manager to acquire equipment information of the computing quick link bus

Establishing a directed graph according to the equipment information;

and determining and calculating access delay information of the quick link memory device according to the directed graph.

Optionally, the host device has a first key, the target computing fast link memory device has a second public key, the method further comprising:

Generating a re-encryption key according to the first key and the second public key;

and sending the re-encryption key to the target computing quick link memory device.

Optionally, the host device further has a first public key, and the method further comprises:

in response to a request to send the information, encrypting the first key by adopting the first public key to generate a key ciphertext;

packaging the key ciphertext and the ciphertext information to generate first encryption information;

and sending the first encryption information to the target computing quick link memory device, wherein the target computing quick link memory device is further used for decrypting the first encryption information based on the re-encryption key.

Optionally, the method further comprises:

receiving second encryption information sent by the target computing quick link memory device;

decrypting the second encrypted information based on the first key.

Optionally, the method further comprises:

initializing the first public key and the first secret key.

Optionally, the method further comprises:

when a quick link memory device receives a host access request, checking a target access memory of the host access request;

calculating a quick link memory device, and responding to the host access request when the target access memory belongs to the host corresponding to the host access request;

and when the target access memory does not belong to the host corresponding to the host access request, the computing quick link memory device refuses the host access request.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.

Referring to fig. 4, an embodiment of the present invention further provides an electronic device, including:

a processor 401 and a storage medium 402, said storage medium 402 storing a computer program executable by said processor 401, said processor 401 executing said computer program when the electronic device is running to execute a multi-host and multi-computing fast link memory device system according to any one of the embodiments of the present invention.

The multi-host and multi-computing fast link memory device system includes:

any one computing quick link memory device in the system is connected with a plurality of hosts through a data center manager, the computing quick link memory device forms a plurality of memory slices based on preset size slices, the single memory slice of any one computing quick link memory device is distributed to one host for use in the same time, the hosts are provided with host identity marks, the computing quick link memory device stores memory management information, and the memory management information records the corresponding relation between the memory slices and the plurality of hosts;

Optionally, the system further comprises:

the host performs access control based on the validity of the access address.

Optionally, the system further comprises:

Optionally, the selection heat calculation formula is:

。

optionally, the system comprises:

the host establishes a directed graph according to the equipment information;

Optionally, the system further comprises:

the host decrypts the second encryption information based on the first key.

Optionally, the system further comprises:

The host initializes the first public key and the first secret key.

Optionally, the system further comprises:

the computing quick link memory device receives the memory allocation request;

Optionally, the system further comprises:

The memory may include a random access memory (Random Access Memory, abbreviated as RAM) or a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.

The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

Referring to fig. 5, an embodiment of the present invention further provides a computer readable storage medium 501, where the storage medium 501 stores a computer program, and when the computer program is executed by a processor, the system of the present invention is implemented by a multi-host and multi-computing fast link memory device.

The multi-host and multi-computing fast link memory device system includes: any one computing quick link memory device in the system is connected with a plurality of hosts through a data center manager, the computing quick link memory device forms a plurality of memory slices based on preset size slices, the single memory slice of any one computing quick link memory device is distributed to one host for use in the same time, the hosts are provided with host identity marks, the computing quick link memory device stores memory management information, and the memory management information records the corresponding relation between the memory slices and the plurality of hosts;

Optionally, the system further comprises:

the host performs access control based on the validity of the access address.

Optionally, the system further comprises:

Optionally, the selection heat calculation formula is:

/>

。

optionally, the system comprises:

the host establishes a directed graph according to the equipment information;

Optionally, the system further comprises:

the host decrypts the second encryption information based on the first key.

Optionally, the system further comprises:

the host initializes the first public key and the first secret key.

Optionally, the system further comprises:

the computing quick link memory device receives the memory allocation request;

Optionally, the system further comprises:

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The foregoing has described in detail a multi-host and multi-computing fast link memory device system, an electronic device and a computer storage medium provided by the present invention, and specific examples have been presented herein to illustrate the principles and implementations of the present invention, and the above examples are only for the purpose of aiding in the understanding of the methods and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. The system is characterized in that any one of the computing quick-link memory devices in the system is connected with a plurality of hosts through a data center manager, the any one of the computing quick-link memory devices forms a plurality of memory slices based on preset size slices, the single memory slice of the any one of the computing quick-link memory devices is distributed to one host for use at the same time, the host is provided with a host identity, the computing quick-link memory device stores memory management information, and the memory management information records the corresponding relation between the memory slices and the plurality of hosts;

The host responds to the access of the target computing quick link memory device to acquire the device parameter information of the target computing quick link memory device;

the host manages the target computing fast link memory device based on the address space;

wherein, the step of determining the selection heat of any computing quick link memory device in response to the memory allocation request, and determining the target computing quick link memory device from any computing quick link memory device according to the selection heat includes:

determining a target computing quick link memory device from the first computing quick link memory device set according to the selection heat;

the step of determining the target computing quick link memory device according to the selection heat from the first computing quick link memory device set includes:

determining the computing quick link memory device of the first bit as the target computing quick link memory device;

the selection heat calculation formula is as follows:

2. The system of claim 1, wherein the system further comprises:

the host performs access control based on the validity of the access address.

3. The system of claim 2, wherein the step of access control based on the validity of the access address comprises:

4. The system of claim 1, wherein the system further comprises:

5. The system of claim 4, wherein the system further comprises:

6. The system of claim 5, wherein the system further comprises:

7. The system of claim 1, wherein the step of screening the computing fast link memory devices provided by the data center manager based on the unallocated memory information and the access latency information to generate a first set of computing fast link memory devices comprises:

8. The system of claim 1, wherein the step of determining a target computing fast link memory device from the first set of computing fast link memory devices based on the selection hotness further comprises:

9. The system of claim 1, wherein the step of determining a target computing fast link memory device from the first set of computing fast link memory devices based on the selection hotness further comprises:

。

10. The system according to claim 1, characterized in that the system comprises:

the host establishes a directed graph according to the equipment information;

11. The system of claim 1, wherein the host device has a first key and the target computing fast link memory device has a second public key, the system further comprising:

12. The system of claim 11, wherein the host device further has a first public key, the system further comprising:

the host responds to an information sending request, encrypts the first key by adopting the first public key, and generates a key ciphertext;

the host packages the key ciphertext and ciphertext information to generate first encryption information;

13. The system of claim 12, wherein the system further comprises:

the host decrypts the second encryption information based on the first key.

14. The system of claim 12, wherein the system further comprises:

the host initializes the first public key and the first secret key.

15. The system of claim 1, wherein the system further comprises:

the computing quick link memory device receives the memory allocation request;

16. The system of claim 1, wherein the system further comprises:

17. An electronic device comprising a processor, a memory, and a computer program stored on the memory and capable of running on the processor, the computer program implementing the multi-host and multi-compute fast link memory device system according to any one of claims 1 to 16 when executed by the processor.

18. A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the multi-host and multi-compute fast link memory device system of any of claims 1 to 16.