CN117480743A

CN117480743A - Receiving and transmitting circuit and receiving and transmitting equipment for clock synchronization

Info

Publication number: CN117480743A
Application number: CN202180099154.9A
Authority: CN
Inventors: 王东; 赵兴; 雷张伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-07-31
Filing date: 2021-07-31
Publication date: 2024-01-30
Also published as: WO2023010234A1

Abstract

A transceiver circuit comprising: a clock adjustment module (A), a phase frequency detector (B) and a first phase-locked loop (C); the first input end of the A is coupled to the input end of the transceiver circuit, the first output end of the A is connected with the first input end of the B, the output end of the B is connected with the input end of the C, and the output end of the C is connected with the second input end of the A and the second input end of the B; b is used for determining the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output at the previous moment of C; c is used for outputting a first clock signal according to the frequency difference; a is used for determining the phase difference between the clock signal of the first transceiver and the current clock signal of the transceiver circuit; adjusting the first clock signal according to the phase difference to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver; and updating a receiving clock signal of the transceiver circuit to a second clock signal, wherein the second clock signal is used for receiving data from the first transceiver device.

Description

Receiving and transmitting circuit and receiving and transmitting equipment for clock synchronization

Technical Field

The embodiment of the application relates to the technical field of electronics, in particular to a transceiver circuit and a transceiver for clock synchronization.

Background

In general, in transmitting data between electronic devices, a data receiving device needs to perform clock signal synchronization (may also be referred to as clock synchronization) with a data transmitting device, so that the data receiving device and the data transmitting device can communicate based on the synchronized clock signals.

The existing clock synchronization method is as follows: a master clock device is configured to provide a reference clock signal to each of the plurality of transceivers, respectively, such that data may be transferred between the plurality of transceivers based on the reference clock signal. For example, a second transceiver device of the plurality of transceiver devices transmits data to a first transceiver device of the plurality of transceiver devices using a reference clock signal provided by the master clock device, and the first transceiver device receives data from the second transceiver device using the reference clock signal provided by the master clock device, that is, the master clock device provides the same clock signal to the first transceiver device and the second transceiver device such that the clock signal of the second transceiver device and the clock signal of the first transceiver device are synchronized.

The above method of clock synchronization needs to separately provide a master clock device, and then a physical clock dedicated line is separately laid out to connect the master clock device with a plurality of transceiver devices, which occupies the interface resources of the transceiver devices.

Disclosure of Invention

The embodiment of the application provides a receiving and transmitting circuit and receiving and transmitting equipment for clock synchronization, which can realize clock synchronization between the receiving and transmitting equipment under the condition of not occupying interface resources of the receiving and transmitting equipment.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a transceiver circuit, including: the device comprises a clock adjustment module, a phase frequency detector and a first phase-locked loop; the first input end of the clock adjustment module is coupled to the input end of the transceiver circuit, the first output end of the clock adjustment module is connected with the first input end of the phase frequency detector, the output end of the phase frequency detector is connected with the input end of the first phase-locked loop, and the output end of the first phase-locked loop is connected with the second input end of the clock adjustment module and the second input end of the phase frequency detector;

the phase frequency detector is configured to determine a frequency difference between a current received clock signal of the transceiver circuit and a clock signal output by the first phase-locked loop at a previous time;

The first phase-locked loop is used for outputting a first clock signal according to the frequency difference;

the clock adjustment module is used for determining a phase difference between a clock signal of the first transceiver and a current clock signal of the transceiver circuit; and adjusting the first clock signal according to the phase difference to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver; and updating a reception clock signal of the transceiver circuit to the second clock signal for receiving data from the first transceiver device.

According to the receiving and transmitting circuit for clock synchronization, the frequency phase discriminator in the receiving and transmitting circuit can determine the frequency difference between the current receiving clock signal of the receiving and transmitting circuit and the clock signal output at the last moment of the first phase-locked loop in the receiving and transmitting circuit; and the first phase-locked loop outputs a first clock signal according to the frequency difference; and then, a clock adjustment module in the transceiver circuit adjusts the first clock signal according to the phase difference between the clock signal of the first transceiver device and the clock signal output by the first phase-locked loop in the transceiver circuit at the last moment to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver device. Compared with the prior art, the transceiver circuit for clock synchronization provided by the embodiment of the application does not need to provide a master clock device for providing the reference clock signal, so that interface resources of the transceiver device are not occupied in the clock synchronization process, that is, the transceiver circuit for clock synchronization provided by the embodiment of the application can not occupy the interface resources of the transceiver device

In one possible implementation manner, the clock adjustment module may include: a phase detection module and a first phase interpolator; a first input end of the phase detection module is coupled to a first input end of the clock adjustment module, an output end of the phase detection module is connected with a first input end of a first phase interpolator, a second input end of the first phase interpolator is coupled to a second input end of the clock adjustment module, an output end of the first phase interpolator is coupled to a first output end of the clock adjustment module, and an output end of the first phase interpolator is connected with a second input end of the phase detection module;

the phase discrimination module is used for determining a phase difference between the clock signal of the first transceiver and the current clock signal of the transceiver circuit;

the first phase interpolator is configured to adjust the first clock signal according to the phase difference to obtain a second clock signal.

In one possible implementation manner, the transceiver circuit further includes: an analog-to-digital converter, the input end of which is coupled to the input end of the transceiver circuit, and the output end of which is connected to the input end of the clock adjustment module;

The analog-to-digital converter is configured to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

In a possible implementation manner, the transceiver circuit further includes a second phase interpolator, a first input end of the second phase interpolator is connected to the output end of the first phase-locked loop, a second input end of the second phase interpolator is connected to the second output end of the clock adjustment module, and an output end of the phase demodulation module is coupled to the second output end of the clock adjustment module;

the second phase interpolator is configured to adjust the first clock signal according to a phase difference output by the second output end of the clock adjustment module, to obtain a third clock signal, where the third clock signal is synchronous with the clock signal of the first transceiver device; and updating a transmission clock signal of the transceiver circuit to the third clock signal, wherein the third clock signal is used for transmitting data to the first transceiver device.

In one possible implementation manner, the transceiver circuit further includes: the input end of the second phase-locked loop is connected with the output end of the phase frequency detector, the output end of the second phase-locked loop is connected with the first input end of the second phase-locked interpolator, the second input end of the second phase-locked interpolator is connected with the second output end of the clock adjustment module, and the output end of the phase detection module is coupled to the second output end of the clock adjustment module;

The second phase-locked loop is configured to output a fourth clock signal according to the frequency difference;

the second phase interpolator is configured to adjust the fourth clock signal according to a phase difference output by the second output end of the clock adjustment module, to obtain a fifth clock signal, where the fifth clock signal is synchronous with the clock signal of the first transceiver; and updating a transmission clock signal of the transceiver circuit to the fifth clock signal, wherein the fifth clock signal is used for transmitting data to the first transceiver device.

In a second aspect, embodiments of the present application provide another transceiver circuit, including: the device comprises a clock adjustment module, a low-pass filter and a first phase-locked loop; the first input end of the clock adjustment module is coupled to the input end of the transceiver circuit, the first output end of the clock adjustment module is connected with the input end of the low-pass filter, the output end of the low-pass filter is connected with the input end of the first phase-locked loop, and the output end of the first phase-locked loop is connected with the second input end of the clock adjustment module;

the low-pass filter is used for determining the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal at one moment on the transceiver circuit;

the clock adjustment module is configured to determine a first phase difference according to a clock signal of the first transceiver and a current receiving clock signal of the transceiver circuit; adjusting the first clock signal according to the first phase difference to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver; and updating a receiving clock signal of the transceiver circuit to the second clock signal, wherein the second clock signal is used for receiving data from the first transceiver device.

According to the receiving and transmitting circuit for clock synchronization, the low-pass filter in the receiving and transmitting circuit can determine the frequency difference between the current receiving clock signal of the receiving and transmitting circuit and the receiving clock signal at one moment on the receiving and transmitting circuit, and the frequency difference is transmitted to the first phase-locked loop; the first phase-locked loop adjusts and outputs a first clock signal according to the frequency difference to the receiving clock signal at one moment on the transceiver circuit, so that the synchronization of the clock signal output by the first phase-locked loop at one moment and the current receiving clock signal of the transceiver circuit in frequency is realized; then, the clock adjustment module determines a first phase difference according to the clock signal of the first transceiver and the current receiving clock signal of the transceiver circuit; and adjusting the first clock signal according to the first phase difference to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver device. Compared with the prior art, the transceiver circuit for clock synchronization provided by the embodiment of the application does not need to set the master clock device for providing the reference clock signal, so that interface resources of the transceiver device are not occupied in the clock synchronization process, that is, the transceiver circuit for clock synchronization provided by the embodiment of the application can realize clock synchronization between the transceiver devices under the condition that the interface resources of the transceiver device are not occupied.

In one possible implementation manner, the low-pass filter is specifically configured to determine, according to a phase difference between a current received clock signal of the transceiver circuit and a received clock signal at a time on the transceiver circuit, the frequency difference between the current received clock signal of the transceiver circuit and the received clock signal at the time on the transceiver circuit.

In one possible implementation manner, the clock adjustment module includes a phase discrimination module and a first phase interpolator; the first input end of the phase detection module is coupled to the first input end of the clock adjustment module, the first output end of the phase detection module is coupled to the first output end of the clock adjustment module, the second output end of the phase detection module is connected with the first input end of the first phase interpolator, the second input end of the first phase interpolator is coupled to the second input end of the clock adjustment module, and the output end of the first phase interpolator is connected with the second input module of the phase detection module;

the phase discrimination module is configured to determine a first phase difference according to the clock signal of the first transceiver and the current receiving clock signal of the transceiver circuit;

the first phase interpolator is configured to adjust the first clock signal according to the first phase difference to obtain a second clock signal.

In one possible implementation, the transceiver circuit further includes an analog-to-digital converter, an input terminal of the analog-to-digital converter being coupled to the input terminal of the transceiver circuit, and an output terminal of the analog-to-digital converter being connected to the input terminal of the clock adjustment module;

In a possible implementation manner, the transceiver circuit further includes a second phase interpolator, a first input end of the second phase interpolator is connected to an output end of the first phase-locked loop, a second input end of the second phase interpolator is connected to a second output end of the clock adjustment module, and an output end of the phase demodulation module is further coupled to a second output end of the clock adjustment module;

the second phase interpolator is configured to adjust the first clock signal according to a second phase difference output by the second output end of the clock adjustment module, so as to obtain the third clock signal, where the third clock signal is synchronous with the clock signal of the first transceiver; and updating a transmission clock signal of the transceiver circuit to a third clock signal for transmitting data to the first transceiver device.

In one possible implementation manner, the transceiver circuit further includes a second phase interpolator and a second phase-locked loop, an input end of the second phase-locked loop is connected to an output end of the low-pass filter, an output end of the second phase-locked loop is connected to a first input end of the second phase interpolator, a second input end of the second phase interpolator is connected to a second output end of the clock adjustment module, and an output end of the phase demodulation module is further coupled to a second output end of the clock adjustment module;

the second phase interpolator is configured to adjust the fourth clock signal according to a phase difference output by the second output end of the clock adjustment module, so as to obtain the fifth clock signal, where the fifth clock signal is synchronous with the clock signal of the first transceiver; and updating a transmission clock signal of the transceiver circuit to the fifth clock signal, wherein the fifth clock signal is used for transmitting data to the first transceiver device.

In a third aspect, embodiments of the present application provide a transceiver device, where the transceiver device includes a transceiver circuit as described in any one of the first aspect and its possible implementation manners, or a transceiver circuit as described in any one of the second aspect and its possible implementation manners.

Drawings

FIG. 1 is a schematic diagram I of a circuit system for clock synchronization according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a phase shift according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram III of a transceiver circuit for clock synchronization according to an embodiment of the present application;

fig. 6 is a schematic diagram of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a communication system according to an embodiment of the present application;

fig. 9 is a schematic diagram of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram seventh of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram eight of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 12 is a schematic diagram nine of a transceiver circuit for clock synchronization according to an embodiment of the present application;

Fig. 13 is a schematic diagram of a transceiver circuit for clock synchronization according to an embodiment of the present disclosure;

fig. 14 is a schematic diagram of a second communication system according to an embodiment of the present application;

fig. 15 is a schematic diagram of a synchronous clock signal flow provided in an embodiment of the present application.

Detailed Description

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone.

The terms first and second and the like in the description and in the claims of embodiments of the present application are used for distinguishing between different objects and not necessarily for describing a particular sequential order of objects. For example, the first clock signal and the second clock signal, etc., are used to distinguish between different clock signals and are not used to describe a particular order of clock signals.

In the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" means two or more. For example, the plurality of processing units refers to two or more processing units; the plurality of systems means two or more systems.

Clock synchronization is the basis of communication between devices, and clock signal synchronization is needed in the process of data transmission between different devices. FIG. 1 is a schematic diagram of a prior art circuit for clock synchronization including device A, device B, device C, and a master clock device; the device A, the device B and the device C are all transceiver devices, and the structure of the transceiver devices is similar. In general, a transceiver apparatus includes: the device comprises a transmitting unit, a receiving unit and a phase buffer, wherein the transmitting unit is used for transmitting data, the receiving unit is used for receiving data, and the phase buffer is used for storing phase offset.

The clock signals used for transmitting or receiving data on the three devices a, B and C are different from each other, so that the master clock device provides a reference clock signal to the devices a, B and C, respectively, that is, the master clock device synchronizes the same reference clock signal to the devices a, B and C, respectively, so that the devices a, B and C all transmit or receive data using the reference clock signal provided by the master clock device, that is, the reference clock signal is the clock signal after clock synchronization by the three devices.

In the process of transmitting data according to the reference clock signal, the phase of the reference clock signal may deviate due to the influence of external factors such as ambient temperature or noise, so that the data transmission device needs to compensate the phase of the reference clock signal to reduce errors between clock signals of three devices, so that the clock signals of the three devices remain synchronous. As shown in fig. 2, before device a sends data to device B, device a first obtains phase offset 1 from the phase buffer, then device a adjusts the reference clock signal according to the phase offset 1 to obtain clock signal 1, and then sends data to device B according to clock signal 1. After device B obtains the actual clock signal (which may be clock signal 1 or may be a clock signal having a certain deviation from the phase of clock signal 1, the deviation being due to the influence of external factors such as ambient temperature or noise) of device a for transmitting data, device B calculates phase offset 2 from the actual clock signal and the reference clock signal of device B, device B adjusts the reference clock signal according to phase offset 2 to obtain clock signal 2, device B then receives device a for transmitting data based on clock signal 2, and device B transmits the phase offset 2 to device a based on clock signal 2 (it is understood that phase offset 2 is transmitted to device a as a data). Then, similarly, the device a calculates the phase offset 3 according to the obtained actual clock signal of the device B for transmitting data (the data is the phase offset 2) and the reference clock signal of the device a, then the device a adjusts the reference clock signal of the device a according to the phase offset 3 to obtain the clock signal 3, and then the device a receives the phase offset 2 transmitted by the device B based on the clock signal 3, and updates the phase offset stored in the phase buffer of the device a from the phase offset 1 to the phase offset 2 for transmitting data to the device B subsequently.

However, the above method of clock synchronization needs to separately provide a master clock device, and then a physical clock dedicated line is separately laid out to connect the master clock device with the data transmitting device and the data receiving device, which occupies the interface resources of the data transmitting device and the data receiving device.

Aiming at the problem that the transceiver occupies the interface resource of the transceiver in the process of clock synchronization in the prior art, the embodiment of the application provides a transceiver circuit for clock synchronization and the transceiver, which can realize clock synchronization among the transceivers under the condition of not occupying the interface resource of the transceiver.

As shown in fig. 3, a transceiver circuit provided in an embodiment of the present application includes: a clock adjustment module 13, a phase frequency detector 11 and a first phase-locked loop 12; the first input end 131 of the clock adjustment module 13 is coupled to the input end of the transceiver circuit, the first output end 132 of the clock adjustment module 13 is connected to the first input end 111 of the phase frequency detector 11, the output end 113 of the phase frequency detector 11 is connected to the input end 121 of the first phase-locked loop 12, and the output end 122 of the first phase-locked loop 12 is connected to the second input end 133 of the clock adjustment module 13 and the second input end 112 of the phase frequency detector 11.

The phase frequency detector 11 is configured to determine a frequency difference between a current received clock signal of the transceiver circuit and a clock signal output at a previous time of the first phase-locked loop 12; the first phase-locked loop 12 is configured to output a first clock signal according to the frequency difference; the clock adjustment module 13 is configured to determine a phase difference between a clock signal of the first transceiver device and a current clock signal of the transceiver circuit; adjusting the first clock signal according to the phase difference to obtain a second clock signal; and updating a reception clock signal of the transceiving circuit to a second clock signal, the second clock signal being synchronized with a clock signal of the first transceiving device, the second clock signal being used for receiving data from the first transceiving device.

In this embodiment, the current receiving clock signal (denoted as clock signal a) of the transceiver circuit is used as a reference clock signal of the phase frequency detector 11, the clock signal (denoted as clock signal b) output at the previous moment of the first phase-locked loop 12 is used as a feedback clock signal of the phase frequency detector 11, and the phase frequency detector 11 performs frequency discrimination on the reference clock signal and the feedback clock signal and outputs a frequency difference between the reference clock signal and the feedback clock signal.

For convenience of description, the transceiver device to which the transceiver circuit shown in fig. 3 is applied will be referred to as a second transceiver device.

Alternatively, the frequency difference between the reference clock signal and the feedback clock signal may be represented by a frequency control word indicating the frequency difference between clock signal a and clock signal b.

In this embodiment, after the frequency difference output by the phase frequency detector 11 is input to the first phase-locked loop 12, the first phase-locked loop 12 adjusts the frequency of the clock signal b according to the frequency difference, so as to obtain a first clock signal, where the frequency of the first clock signal is the same as the frequency of the clock signal b.

According to the receiving and transmitting circuit for clock synchronization, the frequency phase discriminator in the receiving and transmitting circuit can determine the frequency difference between the current receiving clock signal of the receiving and transmitting circuit and the clock signal output at the last moment of the first phase-locked loop in the receiving and transmitting circuit; and the first phase-locked loop outputs a first clock signal according to the frequency difference; and then, a clock adjustment module in the transceiver circuit adjusts the first clock signal according to the phase difference between the clock signal of the first transceiver device and the clock signal output by the first phase-locked loop in the transceiver circuit at the last moment to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver device. Compared with the prior art, the transceiver circuit for clock synchronization provided by the embodiment of the application does not need to separately provide the master clock device for providing the reference clock signal, so that interface resources of the transceiver device are not occupied in the clock synchronization process, that is, the transceiver circuit for clock synchronization provided by the embodiment of the application can realize clock synchronization between the transceiver devices under the condition of not occupying the interface resources of the transceiver device.

Optionally, in conjunction with fig. 3, as shown in fig. 4, the clock adjustment module 13 includes: a phase discrimination module 14 and a first phase interpolator 15; the first input 141 of the phase detection module 14 is coupled to the first input 131 of the clock adjustment module 13, the output 142 of the phase detection module 14 is connected to the first input 151 of the first phase interpolator 15, the second input 152 of the first phase interpolator 15 is coupled to the second input 133 of the clock adjustment module 13, the output 153 of the first phase interpolator 15 is coupled to the first output 132 of the clock adjustment module 13, and the output 153 of the first phase interpolator 15 is connected to the second input 143 of the phase detection module 14.

The phase discrimination module 14 is configured to determine a phase difference between a clock signal of the first transceiver and a current clock signal of the transceiver circuit; the first phase interpolator 15 is configured to adjust the first clock signal according to the phase difference, so as to obtain a second clock signal.

It should be understood that, in the process of adjusting the first clock signal by the first phase interpolator 15 according to the phase difference to obtain the second clock signal, the adjustment of the first clock signal may include any one of the following adjustment modes a or B.

Adjustment mode a: under the condition that the frequency of the clock signal of the first transceiver device and the frequency of the first clock signal have large phase difference, the frequency and the phase of the first clock signal need to be adjusted to obtain a second clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference, for example, when the phase difference is a positive number, the phase of the first clock signal is shifted forward (for example, shifted rightward along the X-axis direction of the coordinate system) by the phase difference; when the phase difference is negative, the phase of the first clock signal is shifted backwards, and the shift amount is the phase difference; since the phase difference is an integral of the frequency difference, the frequency difference between the clock signal of the first transceiver device and the first clock signal is calculated according to the phase difference, and then the frequency of the first clock signal is adjusted according to the frequency difference, for example, when the phase difference is a positive number, the frequency of the first clock signal is reduced by the frequency difference; when the phase difference is negative, the frequency of the first clock signal is increased by the frequency difference.

Adjustment mode B: under the condition that the frequency difference between the clock signal of the first transceiver device and the frequency of the first clock signal is smaller, the frequency of the first clock signal (the frequency difference between the first clock signal and the frequency of the clock signal of the first transceiver device is small, and the frequency difference is negligible, namely, the frequency of the first clock signal is considered to be approximately equal to the frequency of the first transceiver device), and only the phase of the first clock signal is adjusted to obtain the second clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference, for example, when the phase difference is a positive number, the phase of the first clock signal is shifted forward by the phase difference; when the phase difference is negative, the phase of the first clock signal is shifted backward by the phase difference.

Optionally, in conjunction with fig. 4, as shown in fig. 5, a transceiver circuit for clock synchronization provided in an embodiment of the present application may further include: the input 161 of the analog-to-digital converter 16 is coupled to the input of the transceiver circuit, and the output 162 of the analog-to-digital converter 16 is connected to the input 131 of the clock adjustment module 13.

The analog-to-digital converter 16 is configured to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

It will be appreciated that the processing of the clock signal is typically performed in the form of a digital signal, and therefore, after the transceiver circuitry has acquired the clock signal of the first transceiver device (which is an analog signal), the clock signal of the first transceiver device is converted from an analog signal to a digital signal via the analog-to-digital converter 16, and then the clock signal in the form of the digital signal is input to the clock adjustment module 13.

Optionally, the transceiver circuit for clock synchronization provided in the embodiments of the present application may further include a component or a module for synchronizing a transmit clock signal of the transceiver circuit, that is, in a process that the transceiver circuit receives data sent by the first transceiver device, not only synchronizes a receive clock signal of the transceiver circuit with a clock signal of the first transceiver device, but also synchronizes the transmit clock signal of the transceiver circuit with the clock signal of the first transceiver circuit.

In one implementation manner, as shown in fig. 6 in conjunction with fig. 5, the transceiver circuit for clock synchronization provided in this embodiment of the present application further includes a second phase interpolator 17, where a first input 171 of the second phase interpolator 17 is connected to the output 122 of the first phase locked loop, a second input 172 of the second phase interpolator 17 is connected to the second output 134 of the clock adjustment module 13, and the output 142 of the phase demodulation module 14 is coupled to the second output 134 of the clock adjustment module 13.

The second phase interpolator 17 is configured to adjust the first clock signal according to the phase difference output by the second output end 134 of the clock adjustment module 13, so as to obtain a third clock signal, where the third clock signal is synchronous with the clock signal of the first transceiver device; and updating a transmit clock signal of the transceiving circuit to a third clock signal, the third clock signal being used for transmitting data to the first transceiving device.

It should be understood that, similar to the above-mentioned process that the first phase interpolator 15 is configured to adjust the first clock signal according to the above-mentioned phase difference to obtain the second clock signal, the second phase interpolator 17 is configured to adjust the first clock signal according to the above-mentioned phase difference to obtain the third clock signal, where the adjustment of the first clock signal may include any one of the following adjustment modes C and D.

Adjustment mode C: when the frequency of the clock signal of the first transceiver device is greatly different from the frequency of the first clock signal, the frequency and the phase of the first clock signal need to be adjusted to obtain a third clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference; since the phase difference is an integral of the frequency difference, the frequency difference between the clock signal of the first transceiver and the first clock signal is calculated according to the phase difference, and then the frequency of the first clock signal is adjusted according to the frequency difference, so as to obtain an adjusted first clock signal, namely a third clock signal.

It should be understood that the adjustment mode C is similar to the adjustment mode a, and specific reference may be made to the description of the adjustment mode a in the above embodiment.

Adjustment mode D: and under the condition that the frequency of the clock signal of the first transceiver device and the frequency of the first clock signal have smaller phase difference, only the phase of the first clock signal is adjusted to obtain a third clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference, so as to obtain an adjusted first clock signal, i.e., a third clock signal.

It should be understood that the adjustment mode D is similar to the adjustment mode B, and specific reference may be made to the description of the adjustment mode B in the above embodiment.

Optionally, the second transceiver device to which the transceiver circuit provided in the embodiment of the present application is applied includes a transmitting unit and a receiving unit, and it should be understood that the clock adjustment module 13 in the transceiver circuit is disposed on the receiving unit, and the second phase interpolator 17 is disposed on the transmitting unit.

After the second phase interpolator 17 obtains the phase difference between the clock signal of the first transceiver device and the first clock signal, the phase difference may be stored in a buffer table (e.g., look Up Table (LUT)) corresponding to the second phase interpolator 17, and when the second transceiver device sends data to the first transceiver device, the second phase interpolator 17 reads the phase difference from the LUT table, and adjusts the first clock signal according to the phase difference to obtain a third clock signal, so that the second transceiver device sends data to the first transceiver device according to the third clock signal.

Optionally, before the clock signal of the first transceiver device and the phase difference of the first clock signal are input to the second phase interpolator 17, the phase demodulation module 14 in the clock adjustment module 13 filters the phase difference (i.e. the phase demodulation module 14 includes a filter), and the first phase interpolator 15 adjusts the first clock signal according to the filtered phase difference (i.e. a more accurate phase difference); meanwhile, the phase difference stored in the buffer table corresponding to the second phase interpolator 17 is also the filtered phase difference.

In another implementation manner, in conjunction with fig. 5, as shown in fig. 7, a transceiver circuit for clock synchronization provided in an embodiment of the present application may further include: the input end 181 of the second phase-locked loop 18 is connected to the output end 113 of the phase frequency detector 11, the output end 182 of the second phase-locked loop 18 is connected to the first input end 171 of the second phase-locked interpolator 17, the second input end 172 of the second phase-locked interpolator 17 is connected to the second output end 134 of the clock adjustment module 13, and the output end 142 of the phase detection module 14 is coupled to the second output end 134 of the clock adjustment module 13.

The second phase-locked loop 18 is configured to output a fourth clock signal according to a frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal at a time on the transceiver circuit; a second phase interpolator 17, configured to adjust a fourth clock signal according to the phase difference output by the second output end 134 of the clock adjustment module 13, so as to obtain a fifth clock signal, where the fifth clock signal is synchronous with the clock signal of the first transceiver device; and updating a transmission clock signal of the transceiving circuit to a fifth clock signal, wherein the fifth clock signal is used for transmitting data to the first transceiving equipment.

The fourth clock signal and the first clock signal are both clock signals output according to a frequency difference between the current reception clock signal of the transceiver circuit and the clock signal output at the previous time of the first phase-locked loop 12, so the fourth clock signal and the first clock signal are identical clock signals.

It should be understood that, in the process of adjusting the fourth clock signal by the second phase interpolator 17 according to the phase difference to obtain the fifth clock signal, the adjustment of the fourth clock signal may include any one of the following adjustment modes E and F.

Adjustment mode E: when the frequency of the clock signal of the first transceiver device and the frequency of the fourth clock signal have a large difference, the frequency and the phase of the fourth clock signal need to be adjusted to obtain a fifth clock signal. The adjustment mode E is similar to the adjustment mode a, and specific reference is made to the description of the adjustment mode a in the above embodiment.

Adjustment mode F: when the frequency of the clock signal of the first transceiver device and the frequency of the fourth clock signal have a small phase difference, only the phase of the fourth clock signal is adjusted to obtain a fifth clock signal. The adjustment mode F is similar to the adjustment mode B, and specific reference is made to the description of the adjustment mode B in the above embodiment.

Accordingly, the embodiment of the application provides a transceiver device, which comprises a transceiver circuit as shown in any one of fig. 3-7, and clock synchronization can be realized between the transceiver devices with the structural characteristics based on the transceiver circuit.

A process of synchronizing clock signals when transmitting data between the above-mentioned transceiver devices is described in detail below taking a communication system composed of a plurality of transceiver devices (e.g., a first transceiver device and a second transceiver device) including the transceiver circuit provided in the embodiment of the present application as an example.

As shown in fig. 8, when the first transceiver device sends first data to the second transceiver device according to its own clock signal, the specific process of synchronizing the clock signal of the first transceiver device by the transceiver circuit corresponding to the second transceiver device is: a clock adjustment module in the second transceiver determines the phase difference 1 of the clock signals according to the clock signal corresponding to the first data and the current receiving clock signal of the second transceiver; the clock adjustment module adjusts the phase and the frequency of a clock signal output at the last moment of the first phase-locked loop according to the phase difference 1 to obtain a clock signal 1, wherein the clock signal 1 is synchronous with a clock signal of first receiving and transmitting equipment; at this time, the clock adjustment module updates the current received clock signal of the second transceiver device to the clock signal 1. In addition, the clock adjustment module of the second transceiver device transmits the phase difference 1 to a second phase shifter of the second transceiver device; and at the same time, the clock adjustment module of the second transceiver transmits the clock signal 1 to the phase frequency discriminator, the phase frequency discriminator determines the frequency difference 1 of the two clock signals according to the clock signal 1 and the clock signal output by the first phase-locked loop at the last moment, the phase frequency discriminator transmits the frequency difference 1 to the first phase-locked loop, the first phase-locked loop adjusts the frequency of the clock signal output by the first phase-locked loop at the last moment according to the frequency difference 1 to obtain a clock signal 2, wherein the clock signal 2 is synchronous with the frequency of the clock signal 1, and the first phase-locked loop transmits the clock signal 2 to a transmitting unit and a receiving unit of the second transceiver so that when the first transceiver transmits second data to the second transceiver, the clock adjustment module adjusts the clock signal 2 according to the phase difference 2 and then recovers the clock signal corresponding to the second data.

When the first transceiver transmits the second data to the second transceiver, the phase of the clock signal of the transmitted data may be shifted due to the influence of external factors; therefore, when the first transceiver device sends the second data to the second transceiver device, the second transceiver device needs to continuously and synchronously send the clock signal corresponding to the second data, and the synchronization process of the clock signal specifically includes: the clock adjustment module in the second transceiver device determines the phase difference 2 of the clock signals according to the clock signal corresponding to the second data and the current receiving clock signal (namely, the clock signal 1) of the second transceiver device; the clock adjustment module adjusts the phase and frequency of the clock signal 2 output at the last moment of the first phase-locked loop according to the phase difference 2 to obtain a clock signal 3, and what needs to be described here is: the clock signal 3 is synchronized with the frequency of the first transceiver device, so that the clock adjustment module adjusts the frequency of the clock signal 3 by a negligible amount according to the phase difference 2. Then, the clock adjustment module updates the current receiving clock signal (namely, the clock signal 1) of the second transceiver device to a clock signal 3, and in addition, the clock adjustment module transmits the phase difference 2 to a transmitting unit of the second transceiver device; at the same time, the clock adjustment module sends the clock signal 3 to the phase frequency detector; the phase frequency detector determines the frequency difference 2 of the clock signal 3 and the clock signal 2 output by the first phase-locked loop at the last moment, and sends the frequency difference 2 to the first phase-locked loop. The first phase-locked loop adjusts the frequency of the clock signal 2 output by the first phase-locked loop at the last moment according to the frequency difference 2 to obtain a clock signal 4, wherein the clock signal 4 is synchronous with the frequency of the clock signal 3, and the first phase-locked loop sends the clock signal 4 to a sending unit and a receiving unit of the second transceiver.

When the sending unit of the second transceiver receives the clock signal 2 and the phase difference 1, the sending unit synchronizes the clock signal 2 and stores the phase difference in a buffer table corresponding to the sending unit; when the transmitting unit of the second transceiver receives the clock signal 4 and the phase difference 2, the transmitting unit synchronizes the clock signal 4 and updates the phase difference 1 corresponding to the first transceiver in the buffer table to the phase difference 2. When the second transceiver transmits data to the first transceiver, the second phase interpolator in the transmitting unit of the second transceiver adjusts the clock signal 4 according to the phase difference 2 to obtain the clock signal 5, and uses the clock signal 5 to transmit data to the first transceiver, wherein the clock signal 5 is synchronous with the clock signal of the first transceiver.

Aiming at the problem that the transceiver occupies the interface resource of the transceiver in the process of clock synchronization in the prior art, the embodiment of the application provides another transceiver circuit for clock synchronization and the transceiver, which can realize clock synchronization between the transceivers under the condition of not occupying the interface resource of the transceiver.

As shown in fig. 9, a transceiver circuit provided in an embodiment of the present application includes: a clock adjustment module 23, a low pass filter 21 and a first phase locked loop 22; the first input 231 of the clock adjustment module 23 is coupled to the input of the transceiver circuit, the first output 232 of the clock adjustment module 23 is connected to the input 211 of the low-pass filter 21, the output 212 of the low-pass filter 21 is connected to the input 221 of the first phase-locked loop 22, and the output 222 of the first phase-locked loop 22 is connected to the second input 233 of the clock adjustment module 23.

The low-pass filter 21 is used for determining the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal at the moment of the transceiver circuit; the first phase-locked loop 22 is configured to output a first clock signal according to the frequency difference; the clock adjustment module 23 is configured to determine a first phase difference according to a clock signal of the first transceiver and a current receiving clock signal of the transceiver; adjusting the first clock signal according to the first phase difference to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver; and updating a reception clock signal of the transceiving circuit to a second clock signal, the second clock signal being used for receiving data from the first transceiving device.

In this embodiment of the present application, the low-pass filter 21 is specifically configured to determine, according to a phase difference between a current receiving clock signal of the transceiver circuit and a receiving clock signal of a previous time of the transceiver circuit, which are output by the clock adjustment module 23, a frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the previous time of the transceiver circuit. The method for determining the frequency difference specifically comprises the following steps: based on the relationship that the phase difference is an integral of the frequency difference, the frequency difference between the current receive clock of the transceiver circuit and the receive clock signal at a time on the transceiver circuit is calculated from the phase difference.

It should be understood that, the first phase-locked loop 22 is specifically configured to adjust the frequency of the clock signal output at the moment on the first phase-locked loop 22 according to the frequency difference between the current receiving clock of the transceiver circuit and the receiving clock signal at the moment on the transceiver circuit, for example, when the phase difference is a positive number, the frequency of the clock signal output at the moment on the first phase-locked loop 22 is reduced, where the reduced amount is the frequency difference; when the phase difference is negative, increasing the frequency of the clock signal outputted from the first phase-locked loop 22 at a moment by the frequency difference; thereby obtaining a first clock signal. Wherein the first clock signal is synchronized with the frequency of the current receiving clock of the transceiver circuit.

Alternatively, the frequency difference may be expressed in terms of a frequency control word, which is used to indicate the frequency difference between the current receive clock of the transceiver circuit and the receive clock signal at a time on the transceiver circuit.

It should be understood that, the first clock signal is adjusted according to the phase difference to obtain the second clock signal, and the manner in which the first clock signal is adjusted may be specifically referred to the related description of the above embodiment, which is not repeated herein.

Optionally, in conjunction with fig. 9, as shown in fig. 10, the clock adjustment module 23 specifically includes: a phase discrimination module 30 and a first phase interpolator 31; the first input 301 of the phase detection module 30 is coupled to the first input 231 of the clock adjustment module, the first output 302 of the phase detection module 30 is coupled to the first output 232 of the clock adjustment module 23, the second output 303 of the phase detection module 30 is connected to the first input 311 of the first phase interpolator 31, the second input 312 of the first phase interpolator 31 is coupled to the second input 233 of the clock adjustment module 23, and the output 313 of the first phase interpolator 31 is connected to the second input 304 of the phase detection module 30.

The phase discrimination module 30 is configured to determine the first phase difference according to a clock signal of the first transceiver and a current receiving clock signal of the transceiver circuit; the first phase interpolator 31 is configured to adjust the first clock signal according to the first phase difference, so as to obtain a second clock signal.

Optionally, the first output terminal 302 and the second output terminal 303 of the phase detection module 30 are both configured to output a phase difference, and the phase difference output by the first output terminal 302 of the phase detection module 30 may be represented by a phase codeword, where the phase codeword is used to indicate a phase difference between a clock signal of the first transceiver device and a current received clock signal of the transceiver circuit.

Optionally, in conjunction with fig. 10, as shown in fig. 11, a transceiver circuit for clock synchronization provided in an embodiment of the present application may further include: analog-to-digital converter 24, input 241 of analog-to-digital converter 24 is coupled to an input of the transceiver circuit, and output 242 of analog-to-digital converter is coupled to input 231 of clock adjustment module 23.

Wherein the analog-to-digital converter 24 is configured to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

It will be appreciated that the processing of the clock signal is typically performed in the form of a digital signal, and therefore, after the transceiver circuitry has acquired the clock signal of the first transceiver device (which is an analog signal), the clock signal of the first transceiver device is converted from an analog signal to a digital signal via the analog-to-digital converter 24, and then the clock signal in the form of the digital signal is input to the clock adjustment module 23.

In an implementation manner, in conjunction with fig. 11, as shown in fig. 12, a transceiver circuit for clock synchronization provided in an embodiment of the present application may further include: the second phase interpolator 25, the first input 251 of the second phase interpolator 25 is connected to the output 222 of the first phase locked loop 22, the second input 252 of the second phase interpolator 25 is connected to the second output 234 of the clock adjustment module 23, and the output 303 of the phase discrimination module 30 is further coupled to the second output 234 of the clock adjustment module 23.

The second phase interpolator 25 is configured to adjust the first clock signal according to a second phase difference output by the second output end 234 of the clock adjustment module 23, so as to obtain a third clock signal, where the third clock signal is synchronous with the clock signal of the first transceiver device; and updating a transmit clock signal of the transceiving circuit to a third clock signal, the third clock signal being used for transmitting data to the first transceiving device.

It should be understood that, the first clock signal is adjusted according to the second phase difference to obtain the third clock signal, and the manner in which the first clock signal is adjusted may be specifically referred to the related description of the above embodiment, which is not repeated herein.

Optionally, the transceiver device corresponding to the transceiver circuit provided in the embodiment of the present application includes a transmitting unit and a receiving unit, and it should be understood that the clock adjustment module 23 in the transceiver circuit is disposed on the receiving unit, and the second phase interpolator 25 is disposed on the transmitting unit.

It should be noted that, after the second phase interpolator 25 obtains the first clock signal and the second phase difference, the first clock signal is synchronized, and the second phase difference is stored in a buffer table corresponding to the second phase interpolator 25, so long as when the transceiver circuit transmits data to the first transceiver device, the second phase interpolator 25 adjusts the first clock signal according to the second phase difference to obtain a third clock signal, and the third clock signal is used for transmitting data to the first transceiver device.

Optionally, before the second phase difference is input to the second phase interpolator 25, the phase demodulation module 30 (in this case, the phase demodulation module 30 includes a filter) in the clock adjustment module 23 filters the phase difference, and the first phase interpolator 31 adjusts the first clock signal according to the filtered second phase difference (i.e., a more accurate phase difference); meanwhile, the phase difference stored in the buffer table corresponding to the second phase interpolator 25 is also the filtered second phase difference.

In another implementation, in conjunction with FIG. 11, as shown in FIG. 13; the transceiver circuit for clock synchronization provided in the embodiment of the present application may further include: the second phase interpolator 25 and the second phase-locked loop 26, the input 261 of the second phase-locked loop 26 is connected to the output 212 of the low-pass filter 21, the output 262 of the second phase-locked loop 26 is connected to the first input 251 of the second phase interpolator 25, the second input 252 of the second phase interpolator 25 is connected to the second output 234 of the clock adjustment module 23, and the output 303 of the phase discrimination module 30 is further coupled to the second output 234 of the clock adjustment module 23.

The second phase-locked loop 26 is configured to output a fourth clock signal according to a frequency difference between the current received clock signal of the power generation circuit and the received clock signal at a time on the transceiver circuit; a second phase interpolator 25, configured to adjust a fourth clock signal according to the phase difference output by the second output end 234 of the clock adjustment module 23, so as to obtain a fifth clock signal, where the fifth clock signal is synchronous with the clock signal of the first transceiver device; and updating a transmit clock signal of the transceiving circuit to a fifth clock signal for transmitting data to the first transceiving device.

It should be understood that, the fourth clock signal and the first clock signal are both output clock signals according to the frequency difference between the current receiving clock signal of the power generating circuit and the receiving clock signal at the moment on the transceiver circuit, so that the fourth clock signal is identical to the first clock signal.

Accordingly, the embodiment of the application provides a transceiver device, which comprises a transceiver circuit as shown in any one of fig. 9-13, and clock synchronization can be realized between the transceiver devices with the structural characteristics based on the transceiver circuit.

The following describes in detail a process of performing a clock signal in a process of transmitting data between the above-mentioned transceiver devices, taking a communication system composed of a plurality of transceiver devices (for example, a first transceiver device and a second transceiver device) including a transceiver circuit provided in the embodiment of the present application as an example.

As shown in fig. 14, when the first transceiving equipment transmits first data to the second transceiving equipment; a clock adjustment module in the second transceiver determines the phase difference 1 of the clock signals corresponding to the first data according to the clock signals and the current receiving clock signals of the second transceiver; the clock adjustment module adjusts the phase and the frequency of a clock signal output at the last moment of the first phase-locked loop according to the phase difference 1 to obtain a clock signal 1, wherein the clock signal 1 is synchronous with a clock signal of first transceiver equipment; at this time, the clock adjustment module updates the current receiving clock signal of the second transceiver to the clock signal 1; further, the clock adjustment module transmits the phase difference 1 to the transmitting unit of the second transmitting-receiving device and the low-pass filter. The low-pass filter determines the frequency difference 1 between the clock signal corresponding to the first data and the current receiving clock signal (the receiving clock signal before being updated) of the second transceiver according to the phase difference 1, and sends the frequency difference 1 to the first phase-locked loop. The first phase-locked loop adjusts the frequency of a clock signal output by the first phase-locked loop at the last moment according to the frequency difference 1 to obtain a clock signal 2, wherein the clock signal 2 is synchronous with the frequency of the clock signal 1, and the first phase-locked loop sends the clock signal 2 to a sending unit and a receiving unit of the second receiving and transmitting equipment so as to be used for adjusting the clock signal 2 according to the phase difference 2 when the first receiving and transmitting equipment sends second data to the second receiving and transmitting equipment subsequently, and then the clock signal corresponding to the second data is recovered.

When the first transceiver transmits the second data to the second transceiver, the phase of the clock signal of the transmitted data may be shifted due to the influence of external factors; therefore, when the first transceiver device sends the second data to the second transceiver device, the second transceiver device needs to continuously synchronize the clock signal corresponding to the second data, and the synchronization process of the clock signal specifically includes: the clock adjustment module in the second transceiver device determines the phase difference 2 of the clock signals according to the clock signal corresponding to the second data and the current receiving clock signal (namely, the clock signal 1) of the second transceiver device; the clock adjustment module adjusts the phase and frequency of the clock signal 2 output at the last moment of the first phase-locked loop according to the phase difference 2 to obtain a clock signal 3, and what needs to be described here is: the clock signal 3 is synchronous with the frequency of the first transceiver, so the clock adjustment module adjusts the frequency of the clock signal 3 by a small and negligible amount according to the phase difference 2; then, the clock adjustment module updates the current receiving clock signal (i.e. the clock signal 1) of the second transceiver device to the clock signal 3, and in addition, the clock adjustment module sends the phase difference 2 to the sending unit of the second transceiver device and the low-pass filter, and the low-pass filter determines the frequency difference 2 between the clock signal corresponding to the second data and the clock signal 2 output at the last moment of the first phase-locked loop according to the phase difference 2, and sends the frequency difference 2 to the first phase-locked loop. The first phase-locked loop adjusts the frequency of the clock signal 2 output by the first phase-locked loop at the last moment according to the frequency difference 2 to obtain a clock signal 4, wherein the clock signal 4 is synchronous with the frequency of the clock signal 3, and the first phase-locked loop sends the clock signal 4 to a sending unit and a receiving unit of the second transceiver.

As shown in fig. 15, which is a schematic flow chart of a transceiver circuit provided in the embodiment of the present application when synchronizing clock signals of opposite ends, after a transceiver system newly joins a first transceiver device, a second transceiver device periodically sends a random code to the first transceiver device, where the random code may be first data or second data in the above embodiment, or may be other non-service data, so that a receiving clock signal of the first transceiver device is synchronized with a sending clock signal of the second transceiver device. When the second transceiver transmits service data to the first transceiver, the receiving clock signal of the first transceiver synchronizes the transmitting clock signal of the second transceiver, and the influence of external factors such as ambient temperature and ambient noise on the clock signal is more apparent on the phase, so that the first transceiver adjusts the phase of the current receiving clock signal of the first transceiver according to the phase difference between the receiving clock signal corresponding to the service data and the first transceiver, and the synchronization of the receiving clock signal of the first transceiver and the clock signal corresponding to the service data is realized, thereby the first transceiver obtains the service data transmitted by the second transceiver according to the synchronized receiving clock signal.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the methods described in the various embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

A transceiver circuit, comprising: the device comprises a clock adjustment module, a phase frequency detector and a first phase-locked loop; the first input end of the clock adjustment module is coupled to the input end of the transceiver circuit, the first output end of the clock adjustment module is connected with the first input end of the phase frequency detector, the output end of the phase frequency detector is connected with the input end of the first phase-locked loop, and the output end of the first phase-locked loop is connected with the second input end of the clock adjustment module and the second input end of the phase frequency detector;

the phase frequency detector is used for determining the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output by the first phase-locked loop at the last moment;

the first phase-locked loop is used for outputting a first clock signal according to the frequency difference;

The clock adjustment module is used for determining a phase difference between a clock signal of the first transceiver and a current clock signal of the transceiver circuit; the first clock signal is adjusted according to the phase difference, so that a second clock signal is obtained, and the second clock signal is synchronous with the clock signal of the first transceiver; and updating a reception clock signal of the transceiving circuit to the second clock signal, the second clock signal being used for receiving data from the first transceiving device.
The transceiver circuit of claim 1, wherein the clock adjustment module comprises a phase discrimination module and a first phase interpolator; the first input end of the phase detection module is coupled to the first input end of the clock adjustment module, the output end of the phase detection module is connected with the first input end of the first phase interpolator, the second input end of the first phase interpolator is coupled to the second input end of the clock adjustment module, the output end of the first phase interpolator is coupled to the first output end of the clock adjustment module, and the output end of the first phase interpolator is connected with the second input end of the phase detection module;

The phase discrimination module is used for determining a phase difference between a clock signal of the first transceiver and a current clock signal of the transceiver circuit;

the first phase interpolator is configured to adjust the first clock signal according to the phase difference to obtain a second clock signal.
Transceiver circuit according to claim 1 or 2, further comprising an analog-to-digital converter, the input of which is coupled to the input of the transceiver circuit, the output of which is connected to the input of the clock adjustment module;

the analog-to-digital converter is used for converting the clock signal of the first transceiver device from an analog signal to a digital signal.
A transceiver circuit according to any one of claims 1 to 3, further comprising a second phase interpolator, a first input of the second phase interpolator being connected to the output of the first phase locked loop, a second input of the second phase interpolator being connected to the second output of the clock adjustment module, an output of the phase demodulation module being coupled to the second output of the clock adjustment module;

The second phase interpolator is configured to adjust the first clock signal according to a phase difference output by the second output end of the clock adjustment module, so as to obtain a third clock signal, where the third clock signal is synchronous with the clock signal of the first transceiver; and updating a transmission clock signal of the transceiver circuit to the third clock signal, wherein the third clock signal is used for transmitting data to the first transceiver device.
A transceiver circuit according to any one of claims 1 to 3, further comprising: the input end of the second phase-locked loop is connected with the output end of the phase frequency detector, the output end of the second phase-locked loop is connected with the first input end of the second phase-locked interpolator, the second input end of the second phase-locked interpolator is connected with the second output end of the clock adjustment module, and the output end of the phase detection module is coupled to the second output end of the clock adjustment module;

the second phase-locked loop is used for outputting a fourth clock signal according to the frequency difference;

the second phase interpolator is configured to adjust the fourth clock signal according to a phase difference output by the second output end of the clock adjustment module, so as to obtain a fifth clock signal, where the fifth clock signal is synchronous with the clock signal of the first transceiver; and updating a transmission clock signal of the transceiving circuit to the fifth clock signal, wherein the fifth clock signal is used for transmitting data to the first transceiving equipment.
A transceiver circuit, comprising: the device comprises a clock adjustment module, a low-pass filter and a first phase-locked loop; the first input end of the clock adjustment module is coupled to the input end of the transceiver circuit, the first output end of the clock adjustment module is connected with the input end of the low-pass filter, the output end of the low-pass filter is connected with the input end of the first phase-locked loop, and the output end of the first phase-locked loop is connected with the second input end of the clock adjustment module;

the low-pass filter is used for determining the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal at one moment on the transceiver circuit;

the first phase-locked loop is used for outputting a first clock signal according to the frequency difference;

the clock adjustment module is used for determining a first phase difference according to the clock signal of the first transceiver and the current receiving clock signal of the transceiver circuit; adjusting the first clock signal according to the first phase difference to obtain a second clock signal, wherein the second clock signal is synchronous with the clock signal of the first transceiver; and updating a reception clock signal of the transceiving circuit to the second clock signal, the second clock signal being used for receiving data from the first transceiving device.
The transceiver circuit of claim 6, wherein,

the low-pass filter is specifically configured to determine, according to a phase difference between a current receiving clock signal of the transceiver circuit and a receiving clock signal of a previous time of the transceiver circuit, which are output by the clock adjustment module, a frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the previous time of the transceiver circuit.
The transceiver circuit of claim 6 or 7, wherein the clock adjustment module comprises a phase discrimination module and a first phase interpolator; the first input end of the phase detection module is coupled to the first input end of the clock adjustment module, the first output end of the phase detection module is coupled to the first output end of the clock adjustment module, the second output end of the phase detection module is connected with the first input end of the first phase interpolator, the second input end of the first phase interpolator is coupled to the second input end of the clock adjustment module, and the output end of the first phase interpolator is connected with the second input module of the phase detection module;

the phase discrimination module is used for determining the first phase difference according to the clock signal of the first transceiver and the current receiving clock signal of the transceiver circuit;

The first phase interpolator is configured to adjust the first clock signal according to the first phase difference to obtain a second clock signal.
The transceiver circuit of any one of claims 6-8, further comprising an analog-to-digital converter, an input of the analog-to-digital converter being coupled to an input of the transceiver circuit, an output of the analog-to-digital converter being connected to an input of the clock adjustment module;

the analog-to-digital converter is used for converting the clock signal of the first transceiver device from an analog signal to a digital signal.
The transceiver circuit of any one of claims 6 to 9, further comprising a second phase interpolator, a first input of the second phase interpolator being connected to the output of the first phase locked loop, a second input of the second phase interpolator being connected to the second output of the clock adjustment module, the output of the phase demodulation module being further coupled to the second output of the clock adjustment module;

the second phase interpolator is configured to adjust the first clock signal according to a second phase difference output by a second output end of the clock adjustment module, so as to obtain the third clock signal, where the third clock signal is synchronous with a clock signal of the first transceiver; and updating a transmission clock signal of the transceiver circuit to the third clock signal, wherein the third clock signal is used for transmitting data to the first transceiver device.
The transceiver circuit of any one of claims 6 to 9, further comprising a second phase interpolator and a second phase locked loop, the input of the second phase locked loop being connected to the output of the low pass filter, the output of the second phase locked loop being connected to the first input of the second phase interpolator, the second input of the second phase interpolator being connected to the second output of the clock adjustment module, the output of the phase demodulation module being further coupled to the second output of the clock adjustment module;

the second phase-locked loop is used for outputting a fourth clock signal according to the frequency difference;

the second phase interpolator is configured to adjust the fourth clock signal according to a phase difference output by the second output end of the clock adjustment module, so as to obtain the fifth clock signal, where the fifth clock signal is synchronous with the clock signal of the first transceiver; and updating a transmission clock signal of the transceiving circuit to the fifth clock signal, wherein the fifth clock signal is used for transmitting data to the first transceiving equipment.
A transceiver device comprising a transceiver circuit as claimed in any one of claims 1 to 5 or a transceiver circuit as claimed in any one of claims 6 to 11.