CN117478463A

CN117478463A - Equalizer circuit

Info

Publication number: CN117478463A
Application number: CN202310926654.6A
Authority: CN
Inventors: 斋藤晋一
Original assignee: Rohm Co Ltd
Current assignee: Rohm Co Ltd
Priority date: 2022-07-28
Filing date: 2023-07-26
Publication date: 2024-01-30
Also published as: US20240039495A1; JP2024017878A

Abstract

The invention provides an equalizer circuit capable of shaping a multivalued PAM signal. The equalizer circuit (600) includes a variable gain equalizer circuit (610). A3 rd transistor (MN 53) for gain adjustment is inserted between the source of the 1 st transistor (MN 51) and the 1 st current source (IB 51) of the variable gain equalizer circuit (610) constituting the input differential pair. A4 th transistor (MN 54) for gain adjustment is inserted between the source of the 2 nd transistor (MN 52) and the 2 nd current source (IB 52) constituting the input differential pair. The gates of the 3 rd transistor (MN 53) and the 4 th transistor (MN 54) are supplied with the 1 st bias voltage (Vb 1), wherein the DC gain of the variable gain equalizer circuit (610) can be controlled.

Description

Equalizer circuit

Technical Field

The present disclosure relates to an equalizer circuit.

Background

In the conventional serial data transmission, an NRZ (Non Return to Zero: non-return to zero) scheme is the main stream, but in the application requiring a higher transmission rate, a multi-value PAM scheme such as PAM (Pulse Amplitude Modulation: pulse amplitude modulation) 4 is adopted.

[ Prior Art literature ]

[ non-patent literature ]

Non-patent document 1, "6.6A22.5-to-32 Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in nm CMOS",2017IEEE International Solid-State Circuits Confe rence

Disclosure of Invention

[ problem to be solved by the invention ]

In high-speed serial data transmission, waveform distortion occurring when propagating from a transmission path is a problem. The main cause of waveform distortion in the transmission path is high frequency attenuation. As a method of correcting waveform distortion, there is known: pre-emphasis, which pre-emphasizes high frequencies at the transmitting circuit side in order to counteract attenuation in the transmission path; de-emphasis, which pre-attenuates low frequencies at the transmit circuit side in order to balance the high frequencies attenuated in the transmission path.

Alternatively, as another method, the reception device may employ a method of equalizing the reception signal and performing waveform shaping. Further, in the receiving apparatus, it is necessary to amplify the received signal to match the input range of the a/D converter (quantizer) of the subsequent stage. Therefore, in the receiving apparatus, an amplifying function and an equalizing function are necessary.

The present disclosure has been made in view of the related circumstances, and one of exemplary objects thereof is to provide an equalizer circuit capable of properly receiving a multivalued PAM signal.

[ solution for solving the technical problem ]

One aspect of the present disclosure relates to an equalizer circuit. The equalizer circuit includes: a variable gain equalizer circuit, and a 1 st bias circuit that generates a 1 st bias voltage. The variable gain equalizer circuit includes: a 1 st input terminal; a 2 nd input terminal; a 1 st transistor having a gate connected to the 1 st input terminal; a 2 nd transistor having a gate connected to the 2 nd input terminal; the 1 st resistor is connected with the drain electrode of the 1 st transistor; the 2 nd resistor is connected with the drain electrode of the 2 nd transistor; a 1 st current source; a 2 nd current source; a 3 rd transistor connected between the source of the 1 st transistor and the 1 st current source, the gate of which is applied with the 1 st bias voltage; a 4 th transistor connected between a source of the 2 nd transistor and a 2 nd current source, a 1 st bias voltage being applied to a gate thereof; a 3 rd resistor connected between a connection node of the 3 rd transistor and the 1 st current source and a connection node of the 4 th transistor and the 2 nd current source; and a capacitor connected in parallel with the 3 rd resistor.

The results obtained by arbitrarily combining the above components and the results obtained by mutually replacing the components or the expression form among the methods, apparatuses, systems, and the like are also effective as aspects of the present invention or the present disclosure. Furthermore, the description of this item (means for solving the problem) does not describe all the essential features of the present invention. Accordingly, a sub-combination of these features described can also be regarded as the present invention.

Effects of the invention

According to an aspect of the present disclosure, a multivalued PAM signal can be accurately received.

Drawings

Fig. 1 is a circuit diagram of an equalizer circuit of the comparative technique.

Fig. 2 is a circuit diagram of an equalizer circuit of an embodiment.

Fig. 3 is a circuit diagram of the variable gain equalizer circuit of embodiment 1.

Fig. 4 is a circuit diagram of a receiving device including the variable gain equalizer circuit of fig. 3.

Fig. 5 is a circuit diagram showing a configuration example of a D/a converter functioning as a bias circuit.

Fig. 6 is a circuit diagram of a variable gain equalizer circuit of embodiment 2.

Fig. 7 is a circuit diagram of a receiving device including the variable gain equalizer circuit of fig. 6.

Fig. 8 is a block diagram of a transmission system of an N-value PAM (PAM-N) signal of an embodiment.

Detailed Description

A summary of some example embodiments of the present disclosure is described. This summary, as a detailed description that follows, is intended to provide a basic understanding of the embodiments by describing some concepts of one or more embodiments in a simplified form without limiting the scope of the invention or disclosure. This summary is not an extensive overview of all possible implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. For convenience, "one embodiment" is sometimes used to refer to one embodiment (example or modification) or multiple embodiments (example or modification) disclosed in the present specification.

An equalizer circuit of an embodiment includes: a variable gain equalizer circuit; and a 1 st bias circuit generating a 1 st bias voltage. The variable gain equalizer circuit includes: a 1 st input terminal; a 2 nd input terminal; a 1 st transistor having a gate connected to the 1 st input terminal; a 2 nd transistor having a gate connected to the 2 nd input terminal; the 1 st resistor is connected with the drain electrode of the 1 st transistor; the 2 nd resistor is connected with the drain electrode of the 2 nd transistor; a 1 st current source; a 2 nd current source; a 3 rd transistor connected between the source of the 1 st transistor and the 1 st current source, the gate of which is applied with the 1 st bias voltage; a 4 th transistor connected between a source of the 2 nd transistor and a 2 nd current source, a 1 st bias voltage being applied to a gate thereof; a 3 rd resistor connected between a connection node of the 3 rd transistor and the 1 st current source and a connection node between the 4 th transistor and the 2 nd current source; and a capacitor connected in parallel with the 3 rd resistor.

In this configuration, the variable gain equalizer circuit functions as a high-frequency enhancement filter by a combination of the 3 rd resistor and a capacitor (also referred to as an inter-source capacitor). Further, by changing the 1 st bias voltage, the gain of the variable gain equalizer circuit can be changed, and therefore the variable gain equalizer circuit also functions as a variable gain amplifier. That is, in this structure, amplification and equalization of the received signal can be performed in one stage. This structure can reduce the circuit area and reduce the power consumption, compared with the case where the amplifier and the equalizer are arranged as different stages.

In the above configuration, it is possible to suppress excessive amplification of the multi-level reception waveform, and to perform equalization while maintaining the multi-level uniformity.

In one embodiment, the resistance value of the 3 rd resistor may be variable. Thus, the equalizing characteristic can be adjusted according to the resistance value of the 3 rd resistor.

In one embodiment, the 3 rd resistor may be composed of a combination of a plurality of resistors and a plurality of switches, and the resistance value of the 3 rd resistor may be digitally controlled.

In one embodiment, the 3 rd resistor may further comprise a field effect transistor. The equalizer circuit may include a 2 nd bias circuit that provides a 2 nd bias voltage to the gate of the field effect transistor.

In one embodiment, a plurality of variable gain equalizer circuits may be connected in series.

In one embodiment, a plurality of variable gain equalizer circuits may be connected in series. The 3 rd resistor may comprise a field effect transistor. The equalizer circuit may further include a 2 nd bias circuit that supplies a common 2 nd bias voltage to gates of field effect transistors constituting 3 rd resistors of the plurality of variable gain equalizer circuits.

In one embodiment, the 1 st bias circuit may include: at least one current D/a converter that converts the digital input into a current output having a gradation; and an I/V conversion circuit converting an output current of the at least one current D/A converter into a 1 st bias voltage.

In one embodiment, the 2 nd bias circuit may include: at least one current D/a converter that converts the digital input into a current output having a gradation; and an I/V conversion circuit converting an output current of the at least one current D/A converter into a 2 nd bias voltage.

In one embodiment, the equalizer circuit may be monolithically integrated in one semiconductor substrate. The term "integrated" includes a case where all components of the circuit are formed on the semiconductor substrate and a case where main components of the circuit are integrated integrally, and a part of resistance, a capacitor, and the like for adjusting the circuit constant may be provided outside the semiconductor substrate. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit element can be kept uniform.

(embodiment)

Hereinafter, preferred embodiments will be described with reference to the drawings. The same reference numerals are given to the same or equivalent constituent elements, components, and processes shown in the drawings, and overlapping descriptions are appropriately omitted. The embodiments are not limited to the present disclosure and the invention, but are exemplified by all the features and combinations described in the embodiments, and are not necessarily essential to the present disclosure and the invention.

In the present specification, the term "state in which the component a and the component B are connected" refers to a case in which the component a and the component B are directly connected physically, and also includes a case in which the component a and the component B are indirectly connected through another component which does not substantially affect the state of electrical connection of the components and does not impair functions and effects caused by connection. .

Similarly, the term "state in which the component C is connected (provided) between the component a and the component B" includes a case in which the component a is directly connected to the component C or the component B is indirectly connected to the component C, and also includes a case in which the component C is connected to the component C via another component which does not substantially affect the electrical connection state of the component a and the component B, and which does not impair the function or effect produced by the connection.

In the present specification, reference numerals given to electric signals such as voltage signals and current signals, and circuit elements such as resistors, capacitors, and inductors, respectively, denote voltage values, current values, and circuit constants (resistance values, capacitance values, and inductances) as necessary.

In this embodiment, an equalizer circuit for shaping a multi-value signal represented by a PAM4 signal is described. The equalizer circuit has a variable gain amplification function (VGA: variable Gain Amplification) and an equalization function.

VGA function

The reception device of the multi-value signal includes a quantizer (a/D converter) that determines the level of the multi-value level reception signal. The level of the received signal is attenuated by the transmission path, and the attenuation amount varies according to the length of the transmission path. Therefore, in the receiving apparatus, it is necessary to amplify the received signal with an appropriate gain to match the input range of the quantizer. This is the VGA function.

Equalization function

In the transmission path, the high frequency component of the transmitted multivalued signal is attenuated relatively more than the low frequency component, which becomes a cause of waveform distortion of the received signal. In order to correct such waveform distortion, it is necessary to correct frequency components contained in the received signal. This is the equalization function.

First, the equalizer circuit 500 of the comparison technique studied by the present inventors will be described.

Fig. 1 is a circuit diagram of an equalizer circuit 500 of the comparative technique. The equalizer circuit 500 is a waveform shaping circuit, which is composed of 2 stages of an equalizer circuit 510 and a variable gain amplifier 520, and performs waveform shaping on an input differential signal.

The equalizer circuit 510 of the preceding stage and the variable gain amplifier 520 of the following stage have the same basic configuration and are configured by differential amplifiers. The differential amplifier includes input differential pairs mn#1 and mn#2, load resistors rd#1 and RD 3#2, and bias current sources ib#1 and ib#2. Equalizer circuit 510 is # =3 and variable gain amplifier 520 is # =4.

The equalizer circuit 510 includes a parallel circuit of a resistor RS3X and a capacitor CS30, which is connected between the sources of the input differential pair MN31 and MN 32. The equalizer circuit 510 has a frequency characteristic according to the circuit constant of the resistor RS3X and the capacitor CS 30. For example, the resistor RS3X is constituted by a variable resistor, and the frequency characteristic can be adjusted according to the resistance value thereof.

The variable gain amplifier 520 includes a resistor RS4X connected between the sources of the input differential pair MN31, MN 32. The resistor RS4X is a variable resistor, and the gain of the variable gain amplifier 520 can be adjusted according to the resistance value thereof.

The present inventors have studied the equalizer circuit 500 of fig. 1 and as a result have recognized the following problems.

In the multivalued PAM signaling, a plurality of signal levels corresponding to the multivalued states are uniformly arranged. In the case where the amplification capability of the MOS transistor of the equalizer circuit 510 of the preceding stage is large, when the multivalued PAM signal passes through the equalizer circuit 510, the uniform multivalued level is excessively amplified, collapsing to the waveform in which the multivalued level is unevenly arranged.

Further, since the equalizer circuit 510 and the variable gain amplifier 520 are configured as different stages, there is a problem in that a circuit area and current consumption are large.

The equalizer circuit which improves the problem of the comparison technique of fig. 1 will be described below.

Fig. 2 is a circuit diagram of equalizer circuit 600 of an embodiment. Equalizer circuit 600 includes a variable gain equalizer circuit 610 and a 1 st bias circuit 620. The equalizer circuit 600 is a functional IC (Integrated Circuit: integrated circuit) integrally integrated on one semiconductor substrate.

The 1 st bias circuit 620 generates a 1 st bias voltage Vb1.

The variable gain equalizer circuit 610 includes a 1 st input terminal INP, a 2 nd input terminal INN, a 1 st transistor MN51, a 2 nd transistor MN52, a 3 RD transistor MN53, a 4 th transistor MN54, a 1 st resistor RD51, a 2 nd resistor RD52, a 3 RD resistor RS5X, a 1 st current source IB51, a 2 nd current source IB52, and a capacitor CS50.

The 1 st transistor MN51 and the 2 nd transistor MN52 constitute an input differential pair, the gate of the 1 st transistor MN51 is connected to the 1 st input terminal INP, and the gate of the 2 nd transistor MN52 is connected to the 2 nd input terminal INN.

The 1 st resistor RD51 is connected between the drain of the 1 st transistor MN51 and the power supply line. The 2 nd resistor RD52 is connected between the drain of the 2 nd transistor MN52 and the power supply line.

The 1 st current source IB51 and the 2 nd current source IB52 generate constant currents.

The 3 rd transistor MN53 is connected between the source of the 1 st transistor MN51 and the 1 st current source IB51, and the gate thereof is applied with the 1 st bias voltage Vb1 generated by the 1 st bias circuit 620. The 4 th transistor MN54 is connected between the source of the 2 nd transistor MN52 and the 2 nd current source IB52, and the gate thereof is applied with the 1 st bias voltage Vb1.

The 3 rd resistor RS5X is connected between a connection node of the 3 rd transistor MN53 and the 1 st current source IB51 (the source of the 3 rd transistor MN 53) and a connection node of the 4 th transistor MN54 and the 2 nd current source IB52 (i.e., the source of the 4 th transistor MN 54). The capacitor CS50 and the 3 rd resistor RS5X are connected in parallel between the source of the 3 rd transistor MN53 and the source of the 4 th transistor MN 54. Capacitor CS50 is also referred to as an inter-source capacitor.

The 3 rd resistor RS5X may be a variable resistor having a variable resistance value. Instead of or in addition to the resistance value of the 3 rd resistor RS5X, the capacitance value of the capacitor CS50 may also be variable.

The above is the structure of the equalizer circuit 600.

In this configuration, the variable gain equalizer circuit 610 functions as a high-frequency enhancement filter by a combination of the 3 rd resistor RS5X and the capacitor CS50. Further, by changing the 1 st bias voltage Vb1, the gain of the variable gain equalizer circuit 610 can be changed, and thus the variable gain equalizer circuit 610 also functions as a variable gain amplifier. Specifically, when the 1 st bias voltage Vb1 increases, in other words, when the gate-source voltage of the 3 rd transistor MN53 and the 4 th transistor MN54 increases, the gain of the variable gain equalizer circuit 610 becomes high, whereas when the 1 st bias voltage Vb1 decreases, the gate-source voltage of the 3 rd transistor MN53 and the 4 th transistor MN54 decreases, the gain of the variable gain equalizer circuit 610 decreases. The gain is a gain of the entire region including the DC component, and is also called DC gain.

That is, in this structure, both amplification and equalization of the input signal can be performed in one stage. This can reduce the circuit area and reduce the power consumption, as compared with the case where the amplifier and the equalizer are arranged as different stages as shown in the comparison technique of fig. 1.

Further, according to the structure of fig. 2, it is possible to suppress excessive amplification of the reception waveform of the multilevel level, and to perform equalization while maintaining the multilevel level uniform.

Further, by setting the 3 rd resistor RS5X to a variable resistor, the equalizing characteristic of the variable gain equalizer circuit 610 can be adjusted.

Fig. 3 is a circuit diagram of a variable gain equalizer circuit 610A of embodiment 1. The 3 rd resistor RS5X is a variable resistor having a resistance value that can be digitally controlled according to the control signal cnt_eq, and is constituted by a combination of a plurality of resistors r and a plurality of switches sw. The topology of the plurality of resistors and the plurality of switches is not particularly limited, and known techniques may be used.

In practical use, in the case of the variable gain equalizer circuit 610 of only 1 stage, there are cases where the gain is insufficient or proper equalization characteristics cannot be provided. In this case, a plurality of variable gain equalizer circuits 610 may be connected in multiple stages.

Fig. 4 is a circuit diagram of equalizer circuit 600A, which includes variable gain equalizer circuit 610A of fig. 3. The equalizer circuit 600A includes a plurality of variable gain equalizer circuits 610a_1 to 610a_n connected in series and a 1 st bias circuit 620. In this example, n=4.

In this configuration, since the DC gains of the plurality of variable gain equalizer circuits 610a_1 to 610a_n are controlled by the common 1 st bias voltage Vb1, the plurality of variable gain equalizer circuits 610a_1 to 610a_n have the same DC gain.

Specifically, the 1 st bias circuit 620 is provided in common to the plurality of variable gain equalizer circuits 610a_1 to 610a_n, and the plurality of variable gain equalizer circuits 610a_1 to 610a_n are supplied with the same 1 st bias voltage Vb1.

On the other hand, in this structure, the equalizer characteristics of the plurality of variable gain equalizer circuits 610a_1 to 610a_n are independently adjustable. Each variable gain equalizer circuit 610a_i (i=1, 2,..n) includes a digitally controllable variable resistor RS5X shown in fig. 3, provided with an individual equalizer setting cnt_ EQi.

For example, the 1 st bias circuit 620 may include a D/a converter 622 that converts the digital gain set point cnt_dcgain to an analog 1 st bias voltage Vb1.

Fig. 5 is a circuit diagram showing a configuration example of the D/a converter 622 functioning as the 1 st bias circuit 620.

The D/A converter 622 includes an encoder 624, a current DAC (D/A converter) circuit 626, and an I/V conversion circuit

628. Encoder 624 encodes set point cnt_dcgain, and current DAC circuit 626 generates a corresponding encoder

624, the current Idac output. The I/V conversion circuit 628 converts the current Idac to the 1 st bias voltage Vb1. The structure of the D/a converter 622 is not particularly limited, and a resistor division method or the like may be used.

Fig. 6 is a circuit diagram of a variable gain equalizer circuit 610B of embodiment 2. In this embodiment 2, as in embodiment 1, the gain of the variable gain equalizer circuit 610B can be controlled in accordance with the 1 st bias voltage Vb1 supplied to the gates of the transistors MN53, MN 54.

On the other hand, the resistance value of the 3 rd resistor RS5X can be controlled according to the analog 2 nd bias voltage Vb2.

The 3 rd resistor RS5X includes a resistor RS50 connected in parallel and a transistor MN50. The transistor MN50 is an N channel, and is connected between the source of the 3 rd transistor MN53 and the source of the 4 th transistor MN 54.

The above is the structure of the variable gain equalizer circuit 610B. Based on the simulated 2 nd bias voltage Vb2, the impedance of the 5 th transistor MN50 changes, and the resultant impedance of the 3 rd resistor RS5X changes. Thereby, the equalizer characteristic of the variable gain equalizer circuit 610B can be adjusted according to the 2 nd bias voltage Vb2.

Fig. 7 is a circuit diagram of equalizer circuit 600B, which includes variable gain equalizer circuit 610B of fig. 6. The equalizer circuit 600B includes a plurality of variable gain equalizer circuits 610b_1 to 610b_n, a 1 st bias circuit 620, and a 2 nd bias circuit 630 connected in series. In this example, n=4.

In this configuration, since the DC gains of the plurality of variable gain equalizer circuits 610b_1 to 610b_n are controlled by the common 1 st bias voltage Vb1, the plurality of variable gain equalizer circuits 610b_1 to 610b_n have the same DC gain. This is the same as in fig. 4. Specifically, the 1 st bias circuit 620 is provided in common to the plurality of variable gain equalizer circuits 610b_1 to 610b_n, and the plurality of variable gain equalizer circuits 610b_1 to 610b_n are supplied with the same 1 st bias voltage Vb1.

The equalizer characteristics of the plurality of variable gain equalizer circuits 610b_1 to 610b_n are also controlled by the common 2 nd bias voltage Vb2, and thus the plurality of variable gain equalizer circuits 610b_1 to 610b_n have the same equalizer characteristics. In this regard, unlike fig. 4.

Specifically, the 2 nd bias circuit 630 is provided in common to the plurality of variable gain equalizer circuits 610b_1 to 610b_n, and the plurality of variable gain equalizer circuits 610b_1 to 610b_n are supplied with the same 2 nd bias voltage Vb2. For example, the 2 nd bias circuit 630 may include a D/a converter 632 that converts the digital equalizer setting cnt_eq to an analog 2 nd bias voltage Vb2. The D/a converter 632 may have the same structure as the D/a converter 622, and may be, for example, the structure shown in fig. 5.

(use)

Fig. 8 is a block diagram of a transmission system 100 of an N-value PAM (PAM-N) signal of an embodiment. The transmission system 100 includes a transmitting apparatus 200 and a receiving apparatus (deserializer) 300. The transmitting apparatus 200 and the receiving apparatus 300 are connected by a transmission cable 102.

(transmitting device)

The transmitter 200 is a serializer IC (Integrated Circuit: integrated circuit) that receives data S1 to be transmitted to the receiver 300 from an external circuit (not shown), converts the data S1 into a PAM signal S2 having an N value, and transmits the PAM signal S2 to the receiver 300. The kind of the parallel data S1 is not limited, and may be, for example, image data or the like requiring high-capacity and high-speed transmission.

(receiving device)

The reception device 300 is a deserializer IC that receives the PAM-N signal S2 from the transmission device 200 and outputs the received data S3 to other external circuits not shown. The signal transmission between the transmitting apparatus 200 and the receiving apparatus 300 uses differential signals, but single-ended signals may also be used.

Here, PAM (PAM 4) with 4 values (n=4) is exemplified as the PAM-N signal, but the order of the PAM signal is not limited, and the present disclosure is applicable to 8 values, 16 values, and 64 values.

First, the configuration of the transmitting apparatus 200 will be described. The PAM encoder 210 converts the data S1a into PAM-formatted data S1b. In the PAM encoder 210, the data S1b is embedded with a clock signal. The encoding method of the PAM encoder 210 is not particularly limited, and a DC-balanced encoding method such as 8b10b, 10b12b, and 64b66b may be used.

The P/S converter 220 converts the data S1b generated by the PAM encoder 210 into serial data S1c. The PAM driver 230 converts the serial data S1c into an analog PAM-N signal S2 and outputs it.

Next, the structure of the receiving apparatus 300 will be described. The reception apparatus 300 includes a waveform shaping circuit 310, an a/D converter 320, a PAM phase comparator 330, a clock recovery circuit 340, an S/P converter 350, and a PAM decoder 360.

When the PAM-N signal S2 is transmitted from the transmission cable 102, the waveform of the PAM-N signal S2 may be distorted. In order to improve such waveform distortion, a waveform shaping circuit 310 is provided. Waveform distortion may exemplify attenuation due to transmission loss, waveform distortion due to low-pass action of the transmission cable 102, and the like. The waveform shaping circuit 310 waveform-shapes the PAM-N signal S2 so as to approach the ideal PAM signal.

The waveform shaping circuit 310 can have a VGA (Variable Gain Amplification: variable gain amplification) function of amplifying the PAM-N signal S2 with a variable gain and adjusting a Direct Current (DC) amplitude of the PAM-N signal S2, and an Equalization (EQ) function of correcting a frequency characteristic of the PAM-N signal S2.

The a/D converter 320 quantizes the PAM-N signal S2a waveform-shaped by the waveform shaping circuit 310, and converts it into a comparison signal S2b.

The PAM phase comparator 330 receives the comparison signal S2b and latches the plurality of bits b1 to b3 constituting the comparison signal S2b in synchronization with the clock signal CLK (data strobe signal) generated by the clock recovery circuit 340. The PAM phase comparator 330 converts the comparison signal S2b latched by the clock signal CLK into a 2-bit binary code (symbol data) S2c.

The S/P converter 350 converts the binary code S2c into parallel data S2e. The PAM decoder 360 performs the inverse process to the PAM encoder 210 of the transmitting apparatus 200, decodes the DC-balance encoded parallel data S2e, and outputs the data S3.

The waveform shaping circuit 310 according to the embodiment 610 (610A, 610B) can be used as the waveform shaping circuit 310.

(appendix)

The techniques disclosed in this specification may be understood as follows in one aspect.

(item 1)

An equalizer circuit, comprising:

variable gain equalizer circuit

A 1 st bias circuit generating a 1 st bias voltage;

the variable gain equalizer circuit includes:

the 1 st input terminal is provided with a first input terminal,

the 2 nd input terminal is provided with a first input terminal,

a 1 st transistor having a gate connected to the 1 st input terminal,

a 2 nd transistor having a gate connected to the 2 nd input terminal,

a 1 st resistor connected with the drain electrode of the 1 st transistor,

a 2 nd resistor connected with the drain electrode of the 2 nd transistor,

the 1 st current source is provided with a first current source,

a 2 nd current source is provided,

a 3 rd transistor connected between a source of the 1 st transistor and the 1 st current source, a gate thereof being applied with the 1 st bias voltage,

a 4 th transistor connected between a source of the 2 nd transistor and the 2 nd current source, the 1 st bias voltage being applied to a gate thereof,

a 3 rd resistor connected between the connection node of the 3 rd transistor and the 1 st current source and the connection node of the 4 th transistor and the 2 nd current source, and

a capacitor connected in parallel with the 3 rd resistor.

(item 2)

The equalizer circuit of item 1, wherein,

the resistance value of the 3 rd resistor is variable.

(item 3)

The equalizer circuit of item 2, wherein,

the 3 rd resistor is composed of a combination of a plurality of resistors and a plurality of switches, and the resistance value of the 3 rd resistor can be digitally controlled.

(item 4)

The equalizer circuit of item 2, wherein,

the 3 rd resistor comprises a 5 th transistor,

the receiving device further includes a 2 nd bias circuit that supplies a 2 nd bias voltage to the gate of the 5 th transistor.

(item 5)

The equalizer circuit of any one of items 1 to 4, wherein,

the variable gain equalizer circuit is connected in series with a plurality of variable gain equalizer circuits.

(item 6)

The equalizer circuit of item 2, wherein,

the variable gain equalizer circuit is connected in series with a plurality of,

the 3 rd resistor comprises a field effect transistor,

the equalizer circuit further includes a 2 nd bias circuit that supplies a common 2 nd bias voltage to gates of the field effect transistors constituting the 3 rd resistor of the plurality of variable gain equalizer circuits.

(item 7)

The equalizer circuit of any one of items 1 to 6, wherein,

the capacitance value of the capacitor is variable.

(item 8)

The equalizer circuit of any one of items 1 to 7, wherein,

the 1 st bias circuit includes:

at least one current D/A converter converting a digital input into a current output having a gradation, and

and an I/V conversion circuit converting an output current of the at least one current D/A converter into the 1 st bias voltage.

(item 9)

The equalizer circuit of item 4 or 6, wherein,

the 2 nd bias circuit includes:

and an I/V conversion circuit converting an output current of the at least one current D/A converter into the 2 nd bias voltage.

(item 10)

The equalizer circuit of any one of items 1 to 9, wherein,

the equalizer circuit is integrally formed on a semiconductor substrate.

While specific terms have been used to describe embodiments related to the present disclosure, the description is merely illustrative for aiding understanding and does not limit the scope of the present disclosure or the claims. The scope of the present invention is defined by the claims, and therefore, the embodiments, examples, and modifications not described herein are also included in the scope of the present invention.

[ description of reference numerals ]

600 equalizer circuit, 610 variable gain equalizer circuit, 620 1 st bias circuit, 622D/a converter, 630 nd bias circuit, 632D/a converter, MN51 st transistor 1, MN52 nd transistor 2, MN53 RD transistor 3, MN54 th transistor 4, MN50 th transistor 5, IB51 st current source, IB52 nd current source, CS50 capacitor, RD51 st resistor, RD52 nd resistor, RS5X 3 RD resistor, 100 transmission system, 102 transmission cable, 200 transmission circuit, 210PAM encoder, 220P/S converter, 230PAM driver, 300 receiving device, 310 waveform shaping circuit, 320A/D converter, 330PAM phase comparator, 340 clock recovery circuit, 350S/P converter, 360PAM decoder, S2 PAM signal.

Claims

1. An equalizer circuit, comprising:

variable gain equalizer circuit

A 1 st bias circuit generating a 1 st bias voltage;

the variable gain equalizer circuit includes:

the 1 st input terminal is provided with a first input terminal,

the 2 nd input terminal is provided with a first input terminal,

a 1 st transistor having a gate connected to the 1 st input terminal,

a 2 nd transistor having a gate connected to the 2 nd input terminal,

a 1 st resistor connected with the drain electrode of the 1 st transistor,

a 2 nd resistor connected with the drain electrode of the 2 nd transistor,

the 1 st current source is provided with a first current source,

a 2 nd current source is provided,

and a capacitor connected in parallel with the 3 rd resistor.

2. The equalizer circuit of claim 1, wherein,

the resistance value of the 3 rd resistor is variable.

3. The equalizer circuit of claim 2, wherein,

4. The equalizer circuit of claim 2, wherein,

the 3 rd resistor comprises a 5 th transistor,

the equalizer circuit further includes a 2 nd bias circuit that provides a 2 nd bias voltage to the gate of the 5 th transistor.

5. The equalizer circuit of any one of claims 1 to 4 wherein,

6. The equalizer circuit of claim 2, wherein,

the variable gain equalizer circuit is connected in series with a plurality of,

the 3 rd resistor comprises a field effect transistor,

the equalizer circuit further includes a 2 nd bias circuit that supplies a common 2 nd bias voltage to gates of the field effect transistors constituting the 3 rd resistors of the plurality of variable gain equalizer circuits.

7. The equalizer circuit of any one of claims 1 to 4 wherein,

the capacitance value of the capacitor is variable.

8. The equalizer circuit of any one of claims 1 to 4 wherein,

the 1 st bias circuit includes:

9. The equalizer circuit of claim 4 or 6, wherein,

the 2 nd bias circuit includes:

10. The equalizer circuit of any one of claims 1 to 4 wherein,

the equalizer circuit is integrally formed on a semiconductor substrate.