CN117478124A - Bidirectional digital isolator and communication method - Google Patents

Bidirectional digital isolator and communication method Download PDF

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Publication number
CN117478124A
CN117478124A CN202311260335.2A CN202311260335A CN117478124A CN 117478124 A CN117478124 A CN 117478124A CN 202311260335 A CN202311260335 A CN 202311260335A CN 117478124 A CN117478124 A CN 117478124A
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channel
comparator
enabling
output end
enable
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吴传福
岳鹏阁
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Rongpai Semiconductor Shanghai Co ltd
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Rongpai Semiconductor Shanghai Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

The invention relates to the technical field of bus communication, in particular to a bidirectional digital isolator and a communication method, comprising the following steps: a transmitting channel and a receiving channel which are oppositely arranged; the input end of the receiving channel is in short circuit with the output end of the sending channel to form a second data pin and is connected with a second device; the transmitting channel comprises a first comparator and the receiving channel comprises a second comparator; and an enable channel for controlling blocking of the first comparator or the second comparator according to an externally input enable signal. The beneficial effects are that: the transmitting channel and the receiving channel are short-circuited to form a bidirectional receiving and transmitting channel. Then, by enabling the first comparator or the second comparator, the sending channel or the receiving channel is blocked, so that the selection of the data transmission direction is realized, and two data pins are not required to be configured on the first device or the second device.

Description

Bidirectional digital isolator and communication method
Technical Field
The invention relates to the technical field of bus communication, in particular to a bidirectional digital isolator and a communication method.
Background
The digital isolator is a chip which is used for realizing isolation between an electronic system and a user by enabling the digital signal and the analog signal to have very high resistance isolation characteristic when being transmitted in the electronic system. The isolation is introduced by the designer in order to meet safety regulations or to reduce noise in the ground loop, etc. Galvanic isolation ensures that data transfer is not through electrical connections or leakage paths, thereby avoiding security risks. The I2C bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips corporation. It requires only two wires to transfer information between devices connected to the bus. The master device is used to initiate the bus transfer of data and generate a clock to open the transfer device, where any addressed device is considered a slave device.
In the prior art, to avoid excessive environmental noise introduced by the bus signal during transmission, a digital isolator is generally used to isolate the on-line signal, for example, chinese patent CN202110829977.4 discloses a digital isolator comprising: the device comprises a filter, a transmitting circuit, a receiving circuit and an isolation capacitor. The isolation capacitor is connected between the transmitting circuit and the receiving circuit, the filter is connected between the transmitting circuit and the isolation capacitor, the transmitting circuit comprises at least one signal modulation circuit, and the signal modulation circuit is at least connected with one filter. The filter comprises a blocking capacitor and a compensation current element, one end of the blocking capacitor is connected with the output end of the signal modulation circuit, the other end of the blocking capacitor is connected with the compensation current element, the common end of the blocking capacitor and the compensation current element is connected with the isolation capacitor, the free end of the compensation current element is connected with a power supply or grounded, and the free end of the compensation current element is used for compensating common mode current generated by the signal demodulation circuit when the digital isolator generates common mode interference. When the digital isolator is interfered by common mode, the filter acts to compensate common mode current generated by the signal demodulation circuit, so that normal transmission of signals is ensured, and common mode anti-interference of the digital isolator is further enhanced.
However, in practical implementations, the inventors have found that the channel communication direction of such digital isolators is unidirectional, i.e. pointing distally from the local device or distally from the local device. Therefore, when the external device is connected, two data pins of the external device are required to be used for receiving and transmitting respectively, and certain limitation exists in application, for example, the device with only a single data pin and the requirement of bidirectional receiving and transmitting is not applicable.
Disclosure of Invention
In view of the above-mentioned problems in the prior art, a bidirectional digital isolator is now provided; in another aspect, a communication method for the bi-directional digital isolator is also provided.
The specific technical scheme is as follows:
a bi-directional digital isolator comprising:
a transmitting channel and a receiving channel which are oppositely arranged, wherein the transmission direction of the transmitting channel points to a second device from a first device, and the transmission direction of the receiving channel points to the first device from the second device;
the input end of the receiving channel is in short circuit with the output end of the sending channel to form a second data pin and is connected with the second device;
the transmit path includes a first comparator and the receive path includes a second comparator;
and the enabling channel is electrically connected with the enabling ends of the first comparator and the second comparator respectively and controls the blocking of the first comparator or the second comparator according to an externally input enabling signal.
In another aspect, the transmit channel includes:
the input end of the first Schmitt trigger is connected with the input end of the sending channel;
the input end of the first signal isolator is connected with the output end of the first Schmitt trigger;
the input end of the first comparator is connected with the output end of the first signal isolator, and the output end of the first comparator is connected with the output end of the transmitting channel.
In another aspect, the receive channel comprises:
the input end of the second Schmitt trigger is connected with the input end of the receiving channel;
the input end of the second signal isolator is connected with the output end of the second Schmitt trigger;
the input end of the second comparator is connected with the output end of the second signal isolator, and the output end of the second comparator is connected with the output end of the receiving channel.
In another aspect, the first device is a master controller, and the enabling channel includes:
the input end of the first enabling channel is connected with the first device, and the first enabling channel is also connected with the enabling end of the first comparator;
and the input end of the second enabling channel is connected with the first device, and the output end of the second enabling channel is connected with the enabling end of the second comparator.
In another aspect, when the bi-directional digital isolator has only a first enable pin on the same side as the first device and a second enable pin on the same side as the second device, the transmit channel comprises:
an enabling transmission channel, wherein an input end of the enabling transmission channel is connected with the first device, and an output end of the enabling transmission channel is connected with a second enabling pin close to the second device;
the second enabling pin is electrically connected with an enabling end of the first comparator to form the first enabling channel.
On the other hand, when the enabling end of the first comparator inputs a low level, the output end of the sending channel is in a high-resistance state;
when the enabling end of the second comparator inputs low level, the output end of the receiving channel is in a high-resistance state.
A communication method, suitable for the above-mentioned two-way digital isolator, comprising:
when a first device transmits a communication signal to a second device, the first device communicates by adopting a first method, wherein the first method comprises the following steps:
step A1: inputting a low-level enabling signal to the second comparator so as to enable the output end of the receiving channel to be in a high-resistance state;
step A2: the first device inputs the communication signal via a first data pin, such that the second device receives the communication signal via a transmit channel and a second data pin;
when the second device sends the communication signal to the first device, adopting a second method for communication, wherein the second communication method comprises the following steps:
step B1: inputting a low-level enabling signal to a first comparator so as to enable the output end of the sending channel to be in a high-resistance state;
step B2: the second device inputs the communication signal via the second data pin such that the first device receives the communication signal via a receive channel and a first data pin.
On the other hand, when the first device is a master controller in a bus communication protocol, the second communication method further includes, before executing the step B1:
step B01: the first device transmits a low-level enable signal via an enable transmission channel, and the low-level enable signal is input to an enable end of the first comparator via a second enable pin.
The technical scheme has the following advantages or beneficial effects:
aiming at the problem that the digital isolator in the prior art needs to occupy two pins in the bidirectional receiving and transmitting process, in the scheme, a transmitting channel and a receiving channel in the digital isolator are in short circuit, and two sides of the digital isolator are respectively provided with a data pin, so that a bidirectional receiving and transmitting channel is formed. Then, considering the problem that there may be data collision on the bi-directional transmit-receive channel, the enabling channel is further configured to connect the first comparator and the second comparator on the transmit channel, and the first comparator or the second comparator is enabled by feeding high and low levels to the first device side or the second device side, so as to block the transmit channel or the receive channel, thereby realizing selection of the data transmission direction, and two data pins are not required to be configured on the first device or the second device.
Drawings
Embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The drawings, however, are for illustration and description only and are not intended as a definition of the limits of the invention.
FIG. 1 is an overall schematic of an embodiment of the present invention;
FIG. 2 is a schematic diagram of another embodiment of the present invention;
FIG. 3 is a schematic diagram of another embodiment of the present invention;
FIG. 4 is a schematic diagram of a first communication method according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a second communication method according to an embodiment of the invention;
fig. 6 is a schematic diagram of a second communication method according to another embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The invention comprises the following steps:
a bi-directional digital isolator for an I2C bus, as shown in fig. 1, comprising:
a transmitting channel 1 and a receiving channel 2 which are oppositely arranged, wherein the transmission direction of the transmitting channel 1 points to the second device MCU2 from the first device MCU1, and the transmission direction of the receiving channel 2 points to the first device MCU1 from the second device MCU2;
the input end of the transmitting channel 1 is in short circuit with the output end of the receiving channel 2 to form a first data pin and connected with the first device MCU1, and the input end of the receiving channel 2 is in short circuit with the output end of the transmitting channel 1 to form a second data pin and connected with the second device MCU2;
the transmitting channel 1 comprises a first comparator Cmp1 and the receiving channel comprises a second comparator Cmp2;
and an enable channel 3, wherein the enable channel 3 is electrically connected with the enable ends of the first comparator Cmp1 and the second comparator Cmp2 respectively, and controls the blocking of the first comparator Cmp1 or the second comparator Cmp2 according to an externally input enable signal.
Specifically, in this embodiment, a pair of a transmitting channel 1 and a receiving channel 2 is selected in the digital isolator in the prior art, and input ends and output ends on the same side of the digital isolator are shorted to form bidirectional transmitting and receiving pins to connect data pins of the first device MCU1 or the second device MCU 2. On the bidirectional receiving and transmitting pin, the first device MCU1 and the second device MCU2 can both receive and transmit signals through the digital isolator, thereby realizing bidirectional transmission. However, when the first device MCU1 and the second device MCU2 simultaneously transmit signals, signal collision may occur on pins, resulting in abnormal communication. In this regard, in the present embodiment, the first comparator Cmp1 is also introduced on the transmission channel 1, the second comparator Cmp2 is introduced on the reception channel 2, and the first comparator Cmp1 and the second comparator Cmp2 are enabled to be controlled by the enabling channel 3. Specifically, the enable channel 3 is provided with corresponding enable pins on the first device MCU1 side and the second device MCU2 side, respectively, and can be used to output an enable signal to the first comparator Cmp1 or the second comparator Cmp2. The first comparator Cmp1 and the second comparator Cmp2 can be implemented by using a typical comparator circuit, the enabling end is the power supply end of the comparator, the homodromous input end of the comparator is connected with the input end of the transmitting channel 1 or the receiving channel 2, and in the conducting state, the output end is of a push-pull output type, and has a strong current driving capability with internal resistance of 50 ohms. Because the comparator circuit is selected as the control circuit for blocking the transmitting channel 1 and the receiving channel 2, the comparator circuit has the characteristic of conducting in an enabling state and high resistance in a disabling state, when the comparator circuit is used for the transmitting channel 1 and the receiving channel 2, the comparator circuit can conduct or block the transmitting channel 1 and the receiving channel 2 through enabling the channel 3, and then the first device MCU1 and the second device MCU2 can transmit and receive according to the needs.
In one embodiment, the transmission channel 1 further includes:
the input end of the first Schmitt trigger ST1 is connected with the input end of the transmitting channel;
the input end of the first signal isolator iso1 is connected with the output end of the first Schmitt trigger ST 1;
the input end of the first comparator Cmp1 is connected with the output end of the first signal isolator iso1, and the output end of the first comparator Cmp1 is connected with the output end of the transmission channel 1.
The receiving channel 2 further comprises:
the input end of the second Schmitt trigger ST2 is connected with the input end of the receiving channel;
the input end of the second signal isolator iso2 is connected with the output end of the second Schmitt trigger ST 2;
the input end of the second comparator Cmp2 is connected to the output end of the second signal isolator iso2, and the output end of the second comparator Cmp2 is connected to the output end of the receiving channel 2.
Specifically, in order to achieve better effects of signal isolation and interference cancellation, in this embodiment, a schmitt trigger, a signal isolator, and a comparator that are serially connected along a signal transmission direction are sequentially disposed in the transmission channel 1 and the reception channel 2. Wherein the transmission channel 1 includes a first schmitt trigger ST1, a first signal isolator iso1 and a first comparator Cmp1; the reception channel 2 comprises a second schmitt trigger ST2, a second signal isolator iso2 and a second comparator Cmp2. The good effect of eliminating the on-line interference is realized through the Schmitt trigger and the signal isolator.
In one embodiment, as shown in fig. 2, if the first device MCU1 is a master controller, the enabling channel 3 includes:
the input end of the first enabling channel 31 is connected with the first device MCU1, and the first enabling channel is also connected with the enabling end of the first comparator Cmp1;
the input end of the second enabling channel 32 is connected to the first device MCU1, and the output end of the second enabling channel is connected to the enabling end of the second comparator Cmp2.
In particular, in a part of the bus signal, such as an I2C bus system, it is necessary for a certain device to host and control the transceiving on the bus. In this case, in the present embodiment, the enabling channel 3 is split into the first enabling channel 31 and the second enabling channel 32, and both are controlled by the first device MCU1, so that the transmitting/receiving direction is adjusted.
In one embodiment, when the first device MCU1 is a master controller and the bi-directional digital isolator only has a first enable pin on the same side as the first device MCU1 and a second enable pin on the same side as the second device MCU2, the transmit channel 1 comprises:
an enabling transmission channel 33, wherein an input end of the enabling transmission channel 33 is connected with the first device MCU1, and an output end of the enabling transmission channel 33 is connected with a second enabling pin close to the second device MCU2;
the second enable pin is electrically connected to the enable terminal of the first comparator Cmp1 to form a first enable channel 31.
Specifically, for the existing digital isolator, which may only have the first enable pin on the same side as the first device MCU1 and the second enable pin on the same side as the second device MCU2, the control process of the bus system main controller cannot be completed on the first device MCU1 side, in this embodiment, by selecting an additional transmission channel 1 as the enable transmission channel 33 in the digital isolator, the output end of the enable transmission channel 33 is connected to the second enable pin close to the second device MCU2, so that the first device MCU1 can implement the enable control process of the transmission channel 1 through the forwarding of the enable transmission channel 33-the second enable pin.
In the implementation process, the bidirectional digital isolator at least comprises a bidirectional receiving channel consisting of a sending channel 1 and a receiving channel 2, and further comprises a group of enabling channels 3. The enable channel 3 may be composed of a first enable channel 31 and a second enable channel 32; or may consist of an enable transmit channel 33 and a second enable channel 32. Depending on the actual product requirements, an additional alternate transmit channel and/or alternate receive channel may be added, which is enabled by the enable channel 3 or used as a one-way always-on data channel. When the first enable channel 31 inputs a low level, the level state of the output end of the first comparator Cmp1 is constant to be a low level, the output end of the transmitting channel 1 is in a high-impedance state, and the level does not change with the input level of the input end; when the second enable channel 32 inputs a low level, the level state of the output terminal of the second comparator Cmp2 is constant to a low level, the output terminal of the receiving channel 1 is in a high resistance state, and the level does not change with the input level of the input terminal. Accordingly, when the first enable channel 31 or the second enable channel 32 inputs a high level, the transmit channel 1 or the receive channel 1 is turned on to output a communication signal.
Based on the above process, the following scenarios may exist in the actual use process:
when a first device transmits a communication signal to a second device, communication is performed by a first method, as shown in fig. 4, the first method includes:
step A1: inputting a low-level enabling signal to the second comparator so as to enable the output end of the receiving channel to be in a high-resistance state;
step A2: the first device inputs a communication signal via the first data pin such that the second device receives the communication signal via the transmit channel and the second data pin.
Specifically, as shown in the circuit of fig. 3, before the first device MCU1 sends a signal to the second device MCU2, the first device MCU1 sends a second control signal with a low level, so that the second controller Cmp2 is disabled, and the output end of the receiving channel 2 enters a high-impedance state;
on the first device MCU1 side, when the output end of the receiving channel 2 enters a high-impedance state, the first device MCU1 sends a high-speed communication signal to the second device MCU2, and the high-speed communication signal is input through a position where the input end of the sending channel 1 and the output end of the receiving channel 2 are short-circuited, and is reflected as the same high-speed communication signal;
on the side of the second device MCU2, the default input state of the input end of the receiving channel 2 is only 1uA due to the driving capability, and the output end of the transmitting channel 1 is a strong current driving capability with an internal resistance of 50 ohms, so that the level state of the short-circuit point between the output end of the transmitting channel 1 and the input end of the receiving channel 2 will follow the signal on the transmitting channel 1 to be reflected as a high-speed signal. Based on the above analysis, when the first device MCU1 does not send the low-level second control signal in advance, the level state of the short-circuit point between the output end of the transmitting channel 1 and the input end of the receiving channel 2 may be unstable, which affects signal transmission.
When the second device transmits a communication signal to the first device, communication is performed by using a second method, as shown in fig. 5, the second communication method includes:
step B1: inputting a low-level enabling signal to the first comparator so as to enable the output end of the sending channel to be in a high-resistance state;
step B2: the second device inputs a communication signal via the second data pin such that the first device receives the communication signal via the receive channel and the first data pin;
when the first device is a master controller in the bus communication protocol, as shown in fig. 6, the second communication method further includes, before executing step B1:
step B01: the first device transmits a low-level enable signal via an enable transmission channel, and the low-level enable signal is input to an enable end of the first comparator via a second enable pin.
Specifically, as shown in the circuit of fig. 3, before the first device MCU1 sends a signal to the second device MCU2, since the first device MCU1 is the main controller, the first device MCU1 sends a first control signal of low level, and the first comparator Cmp1 in the transmission channel 1 is disabled by enabling the transmission channel 33 to the second enable pin, and the output terminal of the transmission channel 1 enters the high enable state. A step of
On the side of the second device MCU2, after the output end of the transmission channel 1 enters a high-resistance state, the second device MCU2 transmits a high-speed communication signal to the first device MCU1, and the high-speed communication signal is input through the short-circuited position of the input end of the reception channel 2 and the output end of the transmission channel 1 and is reflected as the same high-speed communication signal;
on the first device MCU1 side, the default input state of the input end of the transmitting channel 1 is only 1uA due to the driving capability, and the output end of the receiving channel 2 is a strong current driving capability with an internal resistance of 50 ohms, so that the level state of the short-circuit point between the output end of the receiving channel 2 and the input end of the transmitting channel 1 will follow the signal on the receiving channel 2 to be reflected as a high-speed signal. Based on the above analysis, when the second device MCU2 does not send the low-level second control signal in advance, the level state of the short-circuit point between the input end of the transmitting channel 1 and the output end of the receiving channel 2 may be unstable, which affects signal transmission.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included in the scope of the present invention.

Claims (8)

1. A bi-directional digital isolator comprising:
a transmitting channel and a receiving channel which are oppositely arranged, wherein the transmission direction of the transmitting channel points to a second device from a first device, and the transmission direction of the receiving channel points to the first device from the second device;
the input end of the receiving channel is in short circuit with the output end of the sending channel to form a second data pin and is connected with the second device;
the transmit path includes a first comparator and the receive path includes a second comparator;
and the enabling channel is electrically connected with the enabling ends of the first comparator and the second comparator respectively and controls the blocking of the first comparator or the second comparator according to an externally input enabling signal.
2. The bi-directional digital isolator of claim 1, wherein the transmit channel comprises:
the input end of the first Schmitt trigger is connected with the input end of the sending channel;
the input end of the first signal isolator is connected with the output end of the first Schmitt trigger;
the input end of the first comparator is connected with the output end of the first signal isolator, and the output end of the first comparator is connected with the output end of the transmitting channel.
3. The bi-directional digital isolator of claim 1, wherein the receive channel comprises:
the input end of the second Schmitt trigger is connected with the input end of the receiving channel;
the input end of the second signal isolator is connected with the output end of the second Schmitt trigger;
the input end of the second comparator is connected with the output end of the second signal isolator, and the output end of the second comparator is connected with the output end of the receiving channel.
4. The bi-directional digital isolator of claim 1, wherein the first device is a master controller, and the enabling channel comprises:
the input end of the first enabling channel is connected with the first device, and the first enabling channel is also connected with the enabling end of the first comparator;
and the input end of the second enabling channel is connected with the first device, and the output end of the second enabling channel is connected with the enabling end of the second comparator.
5. The bi-directional digital isolator of claim 4, wherein when the bi-directional digital isolator has only a first enable pin on the same side as the first device and a second enable pin on the same side as the second device, the transmit channel comprises:
an enabling transmission channel, wherein an input end of the enabling transmission channel is connected with the first device, and an output end of the enabling transmission channel is connected with a second enabling pin close to the second device;
the second enabling pin is electrically connected with an enabling end of the first comparator to form the first enabling channel.
6. The bi-directional digital isolator of claim 1, wherein the output of the transmit channel is in a high impedance state when the enable of the first comparator inputs a low level;
when the enabling end of the second comparator inputs low level, the output end of the receiving channel is in a high-resistance state.
7. A method of communication, adapted for use with the bi-directional digital isolator of any one of claims 1-6, comprising:
when a first device transmits a communication signal to a second device, the first device communicates by adopting a first method, wherein the first method comprises the following steps:
step A1: inputting a low-level enabling signal to the second comparator so as to enable the output end of the receiving channel to be in a high-resistance state;
step A2: the first device inputs the communication signal via a first data pin, such that the second device receives the communication signal via a transmit channel and a second data pin;
when the second device sends the communication signal to the first device, adopting a second method for communication, wherein the second communication method comprises the following steps:
step B1: inputting a low-level enabling signal to a first comparator so as to enable the output end of the sending channel to be in a high-resistance state;
step B2: the second device inputs the communication signal via the second data pin such that the first device receives the communication signal via a receive channel and a first data pin.
8. The communication method according to claim 7, wherein when the first device is a master controller in a bus communication protocol, the second communication method further comprises, before performing the step B1:
step B01: the first device transmits a low-level enable signal via an enable transmission channel, and the low-level enable signal is input to an enable end of the first comparator via a second enable pin.
CN202311260335.2A 2023-09-26 2023-09-26 Bidirectional digital isolator and communication method Pending CN117478124A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311260335.2A CN117478124A (en) 2023-09-26 2023-09-26 Bidirectional digital isolator and communication method

Publications (1)

Publication Number Publication Date
CN117478124A true CN117478124A (en) 2024-01-30

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