CN117472806B - Address translation method and device and computer storage medium - Google Patents
Address translation method and device and computer storage medium Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000013507 mapping Methods 0.000 claims abstract description 94
- 230000004044 response Effects 0.000 claims description 22
- 230000014616 translation Effects 0.000 description 45
- 238000010586 diagram Methods 0.000 description 13
- 238000012545 processing Methods 0.000 description 13
- 230000006870 function Effects 0.000 description 11
- 238000009877 rendering Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000013473 artificial intelligence Methods 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- NFRBUOMQJKUACC-UHFFFAOYSA-N triethyl(pentyl)azanium Chemical compound CCCCC[N+](CC)(CC)CC NFRBUOMQJKUACC-UHFFFAOYSA-N 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention relates to the technical field of computers, and discloses an address translation method, an address translation device and a computer storage medium, wherein the address translation method can comprise the following steps: receiving a virtual address to be translated, acquiring a target page table item corresponding to the virtual address to be translated based on a virtual address page table item mapping table, and determining a physical address corresponding to the virtual address to be translated based on the target page table item; and responding to the physical page continuous identification bit in the target page table item to meet the preset condition, acquiring the continuous physical page quantity, and updating the virtual address page table item mapping table according to the continuous physical page quantity.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to an address translation method, an address translation device and a computer storage medium.
Background
After the operating system loads the executable file, a process is created, each instruction and each data in the process are allocated with a virtual address, and after the processor acquires the virtual address, the processor can access the instructions and the data only after translating the virtual address into a physical address of a memory.
In the process of translating the virtual address, if a continuous physical page scene appears, multiple access translations can be caused, and the storage access efficiency is affected.
Disclosure of Invention
In view of this, embodiments of the present invention desirably provide an address translation method, an address translation device, and a computer storage medium; the memory access efficiency when successive physical pages are encountered can be improved.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides an address translation method, including:
receiving a virtual address to be translated, acquiring a target page table item corresponding to the virtual address to be translated based on a virtual address page table item mapping table, and determining a physical address corresponding to the virtual address to be translated based on the target page table item;
and responding to the physical page continuous identification bit in the target page table item to meet a preset condition, acquiring the continuous physical page quantity, and updating the virtual address page table item mapping table according to the continuous physical page quantity and the target page table item.
In some examples, the obtaining the number of consecutive physical pages in response to the physical page consecutive identity bits in the target page table entry satisfying a preset condition includes:
and detecting a continuous number identification bit to acquire the continuous physical page number in response to the physical page continuous identification bit in the target page table entry being 1.
In some examples, the updating the virtual address page table entry mapping table according to the number of consecutive physical pages and the target page table entry includes:
updating the virtual address page table entry mapping table in response to the number of consecutive physical pages being greater than 1, and subtracting 1 from the number of consecutive physical pages;
and ending the updating in response to the number of the continuous physical pages being equal to 1.
In some examples, the updating the virtual address page table entry mapping table includes:
obtaining candidate virtual addresses continuous with the virtual address to be translated;
acquiring candidate page table entries which are continuous with the target page table entries;
and determining a mapping relation between the candidate virtual address and the candidate page table item so as to update the virtual address page table item mapping table.
In some examples, the obtaining, based on the virtual address page table entry mapping table, a target page table entry corresponding to the virtual address to be translated, and determining, based on the target page table entry, a physical address corresponding to the virtual address to be translated includes:
querying a target page table item matched with the virtual address to be translated in the virtual address page table item mapping table;
and responding to the virtual address page table entry mapping table to comprise the target page table entry, and determining a physical address based on the virtual address to be translated and the target page table entry.
In some examples, the determining a physical address based on the virtual address to be translated and the target page table entry includes:
obtaining the virtual page offset in the virtual address to be translated;
determining a physical page number in the target page table entry;
the physical address is determined based on the physical page number and a virtual page offset.
In some examples, the obtaining, based on the virtual address page table entry mapping table, a physical address corresponding to the virtual address to be translated includes:
obtaining a page table starting address in a page table base register in response to the virtual address page table entry mapping table not including the target page table entry;
determining the physical address and the target page table item according to the page table starting address and the virtual address to be translated;
and updating the mapping table of the virtual address page table according to the virtual address to be translated and the target page table.
In some examples, the method further comprises:
and responding to address space switching operation of a user, and updating the virtual address page table item mapping table.
In some examples, the method further comprises:
and responding to the physical page release operation of the user, and formatting the virtual address page table entry mapping table.
In a second aspect, an embodiment of the present invention provides an address translation apparatus, including:
the translation module is used for receiving a virtual address to be translated, acquiring a target page table item corresponding to the virtual address to be translated based on a virtual address page table item mapping table, and determining a physical address corresponding to the virtual address to be translated based on the target page table item;
and the updating module is used for responding to the condition that the physical page continuous identification bit in the target page table item meets the preset condition, acquiring the continuous physical page quantity, and updating the virtual address page table item mapping table according to the continuous physical page quantity and the target page table item.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the address translation method according to the first aspect.
In a fourth aspect, embodiments of the present invention provide a computer storage medium storing at least one instruction for execution by a processor to implement the address translation method of the first aspect.
The embodiment of the invention provides an address translation method, an address translation device and a computer storage medium; and when the physical page corresponding to the virtual address to be translated is detected to be the continuous physical page, the virtual address page table entry mapping table is updated in advance according to the continuous physical page number of the physical page, so that the corresponding physical page number can be directly acquired in the virtual address page table entry mapping table later, multiple access translations are avoided, and the translation speed and the access efficiency are improved.
Drawings
Fig. 1 is a block diagram of an implementation environment provided in an embodiment of the present invention.
Fig. 2 is a block diagram of a virtual address according to an embodiment of the present invention.
Fig. 3 is a block diagram of a physical address according to an embodiment of the present invention.
Fig. 4 is a flowchart of an address translation method according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a virtual address page table entry mapping table according to an embodiment of the present invention.
Fig. 6 is a block diagram of a virtual address according to an embodiment of the present invention.
FIG. 7 is a block diagram of another virtual address according to an embodiment of the present invention.
FIG. 8 is a block diagram of a target page table entry according to an embodiment of the present invention.
FIG. 9 is a block diagram of another target page table entry according to an embodiment of the present invention.
Fig. 10 is a schematic diagram of an address translation device according to an embodiment of the present invention.
Fig. 11 is a schematic structural diagram of an electronic device according to the present invention.
Specific embodiments of the present invention have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Generally, after an operating system of a computer loads an executable file, a process is created, each instruction and data in the process is allocated with a virtual address, after the processor obtains the virtual address, the processor needs to translate the virtual address into a physical address of a memory to access the instruction and the data, and therefore, the translation from the virtual address to the physical address is important. Typically, the processor sends the virtual address to a memory management module (Memory Management Unit, MMU), which translates the virtual address to a physical address and feeds the physical address back to the processor to enable the processor to access the internal memory according to the physical address. The processor may be a core processor, a graphics processor, or other processors, which will not be described herein.
For a general system application scenario, the storage supports 4K page organization management, namely a translation management mode of 12-bit addresses at a time. However, in the context of a graphics processor (Graphics Processing Unit, GPU), when a rendering task accesses a large amount of data, continuous physical page access must occur, which results in frequent translation by the MMU, and has an impact on the performance of address translation.
For example, FIG. 1 shows a schematic diagram of one implementation environment provided by the present invention, in the context of a graphics processor (Graphics Processing Unit, GPU), a GPU chip may include a graphics processor 210, an MMU220, and a backing buffer (TranslationLookaside Buffer, TLB) 230. In some examples, the TLB may be integrated with the MMU to enhance the integration of GPU chips. And the speed of the MMU for accessing the TLB is improved, and the response speed is improved.
In translating the virtual addresses, graphics processor 210 may send Virtual Addresses (VA) to MMU220, where the virtual addresses may include virtual page numbers (Virtual Private Network, VPN) and virtual page offsets (Virtual Page Offset, VPO) as shown in fig. 2. After receiving the VA, the MMU220 may send the VPN in the VA to the TLB230, where the TLB230 queries a Page Table Entry (PTE) corresponding to the VPN in a virtual address Page Table Entry mapping Table according to the VPN, where the PTE may include a physical Page Table Entry PPN and a valid bit, and the valid bit is used to prove whether the physical Page Table Entry is valid, and the specific effect of the valid bit may refer to the related art and is not described herein.
If the PTE corresponding to the VPN is queried in the virtual address page table item mapping table, the PPN in the PTE and the VPO in the VA are utilized to determine the physical address, as shown in fig. 3.
If no PTE corresponding to VPN is found in the virtual address page table entry mapping table, MMU is required to obtain page table starting address according to page table base address register (not shown), and further translate the VA address to obtain PTE corresponding to VPN. The specific translation process may refer to the related art, and will not be described herein.
In the GPU scenario, the amount of access data of the rendering task is large, and a situation of continuous physical page access inevitably occurs, and in this case, the MMU needs to access the Page Table Base Register (PTBR) multiple times to obtain the physical address, which results in lower translation efficiency of the MMU and affects access efficiency of the MMU.
It should be noted that, the condition of continuous physical page access in the address translation method is not limited to the GPU scenario, and may also be performed in a CPU scenario and other scenarios, and specific embodiments are the same as the GPU scenario, which is not described herein again.
Based on the above drawbacks, the present invention proposes an address translation method, referring to fig. 4, which can be performed by the MMU in the GPU chip, including steps S410 to S420.
In step S410, a virtual address to be translated is received, a target page table entry corresponding to the virtual address to be translated is obtained based on the virtual address page table entry mapping table, and a physical address corresponding to the virtual address to be translated is determined based on the target page table entry.
In some example embodiments of the present invention, the MMU may receive a virtual address to be translated sent by the graphics processor, where the virtual address to be translated may include a virtual page number (Virtual Private Network, VPN) and a virtual page offset (Virtual Page Offset, VPO), and the details are described above in detail and are not repeated herein.
After obtaining the virtual address to be translated, the MMU may obtain a target page table entry corresponding to the virtual address to be translated according to the virtual address page table entry mapping table, and determine a physical address corresponding to the virtual address to be translated based on the target page table entry.
Specifically, the virtual address page table entry mapping table may be stored in a TLB, where the virtual address page table entry mapping table stores a mapping relationship between a Virtual Page Number (VPN) and a Page Table Entry (PTE), and referring to fig. 5, the virtual address page table entry mapping table may be formed by m TLB sets, where each TLB set has n entries, each entry has a PTE and a tag bit, the tag bit is a number, and the tag bit of each TLB set cannot be repeated, so that in one TLB set, an entry may be located according to the tag bit, and each set has a unique number called a set number. It is contemplated that the TLB is a two-dimensional array that is positionable to a unique PTE after the set number and tag bits are determined.
Alternatively, referring to fig. 6, a Virtual Page Number (VPN) in a virtual address may be split into two parts, namely a group number and a tag bit, the VPN is composed of the tag bit (TLBT) and the group number, which may also be referred to as a tag index (TLBI).
If the VPN hits the corresponding PTE in the virtual page table, a physical address may be formed from the physical page number PPN in the PTE and the VPO corresponding to the VPN.
If there is a miss, the MMU may derive the physical address of the virtual page table entry (i.e., page Table Entry Address, PTEA) from the page table start address in the Page Table Base Register (PTBR) plus the Virtual Page Number (VPN), then send this physical address to the cache, which queries the internal buffer mapping table according to the PTEA to obtain the PTE, and transmits the PTE to the TLB, which establishes a mapping relationship between VPN and PTE, and the TLB sends the PTE to the MMU to complete the translation of the virtual address to be translated to the physical address. Specific translation processes may refer to related technologies, and are not described herein.
Optionally, the mapping table of the virtual address page table entry may directly store a mapping relationship between a Virtual Page Number (VPN) and a physical address, i.e. the physical address corresponding to the Virtual Page Number (VPN) may be directly queried in the mapping table of the virtual address page table entry according to the Virtual Page Number (VPN).
In step S420, in response to the physical page continuous identification bit in the target page table entry meeting the preset condition, the number of continuous physical pages is obtained, and the virtual address page table entry mapping table is updated according to the number of continuous physical pages and the target page table entry.
In some exemplary embodiments of the present invention, fig. 7 shows a schematic diagram of a target page table entry in the present invention, where the target page table entry may include a physical page number PPN and a physical page continuation identification bit, where the physical page number is used to indicate a physical address, and the physical page continuation identification bit is used to indicate whether the physical page is continuous.
Alternatively, the physical page continuity flag may be 0 or 1, and in some examples, a physical page continuity flag of 1 indicates that the physical page is continuous, and a physical page continuity flag of 0 indicates that the physical page is discontinuous, where the preset condition may be that the physical page continuity flag is 1.
In other examples, a physical page continuity flag of 0 indicates physical page continuity, and a physical page continuity flag of 1 indicates physical page discontinuity, where the preset condition may be that the physical page continuity flag is 0.
It should be noted that, the specific form of the physical page continuous identification bit may be customized according to the user's requirement, for example, whether it is continuous or not is determined by adopting a letter way, for example, a represents continuous, and a represents discontinuous; the Chinese characters are used for representing that the Chinese characters are continuous, the Chinese characters are not continuous, and the like, and the description is omitted in the embodiment of the present invention.
In some examples of the present invention, when the physical page continuous identification bit satisfies a preset condition, the continuous number of physical pages may be obtained, and when the physical page continuous identification bit satisfies the preset condition, the continuous number is equal to or greater than 2, and after the continuous number is obtained, the virtual address page table entry mapping table may be updated according to the continuous number.
Specifically, the PTE corresponding to the continuous physical page and the VPN corresponding to the PTE are stored in the virtual address page table entry mapping table in advance, so that in the subsequent translation process, the MMU can directly obtain the PTE corresponding to the VPN from the virtual address page table entry mapping table, thereby improving the translation rate.
According to the address translation method, the physical page continuous identification bit is added in the target page table item corresponding to the virtual address and is used for acquiring whether the physical page corresponding to the virtual address to be translated is a continuous physical page or not, when the physical page corresponding to the virtual address to be translated is detected to be the continuous physical page, the virtual address page table item mapping table is updated in advance according to the continuous physical page quantity of the physical page, so that the corresponding physical page number can be directly acquired in the virtual address page table item mapping table in the follow-up process, multiple access translation is avoided, and the translation speed and the access efficiency are improved.
In some example embodiments of the present invention, referring to fig. 8, the target page table entry may further include a consecutive number identification bit, where the consecutive number identification bit is used to characterize the number of consecutive physical pages, and the MMU may determine the number of consecutive physical pages according to the consecutive number identification bit. Wherein the number of the continuous physical pages is a positive integer of 1 or more.
After the number of continuous physical pages is obtained, it may be determined whether the number of continuous physical pages is greater than 1, and if the number of continuous physical pages is greater than 1, both the virtual address page number and the physical page number are shifted left by a preset number of bits, where the preset number of bits is related to the physical page mapping, and if the number of continuous physical pages is 4K physical page mapping, the preset number of bits may be 12, and if the number of continuous physical pages is 6K physical page mapping, the preset number of bits may be 18, which is not described in detail in this exemplary embodiment.
And after the virtual address page and the physical page numbers are shifted left, a new mapping relation is obtained, the virtual address page table item mapping table is updated by using the new mapping relation, meanwhile, the number of the continuous physical pages is reduced by 1, the steps are circularly executed until the number of the continuous physical pages is equal to 1, and the updating process is stopped.
Taking the physical page mapping bit 4K physical page mapping as an example, when updating the virtual address page table item mapping table, the virtual page table item and the physical page table item can be moved to the left by 12 bits, then, the virtual identifier and the physical page identifier are added by 1, and the number of the continuous physical pages is reduced by 1 until the number of the continuous physical pages is 1.
Fig. 9 shows a data flow chart of another address translation method of the present invention, it is conceivable that, after the CPU sends a rendering task to the GPU, the GPU sends a virtual address to the MMU through direct memory access (Direct Memory Access, DMA), the MMU obtains the PTE corresponding to the VA from the page table base register PTBR, at this time, step S910 may be executed to determine whether a physical page continuous identification bit in the PTE is set, that is, determine whether the physical page continuous identification bit is 1, if not, step S920 is executed to store the PTE in the TLB, if yes, step S930 is executed to determine whether the continuous physical page quantity is greater than 1, if yes, step S940 is executed to update the TLB, specifically, the virtual page identification is increased by 1, the physical page identification is increased by 1, both the virtual page number and the physical page number are moved by 12 bits to the left, and the continuous physical page quantity is reduced by 1. If not, ending.
In a subsequent process, the MMU may obtain a physical address based on the PTE in the TLB and feed back to the DMA, so that the GPU may access the memory DDR through the physical address PA via the DMA.
In some exemplary embodiments of the present invention, the MMU may further format the virtual address page table entry mapping table in the TLB in response to a physical page release operation by a user. The TLB can be cleaned, and the cache function of the TLB is ensured.
Optionally, the physical page release operation may be sent by an MMU, and after the virtual page table entry mapping is not used in the preset time of the user, the MMU may perform formatting processing on the virtual address page table entry mapping table, where the preset time may be one month, half year, or the like, or may be customized according to the user requirement, which is not described in this example embodiment.
In some examples, the MMU may also update the TLB in response to a user switching operation to an address space, specifically, first update the page table base register PTBR, and update a virtual address page table entry mapping table in the TLB based on the page table base register PTBR. Preventing cache function failures in the TLB.
According to the address translation method, the physical page continuous identification bit is added in the target page table item corresponding to the virtual address and is used for acquiring whether the physical page corresponding to the virtual address to be translated is a continuous physical page or not, when the physical page corresponding to the virtual address to be translated is detected to be the continuous physical page, the virtual address page table item mapping table is updated in advance according to the continuous physical page quantity of the physical page, so that the corresponding physical page number can be directly acquired in the virtual address page table item mapping table in the follow-up process, multiple access translation is avoided, and the translation speed and the access efficiency are improved. Further, in response to a user switching operation on an address space, the TLB is updated, specifically, the page table base register is updated first, and the virtual address page table entry mapping table in the TLB is updated based on the page table base register, so that a cache function failure in the TLB can be prevented.
Further, the present invention also provides an address translation apparatus, referring to fig. 10, the address translation apparatus 1000 may include a translation module 1010 and an update module 1020, where:
the translation module 1010 may be configured to receive a virtual address to be translated, obtain a target page table entry corresponding to the virtual address to be translated based on the virtual address page table entry mapping table, and determine a physical address corresponding to the virtual address to be translated based on the target page table entry.
The updating module 1020 may be configured to obtain the number of consecutive physical pages in response to the physical page consecutive identification bit in the target page table entry satisfying a preset condition, and update the virtual address page table entry mapping table according to the number of consecutive physical pages and the target page table entry.
In some examples, translation module 1010 may be configured to query a virtual address page table entry mapping table for a target page table entry that matches the virtual address to be translated; the response virtual address page table entry mapping table comprises a target page table entry, and a physical address is determined based on the virtual address to be translated and the target page table entry.
In some examples, translation module 1010 may be configured to obtain a virtual page offset in a virtual address to be translated; determining a physical page number in a target page table entry; the physical address is determined based on the physical page number and the virtual page offset.
In some examples, translation module 1010 may be configured to obtain a page table starting address in a page table base register in response to the virtual address page table entry mapping table not including the target page table entry; determining a physical address and a target page table item according to a page table starting address and a virtual address to be translated; and updating the virtual address page table item mapping table according to the virtual address to be translated and the target page table item.
In some examples, a physical page continuation identification bit of 1 indicates physical page continuation and a physical page continuation identification bit of 0 indicates physical page discontinuity, the update module 1020 may be configured to detect the continuation quantity identification bit to obtain the number of consecutive physical pages in response to the physical page continuation identification bit in the target page table entry being 1.
In some examples, the update module 1020 may be configured to update the virtual address page table entry mapping table and decrease the number of consecutive physical pages by 1 in response to the number of consecutive physical pages being greater than 1; and ending the update in response to the number of consecutive physical pages being equal to 1.
In some examples, the update module 1020 may be configured to obtain candidate virtual addresses that are contiguous with the virtual address to be translated; acquiring candidate page table entries which are continuous with the target page table entries; and determining a mapping relation between the candidate virtual address and the candidate page table item so as to update the virtual address page table item mapping table.
Referring to fig. 11, a block diagram of an electronic device according to an exemplary embodiment of the present invention is shown. In some examples, the electronic device may be at least one of a smart phone, a smart watch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The electronic device has a communication function and can access a wired network or a wireless network. An electronic device may refer broadly to one of a plurality of terminals, and those skilled in the art will recognize that the number of terminals may be greater or lesser. In some examples, the electronic device may receive the virtual address to be translated based on the accessed wired network or wireless network. It will be appreciated that the electronic device bears the calculation and processing operations of the technical solution of the present invention, and the embodiment of the present invention is not limited thereto.
As shown in fig. 11, the electronic device of the present invention may include one or more of the following components: a processor 1110 and a memory 1120.
In the alternative, processor 1110 utilizes various interfaces and lines to connect various portions of the overall electronic device, perform various functions of the electronic device, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in memory 1120, and invoking data stored in memory 1120. Alternatively, the processor 1110 may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 1110 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processing unit (Graphics Processing Unit, GPU), a Neural network processing unit (Neural-network Processing Unit, NPU), and a baseband chip, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the touch display screen; the NPU is used to implement artificial intelligence (Artificial Intelligence, AI) functionality; the baseband chip is used for processing wireless communication. It will be appreciated that the baseband chip may not be integrated into the processor 1110 and may be implemented by a single chip.
The memory 1120 may include a random access memory (Random Access Memory, RAM) or a Read-only memory (ROM). Optionally, the memory 1120 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 1120 may be used to store instructions, programs, code, sets of codes, or instruction sets. The memory 1120 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above respective method embodiments, etc.; the storage data area may store data created according to the use of the electronic device, etc.
In addition, those skilled in the art will appreciate that the configuration of the electronic device shown in the above-described figures does not constitute a limitation of the electronic device, and the electronic device may include more or less components than illustrated, or may combine certain components, or may have a different arrangement of components. For example, the electronic device further includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a bluetooth module, etc., which are not described herein.
Embodiments of the present invention also provide a computer readable storage medium storing at least one instruction for execution by a processor to implement the address translation method of the above embodiments.
Embodiments of the present invention also provide a computer program product comprising computer instructions stored in a computer-readable storage medium; the processor of the electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions so that the electronic device executes to implement the address translation method of each of the above embodiments.
Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the embodiments of the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
It should be noted that: the technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision.
The foregoing is merely illustrative embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present invention, and the invention should be covered.
Claims (11)
1. An address translation method, comprising:
receiving a virtual address to be translated, acquiring a target page table item corresponding to the virtual address to be translated based on a virtual address page table item mapping table, and determining a physical address corresponding to the virtual address to be translated based on the target page table item;
responding to the physical page continuous identification bit in the target page table item to meet a preset condition, obtaining the continuous physical page quantity, and updating the virtual address page table item mapping table according to the continuous physical page quantity and the target page table item;
wherein said updating said virtual address page table entry mapping table based on said number of consecutive physical pages and said target page table entry comprises:
updating the virtual address page table entry mapping table based on the target page table entry in response to the number of consecutive physical pages being greater than 1, and subtracting 1 from the number of consecutive physical pages;
ending the update in response to the number of consecutive physical pages being equal to 1;
said updating said virtual address page table entry mapping table based on said number of consecutive physical pages and said target page table entry comprising:
and shifting the virtual address page number and the physical page number left by a preset bit number to obtain a group of new mapping relations, and updating the virtual address page table entry mapping table by using the new mapping relations.
2. The method of claim 1, wherein a physical page continuation identification bit of 1 indicates physical page continuation and a physical page continuation identification bit of 0 indicates physical page discontinuity;
the responding that the physical page continuous identification bit in the target page table item meets the preset condition comprises the following steps:
and detecting a continuous number identification bit to acquire the continuous physical page number in response to the physical page continuous identification bit in the target page table entry being 1.
3. The method of claim 1, wherein the updating the virtual address page table entry mapping table based on the target page table entry comprises:
obtaining candidate virtual addresses continuous with the virtual address to be translated;
acquiring candidate page table entries which are continuous with the target page table entries;
and determining a mapping relation between the candidate virtual address and the candidate page table item so as to update the virtual address page table item mapping table.
4. The method of claim 1, wherein the obtaining, based on the virtual address page table entry mapping table, a target page table entry corresponding to the virtual address to be translated, and determining, based on the target page table entry, a physical address corresponding to the virtual address to be translated, comprises:
querying a target page table item matched with the virtual address to be translated in the virtual address page table item mapping table;
and responding to the virtual address page table entry mapping table to comprise the target page table entry, and determining a physical address based on the virtual address to be translated and the target page table entry.
5. The method of claim 4, wherein the determining a physical address based on the virtual address to be translated and the target page table entry comprises:
obtaining the virtual page offset in the virtual address to be translated;
determining a physical page number in the target page table entry;
the physical address is determined based on the physical page number and a virtual page offset.
6. The method of claim 1, wherein the obtaining, based on the virtual address page table entry mapping table, a target page table entry corresponding to the virtual address to be translated, and determining, based on the target page table entry, a physical address corresponding to the virtual address to be translated, comprises:
obtaining a page table starting address in a page table base register in response to the virtual address page table entry mapping table not including the target page table entry;
determining the target page table item according to the page table starting address and the virtual address to be translated, and determining the physical address based on the target page table item;
and updating the mapping table of the virtual address page table according to the virtual address to be translated and the target page table.
7. The method according to claim 1, wherein the method further comprises:
and responding to address space switching operation of a user, and updating the virtual address page table item mapping table.
8. The method according to claim 1, wherein the method further comprises:
and responding to the physical page release operation of the user, and formatting the virtual address page table entry mapping table.
9. An address translation apparatus, comprising:
the translation module is used for receiving a virtual address to be translated, acquiring a target page table item corresponding to the virtual address to be translated based on a virtual address page table item mapping table, and determining a physical address corresponding to the virtual address to be translated based on the target page table item;
the updating module is used for responding to the condition that the physical page continuous identification bit in the target page table item meets the preset condition, obtaining the continuous physical page quantity, and updating the virtual address page table item mapping table according to the continuous physical page quantity and the target page table item;
wherein said updating said virtual address page table entry mapping table according to said number of consecutive physical pages and said target page table entry comprises:
updating the virtual address page table entry mapping table based on the target page table entry in response to the number of consecutive physical pages being greater than 1, and subtracting 1 from the number of consecutive physical pages;
ending the update in response to the number of consecutive physical pages being equal to 1;
said updating said virtual address page table entry mapping table based on said number of consecutive physical pages and said target page table entry comprising:
and shifting the virtual address page number and the physical page number left by a preset bit number to obtain a group of new mapping relations, and updating the virtual address page table entry mapping table by using the new mapping relations.
10. An electronic device, the electronic device comprising: a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the address translation method of any one of claims 1 to 8.
11. A computer storage medium storing at least one instruction for execution by a processor to implement the address translation method of any one of claims 1 to 8.
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