CN117472637B - Interrupt management method, system, equipment and medium - Google Patents
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Abstract
The invention relates to the technical field of communication data processing, and discloses an interrupt management method, an interrupt management system, interrupt management equipment and an interrupt management medium. The method comprises the following steps: determining the current interrupt number of the interrupt request and the current interrupt number corresponding to each interrupt request based on the interrupt identification logic module according to a plurality of interrupt requests sent by the kernel unit received in the current clock period; respectively caching the current interrupt number and each current interrupt number into an interrupt number caching module and an interrupt number caching module; if the interrupt number buffer module is detected to be not empty, reading the current interrupt number from the interrupt number buffer module through the interrupt logic generation module, and sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number; and generating an interrupt message based on the read current interrupt numbers and the interrupt information table. By the scheme of the invention, the problem of kernel interrupt bottleneck is effectively avoided, and the kernel working efficiency is improved.
Description
Technical Field
The present invention relates to communication data processing technologies, and in particular, to an interrupt management method, system, device, and medium.
Background
The design of the FPGA (Field Programmable Gate Array ) is divided into a shell (shell) part and a dynamic kernel (dynamic kernel) part, and the dynamic kernel realizes the communication with a host driver through register read-write and interrupt signals. When any dynamic kernel needs to initiate an interrupt to a host driver, an interrupt request is sent through an interrupt status register maintained in the dynamic kernel, and the shell logically recognizes the interrupt request to transmit an interrupt vector corresponding to the dynamic kernel to a CPU (Central Processing Unit ) so as to realize the interrupt.
With the progress of chip technology, the expansion of the FPGA logic scale and the increase of the number of FPGA dynamic kernels, under the condition that the high-density FPGA dynamic kernels initiate interrupt signals at the same time, the process of realizing hardware interrupt in the related technology has higher time delay, so that the dynamic kernel interrupt bottleneck is easy to be caused, and further the problem of kernel execution efficiency reduction is caused. Therefore, there is a need to propose an interrupt management method to solve the drawbacks of the related art.
Disclosure of Invention
In view of this, the present invention proposes an interrupt management method, system, device and medium. The problems of low interrupt request identification efficiency, low interrupt address information confirmation speed, kernel interrupt bottleneck and the like in the interrupt message generation process are solved, the working efficiency of the kernel is effectively improved, and higher application value is provided for a time-delay sensitive FPGA application scene.
Based on the above object, an aspect of the embodiments of the present invention provides an interrupt management method, which is applied to a shell unit of a field programmable gate array device, where the shell unit includes an interrupt identification logic module, an interrupt logic generation module, an interrupt number buffer module, and the interrupt management method specifically includes the following steps:
determining the current interrupt number for sending the interrupt request and the current interrupt number corresponding to each interrupt request based on the interrupt identification logic module according to a plurality of interrupt requests sent by the kernel unit received in the current clock period;
respectively caching the current interrupt number and each current interrupt number to the interrupt number caching module and the interrupt number caching module;
if the interrupt number buffer module is detected to be not empty, reading the current interrupt number from the interrupt number buffer module through the interrupt logic generation module, and sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number;
and generating an interrupt message based on the read current interrupt numbers and the interrupt information table.
In some embodiments, the step of reading, by the interrupt logic generating module, the current interrupt number from the interrupt number buffer module, and sequentially reading, based on the current interrupt number, each current interrupt number from the interrupt number buffer module includes:
judging whether the interrupt logic generation module is in an idle state in the current clock period;
if the interrupt logic generation module is detected to be in an idle state in the current clock period, the current interrupt number is read from the interrupt number cache module through the interrupt logic generation module, and the current interrupt numbers corresponding to the current interrupt number are sequentially read from the interrupt number cache module.
In some embodiments, the step of generating an interrupt message based on each of the current interrupt numbers and the interrupt information tables that are read includes:
and acquiring binary codes corresponding to target bits in the current interrupt numbers, inquiring target interrupt position information matched with the binary codes in the interrupt information table through the interrupt logic generation module, and constructing corresponding interrupt information according to the target interrupt position information.
In some embodiments, the interrupt management method further comprises:
if the interrupt logic generation module is detected to be in a non-idle state in the current clock cycle, acquiring a first interrupt number corresponding to the previous clock cycle from the interrupt number buffer module;
judging whether the number of the first interrupt numbers corresponding to the last clock cycle read by the interrupt logic generation module meets the first interrupt number or not;
and if the number of the first interrupt numbers read by the interrupt logic generation module meets the first interrupt number, triggering the interrupt logic generation module to read the current interrupt number from the interrupt number cache module, and sequentially reading the current interrupt numbers corresponding to the current interrupt number from the interrupt number cache module.
In some embodiments, the interrupt management method further comprises:
if the number of the first interrupt numbers read by the interrupt logic generation module does not meet the first interrupt number, continuing to read the first interrupt numbers from the interrupt number cache module by the interrupt logic generation module;
And generating an interrupt message based on the first interrupt number and the interrupt information table, and returning to the step of judging whether the number of the first interrupt numbers corresponding to the previous clock cycle read by the interrupt logic generation module meets the first interrupt number.
In some embodiments, the step of determining, based on the interrupt recognition logic module, a current interrupt number corresponding to each interrupt request includes:
inputting each interrupt request into a lookup table of the interrupt identification logic module, inquiring a kernel code matched with each interrupt request in the lookup table, and taking a binary code of each kernel code as a corresponding current interrupt number.
In some embodiments, the step of determining the current number of interrupts that sent the interrupt request based on the interrupt recognition logic module includes:
all of the interrupt requests are transmitted to a serial carry adder within the interrupt identification logic module to calculate the current interrupt number.
In some embodiments, the step of sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number includes:
Judging whether the number of the current interrupt numbers read by the interrupt logic generation module meets the current interrupt number or not after finishing one current interrupt number per reading;
if the number of the current interrupt numbers read by the interrupt logic generation module does not meet the current interrupt number, continuing to read the interrupt numbers from the interrupt number cache module by the interrupt logic generation module according to the cache sequence, and returning to the step of judging whether the number of the current interrupt numbers read by the interrupt logic generation module meets the current interrupt number;
and stopping the interrupt logic generating module from reading the current interrupt number from the interrupt number caching module if the number of the current interrupt numbers read by the interrupt logic generating module meets the current interrupt number.
In some embodiments, the interrupt management method further comprises:
if the number of the current interrupt numbers read by the interrupt logic generation module meets the current interrupt number, the current interrupt number cached in the interrupt number caching module and the current interrupt number cached in the interrupt number caching module, which corresponds to the current interrupt number, are cleared;
Detecting whether the interrupt number cache module is empty or not;
if the interrupt number buffer module is detected not to be empty, triggering the interrupt logic generation module to read a second interrupt number corresponding to the next clock cycle from the interrupt number buffer module, and reading a second kernel code corresponding to the second interrupt number from the interrupt number buffer module, wherein the second kernel code is a kernel code corresponding to the next clock cycle.
In some embodiments, the interrupt management method further comprises:
and sequentially sending each interrupt message to a central processing unit so as to respond to the interrupt of the kernel corresponding to each interrupt position information.
In some embodiments, the interrupt management method further comprises:
initializing an extended message signal interrupt vector table according to the kernel number information, the interrupt number information and the interrupt position information which are respectively distributed to the kernels by each piece of software and correspond to each kernel in the kernel unit;
and synchronizing all the kernel number information, the interrupt number information and the interrupt position information in the initialized extended message signal interrupt vector table to the interrupt information table.
In some embodiments, the step of receiving the interrupt requests sent by the core unit in the current clock cycle includes:
detecting whether the value of a rising edge signal corresponding to an interrupt signal of each core in the core unit is 1 or not in the current clock cycle;
if any rising edge signal is detected to be 1, determining that the shell unit receives an interrupt request sent by the core unit in the current clock cycle.
In some embodiments, the interrupt management method further comprises:
initializing output signals of the interrupt identification logic module, and sequentially assigning each current interrupt number to a target bit in the initialized output signals according to the sequence from low to high;
and sending the assigned output signal to the interrupt number caching module through the interrupt identification logic module so as to cache all the current interrupt numbers to the interrupt number caching module.
In some implementations, the serial carry adder isAnd a stage serial carry adder, wherein N is the total number of the kernel units.
In some embodiments, the output signal has a bit width of Wherein N is the total number of the kernel units.
In some implementations, the target interrupt location information includes an interrupt vector and an interrupt address.
In some embodiments, the target bit is lowBits, where N is the total number of core units.
In some embodiments, the buffer depth of the interrupt number buffer module and the buffer depth of the interrupt number buffer module are not less than N, where N is the total number of the kernel units.
In another aspect of the embodiment of the present invention, there is also provided an interrupt management system, including:
the identification module is used for determining the current interrupt number for sending the interrupt request and the current interrupt number corresponding to each interrupt request based on the interrupt identification logic module according to a plurality of interrupt requests sent by the kernel unit received in the current clock period;
the buffer module is used for buffering the current interrupt number and each current interrupt number to the interrupt number buffer module and the interrupt number buffer module respectively;
the reading module is used for reading the current interrupt number from the interrupt number buffer module through the interrupt logic generation module if the interrupt logic generation module detects that the interrupt number buffer module is not empty, and sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number;
And the generation module is used for generating an interrupt message based on the read current interrupt numbers and the interrupt information table.
In yet another aspect of the embodiment of the present invention, there is also provided a computer apparatus, including: at least one processor; and a memory storing a computer program executable on the processor, which when executed by the processor, performs the steps of the method as above.
In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The invention has at least the following beneficial technical effects:
(1) According to the interrupt management method, the interrupt number buffer modules and the interrupt number buffer modules are added, so that the processing process of the interrupt identification logic module and the processing process of the interrupt logic generation module in the shell can be respectively and independently performed, namely, the interrupt identification logic module can start a new processing process without waiting for the completion of the ongoing processing process in the interrupt logic generation module, the processing time delay of the interrupt identification logic process is effectively reduced, and a large amount of unnecessary waiting time between the interrupt identification logic module and the interrupt logic generation module is avoided;
(2) According to the interrupt management method, the number of the cores is rapidly determined by using the serial carry adder, the mapping relation between the interrupt request and the interrupt number is stored by setting the lookup table in the interrupt identification logic module, the interrupt number of the core corresponding to the interrupt request is rapidly obtained in a lookup table mode, a large number of complex calculations are avoided, and the interrupt requests sent by a plurality of core units at the same moment are identified in batches in one clock cycle;
(3) According to the interrupt management method, the interrupt information table is set to store the mapping relation between the interrupt numbers and the interrupt address information, once the interrupt logic generation module detects that the interrupt number buffer module is not empty, the interrupt numbers can be read from the interrupt number buffer module according to the interrupt number to serve as indexes, so that interrupt information is quickly generated by inquiring the interrupt address information in the interrupt information table, the time delay generated by the interrupt information is greatly reduced, the problem of a kernel interrupt bottleneck is avoided, the working efficiency of the kernel is improved, and higher application value is provided for the FPGA application scene with sensitive time delay.
In addition, the invention also provides an interrupt management system, a computer device and a computer readable storage medium, which can also achieve the technical effects described above, and are not repeated here.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram illustrating an embodiment of an interrupt management method according to the present invention;
FIG. 2 is a schematic diagram of an embodiment of an FPGA interrupt management structure according to the present invention;
FIG. 3 is a schematic diagram of a related art 2-input interrupt number calculation logic;
FIG. 4 is a schematic diagram of a 2-input interrupt number calculation circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an embodiment of an interrupt management system according to the present invention;
FIG. 6 is a schematic diagram illustrating a computer device according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of an embodiment of a computer readable storage medium according to the present invention.
Detailed Description
The present application will be further described with reference to the drawings and detailed description, which should be understood that, on the premise of no conflict, the following embodiments or technical features may be arbitrarily combined to form new embodiments.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two non-identical entities with the same name or non-identical parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements does not include other steps or elements inherent to the apparatus.
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The flow diagrams depicted in the figures are merely illustrative and not necessarily all of the elements and operations/steps are included or performed in the order described. For example, some operations/steps may be further divided, combined, or partially combined, so that the order of actual execution may be changed according to actual situations.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
The shell portion implements the basic management functions and various data interfaces defined by the device manufacturer for the FPGA heterogeneous accelerator. Basic management functions include downloading of dynamic kernel, programming of Flash-on-board (Flash) chip shell version, message communication of management rights and user rights, hard kernel IP (Internet Protocol, internetworking protocol), and logic implementation of underlying protocol, etc. The data interface includes a data transfer channel between the Host (Host) and the dynamic kernel, which is typically implemented by DMA (Direct Memory Access ) mechanisms of the PCIe (peripheral component interconnect express, high speed serial computer expansion bus standard) bus standard. The dynamic kernel part realizes various functions defined by users, and the dynamic kernel part generally forms a system for realizing specific user functions in a mode of connecting a plurality of kernels in parallel or in series. All user functions can be dynamically switched in a FPGA programming mode, so that the heterogeneous accelerator based on the FPGA has strong universality and flexibility. And maintaining an interrupt state register accessible to the host driver in each kernel, setting one interrupt state register by the kernel when the kernel needs to initiate an interrupt to the host driver, writing an interrupt vector corresponding to the kernel into an address appointed by host system software by the shell through logic identification signals, capturing the action by a CPU interrupt controller so as to realize the interrupt to the host driver, and resetting the interrupt state register of the kernel by the host driver in a register read-write mode after the interrupt processing is completed.
Since each core often works independently, the core interrupt requests have burstiness and uncertainty, i.e., there may be multiple cores initiating interrupt requests at the same time. The shell portion in the related art generally generates a hardware interrupt by detecting the core interrupt signal line one by one. This approach is feasible in scenarios where the kernel layout density is low and the single execution time of the kernel algorithm is long. Assuming that the number of cores is N, so long as the average interrupt request interval of the cores is higher thanThe related art method is used for avoiding the core interrupt bottleneck. However, in a high-density FPGA dynamic kernel scenario, for example, in a scenario where the number of kernels is 1024 and the clock frequency of the shell part is 250MHz, if the kernels execute a lightweight algorithm like matrix inversion or neural network forward computation, the algorithm execution frequency is high, which results in short interrupt request interval time, and the kernel interrupt bottleneck is easily caused by continuously adopting the method of the related technology, which results in the decrease of the kernel working efficiency.
In order to solve the problems, the invention provides an interrupt management method applied to an FPGA shell part, which realizes low-delay hardware interrupt detection and generation, effectively reduces the interrupt processing delay of the shell part and prevents interrupt bottlenecks.
Based on the above object, a first aspect of the embodiments of the present invention proposes an embodiment of an interrupt management method. The interrupt management method is applied to a shell unit of the FPGA, and the shell unit comprises an interrupt identification logic module, an interrupt logic generation module, an interrupt quantity caching module and an interrupt number caching module. As shown in fig. 1, the interrupt management method of the present invention specifically includes the following steps:
step S100, according to a plurality of interrupt requests sent by a core unit received in a current clock period, determining the current interrupt number for sending the interrupt requests and the current interrupt number corresponding to each interrupt request based on an interrupt identification logic module.
Fig. 2 is a schematic diagram of an embodiment of an FPGA interrupt management structure according to the present invention.
In some embodiments, as shown in fig. 2, the shell unit includes an interrupt identification logic module, an interrupt number buffer module, an interrupt generation logic module, and an interrupt information table, and the core unit includes a plurality of cores. Each core sends an interrupt request to the interrupt identification logic module of the shell unit according to the value of the interrupt state register. The interrupt identification logic module is used for calculating the number of cores sending interrupt requests and corresponding interrupt numbers in the same clock cycle, and the interrupt numbers record the positions of the cores corresponding to the interrupt requests in a group of interrupt signal lines, which are binary codes corresponding to the interrupt cores.
In some embodiments, if the total number of cores in a core unit is N, byThe stage serial carry adder can quickly calculate the current interrupt number of the interrupt request sent in the current clock cycle.
In the related art, the FPGA shell part generally uses a manner of detecting the interrupt signal lines of the kernel one by one to generate hardware interrupt, the method firstly builds a one-to-one correspondence between the interrupt signal lines and the kernel in a single thermal coding manner, simultaneously detects the rising edge of each interrupt signal line, caches clock cycles with a certain rising edge subset, detects interrupt positions corresponding to each group of cached interrupt signals one by one with the number of interrupts as counting cycles, deduces an interrupt number corresponding to the kernel which needs to initiate the interrupt according to the interrupt positions, then submits information required for initiating the interrupt to an interrupt management module of PCIe equipment, and the interrupt management module queries an MSIX (Message Signal Interrupt eXtended) function register of the equipment and builds an interrupt TLP (Transaction Layer Protocol, transport layer protocol) frame. Fig. 3 is a schematic diagram of a 2-input interrupt number calculation logic in the related art. In the related art, a gate circuit is used to detect the interrupt position corresponding to the interrupt signal, and if the total number of cores in the core unit is N, it is first required to determine whether the N core interrupt signals are 0 in sequence. When n=2, detection is required through a gate circuit with a number of RTL (Rigister Transfer Level, register transfer stage) module stages of 2n+2, and when N >3, detection is required through a gate circuit with a number of RTL module stages of 2n+2. This results in too long a circuit combining path to output results in one clock cycle when the total number of cores is large. In addition, the interrupt request sent by the core is encoded in a form of a single hot code, the single hot code needs to be converted into a binary code to be used for calculating the final interrupt number, and the conversion process of the single hot code and the binary code in the related art also needs to occupy a large amount of extra gate circuit and network resources.
In some embodiments, the interrupt identification logic of the shell unit determines whether the core has sent an interrupt request by detecting whether the value of the rising edge signal corresponding to the interrupt signal of each core is 1 in each clock cycle. If the rising edge signal corresponding to the interrupt signal of each core is wholly 0, which means that the core unit does not send an interrupt request in the current clock cycle, no processing is performed. If the value of the rising edge signal corresponding to the interrupt signal of any core is 1, the core unit sends an interrupt request in the current clock period, then the lookup table is searched for interrupt numbers matched with the interrupt signal with the value of 1 of the rising edge signal, and the interrupt numbers are sequentially assigned to the target bit of the output signal of the interrupt identification logic module according to the sequence of the interrupt numbers from low to high so as to transmit the interrupt numbers to the interrupt number buffer module. In an example, as shown in fig. 4, a schematic diagram of an embodiment of a 2-input interrupt number calculation circuit provided by the present invention is shown, the number of LUT (Look Up Table) cascade stages in the interrupt number calculation circuit does not change significantly with the increase of the total number of cores, which avoids the problem that the interrupt number calculation circuit is too long due to the increase of the cascade stages in the high-density FPGA core scene, and the calculation of interrupt code cannot be completed in one clock cycle, and the waste of extra gate circuit and net resources caused by single-hot code and binary conversion is avoided by looking Up the LUT to obtain the interrupt number corresponding to the interrupt request. The quick calculation of the interrupt numbers is ensured by setting the corresponding LUT resource unit number aiming at different total cores. Compared with the interrupt number calculation logic circuit in the related art, the interrupt number calculation circuit can finish the calculation of the logic number by only needing 5-6 levels of lookup tables even if the total number of the cores is large, and can easily finish timing sequence convergence.
Wherein, in fig. 3 and fig. 4, kernel_0_interrupt and kernel_1_interrupt respectively represent two input ports, in fig. 3, interrupt_position [1:0] is an interrupt position (i.e. output result) of the binary code in the coding form, and in fig. 4, interrupt_position [1] and interrupt_position [0] are interrupt codes of the binary code in the coding form. Mux in fig. 3 is a multiplexer block, merge circuit block in fig. 3, and Verilog symbols in fig. 3, which are represented as two-bit binary numbers by 2' b11, 2' b00, and 2' b 01. LUT2 in fig. 4 is a lookup table input at two ends, and Vdd is the power supply voltage in the circuit.
Step S200, the current interrupt number and each current interrupt number are respectively cached to an interrupt number caching module and an interrupt number caching module.
In some embodiments, a short time of latching is performed after the current interrupt number and the current interrupt number corresponding to the interrupt request are calculated in the current clock cycle, the current interrupt number is cached to the interrupt number caching module in the latching time, and the current interrupt number is sequentially cached to the interrupt number caching module according to the sequence from low to high of the current interrupt number. Because an indefinite number of cores may exist in each clock cycle to initiate an interrupt request, in order to ensure that the interrupt request of each core is not lost by the shell in a large time scale, the calculation result of the interrupt identification logic module in each clock cycle needs to be cached, and the cache depth of the interrupt number caching module at least corresponds to the total number of cores, or is slightly larger than the total number of cores.
And step S300, if the interrupt number buffer module is detected to be not empty, reading the current interrupt number from the interrupt number buffer module through the interrupt logic generation module, and sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number.
In some embodiments, once the shell unit detects that the interrupt number buffer module is not empty through the interrupt logic generation module, a plurality of interrupt numbers corresponding to the interrupt number buffer module can be read to be sequentially used as indexes, interrupt address information matched with each index is sequentially queried in the interrupt information table, and interrupt information is rapidly generated according to the interrupt address information and sent to the CPU. Meanwhile, the interrupt identification logic module can continue to calculate the interrupt number and the interrupt number corresponding to the interrupt request received in the next clock cycle, and can start a new processing process without waiting for the completion of the processing process of the interrupt logic generation module, so that a large amount of unnecessary waiting time between the interrupt identification logic module and the interrupt logic generation module is avoided.
Step S400, generating an interrupt message based on each read current interrupt number and the interrupt information table.
In some embodiments, the interrupt information table is a cache of a set of core-related interrupt information maintained at the shell unit. Which is indexed by the interrupt number, the contents of the interrupt information table include an interrupt address and an interrupt vector. The MSIX function related register of the PCIe device configuration BAR (base Address register) space can locate the interrupt address and interrupt vector of the kernel, and in the initialization stage of the MSIX vector table of the PCIe device, the interrupt address and interrupt vector distributed by software to the appointed kernel can be synchronously updated into the interrupt information table, so that the interrupt logic generation module can conveniently inquire and independently construct an IRP (Interrupt ReQuest ) TLP frame.
The interrupt management method of the invention, through increasing the buffer modules of the interrupt number and the buffer modules of the interrupt number, the processing process of the interrupt identification logic module and the processing process of the interrupt logic generation module in the shell can be respectively and independently carried out, namely, the interrupt identification logic module can start a new processing process without waiting for the completion of the ongoing processing process in the interrupt logic generation module, thereby effectively reducing the processing time delay of the interrupt identification logic process, avoiding a great deal of unnecessary waiting time between the interrupt identification logic module and the interrupt logic generation module, utilizing the serial carry adder to rapidly determine the interrupt number, and setting a lookup table in the interrupt identification logic module to store the mapping relation between the interrupt request and the interrupt number, the interrupt number of the corresponding kernel of the interrupt request is quickly obtained in a table look-up mode, a large number of complex calculations are avoided, the interrupt requests sent by a plurality of kernel units at the same time are identified in batches in one clock period, further, an interrupt information table is arranged to store the mapping relation between the interrupt number and interrupt address information, once the interrupt logic generation module detects that the interrupt number cache module is not empty, the interrupt number can be read from the interrupt number cache module as an index according to the interrupt number and used for quickly generating interrupt information in the interrupt information table for inquiring the interrupt address information, the time delay generated by the interrupt information is greatly reduced, the problem of the interrupt bottleneck of the kernel is avoided, the working efficiency of the kernel is improved, and higher application value is provided for the FPGA application scene with sensitive time delay.
In some embodiments, the step of reading, by the interrupt logic generating module, the current interrupt number from the interrupt number buffer module, and sequentially reading, based on the current interrupt number, each current interrupt number from the interrupt number buffer module includes: judging whether the interrupt logic generation module is in an idle state in the current clock period; if the interrupt logic generation module is detected to be in an idle state in the current clock period, the current interrupt number is read from the interrupt number buffer module through the interrupt logic generation module, and each current interrupt number with the number corresponding to the current interrupt number is sequentially read from the interrupt number buffer module.
In some embodiments, an interrupt management method of the present invention further includes: if the interrupt logic generation module is detected to be in a non-idle state in the current clock cycle, acquiring a first interrupt number corresponding to the previous clock cycle from the interrupt number buffer module; judging whether the number of the first interrupt numbers corresponding to the last clock cycle read by the interrupt logic generation module meets the first interrupt number or not; if the number of the first interrupt numbers read by the interrupt logic generating module meets the first interrupt number, triggering the interrupt logic generating module to read the current interrupt number from the interrupt number caching module, and sequentially reading each current interrupt number with the number corresponding to the current interrupt number from the interrupt number caching module.
In some embodiments, an interrupt management method of the present invention further includes: if the number of the first interrupt numbers read by the interrupt logic generating module does not meet the first interrupt number, continuing to read the first interrupt numbers from the interrupt number caching module by the interrupt logic generating module; and generating an interrupt message based on the first interrupt number and the interrupt information table, and returning to the step of judging whether the number of the first interrupt numbers corresponding to the last clock cycle read by the interrupt logic generation module meets the first interrupt number.
In some embodiments, if the interrupt logic generation module is in an idle state in the current clock cycle, it indicates that the interrupt logic generation module can immediately start generating an interrupt message corresponding to an interrupt request initiated in the current clock cycle. If the interrupt logic generation module is in a non-idle state in the current clock cycle, the interrupt logic generation module is indicated to process the interrupt request initiated in the previous clock cycle until the logic generation module generates interrupt messages corresponding to the interrupt number in the previous clock cycle, and the interrupt messages corresponding to the interrupt request initiated in the current clock cycle are triggered to start to be generated.
According to the interrupt management method, the interrupt number buffer module and the interrupt number buffer module are added to buffer the calculated interrupt number and interrupt number of each clock cycle, so that the processing process of the interrupt identification logic module and the processing process of the interrupt logic generation module in the shell can be independently carried out, the interrupt identification logic module can continuously calculate the interrupt number and the interrupt number corresponding to the interrupt request received by the other clock cycle while the interrupt identification logic module generates the interrupt message of the previous clock cycle, the processing time delay of the interrupt identification logic process and the generation time delay of the interrupt message are effectively reduced, and a large amount of unnecessary waiting time between the interrupt identification logic module and the interrupt logic generation module is avoided.
In some embodiments, the step of generating an interrupt message based on each current interrupt number and the interrupt information table read includes: the binary codes corresponding to the target bits in the current interrupt numbers are obtained, the interrupt logic generation module inquires target interrupt position information matched with the binary codes in the interrupt information table, and corresponding interrupt information is constructed according to the target interrupt position information.
In some implementations, the target interrupt location information includes an interrupt vector and an interrupt address.
According to the interrupt management method, the interrupt information table is set to store the mapping relation between the interrupt numbers and the interrupt address information, once the interrupt logic generation module detects that the interrupt number buffer module is not empty, the interrupt numbers can be read from the interrupt number buffer module according to the interrupt number to serve as indexes, so that interrupt information can be quickly generated by inquiring the interrupt address information in the interrupt information table, a large amount of complicated calculation is avoided, the time delay generated by the interrupt information is greatly reduced, the problem of the interrupt bottleneck of a kernel is avoided, and the working efficiency of the kernel is improved.
In some embodiments, the step of determining, based on the interrupt identification logic, a current interrupt number corresponding to each interrupt request includes: and inputting each interrupt request into a lookup table of an interrupt identification logic module, inquiring a kernel code matched with each interrupt request in the lookup table, and taking a binary code of each kernel code as a corresponding current interrupt number.
According to the interrupt management method, the lookup table is arranged in the interrupt identification logic module to store the mapping relation between the interrupt request and the interrupt number, the interrupt number of the interrupt request corresponding to the kernel is quickly acquired in a table lookup mode, the interrupt request is not required to be sequentially detected through a gate circuit with multiple RTL (real time link) module stages, meanwhile, the conversion process of single hot codes and binary codes is avoided, the calculation process of interrupt codes is simplified, the interrupt requests sent by a plurality of kernel units at the same moment are identified in batches in one clock cycle, and the kernel delay is effectively reduced to avoid the kernel interrupt bottleneck.
In some embodiments, the step of determining the current number of interrupts sending the interrupt request based on the interrupt identification logic module comprises: all interrupt requests are transmitted to a serial carry adder within the interrupt identification logic to calculate the current interrupt number.
In some implementations, the serial carry adder isAnd a stage serial carry adder, wherein N is the total number of the kernel units.
According to the interrupt management method, the serial carry adder is utilized to rapidly determine the interrupt quantity in one clock period, so that the calculation time delay existing in sequential detection of the gate circuits of the multiple RTL module stages is avoided, and the effect of timing sequence convergence is achieved.
In some embodiments, the step of sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number includes: judging whether the number of the current interrupt numbers read by the interrupt logic generation module meets the current interrupt number or not after finishing reading one current interrupt number; if the number of the current interrupt numbers read by the interrupt logic generating module is not equal to the current interrupt number, continuing to read the interrupt numbers from the interrupt number buffer module by the interrupt logic generating module according to the buffer sequence, and returning to the step of judging whether the number of the current interrupt numbers read by the interrupt logic generating module meets the current interrupt number; if the number of the current interrupt numbers read by the interrupt logic generating module meets the current interrupt number, the interrupt logic generating module is stopped from reading the current interrupt numbers from the interrupt number caching module.
In some embodiments, an interrupt management method of the present invention further includes: if the number of the current interrupt numbers read by the interrupt logic generation module meets the current interrupt number, clearing the current interrupt number cached in the interrupt number caching module and corresponding to the current interrupt number; detecting whether the interrupt quantity buffer memory module is empty or not; if the interrupt number buffer module is detected not to be empty, triggering the interrupt logic generation module to read a second interrupt number corresponding to the next clock cycle from the interrupt number buffer module, and reading a second kernel code corresponding to the second interrupt number from the interrupt number buffer module, wherein the second kernel code is a kernel code corresponding to the next clock cycle.
According to the interrupt management method, the interrupt logic generation module can start to process the corresponding interrupt request only by detecting the non-empty state in the interrupt quantity buffer module, so that the mutual interference between the processing process of the interrupt identification logic module and the processing process of the interrupt logic generation module is reduced, and the calculation time delay of interrupt numbers and the generation time delay of interrupt messages are effectively reduced.
In some embodiments, an interrupt management method of the present invention further includes: and sequentially sending each interrupt message to the central processing unit to respond to the interrupt of the kernel corresponding to each interrupt position information.
In some embodiments, an interrupt management method of the present invention further includes: initializing an extended message signal interrupt vector table according to the kernel number information and the interrupt number information corresponding to each kernel in the kernel unit and the interrupt position information respectively distributed to each kernel by each software; and synchronizing all the kernel number information, the interrupt number information and the interrupt position information in the initialized extended message signal interrupt vector table to an interrupt information table.
In some embodiments, the step of receiving the number of interrupt requests sent by the core unit within the current clock cycle includes: detecting whether the value of a rising edge signal corresponding to an interrupt signal of each core in a core unit is 1 or not in the current clock period; if any rising edge signal is detected to be 1, determining that the shell unit receives an interrupt request sent by the core unit in the current clock cycle.
According to the interrupt management method, the interrupt efficiency of the cores can be guaranteed even under the condition of large number of the cores by consuming LUT resources, the interrupt information table is rapidly determined by synchronizing MSIX information in the BAR space, the accuracy of the mapping relation between the interrupt position information and the interrupt number is guaranteed, and the logic generation module in favor of directly generating interrupt information to enable the CPU to respond to the interrupt of the cores is avoided, so that the bottleneck of the interrupt of the cores is avoided.
In some embodiments, an interrupt management method of the present invention further includes: initializing output signals of the interrupt identification logic module, and sequentially assigning each current interrupt number to a target bit in the initialized output signals according to the sequence from low to high; and sending the assigned output signal to an interrupt number caching module through an interrupt identification logic module so as to cache all current interrupt numbers to the interrupt number caching module.
According to the interrupt management method, the calculation result of each period is cached, so that the interrupt request of the kernel can be ensured not to be lost by the shell under a large time scale.
In some embodiments, the output signal has a bit width ofWhere N is the total number of core units.
In some implementations, the target bit is lowBits, where N is the total number of core units.
In some embodiments, the buffer depth of the interrupt number buffer module and the buffer depth of the interrupt number buffer module are not less than N, where N is the total number of core units.
The interrupt management method of the invention, through increasing the buffer modules of the interrupt number and the buffer modules of the interrupt number, the processing process of the interrupt identification logic module and the processing process of the interrupt logic generation module in the shell can be respectively and independently carried out, namely, the interrupt identification logic module can start a new processing process without waiting for the completion of the ongoing processing process in the interrupt logic generation module, thereby effectively reducing the processing time delay of the interrupt identification logic process, avoiding a great deal of unnecessary waiting time between the interrupt identification logic module and the interrupt logic generation module, utilizing the serial carry adder to rapidly determine the interrupt number, and setting a lookup table in the interrupt identification logic module to store the mapping relation between the interrupt request and the interrupt number, the interrupt number of the corresponding kernel of the interrupt request is quickly obtained in a table look-up mode, a large number of complex calculations are avoided, the interrupt requests sent by a plurality of kernel units at the same time are identified in batches in one clock period, further, an interrupt information table is arranged to store the mapping relation between the interrupt number and interrupt address information, once the interrupt logic generation module detects that the interrupt number cache module is not empty, the interrupt number can be read from the interrupt number cache module as an index according to the interrupt number and used for quickly generating interrupt information in the interrupt information table for inquiring the interrupt address information, the time delay generated by the interrupt information is greatly reduced, the problem of the interrupt bottleneck of the kernel is avoided, the working efficiency of the kernel is improved, and higher application value is provided for the FPGA application scene with sensitive time delay.
It is noted that the above-described figures are only schematic illustrations of processes involved in a method according to an exemplary embodiment of the invention, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.
It should be understood that although described in a certain order, the steps are not necessarily performed sequentially in the order described. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, some steps of the present embodiment may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed alternately or alternately with at least a part of the steps or stages in other steps or other steps.
In some embodiments, referring to fig. 5, the present invention further provides an interrupt management system, where the interrupt management system specifically includes:
The identification module 110 is configured to determine, according to a plurality of interrupt requests sent by the kernel unit and received in a current clock cycle, a current interrupt number for sending the interrupt requests and a current interrupt number corresponding to each interrupt request based on the interrupt identification logic module;
the buffer module 120 is configured to buffer the current interrupt number and each current interrupt number to the interrupt number buffer module and the interrupt number buffer module respectively;
the reading module 130 is configured to, if the interrupt logic generating module detects that the interrupt number buffer module is not empty, read, by the interrupt logic generating module, the current interrupt number from the interrupt number buffer module, and sequentially read each current interrupt number from the interrupt number buffer module based on the current interrupt number;
and the generating module 140 is used for generating an interrupt message based on the read current interrupt numbers and the interrupt information table.
According to the interrupt management system, the number of the interrupt buffer modules and the number of the interrupt buffer modules are increased, so that the processing processes of the interrupt recognition logic module and the processing processes of the interrupt logic generation module in the shell can be respectively and independently performed, namely, the interrupt recognition logic module can start a new processing process without waiting for the completion of the ongoing processing processes in the interrupt logic generation module, the processing time delay of the interrupt recognition logic process is effectively reduced, a large number of unnecessary waiting time between the interrupt recognition logic module and the interrupt logic generation module is avoided, the number of the interrupt is rapidly determined by utilizing the serial carry adder, a lookup table is arranged in the interrupt recognition logic module to store the mapping relation between the interrupt request and the interrupt number, the interrupt number corresponding to the interrupt request is rapidly acquired in a lookup table mode, a large number of complex calculation is avoided, the interrupt request sent by a plurality of kernel units in a clock cycle is realized, the mapping relation between the interrupt number and the interrupt address information is further stored by setting the interrupt information table, once the interrupt logic generation module detects that the number of the interrupt buffer module is not empty, the number of the interrupt logic generation module is rapidly read from the number of the interrupt buffer module as the index information, the problem of the FPGA is solved, the problem of the time delay is greatly solved, the problem of using the time delay is greatly reduced, and the application is greatly reduced, the time delay is avoided, and the problem of a bottleneck is greatly is avoided, and the application is caused.
According to another aspect of the present invention, as shown in fig. 6, according to the same inventive concept, an embodiment of the present invention further provides a computer device 30, in which the computer device 30 includes a processor 310 and a memory 320, the memory 320 storing a computer program 321 executable on the processor, and the processor 310 executing the steps of the method as above.
The invention relates to a computer device, which is characterized in that a processing process of an interrupt identification logic module and a processing process of an interrupt logic generation module in a shell can be respectively and independently carried out by adding an interrupt number buffer module and an interrupt number buffer module, namely, the interrupt identification logic module can start a new processing process without waiting for the completion of the ongoing processing process in the interrupt logic generation module, thereby effectively reducing the processing delay of the interrupt identification logic process, avoiding a large number of unnecessary waiting time between the interrupt identification logic module and the interrupt logic generation module, rapidly determining the interrupt number by utilizing a serial carry adder, setting a lookup table in the interrupt identification logic module to store the mapping relation between interrupt requests and interrupt numbers, rapidly acquiring the interrupt numbers of the interrupt requests corresponding to the cores in a lookup table mode, avoiding a large number of complex calculation, realizing the batch identification of interrupt requests sent by a plurality of core units at the same moment in one clock cycle, further setting an interrupt information table to store the mapping relation between the interrupt numbers and interrupt address information, and once the interrupt logic generation module detects that the interrupt number buffer module is not empty, rapidly determining the interrupt number buffer module is used as the index information, and rapidly reading the interrupt number information from the interrupt number buffer module as index information, thereby avoiding the problem of generating a bottleneck message.
According to another aspect of the present invention, as shown in fig. 7, based on the same inventive concept, an embodiment of the present invention also provides a computer-readable storage medium 40, the computer-readable storage medium 40 storing a computer program 410 which when executed by a processor performs the above method.
Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (21)
1. An interrupt management method is characterized by being applied to a shell unit of a field programmable gate array device, wherein the shell unit comprises an interrupt identification logic module, an interrupt logic generation module, an interrupt number buffer module and an interrupt number buffer module, and the interrupt management method comprises the following steps:
determining the current interrupt number for sending the interrupt request and the current interrupt number corresponding to each interrupt request based on the interrupt identification logic module according to a plurality of interrupt requests sent by the kernel unit received in the current clock period;
respectively caching the current interrupt number and each current interrupt number to the interrupt number caching module and the interrupt number caching module;
if the interrupt number buffer module is detected to be not empty, reading the current interrupt number from the interrupt number buffer module through the interrupt logic generation module, and sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number;
and generating an interrupt message based on the read current interrupt numbers and the interrupt information table.
2. The interrupt management method of claim 1 wherein the step of reading, by the interrupt logic generation module, the current interrupt number from the interrupt number cache module and sequentially reading each of the current interrupt numbers from the interrupt number cache module based on the current interrupt number comprises:
Judging whether the interrupt logic generation module is in an idle state in the current clock period;
if the interrupt logic generation module is detected to be in an idle state in the current clock period, the current interrupt number is read from the interrupt number cache module through the interrupt logic generation module, and the current interrupt numbers corresponding to the current interrupt number are sequentially read from the interrupt number cache module.
3. The interrupt management method of claim 1, wherein the step of generating an interrupt message based on each of the current interrupt numbers and interrupt information tables read, comprises:
and acquiring binary codes corresponding to target bits in the current interrupt numbers, inquiring target interrupt position information matched with the binary codes in the interrupt information table through the interrupt logic generation module, and constructing corresponding interrupt information according to the target interrupt position information.
4. The interrupt management method of claim 2, further comprising:
if the interrupt logic generation module is detected to be in a non-idle state in the current clock cycle, acquiring a first interrupt number corresponding to the previous clock cycle from the interrupt number buffer module;
Judging whether the number of the first interrupt numbers corresponding to the last clock cycle read by the interrupt logic generation module meets the first interrupt number or not;
and if the number of the first interrupt numbers read by the interrupt logic generation module meets the first interrupt number, triggering the interrupt logic generation module to read the current interrupt number from the interrupt number cache module, and sequentially reading the current interrupt numbers corresponding to the current interrupt number from the interrupt number cache module.
5. The interrupt management method of claim 4, further comprising:
if the number of the first interrupt numbers read by the interrupt logic generation module does not meet the first interrupt number, continuing to read the first interrupt numbers from the interrupt number cache module by the interrupt logic generation module;
and generating an interrupt message based on the first interrupt number and the interrupt information table, and returning to the step of judging whether the number of the first interrupt numbers corresponding to the previous clock cycle read by the interrupt logic generation module meets the first interrupt number.
6. The interrupt management method of claim 1 wherein the step of determining a current interrupt number corresponding to each interrupt request based on the interrupt identification logic module comprises:
inputting each interrupt request into a lookup table of the interrupt identification logic module, inquiring a kernel code matched with each interrupt request in the lookup table, and taking a binary code of each kernel code as a corresponding current interrupt number.
7. The interrupt management method of claim 1, wherein the step of determining the current interrupt number to send the interrupt request based on the interrupt identification logic comprises:
all of the interrupt requests are transmitted to a serial carry adder within the interrupt identification logic module to calculate the current interrupt number.
8. The interrupt management method of claim 1 wherein the step of sequentially reading each of the current interrupt numbers from the interrupt number cache module based on the current interrupt number comprises:
judging whether the number of the current interrupt numbers read by the interrupt logic generation module meets the current interrupt number or not after finishing one current interrupt number per reading;
If the number of the current interrupt numbers read by the interrupt logic generating module does not meet the current interrupt number, continuing to read the interrupt numbers from the interrupt number caching module by the interrupt logic generating module according to the caching sequence, and returning to the step of judging whether the number of the current interrupt numbers read by the interrupt logic generating module meets the current interrupt number;
and stopping the interrupt logic generating module from reading the current interrupt number from the interrupt number caching module if the number of the current interrupt numbers read by the interrupt logic generating module meets the current interrupt number.
9. The interrupt management method of claim 8, further comprising:
if the number of the current interrupt numbers read by the interrupt logic generation module meets the current interrupt number, clearing the current interrupt number cached in the interrupt number caching module and the current interrupt number cached in the interrupt number caching module, wherein the number corresponds to the current interrupt number;
detecting whether the interrupt number cache module is empty or not;
If the interrupt number buffer module is detected not to be empty, triggering the interrupt logic generation module to read a second interrupt number corresponding to the next clock cycle from the interrupt number buffer module, and reading a second kernel code corresponding to the second interrupt number from the interrupt number buffer module, wherein the second kernel code is a kernel code corresponding to the next clock cycle.
10. The interrupt management method of claim 3, further comprising:
and sequentially sending each interrupt message to a central processing unit so as to respond to the interrupt of the kernel corresponding to each interrupt position information.
11. The interrupt management method of claim 1, further comprising:
initializing an extended message signal interrupt vector table according to the kernel number information, the interrupt number information and the interrupt position information which are respectively distributed to the kernels by each piece of software and correspond to each kernel in the kernel unit;
and synchronizing all the kernel number information, the interrupt number information and the interrupt position information in the initialized extended message signal interrupt vector table to the interrupt information table.
12. The interrupt management method of claim 1 wherein the step of receiving a number of interrupt requests sent by a core unit within the current clock cycle comprises:
detecting whether the value of a rising edge signal corresponding to an interrupt signal of each core in the core unit is 1 or not in the current clock cycle;
if any rising edge signal is detected to be 1, determining that an interrupt request sent by the kernel unit is received in the current clock cycle.
13. The interrupt management method of claim 6, further comprising:
initializing output signals of the interrupt identification logic module, and sequentially assigning each current interrupt number to a target bit in the initialized output signals according to the sequence from low to high;
and sending the assigned output signal to the interrupt number caching module through the interrupt identification logic module so as to cache all the current interrupt numbers to the interrupt number caching module.
14. The interrupt management method of claim 7 wherein the serial carry adder isAnd the stage serial carry adder, wherein N is the total number of cores in the core unit.
15. The interrupt management method of claim 13 wherein the bit width of the output signal isWherein N is the total number of cores in the core unit.
16. The interrupt management method of claim 3 wherein the target interrupt location information comprises an interrupt vector and an interrupt address.
17. According to the weightsThe interrupt management method of claim 3 wherein the target bit is lowAnd a bit, wherein N is the total number of cores in the core unit.
18. The interrupt management method according to claim 1, wherein the buffer depth of the interrupt number buffer module and the interrupt number buffer module is not less than N, where N is the total number of cores in the core unit.
19. An interrupt management system, comprising:
the identification module is used for determining the current interrupt number for sending the interrupt request and the current interrupt number corresponding to each interrupt request based on the interrupt identification logic module according to a plurality of interrupt requests sent by the kernel unit received in the current clock period;
the buffer module is used for buffering the current interrupt number and each current interrupt number to the interrupt number buffer module and the interrupt number buffer module respectively;
The reading module is used for reading the current interrupt number from the interrupt number buffer module through the interrupt logic generation module if the interrupt number buffer module is detected to be not empty, and sequentially reading each current interrupt number from the interrupt number buffer module based on the current interrupt number;
and the generation module is used for generating an interrupt message based on the read current interrupt numbers and the interrupt information table.
20. A computer device, comprising:
at least one processor; and
a memory storing a computer program executable on the processor, wherein the processor performs the steps of the method of any one of claims 1 to 18 when the program is executed.
21. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor performs the steps of the method according to any one of claims 1 to 18.
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| CN110427337A (en) * | 2019-09-29 | 2019-11-08 | 广东高云半导体科技股份有限公司 | Processor cores and its operation method based on field programmable gate array |
| CN114201276A (en) * | 2021-11-25 | 2022-03-18 | 天津津航技术物理研究所 | FIFO interrupt management based method |
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| CN110427337A (en) * | 2019-09-29 | 2019-11-08 | 广东高云半导体科技股份有限公司 | Processor cores and its operation method based on field programmable gate array |
| CN114201276A (en) * | 2021-11-25 | 2022-03-18 | 天津津航技术物理研究所 | FIFO interrupt management based method |
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