CN117454817B - Engineering processing method and device based on FPGA, electronic equipment and storage medium - Google Patents
Engineering processing method and device based on FPGA, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses an engineering processing method and device based on an FPGA, electronic equipment and a storage medium. The method comprises the following steps: reading a first type of peripheral functions and a redundant second type of peripheral functions which need to be called by the current project from a function table of the current project; fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function; and calling synplify to read the function file of the current project, and generating a netlist file of the current project by adopting the function file of the current project. The technical scheme provided by the embodiment of the invention is used for improving the generating efficiency of the netlist file.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to an engineering processing method, an engineering processing device, electronic equipment and a storage medium based on an FPGA.
Background
In recent years, with the rise of technologies in the fields of communication, digital signal processing, semiconductors, and the like, field-programmable gate arrays (Field Programmable Gate Array, FPGAs) have been increasingly used in a wide variety of fields and have played an extremely important role by virtue of their strong editability and excellent parallel processing capability.
After the corresponding logic codes are designed and relevant constraint conditions are added, the FPGA can synthesize the design files, and the main effect of the synthesis is to convert the micro electronic device (Integrated Circuit Chip, IC) design into a corresponding netlist, and the synthesized netlist quality is directly related to the stability of the function realized by the subsequent FPGA.
In the prior art, the problem of lack of the resource space of the FPGA is solved by optimizing a logic circuit of the design, setting reasonable time sequence constraint and the like, but the optimizing capability of the resource space is very limited in the above way. Therefore, the generating efficiency of the netlist file is limited to a certain extent.
Disclosure of Invention
The invention provides an engineering processing method, an engineering processing device, electronic equipment and a storage medium based on an FPGA (field programmable gate array) so as to improve the generating efficiency of netlist files.
In a first aspect, an embodiment of the present invention provides an engineering processing method based on FPGA, where the method includes:
reading a first type of peripheral functions and a redundant second type of peripheral functions which need to be called by the current project from a function table of the current project;
fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function;
and calling synplify to read the function file of the current project, and generating a netlist file of the current project by adopting the function file of the current project.
In a second aspect, an embodiment of the present invention further provides an engineering processing apparatus based on FPGA, where the apparatus includes:
the information reading module is used for reading the first type of peripheral functions and the redundant second type of peripheral functions required to be called by the current project from the function table of the current project;
the file fusion module is used for fusing the original function files of the first type of peripheral functions and the replacement files of the second type of peripheral functions to obtain the function files of the current engineering; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function;
and the file generation module is used for calling synplify to read the function file of the current project and generating the netlist file of the current project by adopting the function file of the current project.
In a third aspect, an embodiment of the present invention further provides an electronic device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform an FPGA-based engineering method of any of the embodiments of the present invention.
In a fourth aspect, embodiments of the present invention further provide a storage medium containing computer-executable instructions that, when executed by a computer processor, enable the computer processor to perform any one of the FPGA-based engineering processing methods provided by the embodiments of the present invention.
The embodiment of the invention reads the first type of peripheral functions and the redundant second type of peripheral functions which need to be called by the current project from the function table of the current project; fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function; and calling synplify to read the function file of the current project, and generating a netlist file of the current project by adopting the function file of the current project. The technical scheme provided by the embodiment of the invention is used for improving the generating efficiency of the netlist file.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an FPGA-based engineering process method according to a first embodiment of the present invention;
FIG. 2A is a flow chart of another method of engineering processing based on an FPGA according to a second embodiment of the present invention;
FIG. 2B is a flowchart illustrating the traversing of peripheral functions in a traversing function table according to a second embodiment of the present invention;
FIG. 2C is a flow chart of an alternative file use provided in accordance with a second embodiment of the present invention;
FIG. 2D is a flowchart of an FPGA-based integrated flow process according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an engineering processing device based on FPGA according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention, which is an engineering processing method based on FPGA.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In addition, it should be noted that, in the technical scheme of the invention, the related processes of collection, storage, use, processing, transmission, provision, disclosure and the like of the related data and the like all conform to the regulations of related laws and regulations and do not violate the popular regulations.
Example 1
Fig. 1 is a flowchart of an FPGA-based engineering processing method according to an embodiment of the present invention, where the method may be applied to a case of improving the generating efficiency of a generating netlist file, and the method may be performed by an FPGA-based engineering processing device, and the FPGA-based engineering processing device may be implemented in a hardware and/or software form, and the FPGA-based engineering processing device may be configured in an electronic device, and the electronic device may be a terminal device or a server, and the embodiment of the present invention is not limited thereto.
As shown in fig. 1, the engineering processing method based on the FPGA provided by the embodiment of the present invention specifically includes the following steps:
s110, reading the first type of peripheral functions and the redundant second type of peripheral functions which need to be called by the current project from a function table of the current project.
Specifically, in response to the actual demand of the demander, the first type of peripheral functions and the redundant second type of peripheral functions required to be called by the current project can be read from the function table of the current project. That is, at least one peripheral function of the current project can be read from the function table of the current project through the FPGA, and divided into a first type of peripheral function and a redundant second type of peripheral function to be called according to the requirements of the peripheral functions. It should be noted that, the function table of the current project includes at least one peripheral function, each peripheral function corresponds to a design file, that is, each peripheral function corresponds to a different design file. The first type of peripheral functions may be understood as peripheral functions required for the current project, and the redundant second type of peripheral functions may be understood as peripheral functions not required for the current project.
The first type of peripheral functions and the redundant second type of peripheral functions which are required to be called by the current project are read from the function table of the current project, so that follow-up related operations can be carried out according to different requirements on the peripheral functions.
S120, fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function.
Specifically, the original function file of the second type of peripheral function is deleted, the replacement file of the second type of peripheral function can be obtained, and the obtained replacement file of the second type of peripheral function is fused with the original function file of the first type of peripheral function, so that the function file of the current project can be obtained.
Particularly, because the second type peripheral functions are all function files which are not required to be called in the current engineering, the replacement files of the second type peripheral functions can be obtained by deleting the original function files of the second type peripheral functions. It can be understood that the replacement file of the second type of peripheral function obtained after deletion is a further simplified process for the original function file of the second type of peripheral function, and the processing rule of the deletion operation is not limited in the embodiment of the present invention.
The method comprises the steps of obtaining the function file of the current project by fusing the deleted replacement file of the second type of peripheral function with the original function file of the first type of peripheral function, so that the processing flow of the replacement file of the second type of peripheral function can be reduced, the waste of irrelevant computing resources is further reduced, and the subsequent reading and executing efficiency of the function file of the current project is further improved.
S130, calling synplify to read the function file of the current project, and generating a netlist file of the current project by adopting the function file of the current project.
Specifically, synplify may be specifically understood as a tool for generating a netlist file for an FPGA, and the function file of the current project may be read through synplify, so that the read function file of the current project may be used to generate the netlist file of the current project. That is, by using the related configuration instruction that has been set in advance in synplify, the function file of the current project can be read. The relevant configuration instruction includes, but is not limited to, configuration of a file path and at least one conventional configuration item, which may be, for example, a file format of a netlist, adding gate control settings and a file type.
By embedding synplify into FPGA and calling synplify to read the function file of the current project, and then generating the netlist file of the current project by adopting the function file of the current project, the generating efficiency of generating the netlist file can be accelerated. It should be noted that, the FPGA engineering processing method may be developed based on a shell scripting language, and the development scripting language selected by the FPGA engineering processing method is not limited in the embodiment of the present invention.
The embodiment of the invention reads the first type of peripheral functions and the redundant second type of peripheral functions which need to be called by the current project from the function table of the current project; fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function; and calling synplify to read the function file of the current project, and generating a netlist file of the current project by adopting the function file of the current project. The technical scheme provided by the embodiment of the invention is used for improving the generating efficiency of the netlist file.
Example two
Fig. 2A is a flowchart of another engineering processing method based on FPGA according to the second embodiment of the present invention, where the technical solution of the embodiment of the present invention is further optimized based on the foregoing alternative technical solutions.
Further, the method comprises the steps of reading a first type of peripheral functions and a redundant second type of peripheral functions required to be called by the current project from a function table of the current project, further refining the steps of traversing the function table of the current project, and reading names of all peripheral functions and state marks of the peripheral functions from the function table; the status flag is used or redundant; the peripheral functions with the use states are used as the first type of peripheral functions, and the peripheral functions with the redundant states are used as the second type of peripheral functions, so that the generating efficiency of the netlist file is improved. It should be noted that, in the present embodiment, parts not described in the present embodiment may refer to the related expressions of other embodiments, which are not described herein.
As shown in fig. 2A, another engineering processing method based on FPGA provided by the embodiment of the present invention; FIG. 2B is a flowchart illustrating the traversing of peripheral functions in a traversing function table according to a second embodiment of the present invention; FIG. 2C is a flow chart of an alternative file use provided in accordance with a second embodiment of the present invention; fig. 2D is a flowchart of an FPGA-based integrated flow process according to a second embodiment of the present invention, which specifically includes the following steps:
s210, traversing a function table of the current project, and reading names of all peripheral functions and state marks of the peripheral functions from the function table; the status flag is either used or redundant.
S220, taking the peripheral function with the use state as a first type of peripheral function, and taking the peripheral function with the redundant state as a second type of peripheral function.
In particular, the status flag may be specifically understood as being set according to the use requirement of the peripheral function in the current engineering, and thus, the status flag may be used or redundant. By traversing the function table of the current project, the names of the peripheral functions and the state marks of the peripheral functions can be read from the corresponding function table. According to the state flag, the peripheral functions with the use states can be used as the first type of peripheral functions, and the peripheral functions with the redundant states can be used as the second type of peripheral functions.
It should be noted that, when traversing the function table of the current project, the function table in the current project should be traversed one by one until the traversing ends all the function table information, and a flowchart for traversing each peripheral function in the function table is shown in fig. 2B. The names of the peripheral functions and the corresponding state marks of the peripheral functions can be obtained by traversing the function table of the current project, and the selected traversing order and traversing mode are not limited when the function table in the current project is traversed.
In particular, the method of traversing the function table of the current project to obtain the names of the peripheral functions and the status flag information of the peripheral functions in the function table, it can be understood that the names of the peripheral functions and the status flag information of the peripheral functions can be pre-constructed in the function table of the current project in a manual mode and stored in the function table of the current project.
The method comprises the steps of traversing a function table of a current project, reading names of peripheral functions and state marks of the peripheral functions from the function table, and subdividing the peripheral functions according to the state marks, namely, taking the peripheral functions with the state marks being used as first peripheral functions and the peripheral functions with the state marks being redundant as second peripheral functions, so that the subdivided first peripheral functions and second peripheral functions are processed according to different processing flows.
S230, fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function.
Specifically, the function file of the current project can be obtained by fusing the original function file of the first type of peripheral function and the replacement file of the second type of peripheral function, and it is to be noted that the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function. That is, the replacement file of the second type of peripheral function has simplified processing of the processing logic and processing flow of each peripheral function compared to the original function file of the second type of peripheral function.
Optionally, the interface in the replacement file of the second type of peripheral function is compatible with the interface standard of the original function file of the second type of peripheral function.
Specifically, the interface adopted in the replacement file of the second type peripheral function is compatible with the interface of the original function file of the second type peripheral function, that is, the file path of the corresponding replacement file of the second type peripheral function is constructed according to the interface of the original function file of the second type peripheral function, so that the replacement file of the second type peripheral function is conveniently read, and the stability of the FPGA in realizing the related function is ensured.
Optionally, the replacement file of the second type of peripheral function is constructed in the following manner: based on the interface standard of the original function file of the second type of peripheral function, constructing output data for the replacement file of the second type of peripheral function; fixing the constructed output data; deleting processing logic of input data from the original function file of the second type of peripheral function to obtain an intermediate function file; and adopting the constructed output data as the output of the intermediate function file to obtain a replacement file of the second type of peripheral function.
Specifically, the replacement file of the second type of peripheral function may be constructed in such a manner that output data is constructed for the replacement file of the second type of peripheral function based on the interface standard of the original function file of the second type of peripheral function, wherein the constructed output data may be a fixed value. For example, if the original output data is data content information, the corresponding constructed output data may be assigned 0; if the original output data is control signal information, the corresponding constructed output data may be set to be disabled, that is, the control signal is not executed, which is not limited in the embodiment of the present invention.
By deleting the processing logic of the input data from the original function file of the second type of peripheral function, an intermediate function file can be obtained, and the constructed output data is used as the output of the intermediate function file, so that a replacement file of the second type of peripheral function can be obtained, as shown in fig. 2C. It should be noted that, no additional setting is performed on the input data, only the output data is subjected to forced default output, that is, the processing logic of the input data in the original function file of the second type peripheral function is deleted, and the output data with a fixed value, which is constructed in advance, is used as the output of the intermediate function file, so as to obtain the replacement file of the second type peripheral function.
Deleting the original function file of the second type of peripheral function, and fusing the obtained replacement file of the second type of peripheral function with the original function file of the first type of peripheral function to obtain the function file of the current project. The interface in the replacement file of the second type of peripheral function is compatible with the interface standard of the original function file of the second type of peripheral function, so that the replacement file of the second type of peripheral function can be interacted with other function files normally. According to the interface standard of the original function file of the second type peripheral function, fixed output data is built for the replacement file of the second type peripheral function, processing logic for the input data is deleted from the original function file of the second type peripheral function, an intermediate function file can be obtained, the built output data is used as the output of the intermediate function file, and the replacement file of the second type peripheral function can be finally obtained, so that the generating efficiency of the netlist file is improved.
S240, calling synplify to read the function file of the current project, and generating the netlist file of the current project by adopting the function file of the current project.
Specifically, by calling synplify to read the function file of the current project, the function file of the current project can be adopted to generate the netlist file of the current project.
Optionally, after generating the netlist file of the current project by using the function file of the current project, the method further includes: calling Vivado to construct layout and wiring for the current project by adopting the function file of the current project; wherein Vivado is configured as a post-synthesis project mode.
Specifically, vivado can be specifically understood as a tool for performing layout and wiring operation on the FPGA, and after generating a netlist file of the current project, the Vivado can be also called to use a functional file of the current project to construct layout and wiring for the current project, where the Vivado can be configured into a post-synthesis project mode. In particular, the Post-synthesis project mode may be a Post-Synthesis Project mode, which is characterized in that design files are not processed, and thus, repeated generation of netlist files can be avoided, that is, by setting Vivado in the Post-Synthesis Project mode, layout and wiring processing operations can be performed according to the obtained netlist files, and thus, corresponding layout and wiring can be obtained.
In an implementation of an alternative embodiment, an FPGA is illustratively developed using a shell script language, such as a flowchart of an FPGA-based integrated flow process shown in fig. 2D. The FPGA may be used to generate integrated circuits and netlist files and place and route may be generated by invoking the synplify tool and the Vivado tool.
At least one peripheral function file is included in the FPGA, each peripheral function file being associated with a design file. The FPGA reads the function table of the current project, determines the names of the peripheral functions and the state mark information representing the peripheral functions as available or to be removed in an analytic mode, and can acquire the file paths of the corresponding files according to the related information of the peripheral functions obtained by analysis. When the function table of the current project is analyzed, the pre-built peripheral functions and the state flag information of the peripheral functions in the current project should be traversed one by one, so that the peripheral functions are divided into available peripheral devices and peripheral devices to be removed according to the state flag information of the peripheral functions.
In particular, for the peripheral function to be removed, the file path of the peripheral function to be removed is replaced according to the path of the corresponding replacement file constructed in advance, and the difference between the two is that the internal logic of the peripheral function to be removed is subjected to simplified processing, that is, the processing logic is deleted, and only the output data is subjected to immobilization processing, that is, the output result of the original output data as the data content is forcedly assigned to 0, and the output result of the original output data as the control signal is forcedly set to be disabled, that is, the control operation is not executed. It should be noted that, the file path of the peripheral function to be removed is compatible with the interface standard of the path of the pre-constructed replacement file, so as to facilitate reading the path of the corresponding replacement file, thereby ensuring the stability of the FPGA when implementing the related function. In summary, when the FPGA reads the function table of the current project, the FPGA reads the peripheral function to be called normally, and for the peripheral function to be removed, the replacement file of the simplified processing logic corresponding to the peripheral function to be removed can be read, so that the reading and processing of irrelevant hardware resources and logic resources are reduced under the condition that normal interaction with other peripheral files is not affected, and the generating efficiency of the netlist file is improved.
In addition, vivado is used as a tool capable of reading the function file and the netlist file to perform layout and wiring operation, if the Vivado is set to read the function file, the function file can be regenerated according to the read function file, so that in order to avoid repeatedly reading the function file to generate the netlist file, vivado can be configured in a Post-Synthesis Project mode, the mode is set to only read the netlist file by Vivado, and then the layout and wiring operation is performed according to the read netlist file, and corresponding layout and wiring are generated.
The embodiment of the invention can read the names of the peripheral functions and the state marks of the peripheral functions from the corresponding function table by traversing the function table of the current project. According to the state flag, the peripheral functions with the use states can be used as the first type of peripheral functions, and the peripheral functions with the redundant states can be used as the second type of peripheral functions. Deleting the original function file of the second type of peripheral function, and fusing the obtained replacement file of the second type of peripheral function with the original function file of the first type of peripheral function to obtain the function file of the current project. The interface in the replacement file of the second type of peripheral function is compatible with the interface standard of the original function file of the second type of peripheral function, so that the replacement file of the second type of peripheral function can be interacted with other function files normally. According to the interface standard of the original function file of the second type peripheral function, fixed output data is built for the replacement file of the second type peripheral function, processing logic for the input data is deleted from the original function file of the second type peripheral function, an intermediate function file can be obtained, the built output data is used as the output of the intermediate function file, and the replacement file of the second type peripheral function can be finally obtained, so that the generating efficiency of the netlist file is improved. Calling synplify to read a function file of the current project, generating a netlist file of the current project by adopting the function file of the current project, and calling Vivado to construct layout and wiring for the current project by adopting the function file of the current project; wherein Vivado is configured as a post-synthesis project mode. The technical scheme provided by the embodiment of the invention is used for improving the generating efficiency of the netlist file.
Example III
Fig. 3 is a schematic structural diagram of an engineering processing device based on FPGA according to a third embodiment of the present invention. As shown in fig. 3, the engineering processing device based on the FPGA includes: an information reading module 310, a file fusion module 320, and a file generation module 330. Wherein:
an information reading module 310, configured to read, from a function table of a current project, a first type of peripheral function and a redundant second type of peripheral function that need to be called by the current project;
the file fusion module 320 is configured to fuse an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function;
the file generating module 330 is configured to call synplify to read a function file of the current project, and generate a netlist file of the current project using the function file of the current project.
The embodiment of the invention reads the first type of peripheral functions and the redundant second type of peripheral functions which need to be called by the current project from the function table of the current project; fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function; and calling synplify to read the function file of the current project, and generating a netlist file of the current project by adopting the function file of the current project. The technical scheme provided by the embodiment of the invention is used for improving the generating efficiency of the netlist file.
Optionally, the file fusion module 320 includes:
and the interface compatible unit is used for enabling interfaces in the replacement files of the second type of peripheral functions to be compatible with interface standards of original function files of the second type of peripheral functions.
Optionally, the file fusion module 320 includes a file construction unit, including:
an output data construction subunit, configured to construct output data for a replacement file of the second type peripheral function based on an interface standard of an original function file of the second type peripheral function; fixing the constructed output data;
an intermediate file obtaining subunit, configured to delete processing logic for input data from the original function file of the second type of peripheral function, to obtain an intermediate function file;
and the replacing file obtaining subunit is used for obtaining the replacing file of the second type of peripheral function by adopting the constructed output data as the output of the intermediate function file.
Optionally, the information reading module 310 includes:
the function table traversing unit is used for traversing the function table of the current project, and reading the names of the peripheral functions and the state marks of the peripheral functions from the function table; the status flag is used or redundant;
the peripheral function classification unit is used for taking the peripheral function with the use state as a first type of peripheral function and taking the peripheral function with the redundant state as a second type of peripheral function.
Optionally, the device further comprises an engineering wiring module, specifically configured to:
calling Vivado to construct layout and wiring for the current project by adopting the function file of the current project; wherein Vivado is configured as a post-synthesis project mode.
The FPGA-based engineering processing device provided by the embodiment of the invention can execute the FPGA-based engineering processing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example IV
Fig. 4 shows a schematic diagram of an electronic device 400 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the electronic device 400 includes at least one processor 410, and a memory, such as a Read Only Memory (ROM) 420, a Random Access Memory (RAM) 430, etc., communicatively coupled to the at least one processor 410, wherein the memory stores computer programs executable by the at least one processor, and the processor 410 may perform various suitable actions and processes according to the computer programs stored in the Read Only Memory (ROM) 420 or the computer programs loaded from the storage unit 480 into the Random Access Memory (RAM) 430. In (RAM) 430, various programs and data required for the operation of electronic device 400 may also be stored. The processors 410, (RAM) 420, and (RAM) 430 are connected to each other by a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.
Various components in electronic device 400 are connected to I/O interface 450, including: an input unit 460 such as a keyboard, a mouse, etc.; an output unit 470 such as various types of displays, speakers, and the like; a storage unit 480 such as a magnetic disk, an optical disk, or the like; and a communication unit 490, such as a network card, modem, wireless communication transceiver, etc. The communication unit 490 allows the electronic device 400 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks.
Processor 410 can be a variety of general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of processor 410 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 410 performs the various methods and processes described above, such as an FPGA-based engineering process.
In some embodiments, an FPGA-based engineering processing method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 480. In some embodiments, part or all of the computer program may be loaded and/or installed onto electronic device 400 via (RAM) 420 and/or communication unit 490. When the computer program is loaded into (RAM) 430 and executed by processor 410, one or more steps of an FPGA-based engineering process described above may be performed. Alternatively, in other embodiments, processor 410 may be configured to perform an FPGA-based engineering process in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. An engineering processing method based on an FPGA, which is characterized by comprising the following steps:
reading a first type of peripheral functions and a redundant second type of peripheral functions which need to be called by the current project from a function table of the current project; the redundant second type of peripheral functions are peripheral functions which do not need to be called in the current engineering;
fusing an original function file of the first type of peripheral function and a replacement file of the second type of peripheral function to obtain a function file of the current project; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function;
and calling synplify to read the function file of the current project, and generating a netlist file of the current project by adopting the function file of the current project.
2. The method of claim 1, wherein the interface in the alternate file of the second type of peripheral function is compatible with the interface standard of the original function file of the second type of peripheral function.
3. A method according to claim 1 or 2, characterized in that the replacement file for the second type of peripheral function is constructed by:
based on the interface standard of the original function file of the second type of peripheral function, constructing output data for the replacement file of the second type of peripheral function; fixing the constructed output data;
deleting processing logic of input data from the original function file of the second type of peripheral function to obtain an intermediate function file;
and adopting the constructed output data as the output of the intermediate function file to obtain a replacement file of the second type of peripheral function.
4. The method of claim 1, wherein reading the first type of peripheral function and the redundant second type of peripheral function that the current project needs to call from the function table of the current project comprises:
traversing a function table of the current project, and reading names of all peripheral functions and state marks of the peripheral functions from the function table; the status flag is used or redundant;
the peripheral functions with the use states are used as the first type of peripheral functions, and the peripheral functions with the redundant states are used as the second type of peripheral functions.
5. The method of claim 1, after generating the netlist file of the current project using the function file of the current project, further comprising:
calling Vivado to construct layout and wiring for the current project by adopting the function file of the current project; wherein the Vivado is in post-synthesis project mode.
6. An FPGA-based engineering processing apparatus, comprising:
the information reading module is used for reading the first type of peripheral functions and the redundant second type of peripheral functions required to be called by the current project from the function table of the current project; the redundant second type of peripheral functions are peripheral functions which do not need to be called in the current engineering;
the file fusion module is used for fusing the original function files of the first type of peripheral functions and the replacement files of the second type of peripheral functions to obtain the function files of the current engineering; wherein, the replacement file of the second type of peripheral function is obtained by deleting the original function file of the second type of peripheral function;
and the file generation module is used for calling synplify to read the function file of the current project and generating the netlist file of the current project by adopting the function file of the current project.
7. The apparatus of claim 6, wherein the information reading module comprises:
the function table traversing unit is used for traversing the function table of the current project, and reading the names of the peripheral functions and the state marks of the peripheral functions from the function table; the status flag is used or redundant;
the peripheral function classification unit is used for taking the peripheral function with the use state as a first type of peripheral function and taking the peripheral function with the redundant state as a second type of peripheral function.
8. The apparatus of claim 6, further comprising an engineering wiring module;
the engineering wiring module is specifically used for calling Vivado to construct layout wiring for the current engineering by adopting the function file of the current engineering; wherein Vivado is configured as a post-synthesis project mode.
9. An electronic device, comprising:
one or more processors;
a memory for storing one or more programs;
when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement an FPGA-based engineering method of any of claims 1-5.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements an FPGA-based engineering method as claimed in any of claims 1-5.
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