CN117438330B - Planar indentation-based wafer level package RDL rewiring layer defect detection method - Google Patents

Planar indentation-based wafer level package RDL rewiring layer defect detection method Download PDF

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CN117438330B
CN117438330B CN202311744118.0A CN202311744118A CN117438330B CN 117438330 B CN117438330 B CN 117438330B CN 202311744118 A CN202311744118 A CN 202311744118A CN 117438330 B CN117438330 B CN 117438330B
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defect
point
pressing
points
depth
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CN117438330A (en
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王诗兆
习杨
田志强
李丽丹
张适
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Wuchuang Xinyan Technology Wuhan Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing
    • G06F30/3953Routing detailed
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00Details relating to the application field
    • G06F2113/18Chip packaging

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Engineering & Computer Science (AREA)
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Abstract

A wafer level package RDL rewiring layer defect detection method based on planar indentation comprises the following steps: planning an indentation pressing path according to the rewiring layer detection target path to press, and measuring concave data; processing the concave data to obtain a concave degree chart; constructing a defect identification and classification model based on the concave degree chart after normalization treatment; performing defect detection and feedback adjustment on setting parameters based on the defect identification and classification model; and displaying the defect result of the obtained sample. The invention utilizes the RDL layer surface characterization mode to judge and position the internal metal wiring defect condition, effectively solves the problems of time and labor waste, low efficiency, incapability of accurately positioning and the like in the traditional scheme, enables the detection of the internal defects in the RDL layer to be possible in a large scale, and provides better guarantee for advanced three-dimensional packaging.

Description

Planar indentation-based wafer level package RDL rewiring layer defect detection method
Technical Field
The embodiment relates to the field of semiconductor process defect detection, in particular to a defect detection method for a re-wiring layer of a wafer level package RDL based on planar indentation.
Background
RDL technology (Redistributed Layer technology) is an advanced packaging technology that is widely used in Integrated Circuit (IC) design. It is used to create a multi-layered metal wire network between the chip and the package to achieve high density connections and signal transmission. RDL technology is commonly applied to three-dimensional integrated circuits (3D ICs) and System In Package (SiP) to help solve routing and connection problems in high performance chips. With the continuous upgrade of advanced package sizes, the requirements for circuits in wafer level packages are also increasing, and low cost, high performance, high density RDL will also be one of the key technologies for 2.5D IC/3D IC integration.
RDL is to change the contact position of the originally designed IC circuit via the wafer level metal routing process and bump process, so that the IC can be adapted to different package types. A wafer-level metal wiring process comprises the steps of coating an insulating protective layer on an IC, defining a new wire pattern by an exposure and development mode, depositing a Ti barrier layer and a copper seed layer by sputtering, electroplating copper on the exposed Ti/Cu layer for increasing the thickness of the copper layer to ensure the conductivity of a chip circuit, stripping photoresist and etching the Ti/Cu seed layer, and completing RDL manufacture. Repeating this step may be for any or more RDL lines. Although the RDL process is mature, defect problems will inevitably occur in the manufacturing process, and the processes of copper electroplating, insulating layer coating, etching and the like may cause defects, oxidization, interface mismatch and the like of the circuit, and the defects may cause problems of RDL circuit, signal interruption, electrical connection failure and the like of the packaging circuit, and finally, the quality and yield of the chip are reduced.
RDL is a common form of defect due to its special manufacturing process, resulting in a defect-major presence area concentrated inside the device, metal line void defects. The RDL quality detection methods commonly used at present can be simply summarized as destructive detection and non-destructive detection. The cross section of the rewiring layer of the wafer level package is obtained mainly by slicing, and then is observed by a Scanning Electron Microscope (SEM); and the product after RDL processing is electrified and detected mainly by an electric and thermal test mode, and whether partial contact failure or failure occurs in the circuit is judged. Destructive detection is often used for researching a small amount of samples, and the samples can be destroyed in actual production, so that the cost is high and the time consumption is long; non-destructive detection is commonly used in industrial production, but the method is mainly used for judging whether a circuit works normally, and often cannot judge the specific position and defect condition of defect generation, so that the process cannot be improved pertinently. In summary, the current detection method cannot quickly, simply and accurately judge the defect of the RDL rewiring layer.
Disclosure of Invention
In view of the foregoing, the present embodiment has been proposed to provide a wafer level package RDL rewiring layer defect detection method based on planar indentation that overcomes or at least partially solves the foregoing problems.
In order to solve the technical problems, the embodiment of the application discloses the following technical scheme:
a wafer level package RDL rewiring layer defect detection method based on planar indentation comprises the following steps:
s100, planning an indentation pressing path according to a rewiring layer detection target path to press, and measuring concave data;
s200, processing the concave data to obtain a concave degree chart;
s300, carrying out normalization processing on the concave degree chart;
s400, constructing a defect identification and classification model based on the concave degree chart after normalization treatment;
s500, performing defect detection and feedback adjustment on setting parameters based on the defect identification and classification model;
and S600, displaying the obtained sample defect result.
Further, in S100, first, target path response data needs to be acquired, where the response data includes at least: metal wiring design of the region to be tested, so the design data is used for planning a pressing path; and the data of the section diagram is used for providing variable parameters for subsequent normalized data processing work and is also used for final defect calibration. Further, in S100, the micron-level probe is used to press the surface of the RDL layer, all the pressure heads are of the same specification, and the load is controlled by using the load control loading mode, so that the same load is used to control the variables during each pressing, and the loading and unloading time and the loading and unloading rate are ensured to be the same; after pressing, the loaded high-precision optical measuring instrument is used for measuring the pit depth after unloading, and corresponding numbers and measured pit data are recorded.
Further, in S200, a number-recess depth scattergram is constructed and connected to obtain a line graph by the corresponding number recorded in S100 and the measured recess data; and meanwhile, the vertical data of the path to be detected in the step S100 is collected, and the data corresponding to the mark points is output, so that preparation is made for subsequent data normalization processing.
Further, in S300, the normalization processing is performed on the dishing degree chart, and the specific method includes: and measuring metal wire conditions with different depths through a sample experiment in advance, constructing a metal wire depth-dent depth statistical database, obtaining the dent depth of each pressing point on the target path in an ideal state according to the interface conditions of the target path collected in the step S100, and completing the normalization processing of data through the ratio of the actual measured value to the statistical value.
Further, in S400, a defect recognition and classification model is constructed, and the specific method includes:
s401, setting safety position judgment parameters,/>Indicating the error allowed by the measurement, values within this range are considered normal degrees of dishing; using the difference between the maximum value and the minimum value in the database as a safety position judgment parameter +.>
S402, judging a safety point; using the median in the database as the reference value for the measurement dataDepth data is +.>Is recognized by all points of (1)Is a safe point;
s403, distinguishing defect points; the parameters of the defect reaction in the RDL layer in the data chart specifically include: recess depth, recess width, and recess rate of change; wherein the depth and width of the recess reflect the size of the defect, and the rate of change of the recess is reflected by whether the defect has a mutation or not; the three types of parameters are represented using specific data: difference between the depth of the recess and the reference value G0Recess depth and reference value +.>The difference continuously exceeds +.>The number of points>Maximum slope of concave point
Further, for the recess depth and the reference valueDifference size +.>Use +.>Obtained when->When this point is defined as a security point; when->The point is defined as the point where the defect is to be located if the difference between two subsequent pressing points falls to +.>Then it is recognized thatIf the point is an error point, otherwise, the defect is considered to exist; when->In this case, the point is defined as a defective point, and the defect level is defined by +.>Depending on the actual requirement, the defect judgment parameters Di (i=2, 3, … …) are preset and are calculated by +.>The defect degree of the point is judged within a certain range.
Further, for the recess widthIn such a way that in the difference +.>In the calculation process, when the calculated difference value of a certain point is +.>Is greater than->Marking the defect as a temporary starting point; if the pressing point after this point still satisfies +.>Determining that there is a defect, continuing to calculate the difference value until +.>This point is the defect end point and is calculated again forward at the temporary defect start point until +.>The point is a defect start point, and the number of pressing points before the defect start point and the defect end point is calculated to obtain the recess width +.>The method comprises the steps of carrying out a first treatment on the surface of the If the depression depth difference of the pressing point behind the point is reduced to +.>In, the point is recorded as a suspicious point, and the verification is performed again in S500.
Further, the maximum slope for the dip pointAfter the defect range is determined, calculating the slopes of all points in the corresponding defect peak through a peak fitting function, and comparing to obtain the parameter value, wherein the parameter value represents the maximum change rate of the defect degree of the corresponding defect, so that the change condition of the defect is described.
Further, in S500, based on the defect recognition and classification model, performing defect detection and performing feedback adjustment on the setting parameters; the specific method comprises the following steps: re-measuring the suspicious point and the area occupied by the three pressing points before and after, adding two measuring points in the two adjacent points, re-inputting the measured data into the model to judge, if the points are other than the pointStill less than->The point is considered to be the error point if there are other points greater than + ->The defect is considered to exist here, and the defect condition is judged by the model.
The beneficial effects of the above technical scheme provided by the embodiment at least include:
the embodiment discloses a wafer level package RDL rewiring layer defect detection method based on planar indentation, which comprises the following steps: planning an indentation pressing path according to the rewiring layer detection target path to press, and measuring concave data; processing the concave data to obtain a concave degree chart; constructing a defect identification and classification model based on the concave degree chart after normalization treatment; performing defect detection and feedback adjustment on setting parameters based on the defect identification and classification model; and displaying the defect result of the obtained sample.
In the embodiment, the internal defects of the RDL rewiring layer correspond to the surface mechanical response, the cavity defect condition in the circuit can be obtained by measuring the surface pressing depression degree, and the simple and nondestructive detection of the internal defects of the RDL is realized; according to the embodiment, the full-automatic intelligent identification and classification of the defects are realized by constructing the concave depth curve data processing model, and the high-efficiency and large-batch detection and judgment of the internal defects are realized; the embodiment can realize accurate positioning of internal defects in the RDL layer, simplify the positioning process and provide convenience for process optimization. In the embodiment, the internal metal wiring defect condition is judged and positioned by utilizing the RDL layer surface characterization mode, so that the problems that the traditional scheme is time-consuming and labor-consuming, low in efficiency, incapable of positioning accurately and the like are effectively solved, the detection of the internal defects in the RDL layer on a large scale is possible, and a better guarantee is provided for advanced three-dimensional packaging.
The technical scheme of the present embodiment is described in further detail below through the accompanying drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification, illustrate and explain the embodiments, and do not limit the embodiments. In the drawings:
fig. 1 is a flowchart of a method for detecting a defect of a re-wiring layer of a wafer level package RDL based on planar indentation in embodiment 1;
FIG. 2 is a top view of the RDL rewiring layer in embodiment 1;
FIG. 3 is a diagram showing a routing path and a cross-section of a RDL rewiring layer according to embodiment 1;
FIG. 4 is a schematic diagram showing the RDL rewiring layer pressing process in embodiment 1;
FIG. 5 is a line graph of the number after detection versus the depth of defect in example 1;
FIG. 6 is a line graph showing the number after normalization treatment and the test pit depth scatter after connection in example 1;
fig. 7 is a peak fitting diagram of fig. 6.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In order to solve the problems in the prior art, the embodiment of the invention provides a wafer level package RDL rewiring layer defect detection method based on planar indentation.
Examples
The embodiment discloses a method for detecting defect of a rewiring layer of a wafer level package RDL based on planar indentation, as shown in fig. 1, comprising the following steps:
s100, planning an indentation pressing path according to a rewiring layer detection target path to press, and measuring concave data; in S100 of the present embodiment, first, target path response data needs to be acquired, where the response data includes at least: the metal wiring design diagram of the region to be tested, wherein the design diagram data are used for planning a pressing path, and a specific schematic diagram is shown in fig. 2; and the data of the section diagram is used for providing variable parameters for subsequent normalized data processing work and is also used for final defect calibration, and the section diagram is particularly shown in fig. 3. The data can be prepared in advance before the detection is started, and for the same batch of products, the data are all parameters given in the design process and are easy to obtain.
In S100 of this embodiment, the micron-scale probe is used to press the surface of the RDL layer, all the pressure heads use the same specification, and use the load control loading mode, so as to ensure that the same load is used to control the variables during each pressing, and ensure that the loading and unloading time and the loading and unloading rate are the same; after pressing, the loaded high-precision optical measuring instrument is used for measuring the pit depth after unloading, and the corresponding number and the measured pit depth are recorded.
In particular, there are various ways to achieve surface pressing of RDL layers, but considering that the width of RDL wiring varies from several micrometers to tens of micrometers, it is pressed using micrometer-sized probes, in a specific form as shown in fig. 4. In order to control the same variable, a 100nm pressure head is selected for all pressure heads, a load control loading mode is used, the same load is used for controlling the variable when each pressure is pressed, and the loading and unloading time and the loading and unloading speed are ensured to be the same. In order to ensure that the pressing has a certain depth, the maximum load is 10mN, the holding time is 10s, and the measuring temperature is room temperature. After pressing, the loaded high-precision optical measuring instrument is used for measuring the pit depth after unloading, and corresponding numbers and measurement data are recorded.
Specifically, in the pressing process, firstly, the pressing point positions are arranged according to the planned path of the area to be measured, so as to avoid errors caused by boundary effects between adjacent pressing points, the interval between each indentation is controlled to be a fixed value of 0.5 μm, and the pressing points are numbered sequentially according to the pressing path, so that the subsequent data processing is facilitated.
S200, processing the concave data to obtain a concave degree chart, and in S200 of the embodiment, constructing a number-concave depth scatter diagram and connecting the scatter diagrams to obtain a line diagram through corresponding numbers recorded in S100 and measured concave data; and meanwhile, the vertical data of the path to be detected in the step S100 is collected, and the data corresponding to the mark points is output, so that preparation is made for subsequent data normalization processing.
Specifically, in the process of S100 pressing and measuring, since the depth of the RDL rewiring layer metal interconnection line is not uniform, and the metal is greatly different from the elastic model of the surrounding potting material, a shallower metal interconnection line can obtain a smaller pressing depression degree, a deeper metal interconnection line can obtain a larger pressing depression degree, and a pit with a void defect area in the vertical direction can show a deeper depression degree on the basis of the original pit. According to this principle, the test pit depth measured by S100The degrees can be processed as a number-test recess depth scatter plot and the scatter plots can be connected to obtain a line plot, as shown in FIG. 5, which data is recorded as
S300, carrying out normalization processing on the concave degree chart; in S300 of this embodiment, the normalization processing is performed on the dishing degree chart, and the specific method includes: and measuring metal wire conditions with different depths by carrying out an indentation detection experiment of a qualified sample in advance to obtain recess depths under ideal conditions corresponding to the different metal wire depths, defining the recess depths under the ideal conditions as ideal recess depths, and constructing a metal wire depth-ideal recess depth statistical database.
According to the target path sectional diagram collected in the S100, the metal line depth of each pressing point theoretical design on the target path is obtained, and then the ideal depression depth corresponding to each pressing point is obtained based on the database, and the normalization processing of the data is completed by the ratio of the test depression depth of each pressing point to the ideal depression depth average value corresponding to each pressing point in the database, namely, the normalization processing is performed on the data of each pressing point by adopting the following formula:
wherein,normalization parameters for the compression points; />A test depression depth for the pressing point; />And the ideal concave depth corresponding to the pressing point.
Specifically, since the distribution of the metal lines of the RDL rewiring layer is not completely flat, but there is a vertical height change, the height change can cause the thickness of the underfill above the metal to be different, in the pressing process, the metal lines are mainly elastically deformed due to the larger elastic modulus, the original appearance can be restored after being deformed, the underfill is mainly plastically deformed, and the thickness of the underfill is not far greater than the pressing depth, so that the plastic deformation is influenced by the thickness of the underfill, and after the underfill is pressed, the underfill with larger thickness has a larger concave depth. Therefore, if a gradient in the vertical direction exists in the metal line, it is impossible to determine whether the pit is caused by the position or the void by directly using the test data, and therefore normalization processing is required.
Two materials, namely metal wires and underfill, mainly exist in the RDL wiring layer designed in the embodiment, and the metal wires with different depths are required to be measured due to non-linear plastic deformation, so that the height is finally obtainedAnd (3) a concave depth change scatter diagram, and obtaining a smooth curve through curve fitting of the scatter diagram. The above height->The pit depth variation data is a sort of material database that can be preformed in advance and is generic for the same material, different routes, a process that is very easy to perform for a large number of experiments. The same approach can also be used for multi-wiring layers.
In the data collection of S100, we acquire the sectional view of RDL rewiring layer in advance, so that the wire depth of theoretical design for the measurement point is known, through the obtained wire depth-ideal defect depth curve, we can acquire the ideal depression depth value of the corresponding numbered pressing point, by dividing the test depression depth by the ideal depression depth, we can normalize the data, and obtain a straight curve, which is convenient for subsequent parameter processing. The number-test dishing depth line graph shown in FIG. 5 is normalized as shown in FIG. 6, and the peak fitting to FIG. 6 is performed as shown in FIG. 7, and the data is recorded as
S400, constructing a defect identification and classification model based on the concave degree chart after normalization treatment; because the normalized data still has certain fluctuation and the defect degree cannot be intuitively obtained, the analysis of a large amount of data needs to consume a large amount of time of professionals, and the analysis does not meet the industrial production requirement, and therefore the normalized data needs to be processed and output to obtain a mature model.
In S400 of the present embodiment, a defect recognition and classification model is constructed, and the specific method includes:
s401, setting safety position judgment parameters,/>Indicating the error allowed by the measurement, values within this range are considered normal degrees of dishing; using the difference between the maximum value and the minimum value in the database as a safety position judgment parameter +.>
S402, judging a safety point; using the median in the database as the reference value for the measurement dataDepth data is +.>Is considered a safe point;
s403, distinguishing defect points; the parameters of the defect reaction in the RDL layer in the data chart specifically include: recess depth, recess width, and recess rate of change; wherein the depth and width of the recess reflect the size of the defect, and the rate of change of the recess is reflected by whether the defect has a mutation or not; the three parameters of pit depth, pit width, and pit rate of change are expressed using specific data: test pit depthIs +_with reference value->Difference size +.>Test pit depth and reference value +.>The absolute value of the difference continuously exceeds +.>Is>Maximum slope of defect point +.>. All the data can be obtained through normalization processing. Wherein->Defining the defect point comprises satisfying +.>Is provided.
In some preferred embodiments, for the test recess depth and the reference valueDifference size +.>Can useObtained, we define when->When the corresponding point belongs to the security point, i.e. the content as described in S402.
Along the targetThe path sequentially calculates the pressing points; definition meetsIs a defect to be fixed point, if at least one of two subsequent pressing points after the defect to be fixed point satisfies +.>And considering the defect to be fixed as an error point, otherwise, considering the defect to be fixed as the defect point.
The defect degree of the defect point is determined byThe defect judgment parameter Di is preset according to the size of the test object, wherein i is a positive integer greater than or equal to 2, and Di is confirmed based on experimental parameters and judgment precision requirements.
For the width of the recessThe acquisition mode is as follows:
sequentially calculating the pressing points along the target path; definition meetsIs a temporary starting point; if one of the pressing points adjacent to the temporary starting point still satisfies +.>Continuing to calculate each of the pressing points along the target path until satisfaction ++appears>Defining it as an end point; wherein the defect point includes the temporary starting point and the safety point includes the ending point;
calculating each of the pressing points against the direction of the target path, starting again at the temporary starting point, until occurrence ofIs marked as a starting point; wherein the security point comprises the starting point; the start point and the end point are different ones of the press points on the target path;
calculating all the satisfaction between the starting point and the ending pointIs to obtain the depression width +.>
If starting with the temporary starting point, the pressing point along the target path direction satisfiesThe temporary starting point is recorded as a suspicious point, which is re-verified in S500. Similarly, the width conditions may be classified according to the required accuracy of judgment.
Maximum slope for defect pointAfter defect range determination, the normalized parameters are fitted by peak values +.>Forming a fitting function (shown in figure 7) by using the scatter diagram corresponding to the number, calculating the slopes of all defect points in the corresponding defect peak through the fitting function, comparing the slopes, and defining the maximum value as +.>Wherein x represents the number of the pressed point, +.>And representing the maximum change rate of the defect degree of the corresponding defect of the defect point, thereby describing the change condition of the defect. The slope conditions may be classified by the required accuracy of the determination.
Through the normalization processing method of S300 and the recognition and classification criteria of S400, a mature model can be constructed through a computer program, the data can be subjected to rapid normalization processing, and the data can be classified and stored, so that the subsequent data output is facilitated.
S500, performing defect detection and feedback adjustment on setting parameters based on the defect identification and classification model; by the data acquired in S300 and the model constructed in step 4, we can quickly process and classify the data by the computer program. In S400, a partial point is regarded as a suspicious point, and this partial point needs to be measured again. In the present embodiment of the present invention, in the present embodiment,
re-measuring the suspicious points and the areas occupied by the three pressing points before and after the pressing sequence on the target path, adding two additional pressing points in every two adjacent pressing points, and re-inputting the measured data of the additional pressing points into a model to judge;
if the pressing points or the additional pressing points other than the suspicious point still satisfyThe suspicious point is considered as an error point;
if the pressing points or the additional pressing points other than the suspicious point still satisfyAnd considering the suspicious points as defect points, and judging the defect conditions through a model.
And S600, displaying the obtained sample defect result. Specifically, in the defect detection process of S500, the defect condition is identified and classified by the computer software, so as to more clearly display the classification result, and the processed data can be output. In this embodiment, output types are divided into two types, respectively: outputting a number-concave depth color map, and distinguishing the defect situation by using different colors; and outputting a defect marking top view, marking out defect points in the measuring path shown in fig. 3 by using a wire frame, and intuitively obtaining the defect positions. Since the data is already classified in the model, the above classification process is easily implemented by a computer program, and therefore specific implementation steps are not repeated here. The defect detection on this path is completed.
The above steps are mainly directed to single-layer wiring, and the RDL layer of the multi-layer wiring is processed in the same manner as the above steps, and the main difference is that an additional step is needed in the defect judging process. In the data processing process, if multiple layers of defects exist, the degree of the concave generated by the bottom layer of the defect is similar to that of the upper layer of the defect, and in order to distinguish the defect generation position, the embodiment distinguishes the defect generation position by the following way, in the actual process production, as the distance between the two rewiring layers is far away to ensure electrical isolation, and once the defect is generated, the size of the defect has a lower limit range, so that the degree of the concave reflected by the two defects has obvious difference, and in general, the generated defect does not have intersection, so that the defect can be judged by the size of a numerical value; but still there is a small part of the routes having a short distance and an intersection of the concave degrees, and then the defect route can be determined by detecting the electrical performance of the single route after determining the horizontal position of the defect at S600.
The embodiment discloses a wafer level package RDL rewiring layer defect detection method based on planar indentation, which comprises the following steps: planning an indentation pressing path according to the rewiring layer detection target path to press, and measuring concave data; processing the concave data to obtain a concave degree chart; constructing a defect identification and classification model based on the concave degree chart after normalization treatment; performing defect detection and feedback adjustment on setting parameters based on the defect identification and classification model; and displaying the defect result of the obtained sample.
In the embodiment, the internal defects of the RDL rewiring layer correspond to the surface mechanical response, the cavity defect condition in the circuit can be obtained by measuring the surface pressing depression degree, and the simple and nondestructive detection of the internal defects of the RDL is realized; according to the embodiment, the full-automatic intelligent identification and classification of the defects are realized by constructing the concave depth curve data processing model, and the high-efficiency and large-batch detection and judgment of the internal defects are realized; the embodiment can realize accurate positioning of internal defects in the RDL layer, simplify the positioning process and provide convenience for process optimization. In the embodiment, the internal metal wiring defect condition is judged and positioned by utilizing the RDL layer surface characterization mode, so that the problems that the traditional scheme is time-consuming and labor-consuming, low in efficiency, incapable of positioning accurately and the like are effectively solved, the detection of the internal defects in the RDL layer on a large scale is possible, and a better guarantee is provided for advanced three-dimensional packaging.
It should be understood that the specific order or hierarchy of steps in the processes disclosed are examples of exemplary approaches. Based on design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, this example is directed to less than all of the features of a single disclosed embodiment. Thus the following claims are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate preferred embodiment of this example.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. The processor and the storage medium may reside as discrete components in a user terminal.
For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. These software codes may be stored in memory units and executed by processors. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.
The foregoing description includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described herein are intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims. Furthermore, as used in the specification or claims, the term "comprising" is intended to be inclusive in a manner similar to the term "comprising," as interpreted when employed as a transitional word in a claim. Furthermore, any use of the term "or" in the specification of the claims is intended to mean "non-exclusive or".

Claims (11)

1. The method for detecting the defect of the RDL rewiring layer of the wafer-level package based on the planar indentation is characterized by comprising the following steps of:
s100, planning an indentation pressing path according to a target path of rewiring lamination mark detection of a product to be detected to press, forming a plurality of pressing points distributed along the target path, measuring concave data of each pressing point to obtain a test concave depth corresponding to each pressing point, and recording the number of each pressing point along the target path;
s200, processing the test depression depth data of each pressing point to obtain a depression degree chart of the product to be tested;
s300, carrying out normalization processing on the concave degree chart;
s400, constructing a defect identification and classification model based on the concave degree chart after normalization treatment;
s500, performing defect detection and feedback adjustment on setting parameters of an indentation experiment based on the defect identification and classification model;
s600, displaying the obtained sample defect result;
in S100, first, target path response data needs to be acquired, where the response data at least includes: a metal wiring design diagram of the region to be tested, wherein the metal wiring design diagram data are used for planning the target path; and the cross section diagram data are used for providing variable parameters for subsequent normalized data processing work and also used for final defect calibration.
2. The method for detecting the fault of the RDL rewiring layer of the wafer-level package based on the planar indentation as claimed in claim 1, wherein in S100, a micron-level probe is adopted to press the surface of the RDL layer of the product to be detected, all pressure heads are of the same specification, a load control loading mode is used, the same load is used for controlling variables in each pressing, and the loading and unloading time and the loading and unloading rate are ensured to be the same; after pressing, the loaded high-precision optical measuring instrument is used for measuring the pit depth after unloading, and the corresponding number and the test pit depth are recorded.
3. The method for detecting the fault of the re-wiring layer of the wafer level package RDL based on the planar indentation as claimed in claim 1, wherein in S200, a number-test recess depth scatter diagram is constructed by corresponding numbers of each of the pressing points recorded in S100 and a test recess depth, and the scatter diagrams are connected to obtain a line diagram; meanwhile, the cross-section image data of the target path in the vertical direction in the step S100 is collected, corresponding data of each pressing point is output, and preparation is made for subsequent data normalization processing.
4. The method for detecting the defect of the RDL rewiring layer of the wafer level package based on planar indentation as defined in claim 3, wherein in S300, the normalization processing is performed on the graph of the degree of dishing, and the specific method comprises: measuring metal wire conditions with different depths by carrying out an indentation detection experiment of a qualified sample in advance to obtain recess depths under ideal conditions corresponding to the different metal wire depths, defining the recess depths under the ideal conditions as ideal recess depths, and constructing a metal wire depth-ideal recess depth statistical database;
according to the collected section view data of the target path in S100, according to the corresponding situation of the metal wire depth of the pressing point and the metal wire depth in the database, obtaining an ideal depression depth corresponding to each pressing point on the target path, and normalizing the data of each pressing point by the following formula:
wherein,normalization parameters for the compression points; />A test depression depth for the pressing point; />And the ideal concave depth corresponding to the pressing point.
5. A planar indentation based wafer level package as recited in claim 4The rewiring layer defect detection method is characterized in that in S400, a defect identification and classification model is constructed, and the specific method comprises the following steps:
s401, setting safety position judgment parameters corresponding to each pressing point,/>Indicating that the measurement is allowed to be in error; using the difference between the maximum value and the minimum value in the database as a safety position judgment parameter +.>
S402, judging a safety point; normalized parameters defining all of the compression points on the target pathThe median of (2) is the reference value->Satisfy->Is considered as a safety point;
s403, distinguishing defect points;the parameters of the intra-layer defect reaction in the data chart specifically comprise: recess depth, recess width, and recess rate of change; wherein the depth and width of the recess reflect the size of the defect, and the rate of change of the recess is reflected by whether the defect has a mutation or not; the recess depth, the recess width, and the recess change rate are expressed using specific data as: test pit depth->Is +_with reference value->Absolute value of the difference of +.>Test pit depth and reference value +.>The absolute value of the difference continuously exceeds +.>Is>Maximum slope of defect pointThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->Defining the defect point comprises satisfying +.>Is provided.
6. A planar indentation based wafer level package as recited in claim 5The rewiring layer defect detection method is characterized by further comprising the following steps of:
sequentially calculating the pressing points along the target path; definition meetsThe pressing points of (2) are defect points to be fixed, if the defect points to be fixed are two subsequent pressing points, the defect points to be fixed satisfy +.>And considering the defect to be fixed as an error point, otherwise, considering the defect to be fixed as the defect point.
7. A planar indentation based wafer level package as recited in claim 5A rewiring layer defect detection method is characterized in that the recess width is +>The acquisition mode is as follows:
sequentially calculating the pressing points along the target path; definition meetsIs a temporary starting point; if one of the pressing points after the temporary starting point still satisfies +.>Continuing to calculate each of the pressing points along the target path until satisfaction ++appears>Defining it as an end point; wherein the defect point comprisesThe temporary starting point, the safety point comprising the ending point;
calculating each of the pressing points against the direction of the target path, starting again at the temporary starting point, until occurrence ofIs marked as a starting point; wherein the security point comprises the starting point; the start point and the end point are different ones of the press points on the target path;
calculating all the satisfaction between the starting point and the ending pointIs to obtain the depression width +.>
8. A planar indentation based wafer level package as recited in claim 7A rewiring layer defect detection method, wherein, if starting with the temporary starting point, the pressing point along the direction of the target path satisfies the following conditionThe temporary starting point is recorded as a suspicious point, which is re-verified in S500.
9. A wafer level package based on planar indentations as claimed in any of claims 6-8The rewiring layer defect detection method is characterized by further comprising:
determining the defect degree of the defect point, wherein the defect degree of the defect point is determined byIs dependent on the size of the (c).
10. A planar indentation based wafer level package as recited in claim 5A rewiring layer defect detection method characterized in that the maximum slope for defective points is +.>After defect range determination, the normalized parameters are fitted by peak values +.>Forming a fitting function by using the scatter diagram corresponding to the number, calculating the slopes of all defect points in the corresponding defect peak through the fitting function, comparing the slopes, and defining the maximum value as +.>Wherein->Number indicating the pressed point +_>And representing the maximum change rate of the defect degree of the corresponding defect of the defect point, thereby describing the change condition of the defect.
11. A planar indentation based wafer level package as recited in claim 8The rewiring layer defect detection method is characterized by comprising the steps of performing defect detection based on the defect identification and classification model and performing feedback adjustment on setting parameters of an indentation experiment; specific method packageThe method comprises the following steps:
re-measuring the suspicious points and the areas occupied by the three pressing points before and after the pressing sequence on the target path, adding two additional pressing points in every two adjacent pressing points, and re-inputting the measured data of the additional pressing points into a model to judge;
if the pressing points or the additional pressing points other than the suspicious point still satisfyThe suspicious point is considered as an error point;
if the pressing points or the additional pressing points other than the suspicious point still satisfyAnd considering the suspicious points as defect points, and judging the defect conditions through a model.
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