CN117349101A - Chip verification platform and construction method thereof - Google Patents
Chip verification platform and construction method thereof Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Abstract
The invention discloses a chip verification platform and a construction method thereof, which belong to the technical field of chip verification, and the method provided by the invention selects a verification component class predefined by a PVM platform to inherit according to user verification components of actual business division, and constructs a family factory mode, so that the verification components required can be selected for instantiation according to configuration files during operation, unnecessary verification components are completely removed from the verification platform, the occupied space of a memory is reduced, and the simulation speed is improved; meanwhile, when different test cases are operated, the configuration file can be directly modified, and the needed verification component combination can be replaced without modifying the test code, so that the simulation efficiency is improved.
Description
Technical Field
The invention belongs to the technical field of chip verification, and particularly relates to a chip verification platform and a construction method thereof.
Background
Chip verification can be mainly divided into 3 stages: and (5) constructing a verification platform, running simulation and reporting. The verification platform is typically composed of: excitation generator, driver, sampler, reference model, score board, etc. With the development of the IC (integrated chip) industry, the chip scale is increased, the functions are also more and more complex, the verification platform is also more and more complex, and the verification components therein are also increased, as shown in fig. 1.
Along with the increase of verification scale and complexity, the same verification platform has different requirements for verification components when different test cases run simulation. For example, in some test cases, only the verification components VC1-VC4 need be used, and no other verification components need be used, so as to achieve the purpose of saving memory space and simulation time. In the prior art, taking the dominant UVM (Universal Verification Methodology, general verification methodology) verification platform as an example, only verification components VC1-VC4 are used when a testcase is used, and verification components VC5-VC8 are not used. The UVM verification platform can realize that Disable (not enable) cannot use the verification components VC5-VC8 through configuration, so that the verification components VC5-VC8 can be ensured not to be executed, and the purpose of improving the simulation speed is achieved. However, the prior art has the following drawbacks: 1. the testbench still comprises eight verification components VC1-VC8, and when the testbench is executed, the testbench occupies a memory space, and the simulation speed is reduced due to the occupation of a large amount of memory; 2. meanwhile, the verification components VC5-VC8 are not enabled through configuration, and the 4 verification components cannot be completely executed, so that the verification platform needs to schedule the verification components on one hand, a certain simulation time is consumed, and meanwhile, the components are not executed but are executed in an idle mode, and a certain simulation time is still consumed; 3. when running different test cases, the source code needs to be modified to achieve the purpose of disabling different verification components VC.
In summary, the prior art does not effectively improve the memory space occupation, reduce the simulation time, and improve the simulation speed and efficiency.
Disclosure of Invention
In order to solve the problems that in the prior art, the disabled verification assembly still occupies memory space, consumes simulation time and needs to modify source codes when running different test cases, and the like, the invention provides a chip verification platform and a construction method thereof.
The invention is realized by the following technical scheme:
a method of constructing a chip verification platform, the method comprising:
constructing PVM (Parallel VerificationMethodology ) platform verification component class inheritance relation according to verification components of actual business division; the PVM platform is a platform architecture of multi-core parallel simulation realized based on a parallel verification methodology;
creating a family factory class for the PVM platform verifying component class inheritance relationship; each factory class in the family factory class can create the factory class, and the factory class of the father class family can create all subclasses registered in the factory class;
and loading and analyzing the configuration file of the current test case, and selecting a verification component required by dynamically instantiating the current test case from the family factory classes according to the configuration file.
Compared with the prior art, the verification platform still comprises all verification components in a mode of not enabling the unnecessary verification components, and the weight reduction of the verification platform is not really realized, wherein the unnecessary verification components still occupy memory space and consume scheduling time; the method selects the verification component class predefined by the PVM platform to inherit according to the user verification components of the actual business division, and constructs a family factory mode, so that the verification components required can be selected for instantiation according to the configuration file during operation, the unnecessary verification components are completely removed from the verification platform, the occupied space of the memory is reduced, and the simulation speed is improved; meanwhile, when different test cases are operated, the configuration file can be directly modified, and the needed verification component combination can be replaced without modifying the test code, so that the simulation efficiency is improved.
As a preferred embodiment, the PVM platform verification component class inheritance relation construction process specifically comprises the following steps:
acquiring a user verification component divided according to actual services;
and selecting corresponding component class inheritance provided by the PVM platform according to the user verification component, so as to construct and obtain PVM platform verification component class inheritance relation.
As a preferred embodiment, the PVM platform of the present invention provides a verification component base class and a specific verification component class;
the specific verification component comprises an excitation component, a driving component, a register component, a reference model component and a score board component.
As a preferred embodiment, the family factory class creation process of the present invention specifically includes:
acquiring all verification component classes marked as factors;
creating a factory class for each of the validation component classes labeled factory, said factory class providing the following functions:
(1) A function of creating an object;
(2) Automatically registering the factory class of the parent class of all the factory labels, so that the factory class of the parent class has the capability of creating the factory class;
(3) A registration of a subclass is received, with the ability to create all registrations to the factory class.
As a preferred embodiment, the configuration file of the invention is used for configuring verification components required by test cases.
As a preferred embodiment, one of the plant classes of the present invention simultaneously supports the creation of multiple different types of objects, i.e., verification components.
As a preferred embodiment, one of the plant classes of the present invention employs different instantiations when creating a particular type of object.
As a preferred embodiment, the method of the present invention further comprises: when a new user authentication component is added, the new user authentication component is directly added into the original family factory class without changing the logic of the original family factory class. When a new user verification component is needed to be added, the new user verification component is added into the original family factory class only by adopting the method provided by the invention, and the expandability and the retractility are higher.
As a preferred embodiment, the method of the present invention further comprises: dynamic instantiation of different verification component combinations is realized by adjusting the configuration file so as to run different test cases.
On the other hand, the invention provides a chip verification platform which is constructed by the verification components required by the current test case by adopting the method.
The invention has the following advantages and beneficial effects:
1. according to the invention, the verification components of the actual service are selected to inherit from the verification component class predefined by the PVM platform, and the configuration file is loaded and analyzed by combining with the family factory mode, so that the corresponding verification components can be selected for instantiation according to the verification component combination required by the test case configured in the configuration file, thereby ensuring that the test platform only comprises the required verification components, the unnecessary verification components are not instantiated in the test platform, the memory is not occupied during execution, the scheduling time is not occupied, the light weight of the test platform is realized, and the simulation speed and the simulation efficiency are improved.
2. When different test cases run in simulation, the verification component combination in the test code is not required to be adjusted, and the dynamic instantiation of the different verification component combination can be realized by only adjusting the configuration in the configuration file, so that the purpose of improving the simulation efficiency is achieved.
3. Compared with the prior art, the method does not need to make type reloading in advance, all choices are delayed to the operation time, and meanwhile, the type of the real type does not need to be known in advance in the encoding process.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
fig. 1 is a schematic diagram of a conventional verification platform.
FIG. 2 is a schematic diagram of a conventional authentication platform employing a disabling mode.
FIG. 3 is a flow chart of a method according to an embodiment of the invention.
FIG. 4 is an example one of PVM platform class inheritance relationships in accordance with an embodiment of the present invention.
FIG. 5 is an example two of a PVM platform class inheritance relationship in accordance with an embodiment of the present invention.
FIG. 6 is an example one of a verification platform constructed using the method of an embodiment of the present invention.
Fig. 7 is an example two of a verification platform constructed using the method of an embodiment of the present invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Examples:
the conventional UVM verification platform improves the simulation speed by configuring verification components which are not needed to realize Disable (not enabling), however, the verification platform still comprises all the verification components (the verification components which need to be used and the verification components which do not need to be used), namely the verification components which do not need to be used are instantiated, and only are not executed, the memory space is still occupied, and the simulation speed is reduced due to the fact that a large amount of memory space is occupied; meanwhile, by configuring that the unnecessary verification components are not enabled, the unnecessary verification components cannot be guaranteed to be completely disabled, component scheduling still exists, and the disabled verification components can be executed in an idle mode, so that simulation time is consumed; in addition, when running different test cases, because the verification components required by different test cases are different, that is, the verification components to be disabled are also different, the source code needs to be modified to achieve the purpose of disabling the different verification components, which also consumes simulation time. Based on this, the embodiment provides a method for constructing a chip verification platform, and the method is based on a PVM (Parallel VerificationMethodology ) platform, wherein the PVM platform is a platform architecture based on multi-core parallel simulation realized by the parallel verification methodology, and a dynamic instantiation method is adopted to instantiate verification components required by test cases only according to configuration files, so that unused verification components are completely cleared from a testbench (verification platform), the occupied space of a memory is reduced, and meanwhile, the operation of different test cases can be realized only by modifying the configuration files, thereby improving the simulation speed.
As shown in fig. 3, the verification platform construction method provided in this embodiment specifically includes the following steps:
and step 1, constructing a PVM platform verification component class inheritance relationship according to the verification components of the actual business division.
The step 1 comprises the following steps:
and acquiring a user verification component according to the actual business division. Specifically, the user verification component for chip verification is obtained according to actual service division, and generally comprises: stimulus generation component (gnTxVC), driver component (driver), register component (socReg), reference model component (tcBrm), scoreboard component (UScb), etc.
It should be noted that, the PVM platform features are specifically referred to the applicant's prior application patent (202210941533.4, a multi-core parallel simulation method and a platform architecture for implementing multi-core parallel simulation), which are not described herein in detail. In the PVM platform, component base classes (vc classes) have been predefined, as well as various specific component classes (including, but not limited to, stimulus component txVC, driver component drvVC, register component regVC, reference model component brmVC, scoreboard component scbVC, etc.), the specific code is as follows:
load/PVM platform code
class vc ：factory
Member variables of member methods in a// base class
class tx VC of vc ：factory
byte gen (): generation of random excitation data
tobrm (byte txData, byte feedback): transmission of excitation to reference model
toduv (byte txData): transmission of the stimulus to the DUV (Module to be validated)
onProcess (): main loop of/(VC) thread
class drvVC of vc ：factory
onProcess()：
class regVC of vc ：factory
onProcess()：
class brmVC of vc ：factory
onProcess()：
class scbVC of vc ：factory
onProcess()：
Through the codes, the PVM platform predefines verification component base class (vc) and specific verification component class, and mainly comprises an excitation generation component (txVC), a driving component (drvVC), a register component (regVC), a reference model component (brmVC), a scoreboard component (scbVC) and the like.
And selecting corresponding component class inheritance provided by the PVM platform according to the user verification components of the actual business division, thereby constructing and obtaining the PVM platform verification component class inheritance relationship shown in figure 4, wherein the specific codes are as follows:
user authentication platform code
class gnTxVC of txVC ：factory
onProcess()：
User authentication service logic
class driver of drvVC ：factory
onProcess()：
User authentication service logic
class socReg of regVC ：factory
onProcess()：
User authentication service logic
class tcBrm of brmVC ：factory
onProcess()：
User authentication service logic
class UScb of scbVC ：factory
onProcess()：
User authentication service logic
It should be noted that the illustration shown in fig. 4 is merely an exemplary illustration, and in a practical production environment, some relatively complex scenarios may require different excitation components. Different stimulus components are selected in different test cases to verify different modules. For example, in another alternative embodiment, a user authentication component according to a certain actual traffic classification comprises: an excitation component (gnTxVC, ethTxVC, otnTxVC), a drive component (driver), a register component (socReg, ithReg), a reference model component (tcBrm), a scoreboard component (UScb); gnTxVC, ethTxVC, otnTxVC selects the stimulus component (txVC) class inheritance provided by the PVM platform, driver selects the driver component (drvc) class inheritance provided by the PVM platform, socReg, ithReg selects the register component (regVC) class inheritance provided by the PVM platform, tcBrm selects the reference model component (brmVC) class inheritance provided by the PVM platform, and usb selects the scoreboard component (scbVC) class inheritance provided by the PVM platform, resulting in a PVM platform verification component class inheritance relationship as shown in fig. 5.
And 2, verifying the component class inheritance relationship for the PVM platform to create a family factory class.
The step 2 specifically comprises the following sub-steps:
analyzing the inheritance relation of the PVM platform verification component class constructed in the step 1, and obtaining all classes marked as factory (factory) to process and create a family factory class, wherein the family factory class is specifically:
automatically creating a factory class for classes labeled as factory, respectively, the factory class providing the following functions:
(1) The function of creating an object (i.e., verifying component instantiation), whose parametric form is similar to the constructor of the original class;
(2) Automatically registering the parent class factory class of all the factory labels, the parent class factory class of the parent class and the like, so that the factory class of the parent class has the capability of creating the class;
(3) A registration of a subclass is received, thereby having the ability to create all subclasses registered to the factory class.
This embodiment is illustrated by taking fig. 4 as an example, where the inheritance or registration relationship from the child class to the parent class is indicated by an arrow, all classes have factory labels, so a factory class is created for each class, the vc factory class has 5 registered subclasses, which are txVC, drvVC, regVC, brmVC and scbVC, respectively, and the 5 subclasses have registered a subclass, for example, the subclass of txVC is gnTxVC, etc.; depending on the nature of the factory class, the vc base class may create the capabilities of all classes (including itself and all subclasses), txVC has the capability to create itself and the subclasses gnTxVC, and similarly drvc may create itself and the capabilities of the subclasses driver, and so on.
Of the family factory classes, one factory class can simultaneously support the creation of a plurality of different types of objects, and as shown in fig. 4-5, the vc factory class can create either a txVC type or a regVC type.
When a factory class is created in a specific type, different instantiations can be adopted, for example, when a txVC type is created, the factory class can be instantiated through int parameters or double parameters, different parameters are instantiated, and completely different construction functions are adopted.
When the user uses the vc factory class, the user is completely decoupled from the specific type, only needs to know the obtained object and can use the object as the vc, does not need to know whether the specific type is the true vc, and does not change the logic of the user after any type is newly added.
And step 3, loading and analyzing the configuration file of the current test case, and selecting a verification component required by dynamically instantiating the current test case from the family factory classes according to the configuration file.
Compared with the mode of writing source code to instantiate the verification component in the prior art, the method dynamically instantiates the verification component in the mode of configuration files. For example, one test case, test platform 1 (testbench 1), requires gnTxVC, driver, tcBrm and UScb components; another test case, test platform 2 (testbench 2), requires driver, socReg, tcBrm and UScb components. The two test case configuration file codes are as follows:
[pvm ：testbench/1]
[vc ：gnTxVC/1001]
[vc ：driver/1002]
[vc ：tcBrm/1003]
[vc ：UScb/1004]
[pvm ：testbench/2]
[vc ：driver/2001]
[vc ：socReg/2002]
[vc ：tcBrm/2003]
[vc ：UScb/2004]
the PVM platform reads and analyzes the configuration file of the test case 1, and selects a required verification component for instantiation according to the configuration file, wherein the specific codes are as follows:
/(pseudo code)
pvm ☆ p1 =>New ("testbench", 1)// through PVM factory class, create an instance of testbench class, and pass parameter 1 (i.e., pvmid: 1)
vc ☆ v1 =>New ("gnTxVC", 1001)// through vc factory class, create an instance of gnTxVC class, and pass in parameter 1001 (i.e., vcid: 1001)
p1- > addVC (v 1)// v1 is added to p1
vc ☆ v2 =>New ("driver", 1002)// through vc factory class, create an instance of driver class, and enter parameter 1002 (i.e., vcid: 1002)
p1- > addVC (v 2)// v2 is added to p1
vc ☆ v3 =>New ("tcBrm", 1003)// through vc factory class, create an instance of tcBrm class, and import parameter 1003 (i.e., vcid: 1003)
p1- > addVC (v 3)// v3 added to p1
vc ☆ v4 =>New ("UScb", 1004)// through vc factory class, create an instance of UScb class and import parameters 1004 (i.e., vcid: 1004)
p1- > addVC (v 4)// v4 is added to p1
The verification components required by the test platform 1 comprise gnTxVC, driver, tcBrm and UScb components, instantiation codes of the corresponding components are called through character strings to be instantiated, and then simulation tests are conducted based on the instantiated verification components.
The method principle proposed by the embodiment mainly comprises the following steps: the method comprises the steps that instantiation codes of all verification components which can be applied to actual business are created in advance, all verification components which can be applied to actual business are inherited by verification component classes predefined by a PVM platform, a family factory mode is built, namely, a factory class is automatically created for the class marked with the factory, the factory class can provide the capability of creating self and all subclasses registered to the factory class, namely, each factory class can instantiate the self and all verification components registered to the subclasses of the factory class, finally, according to configuration files corresponding to the current test cases, the verification components configured by the configuration files can be selected for dynamic instantiation, the fact that the test platform only comprises the required verification components is guaranteed, the unnecessary verification components cannot be instantiated in the test platform, memory is not occupied during execution, scheduling time is not occupied, light weight of the test platform is achieved, and simulation speed and simulation efficiency are improved. Unlike existing UVMs, there is no need to make type reloads in advance, all choices are delayed to run, and there is no need to know the type of real class in advance at encoding.
When different test cases run in simulation, the dynamic instantiation of different verification component combinations can be realized by only adjusting the configuration file without adjusting the verification component collocation in the test code, thereby achieving the purpose of improving the simulation efficiency.
In addition, the dynamic instantiation process, supported by the family factory model, can instantiate the user authentication component directly at run-time and use it as an authentication component for the base class without prior knowledge of the specific authentication component implemented by the user.
The method provided by the embodiment can save the coding time of the user, the compiling time of the verification code and the simulation running time, the verification code only needs to be coded once and compiled once, different test cases are replaced, the code is not required to be modified and recompiled, and the dynamic instantiation of verification components required by different test cases can be realized only by modifying the configuration of the verification components in the configuration file.
In another alternative embodiment, the construction method further comprises: when a new user verification component is added, the original family factory mode is not required to be changed, and the new user verification component is only directly added into the original family factory mode according to the process, so that the scalability of the built chip verification platform can be improved.
The embodiment of the invention also provides a chip verification platform, which is constructed by adopting the construction method to obtain the verification platform formed by the verification components required by the current test case.
When only verification components VC1-VC4 are needed by one test case, only 4 verification components VC1-VC4 are verified by the above construction method, so that the test platform shown in FIG. 6 and composed of only verification components VC1-VC4 is obtained.
When only verification components VC5-VC8 are needed by one test case, only 4 verification components VC5-VC8 are needed by the test case by the construction method, so that a test platform which is shown in FIG. 7 and is composed of only verification components VC5-VC8 is obtained.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The method for constructing the chip verification platform is characterized by comprising the following steps of:
constructing PVM platform verification component class inheritance relation according to the verification components of actual business division; the PVM platform is a platform architecture of multi-core parallel simulation realized based on a parallel verification methodology;
creating a family factory class for the PVM platform verifying component class inheritance relationship; each factory class in the family factory class can create the factory class, and the factory class of the father class family can create all subclasses registered in the factory class;
and loading and analyzing the configuration file of the current test case, and selecting a verification component required by dynamically instantiating the current test case from the family factory classes according to the configuration file.
2. The method for constructing a chip verification platform according to claim 1, wherein the PVM platform verification component class inheritance relationship construction process specifically comprises:
acquiring a user verification component divided according to actual services;
and selecting corresponding component class inheritance provided by the PVM platform according to the user verification component, so as to construct and obtain PVM platform verification component class inheritance relation.
3. The method for constructing a chip verification platform according to claim 2, wherein the PVM platform provides a verification component base class and a specific verification component class;
the specific verification component comprises an excitation component, a driving component, a register component, a reference model component and a score board component.
4. The method for constructing a chip verification platform according to claim 1, wherein the family factory class creation process specifically includes:
acquiring all verification component classes marked as factors;
creating a factory class for each of the validation component classes labeled factory, said factory class providing the following functions:
(1) A function of creating an object;
(2) Automatically registering the factory class of the parent class of all the factory labels, so that the factory class of the parent class has the capability of creating the factory class;
(3) A registration of a subclass is received, with the ability to create all registrations to the factory class.
5. The method for constructing a chip verification platform according to claim 1, wherein the configuration file is used for configuring verification components required by test cases.
6. The method of claim 4, wherein one of the factory classes supports the creation of multiple different types of objects, i.e., verification components.
7. The method of claim 6, wherein one of the factory classes uses different instantiations when creating a particular type of object.
8. The method for constructing a chip verification platform according to claim 2, further comprising: when a new user authentication component is added, the new user authentication component is directly added into the original family factory class without changing the logic of the original family factory class.
9. The method for constructing a chip verification platform according to claim 1, further comprising: dynamic instantiation of different verification component combinations is realized by adjusting the configuration file so as to run different test cases.
10. A chip verification platform, which is characterized in that the chip verification platform is constructed by the verification components required by the current test case by adopting the method of any one of claims 1-9.
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