CN117348044A - Subcode parallel design method of composite code for reproducing pseudo code ranging - Google Patents
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/30—Acquisition or tracking or demodulation of signals transmitted by the system code related
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/34—Power consumption
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention belongs to the technical field of deep space pseudo code ranging, and discloses a subcode parallel design method of a composite code for reproducing pseudo code ranging, which integrates 77 subcode phases of six subcodes of C1-C6, distributes the 77 subcode phases to a plurality of correlation computing units on average, adopts a serial-parallel combination mode, and carries out parallel operation on the plurality of correlation computing units, wherein each correlation computing unit is multiplexed in a time-sharing mode, and serial processing can be divided into subcode phases of different subcodes. The invention achieves the balance of chip resource consumption and subcode capturing time by designing the serial-parallel structure of the subcode correlator in the on-board regeneration pseudo code module, and has great application value in deep space measurement and control communication.
Description
Technical Field
The invention belongs to the technical field of deep space pseudo code ranging, and particularly relates to a subcode parallel design method of a composite code for reproducing pseudo code ranging.
Background
The deep space detection has long satellite-ground distance, so the time delay and the low level of the satellite received signal make the traditional side tone ranging difficult to meet the requirements of no-fuzzy distance and ranging precision. In the regenerated pseudo code ranging system, the period of the ranging pseudo code is long, and a large unambiguous distance can be obtained. The phase information of the uplink ranging pseudo code is obtained through capturing and tracking on the satellite, and the ranging pseudo code is regenerated in the downlink channel through the phase information. Compared with the uplink ranging pseudo code signal, the downlink ranging pseudo code signal has the same pseudo code phase, but the noise is greatly reduced, and the signal-to-noise ratio is greatly improved, so that the ranging precision is improved. Therefore, the regenerated pseudo code ranging can make up for the deficiency of the traditional side tone ranging so as to adapt to the spacecraft ranging under the deep space exploration background.
Current deep space communication pseudo-code ranging systems mainly use n-fold weighted Tausworthe codes (denoted T4B when n is 4 and T2B when n is 2) recommended by the spatial data system consultation committee (Consultative Committee for Space Data System, CCSDS). T4B or T2B, which are formed by weighting and combining 6 component codes C1-C6, are different in the weight of the clock component code C1: 4 or 2. These 6 subcodes have good cross-correlation peaks with the composite code, so the phase of the composite code can be determined by the correlation of each subcode with the composite code. At present, the deep space widely adopts a CCSDS recommended on-satellite regeneration pseudo code processing module, and the basic structure of the module consists of a chip tracking loop (chip tracking loop, CTL), a subcode related processing unit and a downlink code generator. For example, the regenerative pseudocode processing module of the bepicolobo water star detector adopts the structure. The code correlator in BepiColombo performs serial sliding search in each subcode during correlation computation, and performs parallel search between subcodes. The correlation calculation theoretically needs to be performed is the sum of each sub-code period, 77 times.
The on-satellite pseudo code regeneration processing module in the BepiColombo comprises six correlators (each subcode is C1, C2, … and C6, respectively), 6 correlators adopt a parallel structure, each correlator carries out series search on Li possible subcode phases of the corresponding subcode Ci, and because the lengths of the subcodes are different, the pseudo code capturing time of the structure has a calculation bottleneck on the longest subcode C6, namely other subcodes have to wait for the subcode 6 to finish calculation so as to finish the final capturing of the pseudo code.
Disclosure of Invention
Aiming at the defects of the background technology, the invention provides a subcode parallel design method of a composite code for reproducing pseudo code ranging, which integrates 77 subcode phases of six subcodes from C1 to C6 and distributes the subcode phases to a plurality of correlation calculation units on average, adopts a serial-parallel combination mode, and adopts parallel operation for the plurality of correlation calculation units, wherein each correlation calculation unit is used for multiplexing in a time-sharing way and processing the subcode phases distributed on average in a serial way.
In order to achieve the above purpose, the invention is realized by the following technical scheme:
the invention relates to a subcode parallel design method of a composite code for reproducing pseudo code ranging, which is applied to a deep space probe satellite receiver, wherein a reproducing pseudo code module of a digital baseband processing part of the satellite receiver realizes functions of capturing satellite pseudo codes and reproducing the pseudo codes, a basic structure of the reproducing pseudo code module comprises a code chip tracking ring, a subcode correlation processing unit and a downlink code generator, the subcode correlation processing unit comprises a code correlator, a code generator and a maximum value search decision device, the code correlator is internally provided with a correlation calculation unit, and the subcode parallel design method specifically comprises the following steps:
step 1, tracking, demodulating and receiving clock component codes in a pseudo code sequence by the chip tracking loop;
step 2, the code generator generates each sub-code sequence with the same code phase as the clock component in the step 1;
step 3, the clock component code phase of the received pseudo code sequence is consistent with the clock component code phase of the locally generated 6 sub code sequences, 77 sub code phases of six sub codes of C1-C6 are integrated and considered, the 77 sub code phases are distributed to a plurality of correlation calculation units in a code correlator on average, and sub code phases possibly belonging to different sub codes are calculated in a serial-parallel combination mode;
step 4, the 77 subcode phases of the six subcodes from C1 to C6 are accumulated for a plurality of times, the output value is detected by the maximum value searching and judging device, the phase corresponding to the maximum value of the six subcodes from C1 to C6 is determined, and then the 6 real-time phase values are output to calculate the phase of the composite code;
and 5, after the downlink code generator recovers according to the phases of the six sub-codes C1-C6, generating a sequence identical to the received pseudo code sequence and transmitting the sequence to a receiving station on the ground.
The invention further improves that: in the step 3, the code correlator integrates 77 phases of six subcodes from C1 to C6, and designs a serial-parallel structure of a correlation calculation unit according to actual needs, and the method specifically comprises the following steps:
step 2-1, designing the serial-parallel degree, and determining the number of required related computing units;
step 2-2, integrating 77 phases of the six subcodes of C1 to C6 and sequencing;
step 2-3, evenly distributing 77 phases to each relevant computing unit in step 2-1;
and 2-4, performing parallel computation among the correlation computation units, multiplexing in a time-sharing manner in each correlation computation unit, and serially processing the sub-code phases distributed evenly.
The invention further improves that: the peak detection of the maximum value searching and judging device in the step 4 specifically comprises the following steps: setting 6 decision thresholds, wherein the threshold values are the products of the phase accumulation times and the lengths of all the sub-codes of C1-C6, comparing the accumulated code correlator output values with the decision thresholds, outputting corresponding sub-code sequences if the accumulated code correlator output values are larger than the decision threshold values, and returning to the code correlator for processing operation again if the accumulated code correlator output values are smaller than the decision threshold values.
The invention further improves that: in the step 1, the code pattern of the pseudo code sequence is T2B or T4B, the T2B code pattern and the T4B code pattern are formed by weighted combination of 6 component codes C1-C6, the weight of the clock component code C1 of the T2B code pattern is 2, and the weight of the clock component code C1 of the T4B code pattern is 4.
The beneficial effects of the invention are as follows:
the method solves the problem that the existing on-board regeneration pseudo code module is difficult to balance between chip resource occupation and pseudo code capturing time consumption;
the method of the invention integrates all subcode phases of six subcodes by carrying out serial-parallel combination design on the subcode correlator in the regeneration pseudo code module, and evenly distributes the subcode phases to a plurality of correlation calculation units, and adopts a serial-parallel combination mode, the plurality of correlation calculation units operate in parallel, wherein each correlation calculation unit carries out time division multiplexing, and serial processing can be divided into subcode phases of different subcodes;
the invention determines the priority degree of the chip resource and the pseudo code capturing time in the practical engineering application, flexibly selects the subcode serial-parallel degree of the corresponding regenerated pseudo code module for design, and can flexibly balance between the resource consumption and the pseudo code capturing time.
Under the condition of the same resource consumption, the invention can effectively reduce the pseudo code capturing time.
Drawings
FIG. 1 is a block diagram of a regenerated pseudo code module subcode parallel-combine-parallelism-39-serialization-2 code correlator.
FIG. 2 is a block diagram of a regenerated pseudo code module subcode parallel-combine-parallelism-26-serialization-3 code correlator.
FIG. 3 is a block diagram of a regenerated pseudo code module subcode parallel-combined-parallelism-20-serialization-4 code correlator.
Detailed Description
Embodiments of the invention are disclosed in the drawings, and for purposes of explanation, numerous practical details are set forth in the following description. However, it should be understood that these practical details are not to be taken as limiting the invention. That is, in some embodiments of the invention, these practical details are unnecessary.
The sub-code parallel design method of the composite code for reproducing the pseudo-code ranging is applied to a deep space probe satellite receiver, a reproducing pseudo-code module of a digital baseband processing part of the satellite receiver realizes functions of capturing the satellite pseudo-code and reproducing the pseudo-code, a basic structure of the reproducing pseudo-code module comprises a code tracking ring, a sub-code correlation processing unit and a downlink code generator, the sub-code correlation processing unit comprises a code correlator, a code generator and a maximum value search decision device, the code correlator is provided with a correlation calculation unit, and the sub-code parallel design method specifically comprises the following steps:
step 1, tracking, demodulating and receiving clock component codes in a pseudo code sequence by the chip tracking loop;
step 2, the code generator generates each sub-code sequence with the same code phase as the clock component in the step 1;
and 3, keeping the clock component code phase of the received pseudo code sequence consistent with the clock component code phase of the locally generated 6 sub-code sequences, integrating and considering 77 sub-code phases of six sub-codes of C1 to C6, and uniformly distributing the 77 sub-code phases to a plurality of correlation calculation units in a code correlator, and calculating sub-code phases possibly belonging to different sub-codes in a serial-parallel combination mode.
Step 4, the 77 subcode phases of the six subcodes from C1 to C6 are accumulated for a plurality of times, the output value is detected by the maximum value searching and judging device, the phase corresponding to the maximum value of the six subcodes from C1 to C6 is determined, and then the 6 real-time phase values are output to calculate the phase of the composite code;
and 5, after the downlink code generator recovers according to the phases of the six sub-codes C1-C6, generating a sequence identical to the received pseudo code sequence and transmitting the sequence to a receiving station on the ground.
Example 1
The lengths of the generated subcodes of the T4B code and the T2B code are equal to each other, the lengths of the subcodes of C1 to C6 are 2, 7, 11, 15, 19 and 23 respectively, and therefore the period of the composite code is equal to the product of the lengths of all the subcodes, namely L= 1009470 chips.
Both the T2B and T4B codes contain 1 clock code and thus there is a significant clock component. The code tracking loop can track and demodulate the clock component in the receiving pseudo code sequence, namely T2B or T4B, the clock code demodulated by the code generator receiving code tracking loop generates a local pseudo code identical to the receiving pseudo code sequence, the generated clock code of the local pseudo code keeps the initial phase consistent with the clock code of the receiving pseudo code, and then synchronization of other subsequences is carried out, so that synchronization of the code chips is realized.
The code correlator has correlation calculation unit resources, the quantity of the correlation calculation units is determined according to practical application, 77 phases of six subcodes of C1-C6 are integrated and arranged in sequence, the phases are evenly distributed to a plurality of correlation calculation units, a serial-parallel combination mode is adopted, the correlation calculation units operate in parallel, each correlation calculation unit is multiplexed in a time sharing mode, and subcode phases possibly belonging to different subcodes are processed and calculated in a serial mode. As shown in fig. 1, a structure with a serial degree of 2 and a parallel degree of 39 is designed, and 77 sub-code phases are divided into 39 parts to perform correlation operation, that is, sub-code phases which are averagely distributed in each correlation calculation unit are multiplied by locally generated chip phases in a one-to-one correspondence manner.
The number of the chip phase accumulation times is determined, the output value of the code correlator is accumulated for a plurality of times and then is sent to a maximum value searching decision device, decision thresholds of the maximum value searching decision device are set, the number of the decision thresholds is 6, and the number of the decision thresholds is respectively the product of the number of the phase accumulation times and the length of each sub-code from C1 to C6. And outputting a corresponding subcode sequence if the accumulated code correlator output value is larger than the decision threshold value, and returning to the code correlator for processing operation again if the accumulated code correlator output value is smaller than the decision threshold value.
The subcode parallel design method of the invention is subjected to capture time analysis and resource utilization rate analysis, and specific application is taken as an example, and the selected FPGA adopts 550 Wanlinx devices of Xilinx company, and the model is XQ4VSX55-10FF1148l.
One of the main reference parameters in estimating the acquisition time of different ranging sequences is the chip signal-to-noise ratio 2Ec/N0, where Ec is the received chip energy and N0/2 is the additive Gaussian noise double-sideband noise power spectral density.
Assuming that the integration time is K chips, the energy of each chip is Ec, the noise is additive Gaussian white noise, and the power spectral density of the double sidebands is N0/2, the single synchronization fractional correlation is performed. At this time, the error probability Pe2 of the synchronization judgment is
Wherein the method comprises the steps of
Equivalently, for a given Pe2, the number of integrated chips required for single synchronization fractional correlation of the reverse sequence is
For any subcode, the probability of determining an error between a synchronous cyclic shift and some of its asynchronous cyclic shifts, pe2, is a function of the synchronous and asynchronous fractional correlation coefficients ζ and ψ. Using the above expression and employing the analysis method for the counter signal described above, for a given Pe2 and arbitrarily determined chip SNR value, the number of chips K is
Wherein the method comprises the steps of
From the above equation, given the error probability Pe2, the required number of integrated chips can be calculated based on the subcode parameters λ, ζ.
Taking the chip signal-to-noise ratio snr= -42dB, the chip rate is 2Mcps, and taking the error used in CCSDS 414.0-G-2 analysis as the target of approximately 1%, in the fully parallel structure, each subcode with the code length of Li has Li possible phases, and Li correlation calculation units are needed, and the number of the 6 subcode total correlation calculation units is: 2+7+11+15+19+23=77. Since 6 probe codes operate simultaneously and C6 has the largest period 23 in BepiColombo, the normalized total acquisition time of the system is equivalent to the normalized acquisition time of probe code C6, i.e., the composite code acquisition time is equivalent to the longest correlation computation time required in the six subcodes C1-C6, which is approximately 21 seconds.
The existing structure of the sub-code correlator in the BepiColombo consumes huge FPGA resources, so that a serial-parallel combination mode is adopted in practical engineering application, namely a plurality of correlation calculation units adopt parallel structures, each correlation calculation unit is multiplexed in a time-sharing way, and the pseudo code phases distributed evenly are processed in a serial way.
Let the time required for the correlation computation unit to compute one pseudo code phase be T. Since the 6 detection codes (77 phases) are working in parallel and C6 has the largest period 23, the normalized total acquisition time of the system is equivalent to the normalized acquisition time of the detection code C6, here assuming the normalized acquisition time of C6 to be 23T. When the parallelism, i.e. the number of relevant computing units in the required code correlator is designed to be 2, 3 and 4, the ratio of the corresponding serialization, i.e. the number of subcode phases 77, to the number of relevant computing units is 39, 26 and 20, and the resource consumption and the capture time analysis are respectively carried out on the units:
as shown in fig. 1, in the structure with the parallelism of 39 and the serialization of 2, 39 correlation calculation units are required, and the theoretical acquisition time is about 39T.
As shown in fig. 2, in the structure with the parallelism of 26 and the serialization of 3, 26 correlation calculation units are needed, and the theoretical capture time is about 26T.
As shown in fig. 3, in the structure with 20 parallelism and 4 serialization, only 20 correlation calculation units are needed, and the theoretical capture time is about 20T.
The initial design of the regenerated pseudo code module in BepiColombo and the method of the invention are combined with resource optimization to design 550 Wan gate devices of Xilinx company, and the condition of the Slice resources consumed in the FPGA chip with the model of XQ4VSX55-10FF1148l is compared with that shown in the following table 1; the pseudo code module Slice resource consumption after resource optimization accounts for about 10% of the available resources of the chip.
Table 1 analysis of the design in BepiColombo and the resource consumption of the method of the invention
In summary, the present invention proposes a subcode parallel design method for reproducing a composite code for pseudo code ranging, in which a serial-parallel combination mode is adopted, a plurality of correlation calculation units adopt a full parallel structure, each correlation calculation unit is multiplexed in a time-sharing manner, and the pseudo code phases distributed on average are processed in a serial manner. Under the condition of the same resource consumption, the invention can effectively reduce the subcode capturing time. The invention can also save the consumption of the related calculation unit by increasing the subcode capturing time, achieves the balance of resource consumption and capturing time, and has great application value in deep space measurement and control communication.
The above description is merely of a preferred embodiment of the present invention, the present invention is not limited to the above embodiment, and minor structural modifications may exist in the implementation process, and if various modifications or variations of the present invention do not depart from the spirit and scope of the present invention and fall within the scope of the appended claims and the equivalent technology, the present invention is also intended to include such modifications and variations.
Claims (5)
1. A subcode parallel design method of a composite code for reproducing pseudo code ranging is characterized in that: the sub-code parallel design method is applied to a deep space probe satellite receiver, a regeneration pseudo code module of a digital baseband processing part of the satellite receiver realizes functions of capturing satellite pseudo codes and regenerating the pseudo codes, the basic structure of the regeneration pseudo code module comprises a code chip tracking ring, a sub-code correlation processing unit and a downlink code generator, the sub-code correlation processing unit comprises a code correlator, a code generator and a maximum value search decision device, the code correlator is provided with a correlation calculation unit, and the sub-code parallel design method specifically comprises the following steps:
step 1, tracking, demodulating and receiving clock component codes in a pseudo code sequence by the chip tracking loop;
step 2, the code generator generates each sub-code sequence with the same code phase as the clock component in the step 1;
step 3, the clock component code phase of the received pseudo code sequence is consistent with the clock component code phase of the locally generated 6 subcode sequences, 77 subcode phases of six subcodes of C1-C6 are integrated and considered, and the 77 subcode phases are distributed to a plurality of correlation calculation units in a code correlator on average to calculate subcode phases possibly belonging to different subcodes;
step 4, the 77 subcode phases of the six subcodes from C1 to C6 are accumulated for a plurality of times, the output value is detected by the maximum value searching and judging device, the phase corresponding to the maximum value of the six subcodes from C1 to C6 is determined, and then the 6 real-time phase values are output to calculate the phase of the composite code;
and 5, after the downlink code generator recovers according to the phases of the six sub-codes C1-C6, generating a sequence identical to the received pseudo code sequence and transmitting the sequence to a receiving station on the ground.
2. The sub-code parallel design method for reproducing the composite code of the pseudo-code ranging according to claim 1, wherein: in step 3, the subcode phases which may be classified into different subcodes are calculated by adopting a serial-parallel combination mode.
3. The sub-code parallel design method for reproducing the composite code of the pseudo-code ranging according to claim 2, wherein: in the step 3, the code correlator integrates 77 phases of six subcodes from C1 to C6, and designs a serial-parallel structure of a correlation calculation unit according to actual needs, and the method specifically comprises the following steps:
step 2-1, designing the serial-parallel degree, and determining the number of required related computing units;
step 2-2, integrating 77 phases of the six subcodes of C1 to C6 and sequencing;
step 2-3, evenly distributing 77 phases to each relevant computing unit in step 2-1;
and 2-4, performing parallel computation among the correlation computation units, multiplexing in a time-sharing manner in each correlation computation unit, and serially processing the sub-code phases distributed evenly.
4. The sub-code parallel design method for reproducing the composite code of the pseudo-code ranging according to claim 1, wherein: the peak detection of the maximum value searching and judging device in the step 4 specifically comprises the following steps: setting 6 decision thresholds, wherein the threshold values are the products of the phase accumulation times and the lengths of all the sub-codes of C1-C6, comparing the accumulated code correlator output values with the decision thresholds, outputting corresponding sub-code sequences if the accumulated code correlator output values are larger than the decision threshold values, and returning to the code correlator for processing operation again if the accumulated code correlator output values are smaller than the decision threshold values.
5. The sub-code parallel design method for reproducing the composite code of the pseudo-code ranging according to claim 1, wherein: in the step 1, the code pattern of the pseudo code sequence is T2B or T4B, the T2B code pattern and the T4B code pattern are formed by weighted combination of 6 component codes C1-C6, the weight of the clock component code C1 of the T2B code pattern is 2, and the weight of the clock component code C1 of the T4B code pattern is 4.
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