CN117331866A - Controller cache architecture - Google Patents

Abstract

The application relates to a controller cache architecture. An apparatus may include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized into a plurality of channel groups, and the memory controller includes respective independent caches corresponding to the plurality of channel groups.

Description

Controller cache architecture

PRIORITY INFORMATION

The present application claims the benefit of U.S. provisional application No. 63/357,553 filed on 6/30 of 2022, the contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates generally to semiconductor memory and methods, and in particular, to apparatus, systems, and methods for a controller cache architecture.

Background

Memory devices are typically provided as internal semiconductor integrated circuits in a computer or other electronic system. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.), and includes Random Access Memory (RAM), dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Nonvolatile memory may provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory, such as Phase Change Random Access Memory (PCRAM), resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), such as spin torque transfer random access memory (STT RAM), and the like.

The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and/or instructions for use by the host while the computer or electronic system is operating. For example, during operation of a computing or other electronic system, data, commands, and/or instructions may be transferred between a host and a memory device(s). The controller may be used to manage the transfer of data, commands, and/or instructions between the host and the memory device.

Disclosure of Invention

Aspects of the present disclosure provide an apparatus having a cache architecture, comprising: a plurality of memory devices; and a memory controller coupled to the plurality of memory devices via a plurality of memory channels; wherein the plurality of memory channels are organized into a plurality of channel groups; and wherein the memory controller includes respective independent caches corresponding to the plurality of channel groups.

Another aspect of the present disclosure provides a method for operating a controller cache architecture, comprising: receiving a memory access request at a memory controller; the memory access request is performed by: determining, based on an address corresponding to the memory access request, a particular cache corresponding to the address from a plurality of caches of the memory controller, wherein the plurality of caches correspond to respective channel groups, wherein each channel group comprises a respective memory channel group of a plurality of memory channels coupling a memory device to the memory controller; and a memory device accessing a corresponding memory channel in the channel group corresponding to the particular cache.

Another aspect of the present disclosure provides a memory controller having a cache architecture, comprising: a front end portion configured to couple to a host via an interface; a back end portion configured to be coupled to a plurality of memory devices via a plurality of memory channels, wherein the plurality of memory channels are organized into a plurality of channel groups; and a central portion comprising a plurality of independent caches, wherein each cache of the plurality of independent caches corresponds to a different one of the plurality of channel groups.

Drawings

FIG. 1 is a block diagram of a computing system including a memory controller according to several embodiments of the present disclosure.

FIG. 2 is a block diagram of a memory controller coupled to a plurality of memory devices.

Fig. 3 is a block diagram of a memory controller having a cache architecture according to several embodiments of the present disclosure.

Fig. 4 is a block diagram of a memory controller having a cache architecture according to several embodiments of the present disclosure.

Fig. 5 is a block diagram of a memory controller having a cache architecture according to several embodiments of the present disclosure.

FIG. 6 is a flow chart of a method for operating a memory controller having a cache architecture according to several embodiments of the present disclosure.

Detailed Description

Systems, devices, and methods related to memory controller cache architectures are described. The memory controller may be within a memory system, which may be a memory module, a storage device, or a mixture of memory modules and storage devices. In various embodiments, a memory controller may include a cache architecture that may be used to reduce access latency associated with accessing a memory device to which the memory controller is coupled. The memory controller may be coupled to a plurality of memory devices via a plurality of memory channels that may be organized into a plurality of channel groups. The memory controller may include respective independent caches corresponding to the plurality of channel groups. In various embodiments, the memory controller is configured to operate the plurality of channel groups as independent respective reliability, availability, and serviceability (RAS) channels.

In some previous approaches, a memory controller of a memory system may include an embedded cache that may provide benefits such as reduced latency if the system is in a relative "off-load" state. An unloaded state may refer to a state in which memory access request queues (e.g., read and/or write queues) within a memory system are empty or relatively empty. This reduced latency may be particularly beneficial where memory device technology has a relatively high access latency. However, as the workload (e.g., the number of access requests) increases, providing embedded caches within the memory controller may also result in increased latency. For example, an increased transfer rate from the host to the memory system may result in increased congestion associated with the access queue, which in turn may result in increased latency associated with operating the cache.

Various embodiments of the present disclosure provide a controller cache architecture that may provide benefits such as improved (e.g., reduced) latency as compared to existing approaches. Several embodiments include a memory controller having multiple caches that are independently operable to service separate non-overlapping physical address ranges. The cache architecture described herein may effectively and efficiently operate at a variety of host interface speeds and transfer rates.

As used herein, the singular forms "a," "an," and "the" include the singular and plural referents unless the context clearly dictates otherwise. Furthermore, the word "may" is used throughout this application in a permissive sense (i.e., having the potential to, being able to), rather than the mandatory sense (i.e., must). The term "include" and its derivatives mean "include, but are not limited to. The term "coupled" means directly or indirectly connected. It should be understood that data may be transmitted, received, or exchanged by electronic signals (e.g., current, voltage, etc.) and that the phrase "a signal indicative of data" means that the data itself is transmitted, received, or exchanged in a physical medium.

The figures herein follow a numbering convention in which the first or leading digit(s) correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Like elements or components between different figures may be identified by the use of like numerals. For example, 110 may refer to element "10" in FIG. 1, and similar elements may be labeled 310 in FIG. 3. Similar elements in the figures may be referred to by hyphens and additional numbers or letters. See, for example, elements 130-1, 130-2, 130-N in FIG. 1. Such similar elements may generally be referenced without hyphens and additional numbers or letters. For example, elements 130-1, 130-2, 130-N may be collectively referred to as 130. As used herein, the designators "M", "N" and "X" particularly with respect to the reference numerals in the drawings, indicate that a number of the particular features so designated may be included. As will be appreciated, elements shown in the various embodiments herein may be added, exchanged, and/or deleted to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

Fig. 1 is a block diagram of a computing system 101 including a memory controller 100 according to several embodiments of the present disclosure. The memory controller 100 includes a front end portion 104, a central controller portion 110, and a back end portion 119. The computing system 101 includes a host 103 coupled to a memory controller 100 and memory devices 130-1, …, 130-N. Computing system 101 may be, for example, a High Performance Computing (HPC) data center, as well as various other types of computing systems (e.g., servers, desktop computers, laptop computers, mobile devices, etc.).

Although not shown in fig. 1, the front end portion 104 may include a physical layer (PHY) and a front end controller for interfacing with the host 103 through the bus 102, which bus 102 may include a number of input/output (I/O) lanes. The bus 102 may include various combinations of data, address, and control buses, which may be separate buses or one or more combined buses. In at least one embodiment, the interface between memory controller 100 and host 103 may be a peripheral component interconnect express (PCIe) physical and electrical interface that operates according to a computing express link (CXL) protocol. As non-limiting examples, bus 102 may be a PCIe 5.0 interface operating according to the CXL 2.0 specification or a PCIe 6.0 interface operating according to the CXL 3.0 specification.

CXL is a high-speed Central Processing Unit (CPU) to device and CPU to memory interconnect designed to speed up next-generation data center performance. CXL technology maintains memory consistency between CPU memory space and memory on attached devices (e.g., accelerators, memory buffers, and smart I/O devices), which allows for resource sharing to achieve higher performance, lower software stack complexity, and lower overall system cost. CXLs are designed as industry open standard interfaces for high speed communications, as accelerators are increasingly used to supplement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on PCIe infrastructure, leveraging PCIe physical and electrical interfaces to provide advanced protocols in areas such as input/output (I/O) protocols, memory protocols (e.g., initially allowing hosts and accelerators to share memory), and coherence interfaces. CXL provides protocols with PCIe-like I/O semantics (e.g., cxl.io), cache protocol semantics (e.g., cxl.cache), and memory access semantics (cxl.mem).

The central controller 110 may be responsible for controlling various operations associated with performing memory access requests (e.g., read commands and write commands) from the host 103. For example, as described further below, the central controller 110 may include: cache 111, which may be implemented as multiple independent caches; and various error circuitry (e.g., error detection and/or error correction circuitry) capable of generating error detection and/or error correction data for providing data reliability associated with writing data to memory device 130 and/or reading data from memory device 130, as well as other RAS functionality. As further described herein, such error detection and/or correction circuitry may include, for example, cyclic Redundancy Check (CRC) circuitry, error Correction Code (ECC) circuitry, redundant Array of Independent Disks (RAID) circuitry, and/or "chip-erase" circuitry.

The back end portion 119 may include a number of memory channel controllers (e.g., media controllers) and a Physical (PHY) layer that couples the memory controller 100 to the memory device 130. As used herein, the term "PHY layer" generally refers to the physical layer in the Open Systems Interconnection (OSI) model of computing systems. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transfer data over a physical data transmission medium. In various embodiments, the physical data transmission medium includes memory channels 125-1, …, 125-N. Memory channel 125 may be, for example, a 16-bit channel each coupled to a 16-bit (e.g., x 16) device, two 8-bit (x 8) devices; although embodiments are not limited to a particular backend interface. As another example, lanes 125 may also each include a dual pin Data Mask Inversion (DMI) bus, as well as other possible bus configurations. The back-end portion 119 may exchange data (e.g., user data and error detection and/or correction data) with the memory device 130 via physical pins corresponding to the respective memory channels 125. As further described herein, in several embodiments, the memory channels 125 may be organized into several channel groups, with the memory channels of each group being accessed in association with performing various memory access operations and/or error detection and/or correction operations.

For example, memory device 130 may be a Dynamic Random Access Memory (DRAM) device that operates according to a protocol such as low power double data rate (LPDDRx), which may be referred to as an LPDDRx DRAM device, an LPDDRx memory, or the like. "x" in LPDDRx refers to any of the protocols (e.g., LPDDR 5). However, embodiments are not limited to a particular type of memory device 130. For example, the memory device 130 may be a FeRAM device.

In some embodiments, the memory controller 100 may include a management unit 134 to initialize, configure, and/or monitor characteristics of the memory controller 100. The management unit 134 may include an I/O bus to manage out-of-band data and/or commands, a management unit controller to execute instructions associated with initializing, configuring, and/or monitoring characteristics of the memory controller, and a management unit memory to store data associated with initializing, configuring, and/or monitoring characteristics of the memory controller 100. As used herein, the term "out-of-band" generally refers to a transmission medium that is different from the primary transmission medium of the network. For example, out-of-band data and/or commands may be data and/or commands transmitted to the network using a different transmission medium than that used to transmit data within the network.

Fig. 2 is a block diagram of a memory controller 200 coupled to a plurality of memory devices 230. As shown in fig. 2, the controller 200 includes a front end portion 204, a central portion 210, and a back end portion 219. The controller 200 may be a controller such as the controller 100 described in fig. 1.

The front end portion 204 includes a front end PHY 205 for interfacing with a host via a communication link 202, which may be, for example, a CXL link. The front end 204 includes a front end controller 206 to manage interfaces and communicate with a central controller 210. In embodiments in which link 202 is a CXL link, front-end controller 206 is configured to receive (e.g., from a host) memory access requests for memory device 230 in accordance with the CXL protocol.

The controller 200 is coupled to a memory device 230 via a number of memory channels 225. In this example, the memory channels 225 are organized into a number of channel groups 240-1, 240-2, …, 240-X. In this example, each channel group 240 includes "M" memory channels 225. For example, channel group 240-1 includes memory channels 225-1-1, 225-1-2, …, 225-1-M, channel group 240-2 includes memory channels 225-2-1, 225-2-2, …, 225-2-M, and channel group 240-X includes memory channels 225-X-1, 225-X-2, …, 225-X-M. Although each channel group is shown to include the same number of memory channels 225, embodiments are not so limited.

In this example, the back end portion 219 of the controller 200 includes a plurality of Memory Channel Controllers (MCCs) 228 for interfacing with memory devices 230 corresponding to respective memory channels 225. As shown in FIG. 2, the memory channel controllers 228-1-1, 228-1-2, …, 228-1-M corresponding to the channel group 240-1 are coupled to the memory device 230 via respective channels 225-1-1, 225-1-2, …, 225-1-M. Although not shown in fig. 2, backend 219 includes a PHY memory interface for coupling to memory device 230.

The respective channels 225 of the channel groups 240-1, 240-2, …, 240-X are operated together for the purpose of one or more RAS schemes. Thus, the channel group 240 may be referred to as a "RAS channel". In this example, the channel groups 240-1, 240-2, …, 240-X include respective error circuitry (RAS channel circuitry) 242-1, 242-2, …, 242-X. Error circuitry 242 may include various circuitry for error detection and/or error correction, which may include data recovery. Error circuitry 242 may also include CRC circuitry, ECC circuitry, RAID circuitry, and/or chip erasure circuitry, including various combinations thereof. The channel groups 240-1, 240-2, …, 240-X may be independently operated by the central controller 210 such that memory access requests and/or erroneous operations may be performed individually (and concurrently) on the memory devices 230 corresponding to the respective channel groups 240.

The term "chip delete" generally refers to a form of error correction that protects a memory system (e.g., memory system 101 shown in FIG. 1) from any single memory device 230 (chip) failure and multi-bit errors from any portion of a single memory chip. The chip delete circuitry may increase the stability of the data and collectively correct errors in the data with the desired chip delete protection across a subset of the memory devices 230 (e.g., corresponding to a subset of the respective channel groups 240).

An example chip delete implementation of a channel group 240 that includes eleven memory channels 225 (e.g., "M" =11) corresponding to a bus width of 176 bits (16 bits/channel×11 channels) may include memory devices 230 that write data to eight of the eleven memory channels 225 and write parity data to three of the eleven memory channels 225. Four codewords may be written, each consisting of eleven four-bit symbols, where each symbol belongs to a different channel/device. The first codeword may comprise a first four-bit symbol of each memory device 230, the second codeword may comprise a second four-bit symbol of each memory device 230, the third codeword may comprise a third four-bit symbol of each memory device 230, and the fourth codeword may comprise a fourth four-bit symbol of each memory device 230.

Three parity symbols may allow chip erasure circuitry (e.g., 242) to correct at most one symbol error and detect at most two symbol errors in each codeword. If only two parity symbols are added instead of three, then the chip erasure circuitry may correct at most one symbol error, but only one symbol error. In various embodiments, data symbols and parity symbols may be written or read concurrently from the memory devices of eleven channels (e.g., 225-1-1 through 225-1-11). If each bit symbol in the die fails, only the bit symbol in the codeword from that memory device 230 will fail. This allows the memory contents to be reconstructed despite the complete failure of one memory device 230. The foregoing chip delete operation is considered "correction in operation" because the data is corrected by performing the repair operation without affecting performance. The embodiments are not limited to the specific example chip delete operations described above. In contrast to chip delete operations, which may not involve repair operations, various RAID methods are considered "parity and recovery correction" because the repair process is initiated to recover the data subject to errors. For example, if an error in the sign of a RAID stripe is determined to be uncorrectable, the corresponding data may be recovered/reconstructed by reading the remaining user data of the stripe and xoring with the corresponding parity data of the stripe.

As shown in fig. 2, each of the channel groups 240 may include memory channel data path circuitry (mem_ch) 226 associated with a corresponding memory channel 225 of the particular channel group 240. For example, channel group 240-1 includes memory channel data path circuitry 226-1-1, 226-1-2, …, 226-1-M corresponding to respective channels 225-1-1, 225-1-2, …, 225-1-M. Similarly, channel group 240-2 includes memory channel data path circuitry 226-2-1, 226-2-2, …, 226-2-M corresponding to respective channels 225-2-1, 225-2-2, …, 225-2-M, and channel group 240-X includes memory channel data path circuitry 226-X-1, 226-X-2, …, 226-X-M corresponding to respective channels 225-X-1, 225-X-2, …, 225-X-M. The data path circuitry 226 may include error circuitry corresponding to error detection or error correction on a particular memory channel 225. For example, data path circuitry 226 may include CRC circuitry or ECC circuitry. That is, the error circuitry of the data path circuitry 226 may be associated with a particular memory channel 225 or dedicated to a particular memory channel 225 as compared to the error circuitry 242 that may be associated with multiple channels 225 within the channel group 240.

As shown in fig. 2, the central controller 210 may include a Media Management Layer (MML) 212 that may be used to translate memory access requests according to a particular protocol (e.g., CXL compliant requests) into a protocol that is compliant with a particular memory controller 200 and/or a particular type of memory media (e.g., memory device 230). The central controller 210 may also include a cache 211, which cache 211 may include an associated cache controller. The cache 211 may be used, for example, to temporarily store frequently accessed data (e.g., by a host).

The cache 211 may increase latency of memory operations depending on various factors such as transaction load, hit rate, etc. For example, the cache 211 may operate efficiently at a particular transfer rate (e.g., 32 GT/s) from the host; however, if the transfer rate from the host increases (e.g., to 64 GT/s) such that the clock speed corresponding to the cache 211 cannot keep pace with the increased transfer rate, the cache 211 may become a bottleneck. As another example, if the transfer rate between the front end 204 of the controller 200 and the host (e.g., host transfer rate) increases relative to the transfer rate between the front end 204 and the central controller 210, a memory access request queue (not shown) in the front end 204 and/or a cache lookup request queue (not shown) in the central controller 210 may become full or overloaded.

As described further below, various embodiments of the present disclosure may provide a cache architecture that may reduce adverse effects (e.g., adverse effects on latency) such as may be caused by increased host transfer rates. For example, as shown in fig. 3, 4, and 5, various embodiments may include providing multiple separate caches (e.g., per channel group) that may be operated independently (e.g., by a central controller) to service more memory access requests per unit time than a single cache (e.g., multiple cache lookup operations may be performed in parallel on caches of respective channel groups).

Fig. 3 is a block diagram of a memory controller 300 having a cache architecture according to several embodiments of the present disclosure. The memory controller 300 is similar to the memory controller 200 shown in FIG. 2, except that the cache 211 in FIG. 2 is replaced with a plurality of separate and independently operated caches 311-1, 311-2, …, 311-X corresponding to respective channel groups (e.g., RAS channels) 340-1, 340-2, …, 340-X.

Thus, as shown in fig. 3, the controller 300 includes a front end portion 304, a central portion 310, and a back end portion 319. The front end portion 304 includes a front end PHY 305 for interfacing with a host via a communication link 302, which may be, for example, a CXL link. The front end 304 includes a front end controller 306 to manage the interface and communicate with a central controller 310. In an embodiment in which link 302 is a CXL link, front-end controller 306 is configured to receive (e.g., from a host) memory access requests for memory device 330 in accordance with the CXL protocol.

The controller 200 is coupled to a memory device 330 via a number of memory channels 325. In this example, memory channel 325 is organized into a number of channel groups 340-1, 340-2, …, 340-X. In this example, each channel group 340 includes "M" memory channels 325. For example, channel group 340-1 includes memory channels 325-1-1, 325-1-2, …, 325-1-M, channel group 340-2 includes memory channels 325-2-1, 325-2-2, …, 325-2-M, and channel group 340-X includes memory channels 325-X-1, 325-X-2, …, 325-X-M.

The back end portion 319 of the controller 300 includes a plurality of Memory Channel Controllers (MCCs) 328 for interfacing with memory devices 330 corresponding to respective memory channels 325. As shown in FIG. 3, memory channel controllers 328-1-1, 328-1-2, …, 328-1-M corresponding to channel group 340-1 are coupled to memory device 330 via respective channels 325-1-1, 325-1-2, …, 325-1-M. Although not shown in fig. 3, the back end 319 includes a PHY memory interface for coupling to the memory device 330.

The respective tunnels 325 of the tunnel groups 340-1, 340-2, …, 340-X are operated together for the purpose of one or more RAS schemes. Thus, the channel group 340 may be referred to as a "RAS channel". In this example, the channel groups 340-1, 340-2, …, 340-X include respective error circuitry (RAS channel circuitry) 342-1, 342-2, …, 342-X. Error circuitry 342 may include various circuitry for error detection and/or error correction, which may include data recovery. Error circuitry 342 may also include CRC circuitry, ECC circuitry, RAID circuitry, and/or chip erasure circuitry, including various combinations thereof. The channel groups 340-1, 340-2, …, 340-X may be independently operated by the central controller 310 such that memory access requests and/or erroneous operations may be performed separately (and concurrently) on the memory devices 330 corresponding to the respective channel groups 340.

As shown in fig. 3, each of the channel groups 340 may include memory channel data path circuitry (mem_ch) 326 associated with a corresponding memory channel 325 of the particular channel group 340. For example, channel group 340-1 includes memory channel data path circuitry 326-1-1, 326-1-2, …, 326-1-M corresponding to respective channels 325-1-1, 325-1-2, …, 325-1-M. Similarly, channel group 340-2 includes memory channel data path circuitry 326-2-1, 326-2-2, …, 326-2-M corresponding to respective channels 325-2-1, 325-2-2, …, 325-2-M, and channel group 340-X includes memory channel data path circuitry 326-X-1, 326-X-2, …, 326-X-M corresponding to respective channels 325-X-1, 325-X-2, …, 325-X-M. Data path circuitry 326 may include error circuitry corresponding to error detection or error correction on a particular memory channel 325. For example, the data path circuitry 326 may include CRC circuitry or ECC circuitry. That is, the error circuitry of the data path circuitry 326 may be associated with a particular memory channel 325 or dedicated to a particular memory channel 325 as compared to the error circuitry 342 that may be associated with multiple channels 325 within the channel group 340.

As shown in fig. 3, the central controller 310 may include a Media Management Layer (MML) 312 that may be used to translate memory access requests according to a particular protocol (e.g., CXL compliant requests) into a protocol that is compliant with a particular memory controller 300 and/or a particular type of memory media (e.g., memory device 330).

The central controller 310 includes a plurality of caches 311-1, 311-2, …, 311-X corresponding to respective channel groups 340-1, 340-2, …, 340-X. The cache 311 includes an associated cache controller for independently operating the respective caches. Caches 311-1, 311-2, …, 311-X may be set-associative caches, for example. In various embodiments, the physical address regions associated with the caches 311 (e.g., assigned to the caches 311) do not overlap, which may ensure that all "X" caches 311 may access the memory device 330 concurrently.

A number of embodiments may include receiving a memory access request (e.g., a read or write request) from a host (e.g., host 103 shown in fig. 1) at the memory controller 300. The controller 300 may execute the memory access request by determining to which of the caches 311 the address corresponding to the access request corresponds. The controller may then use the corresponding cache (e.g., 311-1), RAS channel circuitry (e.g., 342-1), memory channel data path circuitry (e.g., 326-1-1, 326-1-2, …, 326-1-M), and back-end memory channel controllers (e.g., 328-1-2, …, 328-1-M) to access the corresponding memory device 330 via the corresponding memory channel (e.g., 325-1-1, 325-1-2, …, 325-1-M) to perform the access request.

Fig. 4 is a block diagram of a memory controller 400 having a cache architecture according to several embodiments of the present disclosure. Memory controller 400 illustrates an example implementation of a particular error detection/correction scheme. Thus, the memory controller 400 is similar to the memory controller 300 described in FIG. 3. Memory controller 400 is coupled to memory devices 430-1 through 430-16 via respective memory channels, such as channel 325 shown in FIG. 3. In this example, the memory channels are organized into two channel groups 440-1 and 440-2, the channel group 440-1 including memory channels corresponding to memory devices 430-1 through 430-8, the channel group 440-2 including memory channels corresponding to memory devices 430-9 through 430-16.

As illustrated in FIG. 4, each of the channel groups 440-1 and 440-2 has a separate cache (and associated cache controller) 411-1 and 411-2 designated. As described further below, channel groups 440-1 and 440-2 include respective corresponding error circuitry components 443-1 and 443-2, 445-1 and 445-2, 447-1 and 447-2. The channel groups 440-1 and 440-2 also include corresponding channel data path error circuitry. In this example, the channel data path circuitry includes CRC circuitry 426-1 through 426-8 corresponding to channel group 440-1 and CRC circuitry 426-9 through 426-16 corresponding to channel group 440-2.

The example memory controller 400 illustrated in FIG. 4 is configured to implement a RAID error recovery scheme separately across the two channel groups 440-1 and 440-2. For example, RAID stripes may be stored across memory devices 430-1 through 430-8, and individual RAID stripes may be stored across memory devices 430-9 through 430-16.

In this example, each channel group 440-1 and 440-2 includes a respective secure encryption component 443-1 and 443-2 (AES ENC/DEC), which secure encryption components 443-1 and 443-2 may be Advanced Encryption Standard (AES) encoders/decoders used, for example, to provide an additional level of security via encryption of data stored to the memory device 430. Each channel group 440-1 and 440-2 may also include a respective authenticity component 445-1 and 445-2 (MAC GEN/CHECK), which authenticity components 445-1 and 445-2 may be, for example, media Access Control (MAC) generators and verifiers for validating the authenticity of data. In various embodiments, central controller 410 may include a CRC component (e.g., as part of MML 412) configured to generate a check value prior to writing data to caches 411-1 and 411-2.

The channel groups 440-1 and 440-2 also include respective RAID engines 447-1 and 447-2 configured to generate and/or update RAID parity data in association with performing the memory access requests. As shown in FIG. 4, each channel group 440-1 and 440-2 includes a CRC component 426 to generate a check value for RAID encoded data before the RAID encoded data is written to the memory device 430 and to check when data is read from the memory device 430. If the CRC check fails, then RAID engines 447-1 and 447-2 may read other devices 430 corresponding to the stripe to recover the data.

The various components in fig. 4 are not described in detail as they are similar to the similar components described in fig. 3. For example, such components include 402, 404, 405, 406, and 419, which are similar to corresponding components in fig. 3.

Fig. 5 is a block diagram of a memory controller 500 having a cache architecture according to several embodiments of the present disclosure. Memory controller 500 illustrates an example implementation of a particular error detection/correction scheme. Thus, the memory controller 500 is similar to the memory controller 300 described in FIG. 3. Memory controller 500 is coupled to memory devices 530-1 through 530-16 via respective memory channels, such as channel 325 shown in FIG. 3. In this example, the memory channels are organized into three channel groups 540-1, 540-2, and 540-3. Channel group 540-1 includes memory channels corresponding to memory devices 530-1 through 530-5, channel group 540-2 includes memory channels corresponding to memory devices 530-6 through 530-10, and channel group 530-3 includes memory channels corresponding to memory devices 530-11 through 530-15.

As illustrated in FIG. 5, each of the channel groups 540-1, 540-2, and 540-3 has a separate cache (and associated cache controller) 511-1, 511-2, and 511-3 designated. As described further below, channel groups 540-1, 540-2, and 540-3 include respective corresponding error circuitry components 543-1, 543-2, and 543-3, 545-1, 545-2, and 545-3, and 549-1, 549-2, and 549-3. The channel groups 540-1, 540-2, and 540-3 also include corresponding channel data path error circuitry. In this example, the channel datapath circuitry includes ECC circuitry 526-1 through 526-5 corresponding to channel group 540-1, ECC circuitry 526-6 through 526-10 corresponding to channel group 540-2, and ECC circuitry 526-11 through 526-15 corresponding to channel group 540-3.

The example memory controller 500 illustrated in FIG. 5 is configured to implement a "run-time" chip erasure correction scheme separately and independently across the three channel groups 540-1, 540-2, and 540-3. For example, considering a 16-bit channel width, separate 80-bit ECC codewords (16 bits by 5 channels) may be written to memory devices 530-1 through 530-5, 530-6 through 530-10, and 530-11 through 530-15.

Similar to the example provided in FIG. 4, in this example, each channel group 540-1, 540-2, and 540-3 includes a respective secure encryption component 543-1, 543-2, and 543-3 (AES ENC/DEC), which may be an Advanced Encryption Standard (AES) encoder/decoder, for example, that is used to provide an additional level of security via encryption of data stored to the memory device 530. Each channel group 540-1, 540-2, and 540-3 may also include a respective authenticity component 545-1, 545-2, and 545-3 (MAC GEN/CHECK), which may be, for example, a Media Access Control (MAC) generator and verifier for validating the authenticity of data. In various embodiments, central controller 510 may include a CRC component (e.g., as part of MML 512) configured to generate a check value prior to writing data to caches 511-1, 511-2, and 511-3.

The channel groups 540-1, 540-2, and 540-3 also include respective chip deletion engines 549-1, 549-2, and 549-3 configured to encode and decode ECC codewords in association with memory access requests (e.g., from a host). As shown in FIG. 5, each channel group 540-1, 540-2, and 540-3 includes an ECC component 526 of ECC data used to generate ECC codewords.

The various components in fig. 5 are not described in detail as they are similar to the similar components described in fig. 3 and 4. For example, such components include 502, 504, 505, 506, and 519, which are similar to corresponding components in fig. 3.

FIG. 6 is a flow chart of a method for operating a memory controller having a cache architecture according to several embodiments of the present disclosure. The methods described herein may be performed by processing logic that may comprise hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. Although shown in a particular order or sequence, the sequence of processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not every embodiment requires all procedures. Other process flows are also possible.

At block 692, the method includes receiving a memory access request (e.g., a read access request or a write access request) at a memory controller (e.g., memory controller 100, 200, 300, 400, 500). At block 694, the method includes executing a memory access request. The memory access request may be performed by determining a particular cache of the plurality of caches of the memory controller (e.g., caches 311-1, 311-2, …, 311-X;411-1, 411-2) that corresponds to the address based on the address corresponding to the memory access request. The plurality of caches may correspond to respective channel groups (e.g., 240-1, 240-2, …, 240-X;340-1, 340-2, …, 340-X;440-1, 440-2;540-1, 540-2, 540-3), where each channel group includes a respective group of memory channels coupling the memory device to the memory controller. The method may include accessing a memory device (e.g., 230, 430, etc.) of a corresponding memory channel corresponding to a particular cache in the channel group.

The plurality of caches corresponds to respective channel groups, wherein each channel group includes a respective memory channel group of a plurality of memory channels coupling the memory device to the memory controller. In this way, multiple caches may be operated (e.g., accessed) in parallel, thereby reducing latency that may occur when only a single cache is used to service all memory channels.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative manner, and not a restrictive one. Combinations of the above embodiments, and other embodiments not explicitly described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. The scope of one or more embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

In the foregoing detailed description, for the purpose of simplifying the disclosure, some features are grouped together in a single embodiment. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims (15)

1. An apparatus having a cache architecture, comprising:

a plurality of memory devices (130-1, …, 130-N; 330); a kind of electronic device with high-pressure air-conditioning system

A memory controller (100; 300;400; 500) coupled to a plurality of memory devices via a plurality of memory channels (125-1, …, 125-N);

wherein the plurality of memory channels are organized into a plurality of channel groups (340-1, 340-2, 340-X;440-1, 440-2;540-1, 540-2, 540-3); and is also provided with

Wherein the memory controller includes respective independent caches (311-1, 311-2, 311-X;411-1, 411-2;511-1, 511-2, 511-3) corresponding to the plurality of channel groups.

2. The apparatus of claim 1, wherein the plurality of channel groups comprise:

a first channel group comprising a first number of the plurality of memory channels; a kind of electronic device with high-pressure air-conditioning system

A second channel group comprising a second number of the plurality of memory channels;

wherein the first group of channels includes first error correction circuitry (342-1) operated by the memory controller in association with accessing memory devices corresponding to the first number of the plurality of memory channels; and is also provided with

Wherein the second group of channels includes second error correction circuitry (342-2) operated by the memory controller and independent of the first error correction circuitry, in association with accessing memory devices corresponding to the second number of the plurality of memory channels.

3. The apparatus of claim 2, wherein the plurality of channel groups comprises:

a third channel group comprising a third number of the plurality of memory channels; and is also provided with

Wherein the third group of channels includes third error correction circuitry (342-X) operated by the memory controller and independent of the first and second error correction circuitry, in association with accessing memory devices corresponding to the third number of the plurality of memory channels.

4. A device according to any one of claims 1 to 3, wherein the memory controller comprises a front-end portion (104; 304;404; 504) comprising a CXL controller coupled to a host (103) via a computational fast link, CXL, link.

5. The apparatus of any one of claims 1-3, wherein the memory controller comprises at least three independent caches corresponding to respective channel groups, and wherein each respective channel group comprises at least two memory channels of the plurality of memory channels.

6. The apparatus of any one of claims 1-3, wherein the respective independent caches correspond to different non-overlapping physical address ranges corresponding to the plurality of memory devices.

7. The apparatus of any one of claims 1-3, wherein the memory controller is configured to operate the plurality of channel groups as independent respective reliability, availability, and serviceability RAS channels.

8. The apparatus of claim 7, wherein the memory controller is configured to implement one of a chip erasure error correction scheme and a RAID error recovery scheme per RAS channel.

9. A method for operating a controller cache architecture, comprising:

receiving a memory access request at a memory controller (100; 300;400; 500);

the memory access request is performed by:

based on an address corresponding to the memory access request, determining a particular cache of a plurality of caches (311-1, 311-2, 311-X;411-1, 411-2;511-1, 511-2, 511-3) of the memory controller to which the address corresponds, wherein the plurality of caches correspond to respective channel groups (340-1, 340-2, 340-X;440-1, 440-2;540-1, 540-2, 540-3), wherein each channel group includes a plurality of memory channels (125-1, …, 330) coupling a memory device (130-1, …, 130-N; 330) to the memory controller,

125-N) is provided; a kind of electronic device with high-pressure air-conditioning system

A memory device of a corresponding memory channel corresponding to the particular cache in the channel group is accessed.

10. The method of claim 9, further comprising accessing the memory devices of corresponding memory channels corresponding to the particular cache in the channel group in parallel.

11. The method of claim 9, further comprising operating the plurality of caches independently.

12. The method of any one of claims 9-11, wherein the respective channel groups include respective independent error correction circuits corresponding thereto.

13. A memory controller having a cache architecture, comprising:

a front end portion (104; 204;304;404; 504) configured to communicate with the interface (102; 202;302;402;

502 Coupled to the host;

a back end portion (119; 219;419; 519) configured to be coupled to a plurality of memory devices (130-1, …, 130-N; 330) via a plurality of memory channels (125-1, …, 125-N), wherein the plurality of memory channels are organized into a plurality of channel groups (340-1, 340-2, 340-X;440-1, 440-2;540-1, 540-2, 540-3); a kind of electronic device with high-pressure air-conditioning system

A central portion (110; 210;310;410; 510) includes a plurality of independent caches (311-1, 311-2, 311-X;411-1, 411-2;511-1, 511-2, 511-3), wherein each cache of the plurality of independent caches corresponds to a different one of the plurality of channel groups.

14. The memory controller of claim 13, wherein for each respective channel group, the central portion includes:

first error circuitry configured to implement error detection/correction across the plurality of memory channels corresponding to the respective channel group; a kind of electronic device with high-pressure air-conditioning system

Second error circuitry configured to implement error detection/correction per memory channel.

15. The memory controller of claim 14, wherein the first error circuitry implements a redundant array of independent disks RAID error correction scheme, and wherein the second error circuitry implements an error correction code ECC scheme or a cyclic redundancy check CRC scheme.