CN117316253B - Chip testing method, testing system, processor and memory medium - Google Patents
Chip testing method, testing system, processor and memory medium Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 214
- 238000012544 monitoring process Methods 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 35
- 238000004458 analytical method Methods 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 18
- 238000010998 test method Methods 0.000 claims abstract description 11
- 230000008859 change Effects 0.000 claims description 15
- 238000012545 processing Methods 0.000 claims description 6
- 238000013101 initial test Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 claims description 3
- 238000013100 final test Methods 0.000 claims description 3
- 238000001514 detection method Methods 0.000 abstract description 5
- 238000012423 maintenance Methods 0.000 abstract description 4
- 238000005192 partition Methods 0.000 abstract description 4
- 238000007405 data analysis Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 238000013102 re-test Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- 238000012795 verification Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a chip testing method, a testing system, a processor and a memory medium, which comprise the steps of writing first testing data into memory units of a chip, adjusting written and read register indexes according to a first rule in the testing process, dividing the chip into a plurality of unit areas, and respectively testing to generate a first testing result; monitoring the temperature of the chip in real time to generate a first monitoring result; inputting second test data into the target area to generate a second monitoring result; comprehensively analyzing to obtain a final analysis result; according to the test method, the temperature of each partition is monitored in real time, and the target area can be reconfirmed by adopting secondary test, so that the problem area can be more accurately positioned and identified, the fixed-point maintenance is facilitated, the problem positioning is more sensitive and accurate by setting two thresholds, the reliability of the test is greatly enhanced, the performance of the chip is more comprehensively and accurately tested, and the accuracy of the detection result is improved.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a chip testing method, a testing system, a processor, and a memory medium.
Background
The chip, also called microcircuit, microchip, integrated circuit (integrated circuit), refers to a silicon chip containing integrated circuit, has small volume, and the chip is an indispensable component in computer hardware, which plays an important role in the overall performance and function of the device. To ensure chip quality, performance testing is typically performed on the chip.
The test method of the chip in the prior art needs to test each memory unit one by one, including writing time, reading time, communication time and programming time, traverse each memory unit and meet the time requirements of various different operations, and particularly in the case of mass production test, the test method can cause a great deal of time consumption, and is difficult to meet the requirement of rapid production; one method is to use parallel test to operate multiple memory units at the same time, which has high requirements on the computing and processing capacity of the computer; the two modes have the defects that the test information of each unit cannot be accurately positioned, the test precision is affected, the accuracy is low, and the fixed-point maintenance is inconvenient.
In view of this, an improvement of the chip testing method in the prior art is needed to solve the technical problem of lower testing accuracy.
Disclosure of Invention
The invention aims to provide a chip testing method, a testing system, a processor and a memory medium, which solve the technical problems.
To achieve the purpose, the invention adopts the following technical scheme:
a method of chip testing, comprising:
writing first test data into a memory unit of the chip, and adjusting the written and read register indexes according to a first rule in the test process; the first rule is to increase a delay index from a minimum step-by-step until the register index reaches a standard register index;
dividing the chip into a plurality of unit areas, and respectively testing to generate a first test result; each region is tested by adopting different binary sequences;
in the testing process, monitoring the temperature of the chip in real time to generate a first monitoring result; if the temperature of any unit area is increased to a first threshold value, marking the corresponding unit area as a target area;
inputting second test data into the target area to generate a second monitoring result; if the temperature of the target area rises to a second threshold value, determining the corresponding unit area as a problem area; if the temperature of the target area is between the first threshold value and the second threshold value, testing the next unit area;
and carrying out comprehensive analysis according to the first test result, the first monitoring result and the second monitoring result to determine the final analysis result of the chip.
Optionally, writing first test data into the memory unit of the chip, and adjusting the written and read register indexes according to a first rule in the test process; the method specifically comprises the following steps:
writing preset first test data into each memory unit of the chip;
during the test, the written-in and read-out register indexes are adjusted according to a defined first rule;
after the register index is adjusted, reading test data from the memory unit, and verifying the read first test data;
and continuing the recording and testing of the next round, gradually adjusting the register index, and performing the writing and reading testing of the new round until the register index reaches the preset standard register index.
Optionally, the chip is divided into a plurality of unit areas, and the unit areas are respectively tested to generate a first test result; the method specifically comprises the following steps:
dividing a chip into a plurality of unit areas;
writing specific first test data into each identified unit area, and then reading and verifying the first test data;
after each unit area test is executed, a corresponding group of associated test results are generated;
and setting a second rule to record and sort each group of associated test results to form a first test result.
Optionally, in the testing process, monitoring the temperature of the chip in real time to generate a first monitoring result; the method specifically comprises the following steps:
in the testing process, a temperature sensor is used for carrying out real-time temperature monitoring on the chip; wherein the temperature sensor covers the whole surface of the chip;
recording the temperature information of each memory unit area monitored in real time into a first monitoring result;
when the temperature of any cell region rises to a preset first threshold, this region is marked as a target region.
Optionally, inputting second test data into the target area to generate a second monitoring result; the method specifically comprises the following steps:
inputting specific second test data to the target area, wherein the second test data comprises fault and abnormal test data;
continuously monitoring the temperature change of the target area in real time after the second test data are input;
recording real-time temperature information of the target area after the second test data is input, and forming a second monitoring result;
if the temperature of the target area is between the first threshold value and the second threshold value, testing the next unit area; if the temperature of the target area is monitored to rise to the second threshold value, determining the target area as a problem area;
further analyzing, testing or repairing the problem area; and continues testing the next cell area.
Optionally, the performing comprehensive analysis according to the first test result, the first monitoring result, and the second monitoring result to determine a final analysis result of the chip specifically includes:
collecting the first test data, the first monitoring result and the second monitoring result into a data set;
analyzing the first test data to obtain the basic performance and working condition of the chip in the initial test stage;
and comparing the temperature change of the target area when the first test and the second test are performed by combining the first monitoring result and the second monitoring result.
Optionally, combining the first monitoring result and the second monitoring result, and comparing the temperature change of the target area when the first test and the second test are performed; and then further comprises:
according to the data, the change trend of the unit area of the chip is found out;
comprehensively analyzing the first test data, the first monitoring result, the second monitoring result and the change trend to find out the overall performance of the chip and predict the existing problems;
based on the comprehensive analysis, obtaining a final test result of the chip;
and sorting the final analysis result into a preset data icon.
The invention also provides a test system, which is applied to the chip test method, and comprises the following steps:
a temperature sensor for detecting the temperature of each unit area of the chip;
the data processing module is used for analyzing the first test result, the first monitoring result and the second monitoring result;
the memory module is used for memorizing the first test data and the second test data;
and the control module is used for controlling the test system to run.
The invention also provides a processor, which comprises a memory and at least one processor, wherein the memory stores instructions;
the processor invokes the instructions in the memory to cause the processor to perform the chip test method as described above.
The invention also provides a memory medium, wherein the memory medium is internally provided with instructions, and the instructions are used for realizing the chip testing method.
Compared with the prior art, the invention has the following beneficial effects: writing the first test data into the memory unit of the chip, and gradually increasing the delay index from the minimum value according to a first rule until the register index reaches the standard register index; dividing the chip into a plurality of unit areas, and independently testing each unit area by using different binary sequences to generate a first test result; dividing the chip into a plurality of unit areas, independently testing each area by using different binary sequences to generate a first test result, obtaining a first monitoring result and a second monitoring result by temperature detection of the unit areas and adjustment of first test data, and comprehensively analyzing to determine a final chip test result; the test method monitors the temperature of each partition in real time, reconfirms the target area by adopting secondary test, not only can locate and identify the problem area more accurately, but also can ensure that the unit area with the problem is convenient for fixed-point maintenance.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.
The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and are not intended to limit the scope of the invention, since any modification, variation in proportions, or adjustment of the size, etc. of the structures, proportions, etc. should be considered as falling within the spirit and scope of the invention, without affecting the effect or achievement of the objective.
FIG. 1 is a flow chart of a chip testing method according to the first embodiment;
FIG. 2 is a second flow chart of the chip testing method according to the first embodiment;
fig. 3 is a third flow chart of the chip testing method according to the first embodiment.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. It is noted that when one component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
Embodiment one:
referring to fig. 1 to 3, an embodiment of the present invention provides a chip testing method, including:
s1, writing first test data into a memory unit of a chip, and adjusting the written and read register indexes according to a first rule in the test process; the first rule is to increase the delay index from the minimum step-by-step until the register index reaches the standard register index;
s2, dividing the chip into a plurality of unit areas, and respectively testing to generate a first test result; each region is tested by adopting different binary sequences;
s3, monitoring the temperature of the chip in real time in the test process, and generating a first monitoring result; if the temperature of any unit area is increased to a first threshold value, marking the corresponding unit area as a target area;
s4, inputting second test data into the target area to generate a second monitoring result; if the temperature of the target area is increased to the second threshold value, determining the corresponding unit area as a problem area; if the temperature of the target area is between the first threshold value and the second threshold value, testing the next unit area;
s5, comprehensively analyzing according to the first test result, the first monitoring result and the second monitoring result to determine a final analysis result of the chip.
The working principle of the invention is as follows: writing the first test data into the memory unit of the chip, and gradually increasing the delay index from the minimum value according to a first rule until the register index reaches the standard register index; dividing the chip into a plurality of unit areas, and independently testing each unit area by using different binary sequences to generate a first test result; dividing the chip into a plurality of unit areas, independently testing each area by using different binary sequences to generate a first test result, obtaining a first monitoring result and a second monitoring result by temperature detection of the unit areas and adjustment of first test data, and comprehensively analyzing to determine a final chip test result; compared with the chip testing method in the prior art, the method has the advantages that the temperature of each partition is monitored in real time, the target area can be reconfirmed by adopting the secondary test, the problem area can be positioned and identified more accurately, the unit area with the problem is convenient for fixed-point maintenance, the problem positioning is more sensitive and accurate by setting two thresholds, the reliability of the test is greatly enhanced, meanwhile, the performance of the chip can be tested more comprehensively and accurately by dynamically adjusting the index of the register and testing the partition, and the accuracy of the detection result is improved.
In this embodiment, step S1 specifically includes:
s11, writing preset first test data into each memory unit of the chip;
in the initialization stage, writing preset first test data into each memory unit of the chip; these data may be specific, preset, or randomly generated for comparison with expected results during subsequent reading and testing.
S12, in the test process, the written-in and read-out register indexes are adjusted according to a defined first rule;
once the first test data is written to the memory cells of the chip, the test process begins; in this process, the written and read register indices are adjusted according to a defined "first rule"; this rule directs how the index value of the register is changed and set to control the timing of data access and transfer; the rule definition steps up the delay index of the register from the minimum until the register index reaches a preset "standard register index". This method allows a series of tests to be performed to test the performance of the chip under different delay conditions.
S13, after the register index is adjusted, reading test data from the memory unit, and verifying the read first test data;
the verification content may be data consistency, such as whether the data matches the written first test data, or time performance, such as whether the time required to read the data is within a preset acceptable range. All test results will be recorded for subsequent comprehensive analysis.
And S14, continuing to record and test for the next round, gradually adjusting the register index, and performing a new round of writing and reading test until the register index reaches a preset standard register index. In the whole process, the test condition is continuously monitored and recorded, and data is provided for subsequent analysis and evaluation.
In this embodiment, step S2 specifically includes:
s21, dividing the chip into a plurality of unit areas;
these cell areas may be divided based on the physical structure of the chip, or based on a data access/read mode or the like. The basis of the specific division can be determined according to the actual application and the chip characteristics.
S22, writing specific first test data into each identified unit area, and then reading and verifying the first test data;
the first test data may further include evaluating access time and stability of the memory unit; these tests may be tailored to the characteristics of the desired area and the intended test targets.
S23, after each unit area test is executed, a corresponding group of associated test results are generated;
the associated test result data may include the specific results (e.g., read-write speed, data integrity, etc.) of each test, as well as any anomalies or errors that may occur with the test; all of these data are collectively referred to as the first test result.
S24, setting a second rule to record and sort each group of associated test results to form a first test result.
The test results of the unit areas can be conveniently compared, and data analysis can be facilitated after the whole test is completed.
In this embodiment, step S3 specifically includes:
s31, in the testing process, a temperature sensor is used for monitoring the temperature of the chip in real time; wherein, the temperature sensor covers the whole surface of the chip;
there is a significant gap in the temperature of the chip in different areas and environments, so real-time and careful monitoring is very critical.
S32, recording the temperature information of each memory unit area monitored in real time into a first monitoring result;
the first monitoring result can analyze the working state of each memory unit under different testing conditions and is also used for subsequent threshold judgment and data analysis.
S33, when the temperature of any cell region rises to a preset first threshold value, this region is marked as a target region.
The first threshold is preset based on the highest operating temperature limit acceptable to the chip and safety, and once the temperature reaches this threshold, the area may be problematic or excessively hot.
When the target areas are marked, the target areas can be used for subsequent retests or detailed analysis, so that the problems of the target areas are ensured to be further analyzed; therefore, the quality of the product can be ensured, and the failure of the memory unit caused by the overhigh temperature can be prevented.
In this embodiment, step S4 specifically includes:
s41, inputting specific second test data to the target area, wherein the second test data comprise fault and abnormal test data;
after confirming that a certain cell area is a target area, specific second test data is input thereto. This set of data may be different from the data used for the initial test in order to further challenge the performance of the cell area or to make more extensive detection for a particular problem.
S42, continuously monitoring the temperature change of the target area in real time after the second test data are input;
s43, recording real-time temperature information of the target area after the second test data is input, and forming a second monitoring result;
s44, if the temperature of the target area is between the first threshold value and the second threshold value, testing the next unit area; if the temperature of the target area is monitored to rise to the second threshold value, determining the target area as a problem area;
s45, further analyzing, testing or repairing the problem area; and continues testing the next cell area.
In this embodiment, step S5 specifically includes:
s51, collecting the first test data, the first monitoring result and the second monitoring result into a data set; ensuring that all data is complete and ordered in the order in which it was generated.
S52, analyzing the first test data to obtain the basic performance and working condition of the chip in the initial test stage; this includes, but is not limited to, the read-write speed, stability of the data.
S53, combining the first monitoring result and the second monitoring result, and comparing the temperature change of the target area when the first test and the second test are performed;
s54, according to the data, the change trend of the unit area of the chip is found out; for example, whether the temperature of a certain cell area always rises under a certain specific operation; whether a particular data pattern causes a temperature rise;
s55, comprehensively analyzing the first test data, the first monitoring result, the second monitoring result and the change trend to find out the overall performance of the chip and predict the existing problems;
s56, obtaining the final test result of the chip based on comprehensive analysis. The result may be a rating, a performance indicator, or a simple pass, fail judgment.
S57, sorting the final analysis result into a preset data icon. For further decision making or action by the relevant personnel or departments.
Embodiment two:
the invention also provides a test system, which is applied to the chip test method as in the first embodiment, and comprises the following steps:
a temperature sensor for detecting the temperature of each unit area of the chip; in the testing process, the sensor monitors and records the temperature change of each area on the chip in real time, and provides key data for subsequent analysis and judgment.
The data processing module is used for analyzing the first test result, the first monitoring result and the second monitoring result; to find out possible problems or deficiencies; this module employs techniques of preset algorithms, exemplified by machine learning or data mining, to more accurately find possible trends and patterns.
The memory module is used for memorizing the first test data and the second test data;
the control module is used for controlling the test system to run; the system is responsible for the operation of the whole system, and guides the temperature sensor, the data processing module and the memory module to perform corresponding operation; based on a preset test plan and data collected in real time, the control module can adjust the testing steps and parameters according to the needs;
it should be noted that, the system can accurately monitor the temperature of each unit area and generate corresponding test data, which is helpful for accurately identifying and locating possible problems; through complex analysis of the data processing module, potential problem trends or structural problems can be found; through the control module, the system can automatically run, and the test plan can be adjusted according to real-time data and analysis results, so that the efficiency and the accuracy are improved, problems can be found and processed in time, the working performance and the stability of the chip can be effectively ensured, and the overall quality and the reliability of the chip are finally improved.
Embodiment III:
the invention also provides a processor, which comprises a memory and at least one processor, wherein the memory stores instructions;
the processor invokes instructions in the memory to cause the processor to perform the chip test method as in embodiment one.
Embodiment four:
the invention also provides a memory medium, and the memory medium is internally provided with instructions for realizing the chip testing method as in the first embodiment.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A method of testing a chip, comprising:
writing first test data into a memory unit of the chip, and adjusting the written and read register indexes according to a first rule in the test process; the first rule is to increase a delay index from a minimum step-by-step until the register index reaches a standard register index;
dividing the chip into a plurality of unit areas, and respectively testing to generate a first test result; each region is tested by adopting different binary sequences;
in the testing process, monitoring the temperature of the chip in real time to generate a first monitoring result; if the temperature of any unit area is increased to a first threshold value, marking the corresponding unit area as a target area;
inputting second test data into the target area to generate a second monitoring result; if the temperature of the target area rises to a second threshold value, determining the corresponding unit area as a problem area; if the temperature of the target area is between the first threshold value and the second threshold value, testing the next unit area;
according to the first test result, the first monitoring result and the second monitoring result, comprehensive analysis is carried out to determine a final analysis result of the chip;
in the testing process, monitoring the temperature of the chip in real time to generate a first monitoring result; the method specifically comprises the following steps:
in the testing process, a temperature sensor is used for carrying out real-time temperature monitoring on the chip; wherein the temperature sensor covers the whole surface of the chip;
recording the temperature information of each memory unit area monitored in real time into a first monitoring result;
when the temperature of any cell region rises to a preset first threshold, this region is marked as a target region.
2. The method of claim 1, wherein first test data is written into memory cells of the chip, and the written and read register indexes are adjusted according to a first rule during the test; the method specifically comprises the following steps:
writing preset first test data into each memory unit of the chip;
during the test, the written-in and read-out register indexes are adjusted according to a defined first rule;
after the register index is adjusted, reading test data from the memory unit, and verifying the read first test data;
and continuing the recording and testing of the next round, gradually adjusting the register index, and performing the writing and reading testing of the new round until the register index reaches the preset standard register index.
3. The method for testing a chip according to claim 1, wherein the chip is divided into a plurality of unit areas, and the unit areas are tested respectively to generate a first test result; the method specifically comprises the following steps:
dividing a chip into a plurality of unit areas;
writing specific first test data into each identified unit area, and then reading and verifying the first test data;
after each unit area test is executed, a corresponding group of associated test results are generated;
and setting a second rule to record and sort each group of associated test results to form a first test result.
4. The chip testing method according to claim 1, wherein second test data is input to the target area to generate a second monitoring result; the method specifically comprises the following steps:
inputting specific second test data to the target area, wherein the second test data comprises fault and abnormal test data;
continuously monitoring the temperature change of the target area in real time after the second test data are input;
recording real-time temperature information of the target area after the second test data is input, and forming a second monitoring result;
if the temperature of the target area is between the first threshold value and the second threshold value, testing the next unit area; if the temperature of the target area is monitored to rise to the second threshold value, determining the target area as a problem area;
further analyzing, testing or repairing the problem area; and continues testing the next cell area.
5. The method for testing a chip according to claim 1, wherein the performing comprehensive analysis according to the first test result and the first and second monitoring results to determine a final analysis result of the chip specifically includes:
collecting the first test data, the first monitoring result and the second monitoring result into a data set;
analyzing the first test data to obtain the basic performance and working condition of the chip in the initial test stage;
and comparing the temperature change of the target area when the first test and the second test are performed by combining the first monitoring result and the second monitoring result.
6. The method of claim 5, wherein the first monitoring result and the second monitoring result are combined to compare a temperature change of the target area when the first test and the second test are performed; and then further comprises:
according to the data, the change trend of the unit area of the chip is found out;
comprehensively analyzing the first test data, the first monitoring result, the second monitoring result and the change trend to find out the overall performance of the chip and predict the existing problems;
based on the comprehensive analysis, obtaining a final test result of the chip;
and sorting the final analysis result into a preset data icon.
7. A test system, applied to the chip test method according to any one of claims 1 to 6, comprising:
a temperature sensor for detecting the temperature of each unit area of the chip;
the data processing module is used for analyzing the first test result, the first monitoring result and the second monitoring result;
the memory module is used for memorizing the first test data and the second test data;
and the control module is used for controlling the test system to run.
8. A processor, comprising a memory and at least one processor, wherein instructions are stored in the memory;
the processor invokes the instructions in the memory to cause the processor to perform the chip test method of any one of claims 1 to 6.
9. A memory medium, wherein instructions are stored on the memory medium, and the instructions are used to implement the chip testing method according to any one of claims 1 to 6.
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| US6230290B1 (en) * | 1997-07-02 | 2001-05-08 | International Business Machines Corporation | Method of self programmed built in self test |
| CN106017727A (en) * | 2016-05-16 | 2016-10-12 | 合肥市芯海电子科技有限公司 | Multi-chip temperature testing and calibrating system and method |
| CN114203253A (en) * | 2021-11-30 | 2022-03-18 | 青岛信芯微电子科技股份有限公司 | Chip memory fault repair device and chip |
| CN116256621A (en) * | 2023-05-15 | 2023-06-13 | 中诚华隆计算机技术有限公司 | Method and device for testing core particle, electronic equipment and storage medium |
| CN116955027A (en) * | 2023-06-28 | 2023-10-27 | 上海格州微电子技术有限公司 | MCU chip test system and test method thereof |
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| KR102477268B1 (en) * | 2018-01-26 | 2022-12-13 | 삼성전자주식회사 | Method and system to monitor information of memory module in real time |
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| US6230290B1 (en) * | 1997-07-02 | 2001-05-08 | International Business Machines Corporation | Method of self programmed built in self test |
| CN106017727A (en) * | 2016-05-16 | 2016-10-12 | 合肥市芯海电子科技有限公司 | Multi-chip temperature testing and calibrating system and method |
| CN114203253A (en) * | 2021-11-30 | 2022-03-18 | 青岛信芯微电子科技股份有限公司 | Chip memory fault repair device and chip |
| CN116256621A (en) * | 2023-05-15 | 2023-06-13 | 中诚华隆计算机技术有限公司 | Method and device for testing core particle, electronic equipment and storage medium |
| CN116955027A (en) * | 2023-06-28 | 2023-10-27 | 上海格州微电子技术有限公司 | MCU chip test system and test method thereof |
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