CN117311080B - Method, device and medium for splitting layout pattern - Google Patents
Method, device and medium for splitting layout pattern Download PDFInfo
- Publication number
- CN117311080B CN117311080B CN202311599166.5A CN202311599166A CN117311080B CN 117311080 B CN117311080 B CN 117311080B CN 202311599166 A CN202311599166 A CN 202311599166A CN 117311080 B CN117311080 B CN 117311080B
- Authority
- CN
- China
- Prior art keywords
- sub
- pattern
- patterns
- segmentation
- parameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 89
- 230000011218 segmentation Effects 0.000 claims abstract description 94
- 238000012360 testing method Methods 0.000 claims abstract description 62
- 230000008569 process Effects 0.000 claims abstract description 55
- 238000005259 measurement Methods 0.000 claims abstract description 30
- 238000001459 lithography Methods 0.000 claims abstract description 17
- 238000012545 processing Methods 0.000 claims description 18
- 238000003860 storage Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 7
- 238000012937 correction Methods 0.000 abstract description 6
- 230000003287 optical effect Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 20
- 238000004891 communication Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 238000003384 imaging method Methods 0.000 description 5
- 239000011295 pitch Substances 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000012549 training Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Methods, devices, and media for splitting layout patterns are provided according to example embodiments of the present disclosure. The method comprises the following steps: generating a test pattern, wherein the layout pattern comprises a plurality of sub-patterns formed by segmentation, and the plurality of sub-patterns have different parameter values for a predetermined segmentation parameter; obtaining corresponding measurement results of geometric parameters of a plurality of sub-patterns in a wafer pattern, wherein the wafer pattern is formed on a wafer based on a test pattern under a target lithography process; and determining a parameter value range of a predetermined segmentation parameter based on corresponding measurement results of geometric parameters of the plurality of sub-patterns for performing layout pattern segmentation under a target lithography process. In this way, the segmentation rules are matched to the lithography process to be used, thereby facilitating an increase in the effect of optical neighbor correction.
Description
Technical Field
Embodiments of the present disclosure relate generally to the field of integrated circuits and, more particularly, relate to a method, apparatus, and medium for splitting layout patterns.
Background
A circuit layout (which may be simply referred to as a layout) is a series of geometric figures converted from a designed and simulated optimized circuit, and includes physical information data related to devices such as integrated circuit dimensions, topology definitions of various layers, and the like. The integrated circuit manufacturer manufactures a mask from this data. The layout pattern on the mask determines the size of the on-chip device or the connection physical layer.
As technology nodes of integrated circuit fabrication processes decrease, distances between target patterns in an integrated circuit decrease, and densities of layout patterns on a mask corresponding to the target patterns increase. Since the lightwaves diffract at the layout pattern of the mask, the actually formed pattern is distorted compared with the layout pattern. For this reason, optical Proximity Correction (OPC) has been proposed to adjust the layout pattern of a mask so as to form a desired target pattern. How to split a layout pattern into multiple segments (segments) is an important link of OPC.
Disclosure of Invention
In a first aspect of the present disclosure, a method for splitting layout patterns is provided. The method comprises the following steps: generating a test pattern, wherein a layout pattern in the test pattern comprises a plurality of sub-patterns formed by segmentation, and the plurality of sub-patterns have different parameter values for a preset segmentation parameter; obtaining corresponding measurement results of geometric parameters of a plurality of sub-patterns in a wafer pattern, wherein the wafer pattern is formed on a wafer based on a test pattern under a target lithography process; and determining a parameter value range of a predetermined segmentation parameter based on corresponding measurement results of geometric parameters of the plurality of sub-patterns for performing layout pattern segmentation under a target lithography process.
In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor, and a memory coupled to the processor. The memory has instructions stored therein that, when executed by the processor, cause the electronic device to perform a method according to the first aspect of the present disclosure.
In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium has a computer program stored thereon. The computer program, when executed by a processor, implements a method according to the first aspect of the present disclosure.
As will be appreciated from the following description, according to embodiments of the present disclosure, a test pattern may be designed that includes a plurality of sub-patterns, each sub-pattern being used to simulate a graphic segment having different parameter values for a predetermined segmentation parameter. Then, imaging is performed on the target photolithography process using such a test pattern, and a range of values of the predetermined segmentation parameters can be obtained based on the measurement of the obtained wafer pattern. The value range can be used for segmentation processing in OPC for a target lithography process, namely, the segmentation rule under the target lithography process can be obtained. In this way, the segmentation rules are made to match the lithography process to be used, thereby improving the OPC effect. Other benefits will be described below in connection with the corresponding embodiments.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:
FIG. 1A shows a schematic diagram of segmenting a line graph;
FIG. 1B shows a schematic diagram of segmenting a diagonal graph;
FIG. 2 illustrates a schematic diagram of an example environment in which some embodiments of the present disclosure may be implemented;
FIG. 3 illustrates a schematic block diagram of an example architecture of segmentation rule generation, according to some embodiments of the present disclosure;
FIG. 4 illustrates a schematic diagram of an example test pattern, according to some embodiments of the present disclosure;
FIG. 5 illustrates a schematic diagram of another example test pattern, according to some embodiments of the present disclosure;
FIG. 6 illustrates a flow chart of a method for splitting layout patterns according to some embodiments of the present disclosure;
fig. 7 illustrates a block diagram of an electronic device in which one or more embodiments of the disclosure may be implemented.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As used herein, the term "Critical Dimension (CD)" refers to the physical feature size in a layout, on a mask, or on a wafer, which is a form of size.
As used herein, the terms "parameter value range" or "value range" and the like may refer to any number and/or form of values. For example, the parameter value range may include a single value, or a plurality of discrete values. As another example, the parameter value range may include a continuous range of values. For another example, the parameter value range may include a combination of a continuous range of values and one or more discrete values.
As used herein, the term "configuration" or simply "configuration" may refer to the shape of the layout pattern itself and/or the relative position of the layout pattern to other layout patterns, such as pitch. One configuration may be defined by dimensions of multiple dimensions, such as width, height, spacing, and so forth.
As briefly mentioned above, as a link of OPC, a segmentation process is required for a layout pattern. In the segmentation process, the type of a layout pattern (also simply referred to as a pattern) to be segmented may be first identified. Example types of graphics may include, but are not limited to, line (line) graphics, corner (corner) graphics, line-end (line-end) graphics, contact graphics, and the like. The corner patterns can be further divided into external corner patterns, internal corner patterns and the like. It should be understood that the types listed above are examples only and are not intended to be limiting in any way.
Then, the layout graph can be segmented based on the type of the layout graph. FIG. 1A illustrates one example of segmenting a line graph to determine a plurality of sub-graphs (also referred to as graph segments). FIG. 1A schematically illustrates the segmentation of patterns 110 and 120 in a layout. As an example, larger graphics may be segmented as follows. For shorter patterns of wire ends, gap ends, contacts, etc., segmentation points may be inserted at the four corners of the rectangle. That is, the line end pattern, the gap end pattern, and the contact pattern themselves will be determined as pattern segments. For areas where projections exist with adjacent graphics (as shown by the dashed lines in fig. 1A), segmentation points, such as segmentation points 130 and 135, may be inserted for the projected locations within the projection range. While inserting segmentation points, such as segmentation points 131 and 132, at predetermined distances from such segmentation points to the left and right, respectively, along the graphic boundary. For the remaining line or void areas, the segmentation points are inserted equidistantly in a predetermined step size.
By the mode, the original larger graph can be divided into a plurality of small layout graphs, namely sub-graphs. Such a sub-graph is determined by a plurality of segmentation points. For example, a polygon may be divided into rectangles determined by 4 segmentation points. In the example of FIG. 1A, graphics 110 and graphics 120 are divided into 12 sub-graphics, namely sub-graphics 101-1 through 101-12, which are also collectively or individually referred to as sub-graphics.
After determining the sub-patterns, a measurement mark may be inserted for each sub-pattern. Metrology marks are used to identify the metrology locations of CDs in a lithographic imaging simulation or actual measurement. For rectangles, the inserted measurement marks are perpendicular to the rectangle sides, such as measurement mark 115 and measurement mark 125.
As an example, for a rectangle into which a line or gap is divided, the metrology mark may be located at the centerline of the rectangle. For example, the metrology mark 125 of the layout pattern 101-11 is located at the centerline of the layout pattern 101-11 (which is rectangular). For a rectangle formed by a line or gap end pattern, the measurement indicia may be a distance from the line or gap end edge that may be 0.9 times the adjacent edge length or other suitable multiple. For example, the metrology mark 115 of the layout pattern 101-4 is not located at the centerline of the layout pattern 101-4, but rather is further away from the line end 150 of the layout pattern 101-4. For a rectangle formed by a pattern of contacts, the measurement indicia may be located at the center of the long sides of the rectangle and at the long sides.
The segmentation example of the line graph is exemplarily described above. In this example, the segmentation parameter includes the length of the divided sub-graph, i.e., the dimension along the horizontal direction of fig. 1A. Other segmentation parameters may also be involved, depending on the type of graphics. Another example is described with reference to fig. 1B. Fig. 1B shows examples of segmentation parameters involved in segmenting a diagonal graph, including outer corner length and inner corner length. As shown in fig. 1B, the corner pattern 160 includes an outer corner 161, an outer corner 162, an outer corner 163, and an inner corner 164. Accordingly, the outer corner length may refer to the length of the graphic segment next to the outer corner, and the inner corner length may refer to the length of the graphic segment next to the inner corner.
It should be understood that the graphics, sub-graphics, segmentation points, and the locations of the metrology marks described with reference to fig. 1A and 1B are merely exemplary and are not intended to limit the scope of the present disclosure. Furthermore, the segmentation parameters described with reference to fig. 1A and 1B are also exemplary, and various suitable segmentation parameters may exist.
The segmentation processing example for graphics is described above. After the pattern is segmented, the lithographic process may be simulated using any suitable lithographic simulation model to perform OPC operations. In the correction stage, according to the result of the lithography simulation, the simulation result at each measurement mark is determined. Based on the simulation results at the measurement marks, it can be determined whether the corresponding graphic segment is moving, or how much distance it is moving, or whether a serif (serif) is added to the graphic segment, etc.
In conventional approaches, the generation of segmentation rules is based on very limited optical parameters, such as the wavelength of light, requirements of the process technology node (e.g., minimum pitch values, etc.). For example, in a conventional scheme, a nominal value of the segment length, a minimum value, an outer angle length, an inner angle length, etc. may be specified. These conventional schemes are basically considered from the aspect of layout design size/configuration without regard to lithographic process features such as positive developed photoresist, negative developed photoresist, light source shape, forbidden pitches and side lobes due to light source shape, etc.
With the development of semiconductor technology, the required resolution is much smaller than the wavelength of the light used for illumination. In this case, the conventional scheme described above causes some problems to occur. For example, the edges of the line pattern formed after imaging may exhibit a wobbled or wavy profile (also referred to as line edge roughness), any operation of merging the pattern segments after correction may not be fully optimized (or erroneously optimized), and the criteria available when the number of electron beam shots is reduced may be limited, etc. In addition, those segments (e.g., sub-graph 101-4 shown in FIG. 1B) that are immediately adjacent to the corners of the polygon have measurement mark points that are not located at the center of the segments, but rather are further from the corners, which have correction convergence problems due to the effect of correction. In addition, the measurement points in each segment sometimes move along or outside the range of the segment to meet certain criteria, such as to meet Manufacturing Rule Checking (MRC) constraints.
In view of this, the conventional segmentation rules do not consider the photolithography process. Such segmentation rules limit the effectiveness of OPC. According to an embodiment of the present disclosure, a scheme for segmentation processing is provided. In this scheme, a test pattern is generated in which a layout pattern includes a plurality of sub-patterns formed by segmentation and the plurality of sub-patterns have different parameter values for predetermined segmentation parameters. And obtaining corresponding measurement results of geometric parameters of the plurality of sub-patterns in the wafer pattern based on the wafer pattern formed by the test pattern on the wafer under the target photoetching process. And determining a parameter value range of the preset segmentation parameter based on corresponding measurement results of the geometric parameters of the multiple sub-patterns, wherein the parameter value range is used for carrying out layout pattern segmentation under the target photoetching process.
In this way, the segmentation rules are made to match the lithography process to be used. This is advantageous in improving OPC effects. For example, in this manner, the segmentation rules may be aligned with the lithography process, thereby improving convergence and resultant quality of OPC.
Example embodiments of the present disclosure are described below with continued reference to the accompanying drawings.
FIG. 2 illustrates a schematic diagram of an example environment 200 in which embodiments of the present disclosure can be implemented. In the example environment 200, the electronic device 210 generates a test pattern 230. The layout pattern in the test pattern 230 includes a plurality of sub-patterns formed by segmentation, that is, includes a plurality of pattern segments. The sub-graphs have different parameter values for the predetermined segmentation parameters. For example, the sub-patterns have different segment lengths. Based on the test pattern 230, the electronic device 210 may determine a parameter value range 240 for a predetermined segment parameter, such as a segment length value range. In some embodiments, the electronic device 210 may also determine a plurality of parameter value ranges for the plurality of test patterns 230 to generate the segmentation rules.
In the example environment 200, the electronic device 210 may be any type of device having computing capabilities, including a terminal device or a server device. The terminal device may be any type of mobile terminal, fixed terminal, or portable terminal, including a mobile handset, desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, media computer, multimedia tablet, personal Communication System (PCS) device, personal navigation device, personal Digital Assistant (PDA), audio/video player, digital camera/camcorder, positioning device, television receiver, radio broadcast receiver, electronic book device, game device, or any combination of the preceding, including accessories and peripherals for these devices, or any combination thereof. The server devices may include, for example, computing systems/servers, such as mainframes, edge computing nodes, computing devices in a cloud environment, and so forth.
It should be understood that the structure and function of environment 200 are described for illustrative purposes only and are not meant to suggest any limitation as to the scope of the disclosure. Example embodiments according to the present disclosure will be described in detail below with reference to fig. 3 to 7.
As mentioned previously, the segmentation process may use various suitable segmentation parameters. Example embodiments of the present disclosure are described below primarily with the example of segment length as a segment parameter. It should be understood that this is merely exemplary and embodiments of the present disclosure are not limited in this respect. The embodiments described with reference to segment lengths may be applied to other segment parameters.
Fig. 3 illustrates a schematic block diagram of an example architecture 300 of segmentation rule generation, according to some embodiments of the present disclosure. In general, a range determination process 310 is performed on at least one test pattern to determine a range of parameter values for a predetermined segmentation parameter. In some embodiments, a rule set for performing a segmentation process under a target lithographic process may in turn be generated based on the respective parameter value ranges.
As shown in fig. 3, the range determining process 310 is performed at least on the test pattern 311. In some embodiments, the range determination process 310 may be performed separately on a plurality of test patterns. In the example of fig. 3, a range determination process 310 is performed on the test pattern 311, resulting in a parameter value range 321; performing a range determination process 310 on the test pattern 312, resulting in a range of parameter values 322; the test pattern 313 performs the range determination process 310, resulting in a range of parameter values 323. It should be understood that the number of test patterns and corresponding parameter value ranges shown in fig. 3 is merely exemplary and not intended to be limiting in any way. Embodiments of the present disclosure are applicable to any number of test patterns.
The layout pattern in each test pattern includes a plurality of sub-patterns formed by segmentation. Sub-graphics may also be referred to as graphics segmentation. The sub-graphs have different parameter values for the predetermined segmentation parameters. For example, the predetermined segment parameter may be a segment length, and then the sub-patterns may have different segment length values. Of course, the predetermined segmentation parameters may be other suitable parameters, and embodiments of the present disclosure are not limited in this respect.
An example is described with reference to fig. 4, in which a test pattern 400 generated for a line pattern is shown. Test pattern 400 includes a plurality of layout patterns, such as layout pattern 410. Taking layout pattern 410 as an example, it includes a plurality of sub-patterns, namely sub-pattern 411, sub-pattern 412, sub-pattern 413, sub-pattern 414, sub-pattern 415. The individual sub-patterns may have different lengths, for example, along the vertical direction of fig. 4. Different lengths of the sub-graph may correspond to different segment lengths.
Fig. 4 shows an enlarged view 450 of a portion of the test pattern 400. As can be seen from view 450, sub-graph 411 corresponds to segment length l1+d1, sub-graph 412 corresponds to segment length l1+d2, and sub-graph 413 corresponds to segment length l1+d3. In this example, L1+D3 is greater than L1+D2, and L1+D2 is greater than L1+D1.
Another example is described with reference to fig. 5, in which a test pattern 500 generated for an angular pattern is shown. Test pattern 500 includes a plurality of layout patterns, such as layout pattern 510. Taking layout pattern 510 as an example, it includes a plurality of sub-patterns, namely sub-pattern 511, sub-pattern 512, sub-pattern 513, sub-pattern 514. The individual sub-patterns may have different lengths, for example, along the vertical direction of fig. 5. Different lengths of the sub-graph may correspond to different segment lengths.
As can be seen from fig. 5, the sub-graph 511 corresponds to the segment length l2+d1, the sub-graph 512 corresponds to the segment length l2+d2, the sub-graph 513 corresponds to the segment length l2+d3, and the sub-graph 514 corresponds to the segment length l2+d4. In this example, L2+D4 is greater than L2+D3, L2+D3 is greater than L2+D2, and L2+D2 is greater than L2+D1.
It should be understood that the test patterns shown in fig. 4 and 5 are merely exemplary and are not intended to limit the scope of the present disclosure. The number and size of the sub-patterns included in the test pattern are merely exemplary.
With continued reference to fig. 3. In some embodiments, if there are multiple test patterns, these test patterns may be generated for different types of layout patterns. For example, test pattern 400 is generated for a line pattern, while test pattern 500 is generated for an angle pattern.
Alternatively or additionally, in some embodiments, the test patterns may be for different graphic configurations. Each pattern configuration may be defined by a plurality of dimensional dimensions, and the plurality of dimensional dimensions includes a single pattern dimension and a spacing between adjacent patterns. Illustratively, the dimensions of the multiple dimensions may include, but are not limited to, the width W, length L, and spacing S from adjacent patterns of the patterns themselves.
Still referring to the examples of fig. 4 and 5. In the example of fig. 4, the pattern configuration for which the test pattern 400 is directed has a length L1, a width W1, and a spacing S1. By fixing two of the length L1, the width W1, and the pitch S1 and varying the other, other pattern configurations can be determined and corresponding test patterns generated. In the example of fig. 5, the pattern configuration for which test pattern 500 is intended has a length L2, a width W2, and a spacing S2. By fixing two of the length L2, the width W2, and the pitch S2 and varying the other, other pattern configurations can be determined and corresponding test patterns generated.
With respect to the generation of the test pattern, in some embodiments, at least a portion of the initial pattern in the initial pattern may be divided into a plurality of sub-patterns along the first direction in accordance with a plurality of parameter values of the predetermined segmentation parameter, each sub-pattern having one of the plurality of parameter values for the predetermined segmentation parameter. Then, the plurality of sub patterns may be moved in a second direction perpendicular to the first direction, respectively, to form a layout pattern in the test pattern. For example, in the example of fig. 4, the sub-patterns 411, 412, 413, 414, 415 have different lengths in the vertical direction and are moved a certain distance in the horizontal direction. As another example, in the example of fig. 5, the sub-patterns 521, 522, 523, 524 have different lengths in the horizontal direction and are moved a certain distance in the vertical direction.
In some embodiments, two adjacent sub-patterns of the sub-patterns are non-aligned in the second direction and offset from each other by a predetermined distance. For example, in the example of fig. 4, there is an offset J1 in the horizontal direction between two adjacent sub-patterns. As another example, in the example of fig. 5, two adjacent sub-patterns among the sub-patterns 521, 522, 523, 524 have an offset J2 in the vertical direction.
While examples of test patterns and pattern configurations are described above, it is to be understood that in some embodiments test patterns for various types of patterns and configurations of patterns may be generated to perfect rule set 350 as much as possible.
The example architecture 300 of fig. 3 continues to be described. The range determination process 310 may be performed for each test pattern. In the range determining process 310, a measurement result of a wafer pattern corresponding to the test pattern may be obtained first. Wafer patterns are formed on the wafer based on the test patterns under the target photolithography process. The target lithographic process may be defined by any suitable process parameters, such as, for example, light source illumination pattern, depth of focus, exposure, etc. Embodiments of the disclosure are not limited in this respect.
For example, a mask with a test pattern may be used to image on a wafer under a target lithography process. After imaging, a wafer pattern, such as a pattern formed on a wafer by photoresist, may be acquired. Image data (i.e., SEM data) of the wafer pattern may then be acquired using a scanning tunneling electron microscope (SEM). The geometric parameters of the wafer pattern may be measured from the image data of the wafer pattern.
The geometric parameters used in embodiments of the present disclosure may include any suitable geometric parameters suitable for assessing lithographic imaging quality. In some embodiments, critical dimensions may be used. The critical dimensions may be measured from SEM top view of the wafer pattern, and values of the critical dimensions at different locations may be measured. Alternatively or additionally, in some embodiments, other geometric parameters may be used. Such a geometrical parameter may be, for example, any feature to be printed on the wafer and addressed with the resolution limit. In the following description, critical dimensions will be mainly taken as examples, but it should be understood that other geometrical parameters are similar.
After obtaining the measurements of the wafer pattern, corresponding measurements of the geometric parameters of the plurality of sub-patterns in the wafer pattern may be obtained. For example, if the geometric parameter of interest is a critical dimension, the corresponding photoresist linewidths of the plurality of sub-patterns may be measured from the image data of the wafer pattern. The measured respective critical dimensions of the plurality of sub-patterns may be determined based on the measured respective photoresist linewidths. For example, the minimum line width of each sub-pattern may be used as a measure of the critical dimension of the sub-pattern. As another example, the average line width of each sub-image may be used as a measure of the critical dimension of the sub-image. For example, with respect to FIG. 4, the corresponding critical dimensions of sub-graphic 411, sub-graphic 412, sub-graphic 413, sub-graphic 414, sub-graphic 415 may be obtained.
Continuing with the description of process 300, after obtaining measurements of geometric parameters of the sub-patterns, a range of parameter values for predetermined segmentation parameters may be determined based on the corresponding measurements for layout pattern segmentation under a target lithographic process. For example, in the case where the predetermined segmentation parameter is a segmentation length, a segmentation length value or a segmentation length range usable when performing segmentation processing under a target photolithography process may be determined.
In some embodiments, if the geometric parameter of interest is a critical dimension, the measurement of the sub-graph may include the measured critical dimension. In such an embodiment, one or more sub-patterns may be selected from the plurality of sub-patterns based on the measured respective critical dimensions of the plurality of sub-patterns. In some embodiments, a sub-graph having a critical dimension closest to the target critical dimension may be selected from a plurality of sub-graphs. Alternatively, in some embodiments, the target critical dimension range may be determined based on the target critical dimension and acceptable critical dimension variations under the target photolithographic process. A sub-graph having a critical dimension within a target critical dimension range may be selected from a plurality of sub-graphs. Thus, those sub-patterns that meet the critical dimension requirements are selected. A range of parameter values for the predetermined segmentation parameter may then be determined based on the corresponding parameter values that the selected one or more sub-graphs have for the predetermined segmentation parameter.
As an example, referring to fig. 4, the critical dimensions of sub-graphic 411, sub-graphic 412, sub-graphic 413, sub-graphic 414, sub-graphic 415 may be determined, respectively, and then one or more sub-graphics whose critical dimensions meet the requirements may be selected. A range of values for the segment length under the target process may be determined based on the segment length of the selected sub-graph. For example, if the critical dimensions of sub-graph 412, sub-graph 413, sub-graph 414 meet the requirements, then the range of segment lengths may be determined based on "L1+D2", "L1+D3", "L1+D4".
As another example, referring to fig. 5, the critical dimensions of sub-graphs 521, 522, 523, 524 may be determined, respectively, i.e., the variation of the critical dimensions along the horizontal direction is considered for determining the segmentation rule. For example, a sub-pattern whose critical dimension satisfies the requirement may be selected from sub-pattern 521, sub-pattern 522, sub-pattern 523, and sub-pattern 524, and the value range of the segment length of the selected sub-pattern may be used as the segment length range in this configuration.
Examples of determining the range of values of the segmentation parameters based on a single test pattern are described above. It will be appreciated that the same or similar process may be performed for each test pattern to obtain multiple ranges of parameter values. These parameter value ranges may be for different pattern configurations, for different pattern types, or for different lithography processes. Based on these parameter value ranges, a rule set 350 for the segmentation process may be obtained. Rules in rule set 350 may be partitioned by corresponding pattern configuration, corresponding pattern type, corresponding photolithography process, and the like. For example, each rule in rule set 350 may be for one of a plurality of graphical configurations.
Thus, when a user needs to split a layout pattern to determine multiple pattern segments, an appropriate rule from rule set 350 may be selected based on the type, configuration, and/or lithography process of the pattern to be segmented.
Fig. 6 illustrates a flow chart of a method 600 for splitting a layout pattern according to some embodiments of the present disclosure. The method 600 may be performed by the electronic device 210 as shown in fig. 2. It should be understood that method 600 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect.
At block 610, the electronic device 210 generates a test pattern, the layout pattern in the test pattern including a plurality of sub-patterns formed by segmentation, and the plurality of sub-patterns having different parameter values for predetermined segmentation parameters.
At block 620, the electronic device 210 obtains respective measurements of geometric parameters of a plurality of sub-patterns in a wafer pattern formed on a wafer under a target photolithography process based on the test pattern.
At block 630, the electronic device 210 determines a range of parameter values for the predetermined segmentation parameters for use in layout pattern segmentation under the target lithographic process based on respective measurements of geometric parameters of the plurality of sub-patterns.
In some embodiments, the geometric parameter comprises a critical dimension, and determining the parameter value range for the predetermined segmentation parameter comprises: selecting one or more sub-patterns from the plurality of sub-patterns based on the measured respective critical dimensions of the plurality of sub-patterns; and determining a parameter value range of the predetermined segmentation parameter based on the corresponding parameter values that the selected one or more sub-graphs have for the predetermined segmentation parameter.
In some embodiments, selecting one or more sub-graphs from the plurality of sub-graphs includes: a sub-graph having a critical dimension closest to the target critical dimension is selected from the plurality of sub-graphs.
In some embodiments, selecting one or more sub-graphs from the plurality of sub-graphs includes: determining a target critical dimension range based on the target critical dimension and acceptable critical dimension variation under the target lithography process; and selecting a sub-graph having a critical dimension within the target critical dimension range from the plurality of sub-graphs.
In some embodiments, obtaining respective measurements of geometric parameters of the plurality of sub-patterns in the wafer pattern comprises: measuring corresponding photoresist linewidths of the plurality of sub-patterns from the image data of the wafer pattern; and determining the measured respective critical dimensions of the plurality of sub-patterns based on the measured respective photoresist linewidths.
In some embodiments, generating the test pattern includes: dividing at least a portion of an initial pattern in the initial pattern into a plurality of sub-patterns according to a plurality of parameter values of a predetermined segmentation parameter along a first direction, each sub-pattern having one of the plurality of parameter values for the predetermined segmentation parameter; and respectively moving the plurality of sub-patterns in a second direction perpendicular to the first direction to form a layout pattern in the test pattern.
In some embodiments, two adjacent sub-patterns of the plurality of sub-patterns are non-aligned in the second direction and offset from each other by a predetermined distance.
In some embodiments, the test pattern is generated for a first graphical configuration of the plurality of graphical configurations, and the method further comprises: performing method 600 for at least one other graphical configuration of the plurality of graphical configurations other than the first graphical configuration to determine at least one other parameter value range; and generating a rule set for layout pattern segmentation under the target lithographic process based on the parameter value range and at least one other parameter value range, each rule in the rule set corresponding to one of the plurality of pattern configurations.
In some embodiments, each of the plurality of graphic configurations is defined by a plurality of dimensional dimensions, and the plurality of dimensional dimensions includes a size of a single graphic and a spacing between adjacent graphics.
In some embodiments, the predetermined segmentation parameter comprises a length of the segment.
Fig. 7 illustrates a block diagram that shows an electronic device 700 in which one or more embodiments of the disclosure may be implemented. It should be understood that the electronic device 700 illustrated in fig. 7 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. The electronic device 700 shown in fig. 7 may be used to implement the electronic device 210 of fig. 2.
As shown in fig. 7, the electronic device 700 is in the form of a general-purpose electronic device. Components of electronic device 700 may include, but are not limited to, one or more processors or processing units 710, memory 720, storage 730, one or more communication units 740, one or more input devices 750, and one or more output devices 760. The processing unit 710 may be an actual or virtual processor and is capable of performing various processes according to programs stored in the memory 720. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capabilities of electronic device 700.
Electronic device 700 typically includes a number of computer storage media. Such a medium may be any available media that is accessible by electronic device 700, including, but not limited to, volatile and non-volatile media, removable and non-removable media. The memory 720 may be volatile memory (e.g., registers, cache, random Access Memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 730 may be a removable or non-removable media and may include machine-readable media such as flash drives, magnetic disks, or any other media that may be capable of storing information and/or data (e.g., training data for training) and may be accessed within electronic device 700.
The electronic device 700 may further include additional removable/non-removable, volatile/nonvolatile storage media. Although not shown in fig. 7, a magnetic disk drive for reading from or writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data medium interfaces. Memory 720 may include a computer program product 725 having one or more program modules configured to perform the various methods or acts of the various embodiments of the disclosure.
The communication unit 740 enables communication with other electronic devices through a communication medium. Additionally, the functionality of the components of the electronic device 700 may be implemented in a single computing cluster or in multiple computing machines capable of communicating over a communication connection. Thus, the electronic device 700 may operate in a networked environment using logical connections to one or more other servers, a network Personal Computer (PC), or another network node.
The input device 750 may be one or more input devices such as a mouse, keyboard, trackball, etc. The output device 760 may be one or more output devices such as a display, speakers, printer, etc. The electronic device 700 may also communicate with one or more external devices (not shown), such as storage devices, display devices, etc., through the communication unit 740, with one or more devices that enable a user to interact with the electronic device 700, or with any device (e.g., network card, modem, etc.) that enables the electronic device 700 to communicate with one or more other electronic devices, as desired. Such communication may be performed via an input/output (I/O) interface (not shown).
According to an exemplary implementation of the present disclosure, a computer-readable storage medium having stored thereon computer-executable instructions, wherein the computer-executable instructions are executed by a processor to implement the method described above is provided. According to an exemplary implementation of the present disclosure, there is also provided a computer program product tangibly stored on a non-transitory computer-readable medium and comprising computer-executable instructions that are executed by a processor to implement the method described above.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus, devices, and computer program products implemented according to the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The foregoing description of implementations of the present disclosure has been provided for illustrative purposes, is not exhaustive, and is not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.
Claims (12)
1. A method for splitting a layout pattern, comprising:
generating a test pattern, wherein a layout pattern in the test pattern comprises a plurality of sub-patterns formed by segmentation, and the plurality of sub-patterns have different parameter values for a predetermined segmentation parameter;
acquiring corresponding measurement results of critical dimensions of the plurality of sub-patterns in a wafer pattern, wherein the wafer pattern is formed on a wafer based on the test pattern under a target photolithography process; and
determining a parameter value range of the predetermined segmentation parameter for performing layout pattern segmentation under the target lithography process based on respective measurements of the critical dimensions of the plurality of sub-patterns,
wherein determining the parameter value range of the predetermined segmentation parameter comprises:
selecting one or more sub-graphs from the plurality of sub-graphs based on the measured respective critical dimensions and the target critical dimensions of the plurality of sub-graphs; and
a range of parameter values for the predetermined segmentation parameter is determined based on the respective parameter values that the selected one or more sub-graphs have for the predetermined segmentation parameter.
2. The method for splitting a layout pattern according to claim 1, wherein selecting one or more sub-patterns from the plurality of sub-patterns comprises:
selecting a sub-graph with a key size closest to the target key size from the plurality of sub-graphs.
3. The method for splitting a layout pattern according to claim 1, wherein selecting one or more sub-patterns from the plurality of sub-patterns comprises:
determining a target critical dimension range based on the target critical dimension and acceptable critical dimension variation under the target lithography process; and
selecting a sub-graph with a critical dimension within the target critical dimension range from the plurality of sub-graphs.
4. The method for splitting a layout pattern according to claim 1, wherein obtaining respective measurements of critical dimensions of the plurality of sub-patterns in the wafer pattern comprises:
measuring corresponding photoresist linewidths of the plurality of sub-patterns from the image data of the wafer pattern; and
based on the measured respective photoresist linewidths, the measured respective critical dimensions of the plurality of sub-patterns are determined.
5. The method for splitting a layout pattern according to claim 1, wherein generating a test pattern comprises:
dividing at least a portion of an initial pattern in an initial pattern into a plurality of sub-patterns along a first direction according to a plurality of parameter values of the predetermined segmentation parameter, each sub-pattern having one of the plurality of parameter values for the predetermined segmentation parameter; and
and respectively moving the plurality of sub-patterns in a second direction perpendicular to the first direction to form the layout pattern in the test pattern.
6. The method for splitting a layout pattern according to claim 5, wherein two adjacent sub-patterns of the plurality of sub-patterns are non-aligned in the second direction and offset from each other by a predetermined distance.
7. The method for splitting a layout pattern according to claim 1, wherein the test pattern is generated for a first one of a plurality of graphic configurations, and the method further comprises:
performing the method of claim 1 for at least one other graphical configuration of the plurality of graphical configurations other than the first graphical configuration to determine at least one other parameter value range; and
based on the parameter value ranges and the at least one other parameter value range, a rule set for layout pattern segmentation under the target lithographic process is generated, each rule in the rule set corresponding to one of the plurality of pattern configurations.
8. The method for splitting a layout pattern according to claim 7, wherein each of the plurality of pattern configurations is defined by a size of a plurality of dimensions, and wherein the size of the plurality of dimensions includes a size of a single pattern and a spacing between adjacent patterns.
9. A method for splitting a layout pattern according to claim 1, wherein the predetermined segmentation parameter comprises a length of a segment.
10. The method for splitting a layout pattern according to claim 1, wherein the predetermined segmentation parameters comprise one of:
the length of the sub-pattern,
the inner angle length of the sub-pattern, or
The outer angular length of the sub-image.
11. An electronic device, comprising:
at least one processing unit; and
at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which when executed by the at least one processing unit, cause the electronic device to perform the method of any one of claims 1 to 10.
12. A computer readable storage medium, having stored thereon a computer program, characterized in that the computer program is executable by a processor to implement the method according to any of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311599166.5A CN117311080B (en) | 2023-11-24 | 2023-11-24 | Method, device and medium for splitting layout pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311599166.5A CN117311080B (en) | 2023-11-24 | 2023-11-24 | Method, device and medium for splitting layout pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117311080A CN117311080A (en) | 2023-12-29 |
| CN117311080B true CN117311080B (en) | 2024-02-27 |
Family
ID=89286887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311599166.5A Active CN117311080B (en) | 2023-11-24 | 2023-11-24 | Method, device and medium for splitting layout pattern |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117311080B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070056583A (en) * | 2005-11-30 | 2007-06-04 | 동부일렉트로닉스 주식회사 | Mask pattern and the forming method thereof in the semiconductor manufacturing process |
| CN101661219A (en) * | 2008-08-28 | 2010-03-03 | 中芯国际集成电路制造(上海)有限公司 | Method and device for correcting mask plate patterns |
| CN108663897A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Optical adjacent correction method |
| CN112415864A (en) * | 2020-11-24 | 2021-02-26 | 上海华力集成电路制造有限公司 | Method for determining OPC minimum segmentation length |
| CN114326290A (en) * | 2022-01-04 | 2022-04-12 | 华虹半导体(无锡)有限公司 | Optical proximity correction method |
| CN115933304A (en) * | 2022-12-29 | 2023-04-07 | 上海集成电路装备材料产业创新中心有限公司 | Optical proximity effect correction method and device, electronic equipment and storage medium |
| WO2023137622A1 (en) * | 2022-01-19 | 2023-07-27 | 华为技术有限公司 | Method and apparatus for determining size of wafer pattern, device, medium and program product |
| CN116594256A (en) * | 2023-04-19 | 2023-08-15 | 上海华力集成电路制造有限公司 | Optical proximity correction method for improving electroplating hole filling capability |
-
2023
- 2023-11-24 CN CN202311599166.5A patent/CN117311080B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070056583A (en) * | 2005-11-30 | 2007-06-04 | 동부일렉트로닉스 주식회사 | Mask pattern and the forming method thereof in the semiconductor manufacturing process |
| CN101661219A (en) * | 2008-08-28 | 2010-03-03 | 中芯国际集成电路制造(上海)有限公司 | Method and device for correcting mask plate patterns |
| CN108663897A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Optical adjacent correction method |
| CN112415864A (en) * | 2020-11-24 | 2021-02-26 | 上海华力集成电路制造有限公司 | Method for determining OPC minimum segmentation length |
| CN114326290A (en) * | 2022-01-04 | 2022-04-12 | 华虹半导体(无锡)有限公司 | Optical proximity correction method |
| WO2023137622A1 (en) * | 2022-01-19 | 2023-07-27 | 华为技术有限公司 | Method and apparatus for determining size of wafer pattern, device, medium and program product |
| CN115933304A (en) * | 2022-12-29 | 2023-04-07 | 上海集成电路装备材料产业创新中心有限公司 | Optical proximity effect correction method and device, electronic equipment and storage medium |
| CN116594256A (en) * | 2023-04-19 | 2023-08-15 | 上海华力集成电路制造有限公司 | Optical proximity correction method for improving electroplating hole filling capability |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117311080A (en) | 2023-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10223494B2 (en) | Semiconductor device manufacturing method and mask manufacturing method | |
| US8166424B2 (en) | Method for constructing OPC model | |
| US20070074143A1 (en) | Dense OPC | |
| JP2009294386A (en) | Lithography simulation method | |
| US20080059939A1 (en) | Performance in model-based opc engine utilizing efficient polygon pinning method | |
| JP2013125906A (en) | Flare map calculation method, flare map calculation program, and method of manufacturing semiconductor device | |
| US7840390B2 (en) | Creating method of simulation model, manufacturing method of photo mask, manufacturing method of semiconductor device, and recording medium | |
| JP2022183203A (en) | Measurement target having gradient periodic structure and method | |
| US7793253B2 (en) | Mask-patterns including intentional breaks | |
| US10755016B2 (en) | Hot spot and process window monitoring | |
| CN115863203B (en) | Test pattern acquisition method, system, device, computer equipment and medium | |
| US6536032B1 (en) | Method of processing exposure mask-pattern data, simulation using this method, and recording medium | |
| US10796070B2 (en) | Layout pattern similarity determination based on binary turning function signatures | |
| US10656530B2 (en) | Application of FreeForm MRC to SRAF optimization based on ILT mask optimization | |
| JP2008129118A (en) | Mask pattern correction program and mask pattern correction system | |
| KR101705445B1 (en) | Method for integrated circuit manufacturing | |
| JP5224853B2 (en) | Pattern prediction method, pattern correction method, semiconductor device manufacturing method, and program | |
| US8127257B2 (en) | Designing method of photo-mask and method of manufacturing semiconductor device using the photo-mask | |
| CN117311080B (en) | Method, device and medium for splitting layout pattern | |
| US8617773B2 (en) | Method of correcting mask pattern, computer program product, and method of manufacturing semiconductor device | |
| CN115630600A (en) | Method, apparatus, and medium for layout processing | |
| JP2008020734A (en) | Design pattern preparation method for semiconductor device, program, and method of manufacturing the semiconductor device | |
| CN112219271B (en) | Hybrid design layout to identify systematic defects associated with optical proximity correction | |
| US10748821B2 (en) | Method and system for measuring pattern placement error on a wafer | |
| US8640059B2 (en) | Forming separation directives using a printing feasibility analysis |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |