CN117294783A - Chip verification method, device and equipment - Google Patents
Chip verification method, device and equipment Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a chip verification method, device and equipment. The method is used for a chip verification device with a first virtual machine and a second virtual machine deployed, and comprises the following steps: acquiring test demand data through a first virtual machine and generating a first data message according to the test demand data, wherein the first data message comprises a network address of a second virtual machine; transmitting the first data message to a network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for transmission to a second virtual machine; and transmitting the second data message to a second virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the second data message by the second virtual machine. The method can improve the efficiency of chip verification.
Description
Technical Field
The present disclosure relates to the field of chip verification technologies, and in particular, to a chip verification method, device, and equipment.
Background
The network processing chip is widely applied to various core switches and is mainly used for realizing communication tasks such as data packet processing, protocol analysis, route searching, firewall and the like.
In the related art, a verification mode for a network processing chip is generally to build a UVM (Universal Verification Methodology ) verification platform, a large number of data messages in different formats are constructed in the UVM verification platform based on different communication protocols, the data messages are used as transactions of the verification platform, and test cases are written for simulation verification.
However, the above-described method of verifying the network processing chip is inefficient.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a chip verification method, apparatus, and device capable of improving verification efficiency.
In a first aspect, the present application provides a chip verification method, for a chip verification device, where a first virtual machine and a second virtual machine are deployed in the chip verification device, the method includes:
acquiring test demand data through a first virtual machine and generating a first data message according to the test demand data, wherein the first data message comprises a network address of a second virtual machine;
transmitting the first data message to a network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for transmission to a second virtual machine;
and transmitting the second data message to a second virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the second data message by the second virtual machine.
In one embodiment, transmitting the first data message to the network processor chip to be authenticated includes:
acquiring a first data message from a first virtual machine through a data transmission module, and transmitting the first data message to a network processor chip through the data transmission module;
transmitting the second data message to the second virtual machine, comprising:
and acquiring a second data message from the network processor chip through the data transmission module, and transmitting the second data message to the second virtual machine through the data transmission module.
In one embodiment, the method for obtaining the first data message from the first virtual machine through the data transmission module and transmitting the first data message to the network processor chip through the data transmission module includes:
acquiring a first data message from a first virtual network port of a first virtual machine through a first socket interface in a data transmission module;
and transmitting the first data message to a first chip network port of the network processor chip through a first network port driver in the data transmission module.
In one embodiment, the method further comprises:
and transmitting the first data message acquired through the first socket interface to the first network port driver through a first direct programming interface in the data transmission module.
In one embodiment, the acquiring, by the data transmission module, the second data packet from the network processor chip, and transmitting, by the data transmission module, the second data packet to the second virtual machine, includes:
acquiring a second data message from a second chip network port of the network processor chip through a second network port monitor in the data transmission module;
and transmitting the second data message to a second virtual network port of the second virtual machine through a second socket interface in the data transmission module.
In one embodiment, the method further comprises:
and transmitting a second data message acquired through a second network port monitor to a second socket interface through a second direct programming interface in the data transmission module.
In one embodiment, obtaining, by the second virtual machine, a chip verification result corresponding to the test requirement data according to the second data packet includes:
analyzing the second data message through the second virtual machine to obtain content data included in the second data message;
and comparing the content data with the test requirement data to obtain a chip verification result.
In one embodiment, the test requirement data is used to indicate a connection establishment function or a connection termination function that verifies the network processor chip; obtaining, by the second virtual machine, a chip verification result corresponding to the test requirement data according to the second data packet, including:
responding to the second data message through the second virtual machine to obtain a third data message;
transmitting the third data message to the network processor chip so that the network processor chip can process the third data message to obtain a fourth data message which is transmitted to the first virtual machine;
and transmitting the fourth data message to the first virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the fourth data message by the first virtual machine.
In a second aspect, the present application further provides a chip verification apparatus, configured to be used in a chip verification device, where a first virtual machine and a second virtual machine are deployed in the chip verification device, where the apparatus includes:
the demand response module is used for acquiring test demand data through the first virtual machine and generating a first data message according to the test demand data, wherein the first data message comprises a network address of the second virtual machine;
the data transmission module is used for transmitting the first data message to the network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for being transmitted to the second virtual machine, and is used for transmitting the second data message to the second virtual machine;
and the result determining module is used for acquiring a chip verification result corresponding to the test requirement data according to the second data message through the second virtual machine.
In a third aspect, the present application further provides a chip verification device. The chip verification device is provided with a first virtual machine and a second virtual machine, the chip verification device comprises a memory and a processor, the memory stores a computer program, and the processor realizes the steps of the method according to the first aspect when executing the computer program.
The method is used for deploying the chip verification equipment with the first virtual machine and the second virtual machine, acquiring test demand data through the first virtual machine and generating a first data message according to the test demand data, wherein the first data message comprises a network address of the second virtual machine; transmitting the first data message to a network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for transmission to a second virtual machine; transmitting the second data message to a second virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the second data message by the second virtual machine; therefore, the virtual machine can generate and analyze data messages meeting various communication protocols according to the test requirement data to simulate the real use scene of the network processor chip so as to simulate and verify the network processor chip, and the data messages in the whole verification process come from the virtual machine, so that the problem of low verification efficiency caused by the fact that the data messages corresponding to different communication protocols are required to be constructed in a verification platform in the traditional technology to serve as test excitation is solved; the chip verification method has high verification efficiency.
Drawings
FIG. 1 is a block diagram of a chip authentication device in one embodiment;
FIG. 2 is a flow chart of a chip verification method in one embodiment;
FIG. 3 is a flow chart of a method for obtaining a chip verification result in one embodiment;
FIG. 4 is a block diagram of a chip authentication device according to another embodiment;
FIG. 5 is a flow diagram of a data transmission process in one embodiment;
FIG. 6 is a flow chart of a chip verification method according to another embodiment;
FIG. 7 is a block diagram of a chip authentication device in one embodiment;
fig. 8 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be appreciated that the terms "first," "second," etc. as used herein may be used to describe each virtual machine or various data messages, but these virtual machines and data messages are not limited by these terms. These terms are used only to distinguish a first virtual machine from another virtual machine, and only to distinguish a first data message from other data messages. For example, a first virtual machine may be referred to as a second virtual machine, and similarly, a second virtual machine may be referred to as a first virtual machine, without departing from the scope of the present application. Both the first virtual machine and the second virtual machine are virtual machines, but they are not the same virtual machine.
The chip verification method provided by the embodiment of the application can be applied to chip verification equipment shown in fig. 1. The chip verification device is provided with a plurality of virtual machines, and the network processor chip to be verified exists in the form of RTL (Register Transfer Level, register transmission level) codes in the verification process, and is simulated by simulation software, such as VCS (Verilogcompile Simulator, compiling type Verilog simulator), iverilog (Icarus Verilog), verilor and the like. And constructing virtual machines 1 to n based on an operating system of the chip verification equipment, wherein each virtual machine corresponds to each network port of the network processor chip to be verified. The virtual machine is a software simulation computer environment, and can simulate a plurality of complete computer systems on an actual computer system. A veth pair (virtual Ethernet pair, virtual network port pair) is arranged in each virtual machine in the chip verification equipment, one end of the veth pair is positioned in the virtual machine, and the other end of the veth pair is positioned outside the virtual machine; wherein, the veth (virtual Ethernet) inside the virtual machine configures a corresponding IP (Internet Protocol, network protocol) address; for example, the network processor chip to be verified has n network ports capable of inputting and outputting, so n virtual machines are established, the virtual network ports inside each virtual machine are respectively defined as vethi_1, vethi_2, vethi_3, & gt, vethi_n, and IP addresses are respectively configured as 10.10.10.1, 10.10.10.2, 10.10.10.3, & gt, 10.10.10.n, and the virtual network ports outside the virtual machines are defined as vetho_1, vetho_2, vetho_3, & gt, vetho_n. Each virtual machine described in fig. 1 can perform data message generation processing, analysis processing, response processing and the like based on a kernel protocol stack of the chip verification device; the operating system of the chip verification device can be a Windows operating system or a Linux operating system; the chip authentication device may be a server or a computer terminal device.
In an exemplary embodiment, please refer to fig. 2, a chip verification method is provided, and an example of application of the method to the chip verification device shown in fig. 1 is described, where a first virtual machine and a second virtual machine are deployed in the chip verification device, and the first virtual machine and the second virtual machine may be any two of multiple virtual machines deployed in the chip verification device. As shown in fig. 2, the method comprises the steps of:
step 202, obtaining test requirement data through a first virtual machine and generating a first data message according to the test requirement data, wherein the first data message comprises a network address of a second virtual machine.
In this embodiment, the first virtual machine is used as a sender of the data packet, and the second virtual machine is used as a receiver of the data packet. The test requirement data may be that the first virtual machine sends a data packet to the second virtual machine, or that the first virtual machine applies to establish a TCP (Transmission Control Protocol ) connection with the second virtual machine, or that the first virtual machine requests to disconnect the TCP from the second virtual machine, or the like.
In one possible implementation manner, the test requirement data is that the first virtual machine sends a data message meeting the IPv4 (Internet Protocol version, network protocol version 4) and TCP protocol to the second virtual machine, and the first virtual machine can send packets by calling a packet sending tool; the chip verification device is based on a Linux system, and the adopted package issuing tool is sendip, and the corresponding command acts are as follows:
sendip -p ipv4 -is 10.10.10.1 -id 10.10.10.2 -p tcp -d testdata0123 10.10.10.2。
wherein, "10.10.10.1" is the network address of the first virtual machine, "10.10.10.2" is the network address of the second virtual machine, and the content data of the message is "testdata0123".
And the first virtual machine generates a corresponding first data message by using the kernel protocol stack according to the test requirement data.
Step 204, transmitting the first data message to the network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for being transmitted to the second virtual machine.
In the chip verification process, the network processor chip to be verified processes the first data message, and illustratively analyzes the first data message according to the TCP protocol and the IPv4 protocol, searches the routing table according to the destination address included in the header of the first data message Wen Zhongbao, and changes the header information of the data link of the first data message to obtain the second data message.
And 206, transmitting the second data message to the second virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the second data message by the second virtual machine.
The test requirement data indicates that the destination address of the first data message generated by the first virtual machine is the second virtual machine, the second data message is transmitted to the second virtual machine, and whether the verification is successful or not is judged according to the receiving condition of the second data message, the analysis condition of the second data message, the response condition of the second data message or the like of the second virtual machine.
In one possible implementation, the test requirement data is used to indicate a data forwarding function to authenticate the network processor chip; in this embodiment, the second virtual machine analyzes the second data packet to obtain content data included in the second data packet; and comparing the content data with the test requirement data to obtain a chip verification result.
After the second virtual machine receives the second data message, the second data message is analyzed and processed through the kernel protocol stack, and content data included in the second data message is obtained. And if the content data included in the second data message is the same as the test requirement data, the chip verification result aiming at the test requirement data is considered to be verification passing.
If the second virtual machine does not receive the second data message, the chip verification result at the time is verification failure; if the second virtual machine receives the second data message, but analysis of the second data message fails, the chip verification result is considered as verification failure; if the second virtual machine receives the second data message, but after the kernel protocol stack analyzes the second data message, the obtained content data is different from the test requirement data, and the chip verification result is considered as verification failure.
In another possible embodiment, the test requirement data is used to indicate a verification of a connection establishment function or a connection termination function of the network processor chip; referring to fig. 3, in this embodiment, a process of obtaining, by a second virtual machine, a chip verification result corresponding to test requirement data according to a second data packet includes:
and 302, responding to the second data message through the second virtual machine to obtain a third data message.
Step 304, the third data packet is transmitted to the network processor chip, so that the network processor chip processes the third data packet to obtain a fourth data packet for transmission to the first virtual machine.
Step 306, transmitting the fourth data message to the first virtual machine, and obtaining, by the first virtual machine, a chip verification result corresponding to the test requirement data according to the fourth data message.
Illustratively, the test requirement data is used to indicate a connection setup function for verifying the network processor chip, i.e. a handshake mechanism for different communication protocols. For example, the test requirement data is used to indicate a handshake mechanism for verifying whether the network processor chip can implement ICMP (Internet Control Message Protocol, network control message protocol), specifically, corresponding command behavior: ping 10.10.10.2, wherein the ping command is based on ICMP protocol checking if the first virtual machine and the second virtual machine are in network connectivity.
The ICMP protocol based connection setup requires three handshakes, i.e. the first virtual machine and the second virtual machine need three data interactions:
first data interaction: the first virtual machine sends a SYN (synchronization) message (i.e., a first data message) and waits for the second virtual machine to acknowledge.
And (3) performing second data interaction: when the second virtual machine receives the second data message forwarded by the network processor chip and based on the first data message, the kernel protocol stack processes the second data message, and responds to the SYN message to generate a SYN-ACK (synchronization-acknowledgement) message (i.e., a third data message), that is, step 302 in this embodiment; and waiting for confirmation of the first virtual machine.
After being processed by the network processor chip, the processed data message is transmitted to the first virtual machine.
Third data interaction: the first virtual machine receives and confirms the SYN-ACK message (which is marked as a fourth data message in the embodiment after being processed by the network processor chip), the kernel protocol stack processes the SYN-ACK message, generates and sends an ACK (acknowledgement) message for the SYN-ACK message, and at this time, the three-way handshake is completed, and connection is established between the two virtual machines.
The first virtual machine receives the fourth data message and generates an event identifier corresponding to the fourth data message and sent by the ACK message, for example, the first virtual machine can pop up a notification message to inform that the time is consumed in the connection establishment process, and the chip verification result is determined to be successful in verification according to the sampling of the notification message in the first virtual machine.
For example, if the three-way handshake fails, the first virtual machine may pop up a notification message to notify that the connection establishment fails, and determine that the chip verification result is verification failure according to sampling the notification message in the first virtual machine.
In the verification process of the three-way handshake mechanism, two virtual machines need to receive and send data messages, all the data messages are generated and analyzed by a kernel protocol stack of chip verification equipment, the data messages are processed by a network processor chip to be verified, and if the chip verification result is that verification is successful, namely network communication between the first virtual machine and the second virtual machine after a ping command is performed, the network processor chip can forward the data messages meeting the ICMP protocol data type and the handshake mechanism in a real use scene; thus, the problems of difficult realization and poor authenticity caused by constructing synchronous messages and acknowledgement messages in a handshake mechanism through an excitation sequence in the traditional technology are avoided.
The test requirement data may also be used to indicate a connection termination function that verifies whether the network processor chip can implement a four-swing mechanism or the like.
The chip verification method provided by the embodiment is used for deploying the chip verification equipment with the first virtual machine and the second virtual machine, and comprises the steps of obtaining test requirement data through the first virtual machine and generating a first data message according to the test requirement data, wherein the first data message comprises a network address of the second virtual machine; transmitting the first data message to a network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for transmission to a second virtual machine; transmitting the second data message to a second virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the second data message by the second virtual machine; therefore, the virtual machine can generate and analyze data messages meeting various communication protocols according to the test requirement data to simulate the real use scene of the network processor chip so as to simulate and verify the network processor chip, and the data messages in the whole verification process come from the virtual machine, so that the problem of low verification efficiency caused by the fact that the data messages corresponding to different communication protocols are required to be constructed in a verification platform in the traditional technology to serve as test excitation is solved; the chip verification method provided by the embodiment has high verification efficiency.
In an exemplary embodiment, please refer to fig. 4, in which data transmission is performed between each virtual machine and the network processor chip to be verified through a data transmission module. As shown in fig. 5, the process of transmitting the first data packet to the network processor chip to be verified and transmitting the second data packet to the second virtual machine in this embodiment includes:
step 502, a first data message is obtained from a first virtual machine through a data transmission module, and the first data message is transmitted to a network processor chip through the data transmission module.
In one possible implementation manner, the environment layer of the data transmission module includes a first portal driver (corresponding to port_driver_1 in fig. 4) and a first portal monitor (corresponding to port_monitor_1 in fig. 4) corresponding to a first chip portal of the network processor chip, where a driving function corresponding to the first chip portal is written in the first portal driver, mainly performing a function of inputting a data packet from the first virtual machine to the network processor chip, and a sampling function corresponding to the first chip portal is written in the first portal monitor, mainly performing a function of sampling and collecting a data packet output after being processed by the network processor chip.
In this embodiment, the data transmission module further includes a first socket interface, configured to obtain a first data packet from the first virtual machine.
The data transmission module is generally written in hardware programming languages such as system Verilog and the like, and cannot directly sample and drive data of a virtual network port of a virtual machine, so that a socket interface is established in the data transmission module by means of other programming languages, the socket interface is bound with a corresponding virtual network port, and sampling and driving of cyclic scanning are carried out.
Illustratively, after the socket interface is established, the socket interface is bound with the virtual network port of the corresponding virtual machine by using a bind function, the virtual network port is sampled by using a recvfrom function, and the virtual network port is driven by using a sendto function.
In this embodiment, step 502 includes step A1 and step A2:
step A1, a first data message is obtained from a first virtual network port of a first virtual machine through a first socket interface in a data transmission module.
And step A2, transmitting the first data message to a first chip network port of the network processor chip through a first network port driver in the data transmission module.
In one possible embodiment, the data transmission module further includes a direct programming interface (Direct Programming Interfac, DPI) corresponding to each socket interface. DPI is an interface that connects SystemVerilog directly to external language; in this embodiment, a first data packet acquired through a first socket interface is transmitted to a first portal driver through a first direct programming interface in the data transmission module. Thus, the first portal driver and the first socket interface can directly perform data transmission through the first direct programming interface.
Wherein, DPI comprises two layers: the system verilog layer and the external language layer are isolated from each other, which programming language is actually used as the external language layer is irrelevant to the system verilog end, the general external language layer uses a C language, and correspondingly, in this embodiment, at least one end of each socket interface connected with the DPI is implemented by using a C language algorithm model, and the other end of each socket interface can be implemented by using a C language algorithm model or using other language algorithm models.
In another possible implementation manner, the transmission of the first data message is realized between the first socket interface and the first portal driver through other system functions or a mode of sharing memory or sharing files.
Step 504, the second data packet is obtained from the network processor chip through the data transmission module, and the second data packet is transmitted to the second virtual machine through the data transmission module.
In one possible implementation, the environment layer of the data transmission module includes a second portal driver (corresponding to port_driver_2 in fig. 4) and a second portal monitor (corresponding to port_monitor_2 in fig. 4) corresponding to a second chip portal of the network processing chip, and a second socket interface, for transmitting a second data packet to the second virtual machine.
In this embodiment, step 504 includes step B1 and step B2:
and step B1, acquiring a second data message from a second chip network port of the network processor chip through a second network port monitor in the data transmission module.
And B2, transmitting a second data message to a second virtual network port of a second virtual machine through a second socket interface in the data transmission module.
In one possible implementation manner, the provided chip verification method further comprises the following steps: and transmitting a second data message acquired through a second network port monitor to a second socket interface through a second direct programming interface in the data transmission module. Thus, data transmission is realized between the second network port monitor and the second socket interface through the second direct programming interface.
In one embodiment, please refer to fig. 6, a chip verification method is provided for the chip verification device shown in fig. 4, the method includes:
in step 601, test requirement data is obtained through a first virtual machine, and a first data message is generated according to the test requirement data, wherein the first data message comprises a network address of a second virtual machine.
Step 602, obtaining a first data packet from a first virtual portal of a first virtual machine through a first socket interface in a data transmission module.
Step 603, transmitting, by a first direct programming interface in the data transmission module, a first data packet acquired through the first socket interface to the first portal driver.
Step 604, transmitting the first data message to the first chip network port of the network processor chip to be verified through the first network port driver in the data transmission module, so that the network processor chip processes the first data message to obtain a second data message for transmission to the second virtual machine.
Step 605, obtaining a second data packet from a second chip port of the network processor chip through a second port monitor in the data transmission module.
Step 606, transmitting the second data message acquired by the second portal monitor to the second socket interface through the second direct programming interface in the data transmission module.
In step 607, the second data packet is transmitted to the second virtual portal of the second virtual machine through the second socket interface in the data transmission module.
And 608, obtaining a chip verification result corresponding to the test requirement data according to the second data message by the second virtual machine.
Optionally, the obtaining, by the second virtual machine, a chip verification result corresponding to the test requirement data according to the second data packet includes: analyzing the second data message through the second virtual machine to obtain content data included in the second data message; and comparing the content data with the test requirement data to obtain a chip verification result.
Optionally, the obtaining, by the second virtual machine, a chip verification result corresponding to the test requirement data according to the second data packet includes: responding to the second data message through the second virtual machine to obtain a third data message; transmitting the third data message to the network processor chip so that the network processor chip can process the third data message to obtain a fourth data message which is transmitted to the first virtual machine; and transmitting the fourth data message to the first virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the fourth data message by the first virtual machine.
For example, with reference to fig. 4 in combination, using the chip verification method provided above, capturing a first data packet sent by veth_1 through a socket_1 interface, sending the first data packet to port_driver_1 through a DPI-C interface, and then driving the first data packet to a first chip port_1 of a network processor chip by the port_driver_1; and after being processed by the network processor chip, the corresponding port_monitor_2 samples a second chip network port port_2 and sends the second chip network port port_2 to a socket_2 interface through a DPI-C interface, and finally, the second chip network port port_2 is sent to the socket_2 interface to enter a second virtual machine.
It should be understood that, although the steps in the flowcharts related to the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a chip verification device for realizing the above related chip verification method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in one or more embodiments of the chip verification device provided below may be referred to the limitation of the chip verification method hereinabove, and will not be repeated here.
In one embodiment, as shown in fig. 7, there is provided a chip verification apparatus for a chip verification device, wherein a first virtual machine and a second virtual machine are disposed in the chip verification device, the apparatus comprising: a demand response module 702, a data transmission module 704, and a result determination module 706, wherein:
the demand response module 702 is configured to obtain test demand data through the first virtual machine and generate a first data packet according to the test demand data, where the first data packet includes a network address of the second virtual machine.
The data transmission module 704 is configured to transmit the first data packet to the network processor chip to be verified, so that the network processor chip processes the first data packet to obtain a second data packet for transmission to the second virtual machine, and is configured to transmit the second data packet to the second virtual machine.
The result determining module 706 is configured to obtain, by using the second virtual machine according to the second data packet, a chip verification result corresponding to the test requirement data.
In an exemplary embodiment, the data transmission module 704 is configured to obtain a first data packet from the first virtual machine, and transmit the first data packet to the network processor chip; and the network processor chip is used for acquiring the second data message from the network processor chip and transmitting the second data message to the second virtual machine.
In an exemplary embodiment, the data transmission module 704 is configured to obtain a first data packet from a first virtual portal of the first virtual machine through a first socket interface, and transmit the first data packet to a first chip portal of the network processor chip through a first portal driver.
In an exemplary embodiment, the data transmission module 704 is further configured to transmit, via the first direct programming interface, the first data packet obtained via the first socket interface to the first portal driver.
In an exemplary embodiment, the data transmission module 704 is configured to obtain, by using a second portal monitor, a second data packet from a second chip portal of the network processor chip, and transmit, by using a second socket interface, the second data packet to a second virtual portal of the second virtual machine.
In an exemplary embodiment, the data transmission module 704 is further configured to transmit, via the second direct programming interface, the second data packet obtained via the second portal monitor to the second socket interface.
In an exemplary embodiment, the result determining module 706 is configured to parse the second data packet through the second virtual machine to obtain content data included in the second data packet, and compare the content data with the test requirement data to obtain the chip verification result.
In an exemplary embodiment, the test requirement data is used to instruct to verify a connection establishment function or a connection termination function of the network processor chip, and the result determining module 706 is used to perform response processing on the second data packet through the second virtual machine, so as to obtain a third data packet; the data transmission module 704 is further configured to transmit the third data packet to the network processor chip, so that the network processor chip processes the third data packet to obtain a fourth data packet for transmission to the first virtual machine, and transmit the fourth data packet to the first virtual machine; the result determining module 706 is configured to obtain, by using the first virtual machine according to the fourth data packet, a chip verification result corresponding to the test requirement data.
The respective modules in the above-described chip authentication apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a chip authentication device, which may be a server, is provided, in which a first virtual machine and a second virtual machine are deployed, and an internal structure diagram thereof may be as shown in fig. 8. The computer device includes a processor, a memory, an Input/Output interface (I/O) and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used for storing data which needs to be called in the execution process of the chip verification method. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a chip authentication method.
It will be appreciated by those skilled in the art that the structure shown in fig. 8 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In an embodiment, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method embodiments described above when the computer program is executed.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the method embodiments described above.
In an embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the method embodiments described above.
It should be noted that, the user information (including, but not limited to, user equipment information, user personal information, etc.) and the data (including, but not limited to, data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data are required to comply with the related laws and regulations and standards of the related countries and regions.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the various embodiments provided herein may include at least one of relational databases and non-relational databases. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic units, quantum computing-based data processing logic units, etc., without being limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A chip authentication method for a chip authentication device, the chip authentication device having a first virtual machine and a second virtual machine disposed therein, the method comprising:
acquiring test demand data through the first virtual machine and generating a first data message according to the test demand data, wherein the first data message comprises a network address of the second virtual machine;
transmitting the first data message to a network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for transmission to the second virtual machine;
and transmitting the second data message to the second virtual machine, and acquiring a chip verification result corresponding to the test requirement data through the second virtual machine according to the second data message.
2. The method of claim 1, wherein transmitting the first data message to a network processor chip to be authenticated comprises:
acquiring the first data message from the first virtual machine through a data transmission module, and transmitting the first data message to the network processor chip through the data transmission module;
the transmitting the second data message to the second virtual machine includes:
and acquiring the second data message from the network processor chip through the data transmission module, and transmitting the second data message to the second virtual machine through the data transmission module.
3. The method of claim 2, wherein the obtaining, by the data transmission module, the first data packet from the first virtual machine and transmitting, by the data transmission module, the first data packet to the network processor chip, comprises:
acquiring the first data message from a first virtual network port of the first virtual machine through a first socket interface in the data transmission module;
and transmitting the first data message to a first chip network port of the network processor chip through a first network port driver in the data transmission module.
4. A method according to claim 3, characterized in that the method further comprises:
and transmitting the first data message acquired through the first socket interface to the first network port driver through a first direct programming interface in the data transmission module.
5. The method of claim 3, wherein the obtaining, by the data transmission module, the second data packet from the network processor chip and transmitting, by the data transmission module, the second data packet to the second virtual machine, comprises:
acquiring the second data message from a second chip network port of the network processor chip through a second network port monitor in the data transmission module;
and transmitting the second data message to a second virtual network port of the second virtual machine through a second socket interface in the data transmission module.
6. The method of claim 5, wherein the method further comprises:
and transmitting the second data message acquired by the second network port monitor to the second socket interface through a second direct programming interface in the data transmission module.
7. The method of claim 1, wherein the obtaining, by the second virtual machine, the chip verification result corresponding to the test requirement data according to the second data packet includes:
analyzing the second data message through the second virtual machine to obtain content data included in the second data message;
and comparing the content data with the test requirement data to obtain the chip verification result.
8. The method of claim 1, wherein the test requirement data is used to indicate verification of a connection establishment function or a connection termination function of the network processor chip; the obtaining, by the second virtual machine, a chip verification result corresponding to the test requirement data according to the second data packet includes:
responding to the second data message through the second virtual machine to obtain a third data message;
transmitting the third data message to the network processor chip so that the network processor chip can process the third data message to obtain a fourth data message for transmission to the first virtual machine;
and transmitting the fourth data message to the first virtual machine, and acquiring a chip verification result corresponding to the test requirement data according to the fourth data message through the first virtual machine.
9. A chip authentication apparatus for a chip authentication device having a first virtual machine and a second virtual machine disposed therein, the apparatus comprising:
the demand response module is used for acquiring test demand data through the first virtual machine and generating a first data message according to the test demand data, wherein the first data message comprises a network address of the second virtual machine;
the data transmission module is used for transmitting the first data message to a network processor chip to be verified, so that the network processor chip processes the first data message to obtain a second data message for transmitting to the second virtual machine, and is used for transmitting the second data message to the second virtual machine;
and the result determining module is used for acquiring a chip verification result corresponding to the test requirement data according to the second data message through the second virtual machine.
10. A chip authentication device, characterized in that a first virtual machine and a second virtual machine are deployed in the chip authentication device, the chip authentication device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of the method according to any of claims 1 to 8 when the computer program is executed.
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