CN117240795A - Scheduling method and system supporting multi-mode processing logic - Google Patents

Abstract

The invention discloses a scheduling method and a scheduling system supporting multi-mode processing logic, wherein the method comprises the following steps: marking user messages according to message processing logic and QoS service requirements predefined by users, and mapping message classification to different flow queues through the marks; by utilizing the capability of the programmable switch, the effect of hardware hierarchical QoS is realized by using only a single queue through hierarchical level calculation and admission control, and the fair scheduling among different processing logics and the multi-service programmable scheduling in each processing logic are realized. A Polymorphic PIFO prototype framework is realized on a hardware Barefoot Tofino switch, and the result shows that the Polymorphic PIFO can ensure the isolated coexistence of multi-mode processing logic and realize a self-defined programmable queue scheduling algorithm.

Description

Scheduling method and system supporting multi-mode processing logic

Technical Field

The present invention relates to the field of packet scheduling technologies, and in particular, to a scheduling method and system supporting multi-mode processing logic.

Background

With the expansion of application scale such as live broadcast and network conference, the application features are not limited to the traditional end-to-end network transmission mode. For example, in some scenarios the user is more concerned with content than the serving communication entity, which exposes the stiffness of IP addressing. The current network is a best effort transmission mode and is completely independent of the traffic scenario. Thus, although developers can implement different application functions through rich application layer technologies, a network transmission manner is not optimal to a certain extent.

In order to solve the problem of IP waist thinning and break the dilemma of network development, the academic circles at home and abroad develop numerous basic theories and key technical researches aiming at the future network field. The 'subversion' technical route directly discards the existing IP thin waist model, and deploys a brand new network system architecture to adapt to the requirements of future networks. The content identification, the identity identification, the geographic position identification and other various identification systems are widely studied, and meanwhile, in order to strive for integrating various network advantages and improving the bearing capacity of the network to multiple services, various identification fusion network schemes, such as a multi-mode network environment, are provided so as to support user-defined access identification structures and data message structures and process messages according to user-defined logic.

The multi-mode network fusion scheme comprises a plurality of identification systems, and each identification has different design concepts, operation modes, communication models and adaptation services. When multiple processing logics run in the same physical environment, the multiple processing logics need to share network resources, and if no good mechanism is provided for guaranteeing isolation among the processing logics, the mutual preemption of the resources among the processing logics is extremely easy to cause, and the actual running performance of the network is affected.

The network processing logic isolation is the comprehensive experience description of the user plane, and relates to various factors such as bandwidth allocation, resource allocation, forwarding behavior and the like. The scientific problems described are: the processing logics coexist in the same network environment, and the processing logics do not influence each other when the nodes and the network resources are shared. When multiple processing logic shares nodes and network resources, the performance impact should be limited. How to guarantee that each network processing logic can process and send messages fairly according to the allocated physical resources requires a resource guarantee method based on data packet scheduling at the data packet level.

There are many packet scheduling algorithms currently available to accommodate different application scenarios. But these algorithms are both tied to hardware and fixed scenarios. The scheduling algorithm itself has no programmability, and the scheduling algorithm supported by the switch is less. Although the scheduling parameters can be adjusted, after the switch is designed, the algorithm logic cannot be modified or a completely new algorithm is added. Therefore, to achieve the goal of customizing, validating, and modifying scheduling algorithms according to application requirements, a queue abstraction structure needs to be sought to support the expression of multiple packet scheduling.

Disclosure of Invention

Aiming at the problems, the invention provides a scheduling method and a scheduling system for supporting multi-mode processing logic, which ensure that the flow change of one processing logic does not influence the flow scheduling of another processing logic, can highly customize a data packet scheduling algorithm according to service requirements and improve the expandability of queue scheduling, and support the expression of a queue abstract structure of multi-mode processing logic. The capability of a programmable switch is utilized to apply programmable queue scheduling to an HQoS mechanism, and hierarchical programmable scheduling is realized on hardware by using only one queue, so that customizable QoS service is provided for multi-mode processing logic, which is called as a Polymorphic PIFO framework.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

in one aspect, the present invention provides a scheduling method supporting multi-mode processing logic, including:

step 1: marking user messages according to message processing logic and QoS service requirements predefined by users, and mapping message classification to different flow queues through the marks;

step 2: by utilizing the capability of the programmable switch, the effect of hardware hierarchical QoS is realized by using only a single queue through hierarchical level calculation and admission control, and the fair scheduling among different processing logics and the multi-service programmable scheduling in each processing logic are realized.

Further, the step 1 includes:

and classifying and marking the users and the services on the edge side to distinguish different users and different services, providing differential services for the different services of the different users, distinguishing the service messages of each user according to classification conditions by the equipment, marking the different service messages of each user by using different serv.types, and adding the messages into different flow queues for scheduling.

Further, the step 2 includes:

when a data packet arrives at a switch, the switch extracts a data packet classification mark to obtain a scheduling algorithm of a flow to which the data packet belongs; then the exchanger updates the arrival byte estimation of the stream aggregate to which the data packet belongs and obtains the grade value of the stream; then using admission control to decide whether to receive the data packet, the class threshold being determined by a received byte estimate and an arrival byte estimate; after that, the switch recursively updates the rank value of each flow set in the hierarchy according to the scheduling policy determined by each layer; queuing the data packet to the end of the queue; at egress, when the queue is not empty, the packet is dequeued from the head of the queue and sent out.

Further, the rank threshold is calculated as follows:

where a (i) represents the arrival byte estimate of node i, b (i) represents the received byte estimate of node i, and k represents the burst tolerance parameter.

Further, the admission control includes:

allocating a space to tolerate small bursts with parameter k, when a (i). Ltoreq.k.b (i), all packets are allowed to enqueue, by maintaining a sliding window of recently received packets, receiving only R (i) values no greater than R (i) using as a criterion the class value R (i) to each layer of the packetIf not, discarding the data packet.

Further, the calculation of the rank value is initiated by the leaf node, and the rank value of each node is calculated in a recursive manner.

Further, when the scheduling algorithm associated with the user flow queue is maximum and minimum fair scheduling, the level of the data packet is the fair quota information of the flow.

Further, according to the scheduling rule of the user demand, the flow queues are combined into class queues, and service messages in different class queues are used as a flow combination and mapped into the next-level group queues; when the class queue scheduling rule is weighted fair scheduling, calculating the grade according to the weighted value and the size of the data packet; when the scheduling algorithm associated between the group queues is a strict priority algorithm, the class of the group queues is the priority of each group queue.

Further, the programmable switch comprises a Barefoot Tofino switch.

The invention further provides a dispatching system supporting multi-mode processing logic, which comprises a message classification marker and a programmable hierarchical dispatcher;

the message classification marker is used for marking the user message according to the message processing logic and the QoS service requirement predefined by the user, and mapping the message classification to different flow queues through the mark;

the programmable hierarchical scheduler is used for realizing the effect of hardware hierarchical QoS by using only a single queue through hierarchical level calculation and admission control by utilizing the capability of the programmable switch, and realizing fair scheduling among different processing logics and multi-service programmable scheduling in each processing logic.

Further, the packet classification marker is specifically configured to:

and classifying and marking the users and the services on the edge side to distinguish different users and different services, providing differential services for the different services of the different users, distinguishing the service messages of each user according to classification conditions by the equipment, marking the different service messages of each user by using different serv.types, and adding the messages into different flow queues for scheduling.

Further, the programmable hierarchical scheduler is specifically configured to:

when a data packet arrives at a switch, the switch extracts a data packet classification mark to obtain a scheduling algorithm of a flow to which the data packet belongs; then the exchanger updates the arrival byte estimation of the stream aggregate to which the data packet belongs and obtains the grade value of the stream; then using admission control to decide whether to receive the data packet, the class threshold being determined by a received byte estimate and an arrival byte estimate; after that, the switch recursively updates the rank value of each flow set in the hierarchy according to the scheduling policy determined by each layer; queuing the data packet to the end of the queue; at egress, when the queue is not empty, the packet is dequeued from the head of the queue and sent out.

Further, the rank threshold is calculated as follows:

where a (i) represents the arrival byte estimate of node i, b (i) represents the received byte estimate of node i, and k represents the burst tolerance parameter.

Further, the admission control includes:

allocating a space to tolerate small bursts with parameter k, all packets being allowed to enqueue when a (i). Ltoreq.k.b (i), by maintenanceA sliding window for recently received packets, receiving only R (i) values not greater than using as a criterion the class value R (i) to each layer of the packetIf not, discarding the data packet.

Further, the calculation of the rank value is initiated by the leaf node, and the rank value of each node is calculated in a recursive manner.

Further, when the scheduling algorithm associated with the user flow queue is a max-min fairness algorithm, the level of the data packet is flow fairness quota information.

Further, according to the scheduling rule of the user demand, the flow queues are combined into class queues, and service messages in different class queues are used as a flow combination and mapped into the next-level group queues; when the class queue scheduling rule is weighted fair scheduling, calculating the grade according to the weighted value and the size of the data packet; when the scheduling algorithm associated between the group queues is a strict priority algorithm, the class of the group queues is the priority of each group queue.

Compared with the prior art, the invention has the beneficial effects that:

1) The programmable scheduling prototype Polymorphic PIFO supporting the multi-mode processing logic is provided, and the hierarchical customizable queue scheduling algorithm can be realized on hardware at a linear speed.

2) By utilizing the capability of the programmable switch, the effect of hardware hierarchical QoS is realized by using only a single queue through hierarchical level calculation and admission control, and the method has no flow-by-flow state and complex hierarchical queue management.

3) A Polymorphic PIFO prototype framework is realized on a hardware Barefoot Tofino switch, and the result shows that the Polymorphic PIFO can ensure the isolated coexistence of multi-mode processing logic and realize a self-defined programmable queue scheduling algorithm.

Drawings

FIG. 1 is a schematic block diagram of a scheduling method supporting multi-mode processing logic according to an embodiment of the present invention;

FIG. 2 is a prototype of a scheduling method supporting multi-modal processing logic according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a message classification process according to an embodiment of the present invention;

fig. 4 is a schematic diagram of hierarchical rank values and admission control according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a tree structure for rank value update according to an embodiment of the present invention.

Detailed Description

The invention is further illustrated by the following description of specific embodiments in conjunction with the accompanying drawings:

in view of the fact that IP networks are deployed globally, subverted new network attempts are difficult to succeed, and the realization of the integration of new networks with existing networks is a new idea of future internet development. The novel converged network comprises a plurality of identification systems of different processing logics, and because of the differences of message formats, routing protocols, exchange modes, forwarding logics and the like of the various identification systems, when the various processing logics operate on the same physical environment, the various processing logics need to share physical resources such as computing resources, memory resources, link resources and the like. Therefore, how to unify the scheduling problem among various processing logics and the scheduling problem in a single processing logic to the limited queue resource expression is needed, and the performance isolation of various network processing logics is supported by a brand-new scheduling algorithm, so that the performance isolation is not affected, and customizable deterministic QoS service is provided for various processing logics/multiple services.

Conventional QoS techniques typically distribute messages to corresponding queues for queuing according to a service type, and then forward the queued messages out of the interface according to various scheduling algorithms. Because the queuing process of the traditional QoS technology only has one-stage queue scheduling, in the access network, under the conditions that the user scale is large and the service types of users are more and more abundant, the classification mechanism is difficult to meet the requirement of fine flow management in multi-user multi-service scenes, and the layering of the HQoS technology is more suitable for the scenes.

As shown in fig. 1, after a data packet arrives at a switch, the data packet is classified according to classification rules such as a packet logic identifier, a local identifier is allocated to the packet, and the data packet with the same processing logic is put into a corresponding flow queue through the identifier. The service messages with the same service characteristics in different flow queues are used as a flow combination, and a user can customize a scheduling strategy required to be executed by the messages in the flow queue combination, and schedule the messages in the different flow queues to a next class queue for scheduling. And carrying out flow combination on the service messages in different types of queues with the same characteristics, wherein a user can customize a scheduling strategy executed by the messages in the type of queue combination, and schedule the messages in the different types of queues to a next-level group queue for scheduling. And dispatching the flow in the group queue into the queue of the outbound interface according to a self-defined dispatching strategy, and forwarding the messages in the queue of the outbound interface in sequence. (the number of scheduling levels depends on the needs of the traffic schedule).

Let processing logic 1 carry all traffic for user 1 and processing logic 2 carry all traffic for user 2. User 1 is a VIP user, comprising data and video services, and user 2 is a general user, comprising voice and file services. The two-stage scheduling which can be provided by the hierarchical QoS is scheduling based on users and scheduling based on services, the scheduling among the users can ensure that messages of VIP users are sent preferentially, and the scheduling among the services is scheduled based on different service requirements of each user, so that the requirements of bandwidth, time delay and the like of the users are ensured.

To intuitively illustrate the method of the present invention, a simple example is provided. Suppose user 1 data traffic message i is labeled F1 and user 1 video traffic message j is labeled F2. After the messages i and j arrive at the switch, the user messages i and j are respectively put into the flow queues F1 and F2 according to the identification. The service messages in the two flow queues belong to the same user, all the flows of the user need to be shaped uniformly, and the corresponding scheduling algorithm is configured for the two flow queues by using the programmable algorithm and mapped into the class queues for scheduling. In the programmable hierarchical scheduling portion, a user may define scheduling rules according to needs, with the programmability of how to calculate the ordering of each packet. Assuming that the scheduling algorithm associated with the user flow queue is the shortest remaining processing time SRPT, the class (rank) of the packet is the remaining processing time of the flow (or the remaining bytes of the flow). The remaining processing time of the flow queue F1 is 1, and the remaining processing time of the flow queue F2 is 2, that is, rank.f1=1, rank.f2=2. The flow queue is scheduled as class queue c1= { i, j } according to the scheduling rule SRPT. Similarly, service messages m and n of the user 2 are respectively put into flow queues F3 and F4, and the flow queues are combined into class queues c2= { n, m } according to a certain scheduling rule of the user demand.

The service messages in different types of queues are used as a flow combination and mapped to the next-stage group queue, namely, the types of queues C1 and C2 are combined into a group queue G1 according to a scheduling rule. Assuming that the class queue scheduling rule is weighted fair scheduling WFQ, a rank (rank) is calculated according to a weighted value and a packet size, rank=previous_rank+weight_packet_length, rank.c1=10, rank.c2=20, and the class queue is scheduled as a group queue g1= { C1, C2}, according to the rank value, where weight represents a weight, previous_rank represents a rank of a Previous packet, and new_packet_length represents a length of the packet. Similarly, according to the scheduling rule of the user requirement, the service messages of the user 3 and the user 4 can be scheduled into a group queue G2 finally. Assuming that the scheduling algorithm associated between the group queues is a strict priority algorithm, the rank level is the priority of each group queue, rank.g1=priority.g1=2, rank.g2=priority.g2=1 is set, and according to the strict priority scheduling rule, the traffic in the group queues is scheduled to the queues of the outgoing interfaces, and the messages output= { G2, G1} = { { { { { a, b }, { d, c }, { i, j }, { n, m } }, in the interfaces are sequentially transferred.

Prototype design

As shown in fig. 2, a key idea of a hierarchical programmable queue scheduling method supporting multi-mode processing logic, namely a Polymorphic PIFO prototype, is to provide customizable queue scheduling for a hierarchical QoS scheme by identifying traffic flows of each processing logic in a programmable hierarchical scheduling manner. Different processing logic is used for bearing multiple services of different users, providing refined flow management for multiple users and multiple services, executing a hierarchical scheduling mechanism to ensure performance isolation, and providing customizable QoS service for users. The Polymorphic PIFO prototype implements hierarchical scheduling using only a single queue, i.e., a single queue can support multiple stream scheduling. However, as the programmable device cannot realize the multi-level queue, the Polymorphic PIFO prototype uses hierarchical rank calculation and admission control, and only uses the one-level queue to realize hierarchical scheduling.

The Polymorphic PIFO prototype framework is mainly composed of two parts: message classification and programmable hierarchical scheduling.

Message classification: as shown in fig. 3, the access switch assigns an identifier to the message, and maps the message to the flow queue through the identifier. And distinguishing voice service, data service and video service of different processing logics, and placing the message into a corresponding flow queue to wait for scheduling.

Programmable hierarchical scheduling: as shown in fig. 4, "hierarchy" is a logical concept in that when physically implemented they are actually separate queues, arranged into separate groups, meaning that only a single level of queues is required in hardware, which can be implemented on devices that do not support a hierarchy. Through hierarchical rank value calculation and admission control, the effect of approximate HQoS is achieved. As shown in the figure, the queue F and the queue C are not actual queues, and do not buffer the message, and the actual work is the calculation of the rank value. And processing the data packets based on the rank value admission control according to different queue scheduling strategies, preferentially scheduling the data packets with low rank value, and discarding the data packets with rank value higher than a threshold value.

Further, the following expansion is performed:

packet marking

And classifying and marking the users and the services on the edge side so as to distinguish different users from different services and provide differential services for different services of different users. The ID is a local identifier assigned by the device to the message, and the system maps the message to the flow queue through the identifier. Typically, the user.type of each ID represents the flow aggregation to which the packet belongs in the flow hierarchy, i.e. represents a different traffic aggregation for a certain user. The serv.type of each ID can be used for identifying one type of service of a certain user, the device distinguishes the service message of each user according to the classification condition, then identifies different service messages of each user by using different serv.types, and adds the messages into different flow queues for scheduling.

According to different application scenes, different rules can be adopted to classify the users. For example, an operator pushes out a home bandwidth package in a certain cell, including three services of voice over IP (VoIP), television over IP (IPTV), and high-speed internet surfing. Each household is a user with three different services, each service of each household being classified by the rule. VoIP traffic of all users is mapped to T, IPTV traffic of all users is mapped to V, high-speed internet traffic of all users is mapped to H, and individual households are labeled a, B, c. And bandwidth allocation is carried out among the services of each family through hierarchical multilevel scheduling, so that the service quality is ensured.

Rank (rank) calculation

In programmable hierarchical scheduling, each layer may employ any scheduling algorithm. Any scheduling algorithm is finally mapped into a rank value, and the admission control is executed according to the rank value to decide to forward or discard the data packet. The threshold is determined by the dynamic change in the difference between the arrival rate and the departure rate. When the arrival rate significantly exceeds the departure rate, the threshold becomes more stringent, which ensures that the rate at which packets are accepted approximately matches the departure rate. The hierarchical scheduling is realized by recursively calculating the rank value of each node, processing the data packets based on the rank value admission control according to different queue scheduling strategies, preferentially scheduling the data packets with low rank value, and discarding the data packets with rank value higher than a threshold value.

In programmable hierarchical scheduling, the calculation of the rank value is initiated by the leaf node, as shown in fig. 5. In fig. 5, node i represents a leaf flow. The leaf flows are aggregated into traffic flow C _i Traffic flow C _i Aggregation into user group node G _i The individual user groups are aggregated into a root node physical queue. When the leaf node is accessed in one stage, the parent node needs to request the service related acceptance byte length b (Ci) from its parent node, if the parent node does not calculate the stored data packet acceptance byte length in the current stage, it will request the acceptance byte length b (Gi) from its parent node, thenAnd so on. After the request arrives at the root node, the update root node accept byte length b (root) is calculated. The accepted byte length b (Gi) of the update child node is calculated from b (root), and the rank value R (Gi) of the update intermediate node is recursively calculated in combination with the arriving byte length. And so on, arriving leaf nodes update their rank value R (i). When the request reaches a node for which the accepted byte length has been calculated at the current stage, no further upstream requests are performed. The method realizes the isolation assurance of the user level and the service level.

The arrival byte length estimation is used to estimate the arrival byte of the stream aggregation of nodes in the hierarchy, using a (i) to represent the arrival byte length of node i. The accepted byte length estimate is used to estimate the queue size of the target queue, with b (i) representing the accepted byte length of node i. It uses the difference between the arrival byte length a (i) and the acceptance byte length b (i) to obtain the difference between the arrival rate and the departure rate. The threshold for admission control is more stringent when the arrival byte length approaches the target acceptance byte length. A space is allocated to tolerate a small burst with parameter k and when the byte length is reached within a threshold (i.e. a (i). Ltoreq.k.b (i)), all packets are allowed to enqueue. The rank value R (i) to each layer of the packet is used as a criterion by maintaining a sliding window of recently received packets. Receiving only R (i) values not greater thanIf not, discarding the data packet.

Algorithm 2 gives a pseudo code for programmable hierarchical scheduling. When a packet arrives at the switch, the switch extracts the packet classification label and obtains the scheduling algorithm (line 1-4) of the flow to which the packet belongs. The switch then updates the arrival byte estimates for the stream aggregate to which the packet belongs and obtains the rank value (line 5-7) for that stream. Admission control is then used to decide whether to receive a packet, the threshold being determined by a received byte estimate b (i) and an arriving byte estimate a (i) (line 8-14). After this, the switch recursively updates the rank value (line 15-17) for each flow set in the hierarchy according to the scheduling policy determined by the layers. The queue is a FIFO queue that queues packets to the end of the queue. At egress, when the queue is not empty, the packet is dequeued from the head of the queue and sent out (line 23-26).

Data plane design and implementation

As an implementation manner, in this section, a data plane design for implementing a Polymorphic PIFO prototype framework on a programmable switch Barefoot Tofino is described, taking a fair scheduling algorithm as an example for each layer of scheduling algorithm. Fair queuing is a canonical mechanism that provides fair bandwidth allocation for network traffic by ensuring that each flow gets a fair share, regardless of other flows. The link sharing among different processing logics is realized through the fair queuing of hierarchical rank value calculation, so that a maximum and minimum fairness algorithm is realized. In this way fair queuing forces isolation between competing flows, thereby ensuring that normal flows are immune to behaving endless flows. Based on the structure of the programmable switch, it is demonstrated how the data packet classification labels, rate estimation, and rank value hierarchical computation logic are designed and implemented on the programmable switch.

Definition:

active node: a congested or backlogged node;

w _i : the integer weight of the node i allocates the link capacity according to the weight proportion, and can be set as the guaranteed bandwidth of the node i;

r (i): the level of node i, expressed using a fair quota;

b (i): the balance of node i, the number of bytes allowed to be transferred.

Each node represents a flow, the node at the top of the hierarchy (called root) represents the network interface where the scheduling algorithm is active, all the traffic maps that are reachedTo the leaf node. The internal nodes are neither root nor leaf nodes. The internal and root requests and allocations consist of the total requests and allocations of their child nodes, respectively. The available capacity of the internal node depends on the requests of leaf nodes in all branches in the hierarchy. Each node is associated with an integer weight w _i May be set as a rate guarantee for that node.

Message classification marking: first, at the MAC layer, different processing logic is identified with the ethernet frame type etherType field, including IPv 4-based, content name-based, geographic location-based, identity information-based processing logic, and the like. When the packet is matched with the ethertype=0x0800, executing IPv4 packet forwarding logic, and analyzing according to an IPv4 message format; when the packet is matched with the ethertype=0x8624, executing packet forwarding logic based on the content name, and analyzing according to the NDN message format; when the packet is matched with the ethertype=0x8947, executing the packet forwarding logic based on the geographic position, and analyzing according to the GeoNetworkIng message format; and when the packet is matched with the ethertype=0x27c0, executing the packet forwarding logic based on the identity information, and analyzing according to the mobile first message format. And secondly, classifying and marking the users and the services carried by different processing logics, distinguishing the users and the different services of the different processing logics according to predefined QoS service requirements, and providing differential services for the different services of the different users. After the packet arrives at the edge switch, the packet is marked with Setvalid (). According to the classification mark of the user to the message, the edge switch newly adds a header field pkt.id, wherein the pkt.id field comprises user information user.type and service information serv.type. After the packet arrives at the switch, the Setvalid () function marks pkt.id as legal, and merges this field into the corresponding position of the packet when encapsulating the packet. After the data message arrives at the core switch, the switch reads the pkt.id field value to determine the flow queue to which the data packet belongs, and adds the flow queue to wait for scheduling.

Fairness estimation: and estimating the arrival byte length, performing fair scheduling according to the arrival byte length of each data packet, and estimating by using the length of the occupied queue and the total length of the queue. Requesting bandwidth from the target queue, obtaining the occupied length of the service message according to the mark, calculating an updated fair quota f through the ratio of the service message to the length of the queue, and returning the byte length of the message which can be transmitted. When all the arrival byte lengths are smaller than the target queue length, the fair quota f is the maximum data packet arrival byte length, and all the data packets are received; when all the arrival byte lengths exceed the target queue length, a fair quota f is calculated according to the arrival byte length ratio and the received byte length between the data packets. The arriving byte length receives the data packet within the fair quota and discards the data packet outside the fair quota. Specifically, the switch needs to read the fair quota to calculate the drop probability, and then updates the acceptable byte length according to whether to receive or drop the data packet, and then uses to update the fair quota f.

The difficulty with a traffic manager module having queue length information between the ingress pipe and the egress pipe is that the queue length information is only available when a packet passes through the traffic manager and can therefore only be read at the egress pipe. But requires the calculation of an updated fair quota on the ingress pipe to acquire the queue length. A loop-based queue length estimation method is used to transfer queue length information from the outlet pipe to the inlet pipe. Specifically, a register array is used to store the queue length of each of the egress ports in the egress pipe, denoted q_len_ingress. After the message passes through the traffic manager, the value of the queue length may be written into q_len_entry. At the same time there is a copy of the register array at the entry pipe, denoted q_len_ingress. The queue length is read from q_len_entry of the egress pipe using a set of work packets. When the work packets leave the egress pipe, they are re-circulated to re-enter the ingress pipe and update the queue length in q_len_ingress using the values they read.

When a work packet is ready for a queue length at the ingress pipe, normally arriving packets can access the queue length information at the ingress pipe. And then, calculating an updated fair quota according to the ratio of the queue length to the queue length occupied by the data packet of the type, and comparing the fair quota with the data packet length to determine whether to receive the length and the probability of discarding the data packet. If a packet is received, it also writes the current queue length to the egress pipe. Barefoot Tofino 2 can read the queue length directly at the ingress pipe without recirculation.

rank value (fair quota) hierarchical computation: the packet scheduling algorithm is programmable to refer to how the rank of each packet is calculated. In this example, the rank of the max-min fair scheduling algorithm is the fair quota. The fair quota is compared to the number of bytes that can be transmitted to determine whether to transmit the data packet. The fair quota of one node is recalculated and allocated during the main round of access. If at the end of the main round, some nodes have unused quota, the remaining round is started, where the unused quota will be allocated to the active nodes. If there is still unused quota after the end of the remaining rounds, additional remaining rounds are started.

Each node maintains the number of bytes (b _i ). In the master round, the root assigns the remaining amounts to its children, which in turn assign the remaining amounts to their own children, and so on.

In each round, all active internal nodes recalculate the number of bytes that a child node with a weight set to 1 can transmit in that round, which is called a fair quota. The fair quota for node i is defined as:

where Child (i) represents a Child node of node i.

Before calculating the fair quota, each node i updates its balance and remainder. For the root node:

b(root)＝b(root)+r(root)，r(root)＝0

that is, the remainder is added to the balance and then reset. For an active internal node, update is:

b(i)＝b(i)+r(i)+w _i R(C _i )，b(C _i )＝b(C _i )-w _i R(C _i )，r(i)＝0

here, the balance of node i increases by w _i R(C _i ) While parent node C _i The balance of (c) is reduced by the same amount. And the remaining r (i) is added to the balance and then reset. Since the quota of the internal node depends on the fair quota of the parent node, the updating of the balance and the calculation of the quota are performed in a top-down manner. Before an active leaf node makes a round of transmission, it performs an update:

b(i)＝b(i)+w _i R(C _i )，b(C _i )＝b(C _i )-w _i R(C _i )

updating of the balance and calculation of the fair quota are initiated by the leaf node. Node i is an active leaf node that requests a fair quota R (C _i ). If the parent node has not calculated its quota in the current round, it will send it to its own parent node G _i A request for a fair quota is sent, and so on. If the root node is reached and the scheduler is in the master round, the root node's balance b (root) and quota R (root) are calculated, and then the quota is passed on to child node G _i . In the remainder round, the root return quota is R (root) =0. Next, internal nodes Ci and G _i Their balances are updated with fair quotas from their respective parent nodes and their own fair quotas are calculated. In the last step, the leaf node updates its own balance. When the request reaches a node whose quota has been calculated in the current round, no further upstream requests are made.

Before sending the data packet, when the leaf node i is accessed in the polling, the balance is updated according to the quota of the father node. If the length of the data packet at the head of the queue is L and the balance of i is greater than L, the data packet is sent, and then the balance of the leaf and the root node is updated.

b(i)＝b(i)-L,b(root)＝b(root)+L

By increasing the balance of the root node for each transmitted packet, the root will accumulate a balance for allocation on the next master round. As long as there is a sufficient balance, node i can continue to transmit packets. If the packet size at the head of the queue is L and b _i <L, then the scheduler turns to the wheelThe next node in the poll. If leaf node i is serviced and there are no more packets to transmit, it becomes idle and returns the remaining balance to its parent. For example, node i becomes idle with a balance b (i). Then perform the update:

r(C _i )＝r(C _i )+b(i)，b(i)＝0

the root node and active internal nodes also reserve a residual r, representing the bytes that the previous round of collection from the offspring is allowed to be transmitted, initially setting r (i) =0. The remaining functions. The remainder of the internal node i or root collects the balance returned by the idle child nodes in the current round. The reason for not adding the return balance of the free child node immediately to the parent node is to prevent the return balance from being used in the current round. This is advantageous for leaf nodes that are accessed later in the poll. By adding the remainder to the balance only at the beginning of a new round, it is ensured that all offspring can obtain a portion of the unused balance.

A new master round is started only when the sum of all quota allocated to the node has been used for transmission. A node will only run out of its full quota when it is free in the current round. This results in an unused balance being added to the remainder. If this occurs, the remainder accumulated in one round will be assigned to the offspring node in the subsequent remaining round. At least one internal node i at the beginning of the condition of the remaining rounds satisfies the sum of the balance plus the remaining not less than the weight, i.e. the node calculates a non-zero quota using its balance and the remaining.

The working principle of the rest wheel is the same as that of the main wheel. First all backlogged nodes are marked as active, then a complete active node cycle, the balance is updated and the quota is calculated. The only difference from the master is that the quota for the root is set to 0, which means that no new quota is distributed from the root. If at the end of the remaining round there is still one internal node j, satisfying the sum of the balance plus the remaining not less than the sum of the weights, another round of remaining rounds is started. This process continues until none of the internal nodes satisfies this condition, in which case a new master wheel is started.

Since the balance is a transfer allowance and the remainder is an unused transfer allowance, maintaining invariance ensures that the maximum traffic transferred in one round does not drift.

On the basis of the embodiment, the invention also provides a scheduling system supporting multi-mode processing logic, which comprises a message classification marker and a programmable hierarchical scheduler;

the message classification marker is used for marking the user message according to the message processing logic and the QoS service requirement predefined by the user, and mapping the message classification to different flow queues through the mark;

the programmable hierarchical scheduler is used for realizing the effect of hardware hierarchical QoS by using only a single queue through hierarchical level calculation and admission control by utilizing the capability of the programmable switch, and realizing fair scheduling among different processing logics and multi-service programmable scheduling in each processing logic.

Further, the packet classification marker is specifically configured to:

and classifying and marking the users and the services on the edge side to distinguish different users and different services, providing differential services for the different services of the different users, distinguishing the service messages of each user according to classification conditions by the equipment, marking the different service messages of each user by using different serv.types, and adding the messages into different flow queues for scheduling.

Further, the programmable hierarchical scheduler is specifically configured to:

when a data packet arrives at a switch, the switch extracts a data packet classification mark to obtain a scheduling algorithm of a flow to which the data packet belongs; then the exchanger updates the arrival byte estimation of the stream aggregate to which the data packet belongs and obtains the grade value of the stream; then using admission control to decide whether to receive the data packet, the class threshold being determined by a received byte estimate and an arrival byte estimate; after that, the switch recursively updates the rank value of each flow set in the hierarchy according to the scheduling policy determined by each layer; queuing the data packet to the end of the queue; at egress, when the queue is not empty, the packet is dequeued from the head of the queue and sent out.

Further, the rank threshold is calculated as follows:

/>

where a (i) represents the arrival byte estimate of node i, b (i) represents the received byte estimate of node i, and k represents the burst tolerance parameter.

Further, the admission control includes:

allocating a space to tolerate small bursts with parameter k, when a (i). Ltoreq.k.b (i), all packets are allowed to enqueue, by maintaining a sliding window of recently received packets, receiving only R (i) values no greater than R (i) using as a criterion the class value R (i) to each layer of the packetIf not, discarding the data packet.

Further, the calculation of the rank value is initiated by the leaf node, and the rank value of each node is calculated in a recursive manner.

Further, when the scheduling algorithm associated with the user flow queue is maximum and minimum fair scheduling, the level of the data packet is the fair quota information of the flow.

Further, according to the scheduling rule of the user demand, the flow queues are combined into class queues, and service messages in different class queues are used as a flow combination and mapped into the next-level group queues; when the class queue scheduling rule is weighted fair scheduling, calculating the grade according to the weighted value and the size of the data packet; when the scheduling algorithm associated between the group queues is a strict priority algorithm, the class of the group queues is the priority of each group queue.

In summary, the invention provides a programmable scheduling prototype Polymorphic PIFO supporting multi-mode processing logic, which can realize a hierarchical customizable queue scheduling algorithm on hardware at a linear speed. And by utilizing the capability of the programmable switch and hierarchical level calculation and admission control, the effect of hardware hierarchical QoS is realized by using only a single queue, no flow-by-flow state exists, and no complicated hierarchical queue management exists. A Polymorphic PIFO prototype framework is realized on a hardware Barefoot Tofino switch, and the result shows that the Polymorphic PIFO can ensure the isolated coexistence of multi-mode processing logic and realize a self-defined programmable queue scheduling algorithm.

The foregoing is merely illustrative of the preferred embodiments of this invention, and it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of this invention, and it is intended to cover such modifications and changes as fall within the true scope of the invention.

Claims (10)

1. A scheduling method supporting multi-modal processing logic, comprising:

step 1: marking user messages according to message processing logic and QoS service requirements predefined by users, and mapping message classification to different flow queues through the marks;

step 2: by utilizing the capability of the programmable switch, the effect of hardware hierarchical QoS is realized by using only a single queue through hierarchical level calculation and admission control, and the fair scheduling among different processing logics and the multi-service programmable scheduling in each processing logic are realized.

2. The scheduling method supporting multi-mode processing logic according to claim 1, wherein said step 1 comprises:

and classifying and marking the users and the services on the edge side to distinguish different users and different services, providing differential services for the different services of the different users, distinguishing the service messages of each user according to classification conditions by the equipment, marking the different service messages of each user by using different serv.types, and adding the messages into different flow queues for scheduling.

3. The scheduling method supporting multi-mode processing logic according to claim 1, wherein said step 2 comprises:

when a data packet arrives at a switch, the switch extracts a data packet classification mark to obtain a scheduling algorithm of a flow to which the data packet belongs; then the exchanger updates the arrival byte estimation of the stream aggregate to which the data packet belongs and obtains the grade value of the stream; then using admission control to decide whether to receive the data packet, the class threshold being determined by a received byte estimate and an arrival byte estimate; after that, the switch recursively updates the rank value of each flow set in the hierarchy according to the scheduling policy determined by each layer; queuing the data packet to the end of the queue; at egress, when the queue is not empty, the packet is dequeued from the head of the queue and sent out.

4. A scheduling method supporting multi-modal processing logic according to claim 3, wherein the level threshold is calculated as follows:

where a (i) represents the arrival byte estimate of node i, b (i) represents the received byte estimate of node i, and k represents the burst tolerance parameter.

5. The scheduling method supporting multi-modal processing logic as set forth in claim 4, wherein the admission control includes:

allocating a space to tolerate small bursts with parameter k, when a (i). Ltoreq.k.b (i), all packets are allowed to enqueue, by maintaining a sliding window of recently received packets, receiving only R (i) values no greater than R (i) using as a criterion the class value R (i) to each layer of the packetIf not, discarding the data packet.

6. A scheduling method supporting multi-modal processing logic according to claim 1, wherein the calculation of the rank value is initiated by a leaf node, and the rank value of each node is calculated in a recursive manner.

7. A scheduling method supporting multi-modal processing logic according to claim 3, wherein the level of the data packet is a fair quota of the flow when the scheduling algorithm associated with the user flow queue is maximum minimum fair scheduling.

8. The scheduling method supporting multi-mode processing logic according to claim 3, wherein according to the scheduling rule of user demands, the flow queues are combined into class queues, and service messages in different class queues are mapped into a next-level group queue as a flow combination; when the class queue scheduling rule is weighted fair scheduling, calculating the grade according to the weighted value and the size of the data packet; when the scheduling algorithm associated between the group queues is a strict priority algorithm, the class of the group queues is the priority of each group queue.

9. The scheduling method supporting multi-modal processing logic of claim 1, wherein the programmable switch comprises a Barefoot Tofino switch.

10. A scheduling system supporting multi-mode processing logic is characterized by comprising a message classification marker and a programmable hierarchical scheduler;

the message classification marker is used for marking the user message according to the message processing logic and the QoS service requirement predefined by the user, and mapping the message classification to different flow queues through the mark;

the programmable hierarchical scheduler is used for realizing the effect of hardware hierarchical QoS by using only a single queue through hierarchical level calculation and admission control by utilizing the capability of the programmable switch, and realizing fair scheduling among different processing logics and multi-service programmable scheduling in each processing logic.