CN117236239B - Universal connectivity test method, apparatus and medium for digital circuit verification - Google Patents
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- 238000013515 script Methods 0.000 claims abstract description 32
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Abstract
The invention discloses a universal connectivity test method, equipment and medium for digital circuit verification, which comprises the following specific steps: acquiring a target detection path, and checking the time sequence connection relation of a source end and a destination end; based on the time sequence connection relation of the source end and the destination end, carrying out communication test on the target running time of the digital circuit; the definition language describes the connection relation, a script is adopted to generate a command script when the simulation tool runs, and codes required by the connectivity test are generated according to script analysis. The input and the write of the time sequence connection relation between the source end and the destination end are close to natural language, the method is clear and convenient to confirm, other related codes and environments are automatically generated only by inputting and writing the connection relation, the complex connection relation of non-1 to 1 is supported, the breakpoint function of the simulation tool is utilized to support the time sequence path, the communication test is carried out after the digital circuit is operated to a certain point, the whole set of environment can be automatically generated, and the compiling complexity is reduced.
Description
Technical Field
The invention relates to the technical field of digital circuit detection, in particular to a universal connectivity test method, device and medium for digital circuit verification.
Background
The prior art has the following methods for testing connectivity of a source terminal and a destination terminal:
the first method is based on RTL codes, such as to test connectivity of a source terminal (source) and a destination terminal (destination). The source may be set to a certain value (force is used in verilog), and then the destination may be checked for consistency between the value and the set value.
And secondly, using a running time Command (CLI) provided by a simulation tool, using the CLI command to set the source end information to a certain value, and then using the CLI to acquire the value of the destination end to check whether the two values are equal.
Description of prior art problems and defects:
the first method is that a large amount of non-recommended forced assignment (force) methods are used, and various side effects are easily introduced. And once modified, the entire design and environment code needs to be recompiled, which is often time consuming;
the second method solves the problem of recompilation, but writing a large amount of codes by hand is very error-prone and difficult to debug, and in addition, the method cannot be used for some complex scenes (such as a path crossing registers, requiring software and hardware to cooperate and then test).
Disclosure of Invention
The invention aims to provide a universal connectivity test method, equipment and medium for digital circuit verification, which are characterized in that the input and the output based on the time sequence connection relation between a source end and a destination end are close to natural language, the input and the output are clear, the confirmation is convenient, only the input and the output are needed, other related codes and environments are automatically generated, the complex connection relation of non-1 to 1 can be supported, the breakpoint function of a simulation tool is utilized to support a time sequence path, and the communication test is optionally carried out after the digital circuit runs to a certain point, so that the whole set of environment can be automatically generated, and the compiling complexity is reduced.
The invention is realized by the following technical scheme:
the first aspect of the present invention provides a universal connectivity test method for digital circuit verification, comprising the following specific steps:
acquiring a target detection path, and checking the time sequence connection relation of a source end and a destination end;
based on the time sequence connection relation of the source end and the destination end, carrying out communication test on the target running time of the digital circuit;
the definition language describes the connection relation, a script is adopted to generate a command script when the simulation tool runs, and codes required by the connectivity test are generated according to script analysis.
The invention has the advantages that the input and the write based on the time sequence connection relation between the source end and the destination end are close to natural language, the invention is clear, the confirmation is convenient, only the input and the write connection relation is needed, other related codes and environments are generated fully automatically, the complex connection relation of non-1 to 1 can be supported, the breakpoint function of the simulation tool is utilized to support the time sequence path, the communication test is carried out after the digital circuit runs to a certain point, the whole set of environments can be automatically generated, and the compiling complexity is reduced.
Further, the checking whether the source terminal and the destination terminal meet the time sequence connection specifically includes:
defining global variables and setting signal input values;
operating a designated clock period to obtain the value of an input signal;
compare whether the two input values are equal.
Further, the checking of the timing connection of the source and destination includes checking a pure combinational logic path and a timing path including a register.
Further, the checking the time sequence connection of the source end and the destination end for the pure combinational logic path specifically includes:
defining the successful times of the global variable passNum record and the failed times of the failNum record;
setting a signal to be tested at a source end to be 0x55555555, and running a clock period to be 1ps;
acquiring a value of a target end signal, and comparing whether the value of the target end signal is equal to 0 xaaaaaaa;
if the values are equal, the passNum value is added with 1, and the print signal name and 0x 5555555555 pass the test;
if not, adding 1 to the failNum value, and the print signal name and 0x55555555 do not pass the test;
setting a signal to be tested at a source end as Oxaaaaaaaa, and waiting for a signal at a destination end to be 0 xaaaaaaa;
running 50 clocks, obtaining the value of a destination end signal, and comparing whether the value of the destination end signal is equal to 0 xaaaaaaa;
if the values are equal, adding 1 to the passNum value, and enabling the print signal name and the 0 xaaaaaaaaa to pass the test;
if not, the failNum value is added to 1, and the print signal name and 0 xaaaaaaaaa fail the test.
Further, the checking the timing connection between the source end and the destination end of the timing path including the register specifically includes:
defining the successful times of the global variable passNum record and the failed times of the failNum record;
setting a signal to be tested at a source end to be 0x55555555, waiting for a signal at a destination end to be 0x55555555, and running 50 clocks;
comparing whether the value of the destination signal is equal to 0 xaaaaaaaaa;
if the values are equal, the passNum value is added with 1, and the print signal name and 0x 5555555555 pass the test;
if not, adding 1 to the failNum value, and the print signal name and 0x55555555 do not pass the test;
setting a signal to be tested at a source end as Oxaaaaaaaa, and waiting for a signal at a destination end to be 0 xaaaaaaa;
running 50 clocks, obtaining the value of a destination end signal, and comparing whether the value of the destination end signal is equal to 0 xaaaaaaa;
if the values are equal, adding 1 to the passNum value, and enabling the print signal name and the 0 xaaaaaaaaa to pass the test;
if not, the failNum value is added to 1, and the print signal name and 0 xaaaaaaaaa fail the test.
Further, the performing the connectivity test on the target runtime of the digital circuit includes:
starting the simulation, waiting for the value of a certain signal to be equal to the set value
Starting a digital circuit to write a set value, triggering a simulation breakpoint, and judging whether a timing path supports a register or not based on the breakpoint;
if yes, invoking time sequence connection check of a source end and a destination end of the pure combination logic path to test;
if not, the time sequence connection check of the source end and the destination end of the time sequence path containing the register is called for testing.
Further, the defined language includes:
sw, describing whether the test case is to be synchronized with the digital circuit;
conn, all connection relations, the value is an array, and each element is a pair of connection relations;
src, the source signal, is the adhesion of multiple signals;
dst, destination signal array, each element contains timing and signal information;
timing, the combined path is also a time sequence path;
signal, the target signal, is a sticky of multiple signals.
Further, the generating a command script of the simulation tool during operation by using the script specifically includes:
reading in a connection description file;
traversing each connection relation path, traversing each end path, and judging whether the paths are combined paths or not;
if yes, invoking time sequence connection check of a source end and a destination end of the pure combination logic path to carry out combination path check;
if not, invoking time sequence connection check of the source end and the destination end of the pure combination logic path to perform time sequence path check;
generating cli scripts according to the checking result;
judging whether sw is true, if so, generating a c use case, and if not, directly outputting;
and generating other running environment scripts, and constructing a complete connectivity test platform by combining the cli scripts and the c use cases.
A second aspect of the invention provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing a generic connectivity test method for digital circuit verification when executing the program.
A third aspect of the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements a universal connectivity test method for digital circuit verification.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the input and the write of the time sequence connection relation based on the source end and the destination end are close to natural language, the input and the write are clear, the confirmation is convenient, only the input and the write are needed, other related codes and environments are generated fully automatically, the complex connection relation of non-1 to 1 can be supported, the breakpoint function of the simulation tool is utilized to support the time sequence path, the communication test is carried out after the digital circuit is operated to a certain point, the whole set of environment can be automatically generated, and the compiling complexity is reduced;
a scenario of software-hardware coordination may be supported by examining a pure combinational logic path and a timing path containing registers, which may be supported.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a method of testing connectivity in an embodiment of the present invention;
FIG. 2 is a timing connection checking method for source and destination of a pure combinational logic path according to an embodiment of the present invention;
FIG. 3 is a timing connection checking method for source and destination of a timing path including registers according to an embodiment of the present invention;
FIG. 4 is a method for performing a connectivity test on a target runtime of a digital circuit in an embodiment of the present invention;
FIG. 5 is an example of a connection relationship in an embodiment of the present invention;
fig. 6 is a script generation method in an embodiment of the present invention.
Description of the embodiments
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Example 1
As shown in fig. 1, a first aspect of the present embodiment provides a universal connectivity test method for digital circuit verification, including the following specific steps:
acquiring a target detection path, and checking the time sequence connection relation of a source end and a destination end;
based on the time sequence connection relation of the source end and the destination end, carrying out communication test on the target running time of the digital circuit;
the definition language describes the connection relation, a script is adopted to generate a command script when the simulation tool runs, and codes required by the connectivity test are generated according to script analysis.
The embodiment is based on the improvement of the second method in the prior art, and is formed by: framing, and packaging common operations; using the breakpoint function of the emulation tool to support a timing path containing registers; optionally, after the digital circuit runs to a certain point, carrying out a communication test; generating command scripts for the runtime of the simulation tool using scripts (e.g., python/perl); defining a special language to describe the connection relation, and analyzing and generating all codes required by the test by using a script; the embodiment has the advantages that the input and the write of the time sequence connection relation based on the source end and the destination end are close to natural language, the definition is clear, the confirmation is convenient, only the input and the write of the connection relation is needed, other related codes and environments are generated fully automatically, the complex connection relation of non-1 to 1 can be supported, the breakpoint function of the simulation tool is utilized to support the time sequence path, the communication test is carried out after the digital circuit runs to a certain point, the whole set of environments can be automatically generated, and the compiling complexity is reduced.
In some possible embodiments, CLI (command line interface-line interface) of the current mainstream simulator is based on TCL language, so API functions (Application Programming Interface, application program interface) of common operations are defined based on TCL, and the defined functions include:
1.1. comparing whether the two input values are equal;
1.2. comparing the m-th to n-th bits of the two input values;
1.3. checking whether the path contains an input character;
1.4. setting a disposable breakpoint (only triggered once);
1.5. setting the value of the one-time breakpoint wait signal equal to the input value (special case of 4 above);
1.6. setting a permanent breakpoint (which is triggered all the time as long as the condition is satisfied);
1.7. setting the signal as an input value;
1.8. acquiring a value of an input signal (path);
1.9. running a specified clock period;
1.10. writing the test result condition into a register which can be directly accessed by software and hardware;
1.11. sequentially calling 1.7,1.8,1.1 above to check whether the source terminal and the destination terminal meet direct connectivity;
1.12. the above 1.7,1.5,1.8,1.1 is invoked in turn to check whether the source and destination meet timing connectivity.
In some possible embodiments, checking whether the source and destination terminals satisfy the timing connection specifically includes:
defining global variables and setting signal input values;
operating a designated clock period to obtain the value of an input signal;
compare whether the two input values are equal.
In some possible embodiments, checking the timing connection of the source and destination includes checking a pure combinational logic path and a timing path containing registers.
As shown in fig. 2, performing timing connection check of a source end and a destination end on a pure combinational logic path specifically includes:
defining the successful times of the global variable passNum record and the failed times of the failNum record;
setting a signal to be tested at a source end to be 0x55555555, and running a clock period to be 1ps;
acquiring a value of a target end signal, and comparing whether the value of the target end signal is equal to 0 xaaaaaaa;
if the values are equal, the passNum value is added with 1, and the print signal name and 0x 5555555555 pass the test;
if not, adding 1 to the failNum value, and the print signal name and 0x55555555 do not pass the test;
setting a signal to be tested at a source end as Oxaaaaaaaa, and waiting for a signal at a destination end to be 0 xaaaaaaa;
running 50 clocks, obtaining the value of a destination end signal, and comparing whether the value of the destination end signal is equal to 0 xaaaaaaa;
if the values are equal, adding 1 to the passNum value, and enabling the print signal name and the 0 xaaaaaaaaa to pass the test;
if not, the failNum value is added to 1, and the print signal name and 0 xaaaaaaaaa fail the test.
As shown in fig. 3, performing timing connection check of a source end and a destination end on a timing path including a register specifically includes:
defining the successful times of the global variable passNum record and the failed times of the failNum record;
setting a signal to be tested at a source end to be 0x55555555, waiting for a signal at a destination end to be 0x55555555, and running 50 clocks;
comparing whether the value of the destination signal is equal to 0 xaaaaaaaaa;
if the values are equal, the passNum value is added with 1, and the print signal name and 0x 5555555555 pass the test;
if not, adding 1 to the failNum value, and the print signal name and 0x55555555 do not pass the test;
setting a signal to be tested at a source end as Oxaaaaaaaa, and waiting for a signal at a destination end to be 0 xaaaaaaa;
running 50 clocks, obtaining the value of a destination end signal, and comparing whether the value of the destination end signal is equal to 0 xaaaaaaa;
if the values are equal, adding 1 to the passNum value, and enabling the print signal name and the 0 xaaaaaaaaa to pass the test;
if not, the failNum value is added to 1, and the print signal name and 0 xaaaaaaaaa fail the test.
As shown in fig. 4, performing a connectivity test on a target runtime of a digital circuit includes:
starting simulation, and waiting for the value of a certain signal to be equal to a set value;
starting a digital circuit to write a set value, triggering a simulation breakpoint, and judging whether a timing path supports a register or not based on the breakpoint;
if yes, invoking time sequence connection check of a source end and a destination end of the pure combination logic path to test;
if not, the time sequence connection check of the source end and the destination end of the time sequence path containing the register is called for testing.
In some possible embodiments, the defined language includes:
sw, describing whether the test case is to be synchronized with the digital circuit;
conn, all connection relations, the value is an array, and each element is a pair of connection relations;
src, the source signal, is the adhesion of multiple signals;
dst, destination signal array, each element contains timing and signal information;
timing, the combined path is also a time sequence path;
signal, the target signal, is a sticky of multiple signals.
The above blocking is a concept in verilog, such as two 32-bit signals a [31:0], b [31:0] blocking, the result of which is a 64-bit signal { a [31:0], b [31:0] }. As shown in fig. 5, an example of a connection relationship is provided, which may be described in the following language:
{
"sw":true,
"conn":[
{
"src":["top.dut.src0_H[31:0]","top.dut.src0_L[31:0]"],
"dst":[
{"timing":"comb","signal":["top.dut.src0_dst0_H[15:0]","top.dut.src0_dst0_M[15:0]","top.dut.src0_dst0_L[31:0]"]},
{"timing":"comb","signal":["top.dut.src0_dst1_H","top.dut.src0_dst1_M","top.dut.src0_dst1_L"]},
{"timing":"seq","signal":["top.dut.src0_dst2_H","top.dut.src0_dst2_M","top.dut.src0_dst2_L"]}
]
},
]
}
with the above connection relation, the aforementioned code can be automatically generated through script, as shown in fig. 6, and the script is used to generate command script when the simulation tool runs, specifically including:
reading in a connection description file;
traversing each connection relation path, traversing each end path, and judging whether the paths are combined paths or not;
if yes, invoking time sequence connection check of a source end and a destination end of the pure combination logic path to carry out combination path check;
if not, invoking time sequence connection check of the source end and the destination end of the pure combination logic path to perform time sequence path check;
generating cli scripts according to the checking result;
judging whether sw is true, if so, generating a c use case, and if not, directly outputting;
and generating other running environment scripts, and constructing a complete connectivity test platform by combining the cli scripts and the c use cases.
A second aspect of the present embodiment provides an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing a generic connectivity test method for digital circuit verification when the program is executed by the processor.
A third aspect of the present embodiment provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a universal connectivity test method for digital circuit verification.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (9)
1. A universal connectivity test method for digital circuit verification, comprising the following specific steps:
acquiring a target detection path, and checking the time sequence connection relation of a source end and a destination end;
based on the time sequence connection relation of the source end and the destination end, carrying out communication test on the target running time of the digital circuit;
the communication test for the target operation time of the digital circuit comprises the following steps:
starting simulation, and waiting for the value of a certain signal to be equal to a set value;
starting a digital circuit to write a set value, triggering a simulation breakpoint, and judging whether a timing path supports a register or not based on the breakpoint;
if yes, invoking time sequence connection check of a source end and a destination end of the pure combination logic path to test;
if not, invoking a time sequence connection check of a source end and a destination end of a time sequence path containing a register to test;
the definition language describes the connection relation, a script is adopted to generate a command script when the simulation tool runs, and codes required by the connectivity test are generated according to script analysis.
2. The universal connectivity test method for digital circuit verification according to claim 1, wherein checking whether the source and destination terminals satisfy a timing connection comprises:
defining global variables and setting signal input values;
operating a designated clock period to obtain the value of an input signal;
compare whether the two input values are equal.
3. The universal connectivity test method for digital circuit verification according to claim 2, wherein checking the timing connections of the source and destination terminals comprises checking a pure combinational logic path and a timing path containing registers.
4. A universal connectivity test method for digital circuit verification according to claim 3, wherein said checking of the timing connection of source and destination ends for a pure combinational logic path comprises:
defining the successful times of the global variable passNum record and the failed times of the failNum record;
setting a signal to be tested at a source end to be 0x55555555, and running a clock period to be 1ps;
acquiring a value of a target end signal, and comparing whether the value of the target end signal is equal to 0 xaaaaaaa;
if the values are equal, the passNum value is added with 1, and the print signal name and 0x 5555555555 pass the test;
if not, adding 1 to the failNum value, and the print signal name and 0x55555555 do not pass the test;
setting a signal to be tested at a source end as Oxaaaaaaaa, and waiting for a signal at a destination end to be 0 xaaaaaaa;
running 50 clocks, obtaining the value of a destination end signal, and comparing whether the value of the destination end signal is equal to 0 xaaaaaaa;
if the values are equal, adding 1 to the passNum value, and enabling the print signal name and the 0 xaaaaaaaaa to pass the test;
if not, the failNum value is added to 1, and the print signal name and 0 xaaaaaaaaa fail the test.
5. The universal connectivity test method for digital circuit verification according to claim 4, wherein said checking the timing connection of the source and destination ends of the timing path containing the register, in particular, comprises:
defining the successful times of the global variable passNum record and the failed times of the failNum record;
setting a signal to be tested at a source end to be 0x55555555, waiting for a signal at a destination end to be 0x55555555, and running 50 clocks;
comparing whether the value of the destination signal is equal to 0 xaaaaaaaaa;
if the values are equal, the passNum value is added with 1, and the print signal name and 0x 5555555555 pass the test;
if not, adding 1 to the failNum value, and the print signal name and 0x55555555 do not pass the test;
setting a signal to be tested at a source end as Oxaaaaaaaa, and waiting for a signal at a destination end to be 0 xaaaaaaa;
running 50 clocks, obtaining the value of a destination end signal, and comparing whether the value of the destination end signal is equal to 0 xaaaaaaa;
if the values are equal, adding 1 to the passNum value, and enabling the print signal name and the 0 xaaaaaaaaa to pass the test;
if not, the failNum value is added to 1, and the print signal name and 0 xaaaaaaaaa fail the test.
6. The universal connectivity test method for digital circuit verification according to claim 5, wherein said defined language comprises:
sw, describing whether the test case is to be synchronized with the digital circuit;
conn, all connection relations, the value is an array, and each element is a pair of connection relations;
src, the source signal, is the adhesion of multiple signals;
dst, destination signal array, each element contains timing and signal information;
timing, the combined path is also a time sequence path;
signal, the target signal, is a sticky of multiple signals.
7. The universal connectivity test method for digital circuit verification according to claim 6, wherein said generating a command script at the time of running a simulation tool using the script, in particular, comprises:
reading in a connection description file;
traversing each connection relation path, traversing each end path, and judging whether the paths are combined paths or not;
if yes, invoking time sequence connection check of a source end and a destination end of the pure combination logic path to carry out combination path check;
if not, invoking time sequence connection check of the source end and the destination end of the pure combination logic path to perform time sequence path check;
generating cli scripts according to the checking result;
judging whether sw is true, if so, generating a c use case, and if not, directly outputting;
and generating other running environment scripts, and constructing a complete connectivity test platform by combining the cli scripts and the c use cases.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the generic connectivity test method for digital circuit verification according to any of claims 1 to 7 when the program is executed by the processor.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the universal connectivity test method for digital circuit verification according to any one of claims 1 to 7.
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