CN117234729B - Dynamic memory protection method, device, computer equipment and storage medium - Google Patents
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Abstract
The invention relates to the technical field of computers, and discloses a dynamic memory protection method, a device, computer equipment and a storage medium, wherein the method comprises the following steps: preloading an association table; the association table comprises a plurality of tasks and a plurality of memory access areas which are in one-to-one correspondence with the plurality of tasks; when a multi-task system starts a task or switches tasks, determining a target memory access area corresponding to the target task from an association table, and loading memory access rights corresponding to the target memory access area into a memory protection unit; the memory protection unit is used for limiting memory access to the target task according to the memory access authority; and performing context switching processing on the target task based on the CPU so as to execute the target task. The invention can realize fine inter-task memory isolation, and ensure that each task can only access the memory area required by the task without disturbing the data of other tasks.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a dynamic memory protection method, a dynamic memory protection device, a computer device, and a storage medium.
Background
The problem of limited numbers of Memory Protection Units (MPUs) is common to microcontrollers (Microcontroller Unit, MCUs) currently on the market, which makes it impossible to meet individual memory access restrictions for each task in the case of static configuration. This presents a serious set of problems such as destructive stack overflows, unintended accesses, memory conflicts, etc., which cannot be completely eradicated, especially in situations where the tasks are excessive and the number of MPUs is limited. Memory isolation between tasks is particularly important in many embedded systems, particularly in multitasking operating systems (Real Time Operating System, RTOS). If memory access between tasks is not effectively restricted and managed, serious problems such as data corruption, system crashes and the like may result.
Therefore, there is a need for a dynamic memory protection method that can achieve fine inter-task memory isolation, and ensure that each task can only access its required memory area without disturbing the data of other tasks.
Disclosure of Invention
In view of the above, the present invention provides a dynamic memory protection method, apparatus, computer device and storage medium, so as to solve the problems of data corruption and system crash caused by that the memory access between tasks is not limited and managed effectively in the related art.
In a first aspect, the present invention provides a dynamic memory protection method, including:
preloading an association table; the association table comprises a plurality of tasks and a plurality of memory access areas which are in one-to-one correspondence with the plurality of tasks;
when a multi-task system starts a task or switches tasks, determining a target memory access area corresponding to the target task from the association table, and loading memory access rights corresponding to the target memory access area into a memory protection unit; the memory protection unit is used for limiting memory access to the target task according to the memory access authority;
and performing context switching processing on the target task based on the CPU so as to execute the target task.
According to the dynamic memory protection method provided by the invention, when the task is started or switched by the multi-task system, the target memory access area corresponding to the target task is determined from the association table, and the memory access authority corresponding to the target memory access area is loaded into the memory protection unit, so that the memory protection unit performs memory access restriction on the target task according to the memory access authority, fine inter-task memory isolation can be realized, and each task can only access the memory area required by the task without disturbing the data of other tasks.
In an alternative embodiment, the method further comprises:
judging whether the first task has stack overflow or unexpected access; the first task is a currently running task;
triggering abnormal interruption according to a guarantee mechanism if the first task has the stack overflow condition or the unexpected access condition;
determining an exception handling mechanism corresponding to the exception type, and handling the exception event according to the exception handling mechanism.
In an alternative embodiment, the unexpected access condition includes a presence of a memory address outside of the memory protection unit configuration in a current access memory address, an address not accessible by the access bus.
According to the dynamic memory protection method provided by the invention, when a stack overflow condition or an unexpected access condition occurs in the first task, abnormal interruption is triggered according to a guarantee mechanism; the method and the device have the advantages that the exception handling mechanism corresponding to the exception type is determined, and the exception event is handled according to the exception handling mechanism, so that the exception memory access of the task can be monitored and handled in time, and the stability and reliability of an operating system are ensured.
In an alternative embodiment, the method further comprises:
when a second task preempts the CPU control right of the first task, determining a second memory access area corresponding to the second task from the association table;
loading a second memory access right corresponding to the second memory access region into a memory protection unit; the memory protection unit is used for limiting memory access of the second task according to the second memory access authority;
when the execution period of the first task reaches a preset period or a preset event is triggered, determining a third memory access area corresponding to a third task from the association table;
loading a third memory access right corresponding to the third memory access region into a memory protection unit; the memory protection unit is used for limiting memory access of the third task according to the third memory access authority;
wherein the second task has a higher priority than the first task.
According to the dynamic memory protection method provided by the invention, when the task is preempted or the execution period of the task reaches a preset period, the memory access authority corresponding to the memory access area is loaded into the memory protection unit; the memory protection unit is used for limiting the memory access of the task according to the memory access authority, and can flexibly adapt to the memory access requirements of different tasks by dynamically configuring MPU resources, thereby providing a more powerful and flexible memory protection mechanism for the embedded system.
In an alternative embodiment, the context switch processing is performed on the target task based on the CPU, including:
suspending the execution state of the previous task and storing the context of the previous task into a memory;
and retrieving the context of the target task from the memory, and restoring the context to a register of the CPU so as to transfer the controller of the CPU from the last task to the target task.
In an optional implementation manner, when the multi-task system starts a task or switches tasks, determining a target memory access area corresponding to the target task from the association table, and loading memory access rights corresponding to the target memory access area into a memory protection unit, where the method includes:
when the multi-task system starts a plurality of first tasks simultaneously, performing associated configuration of memory access areas on the plurality of first tasks by using a memory protection unit;
when the multi-task system switches tasks, performing associated configuration of a memory access area on a second task by using a memory protection unit; the second task is the next task;
the association configuration comprises the allocation of a corresponding memory access area for each task to be executed.
According to the dynamic memory protection method provided by the invention, when a task is started or switched, the memory protection unit is utilized to perform the associated configuration of the memory access area for the task, so that MPU resources can be dynamically configured, each task obtains proper memory access authority when running, and the problem that the number of memory protection units in the current MCU is limited is effectively solved.
In a second aspect, the present invention provides a dynamic memory protection device, including:
the association table loading module is used for pre-loading the association table; the association table comprises a plurality of tasks and a plurality of memory access areas which are in one-to-one correspondence with the plurality of tasks;
the memory configuration module is used for determining a target memory access area corresponding to the target task from the association table when the multi-task system starts the task or switches the task, and loading the memory access authority corresponding to the target memory access area into the memory protection unit; the memory protection unit is used for limiting memory access to the target task according to the memory access authority;
and the task execution module is used for performing context switching processing on the target task based on the CPU so as to execute the target task.
In an alternative embodiment, the apparatus further comprises:
the task judging module is used for judging whether the first task has stack overflow condition or unexpected access condition; the first task is a currently running task;
the abnormal interruption module is used for triggering abnormal interruption according to a guarantee mechanism if the first task generates the stack overflow condition or the unexpected access condition;
the exception handling module is used for determining an exception handling mechanism corresponding to the exception type and handling the exception event according to the exception handling mechanism.
In a third aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection, computer instructions are stored in the memory, and the processor executes the computer instructions, so that the dynamic memory protection method of the first aspect or any implementation manner corresponding to the first aspect is executed.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the dynamic memory protection method of the first aspect or any of its corresponding embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a dynamic memory protection method according to an embodiment of the invention;
FIG. 2 is a flow chart of an embodiment of dynamic memory protection according to an embodiment of the invention;
FIG. 3 is a schematic diagram of MPU resource allocation in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of memory access region allocation according to an embodiment of the present invention;
FIG. 5 is a flow chart of another dynamic memory protection according to an embodiment of the invention;
FIG. 6 is a flowchart of a method for dynamic memory protection according to an embodiment of the present invention;
FIG. 7 is a flowchart of a method for dynamic memory protection according to an embodiment of the invention;
FIG. 8 is a block diagram of a dynamic memory protection device according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Currently, microcontrollers (MCUs) on the market generally suffer from a limited number of Memory Protection Units (MPUs), which makes it impossible to meet individual memory access restrictions for each task in a static configuration. This presents a serious set of problems such as destructive stack overflows, unintended accesses, memory conflicts, etc., which cannot be completely eradicated, especially in situations where the tasks are excessive and the number of MPUs is limited. Memory isolation between tasks is particularly important in many embedded systems, particularly in a multitasking operating system (RTOS). If memory access between tasks is not effectively restricted and managed, serious problems such as data corruption, system crashes and the like may result.
In order to improve the stability and security of the embedded system, a dynamic memory protection scheme is needed to solve the problem that the number of memory protection units in the current MCU is limited, so as to implement individual memory access limitation for each task. By dynamically allocating MPU resources, each task is enabled to obtain appropriate MPU resources and memory access rights at runtime without relying on static configuration. By introducing the technical scheme of dynamically configuring the MPU, the embedded system can realize finer inter-task memory isolation, and each task can only access the memory area required by the task without disturbing the data of other tasks.
In accordance with an embodiment of the present invention, there is provided a dynamic memory protection method embodiment, it being noted that the steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer executable instructions, and, although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.
In this embodiment, a dynamic memory protection method is provided, fig. 1 is a flowchart of a dynamic memory protection method according to an embodiment of the present invention, and as shown in fig. 1, the flowchart includes the following steps:
step S101, pre-loading an association table; the association table comprises a plurality of tasks and a plurality of memory access areas corresponding to the tasks one by one.
Specifically, as shown in fig. 2: before the multi-task system is started, a correlation table is needed to be preloaded, wherein the correlation table refers to a task and memory protection corresponding table and is used for limiting the range of memory access of each task, namely, each task corresponds to a unique memory access area.
Step S102, when a multi-task system starts a task or switches tasks, determining a target memory access area corresponding to the target task from the association table, and loading memory access rights corresponding to the target memory access area into a memory protection unit; and the memory protection unit is used for limiting the memory access of the target task according to the memory access authority.
In particular, the multitasking system may be a multitasking operating system (Real Time Operating System, RTOS) allowing multiple tasks to run simultaneously. The memory protection unit (MemoryProtectionUnit, MPU) provides a memory area protection function, and can ensure that the running task does not destroy other tasks, namely, prevent system resources and other tasks from being illegally accessed.
More specifically, after the multi-task system is started, and when a task is started or a task is switched, memory access permission corresponding to the task needs to be loaded to a memory protection unit, and memory access restriction is performed on the task to be executed by the memory protection unit, for example: before a Task is started or a Task is switched, an association configuration with a Memory Protection Unit (MPU) needs to be established for each Task to be started (for example, "Task a", "Task B" and "Task C" in fig. 3), and the association configuration is mainly used for allocating corresponding memory rights to the Task, for example, as shown in fig. 4: an MPU configuration a in a Memory Protection Unit (MPU) can give a "Task a memory access area" corresponding to "Task a", an MPU configuration B can give a "Task B memory access area" corresponding to "Task B", and an MPU configuration C can give a "Task C memory access area" corresponding to "Task C".
Through dynamically distributing MPU resources of the memory protection unit, memory access areas of each task can be limited, and the tasks are ensured not to be mutually interfered. For each Task (Task), the MPU configuration can precisely define the memory area and permissions it can access.
More specifically, resources required by the operating system need to be configured when the multitasking system is started.
Step S103, performing context switching processing on the target task based on the CPU so as to execute the target task.
Specifically, a task context refers to an environment in which a task runs. The task context may include the contents of a program counter, a stack pointer, and a general purpose register. In a multitasking system, context switching refers to an event that occurs when control of a CPU is transferred from an operating task to another ready task, the current operating task is transferred to a ready (or suspended, deleted) state, and the other selected ready task becomes the current task. The context switch includes saving the running environment of the current task and restoring the running environment where the task is to be run. The context content depends on the specific CPU.
The dynamic memory protection method provided by the invention has the following technical effects:
1. according to the invention, through dynamically configuring MPU resources, the system can flexibly adapt to memory access requirements of different tasks, the problem of limited number of MPUs is avoided, and finer inter-task memory isolation is provided.
2. The invention can ensure that each task obtains proper MPU resource and memory access authority, effectively avoids the problems of destructive stack overflow, unexpected access, memory conflict and the like, and improves the safety of the system.
3. By setting the exception handling mechanism, the invention can timely handle the exception memory access of the task, and ensure the stability and reliability of the system.
In this embodiment, a dynamic memory protection method is provided, and fig. 5 is a flowchart of the dynamic memory protection method according to an embodiment of the present invention, as shown in fig. 5, where the flowchart includes the following steps:
step S201, pre-loading the association table; the association table comprises a plurality of tasks and a plurality of memory access areas corresponding to the tasks one by one. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S202, when a multi-task system starts a task or switches tasks, determining a target memory access area corresponding to the target task from the association table, and loading memory access rights corresponding to the target memory access area into a memory protection unit; and the memory protection unit is used for limiting the memory access of the target task according to the memory access authority. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S203, performing a context switch process on the target task based on the CPU, so as to execute the target task. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S204, judging whether the first task has stack overflow condition or unexpected access condition; the first task is a currently running task.
Specifically, the stack overflow condition refers to a condition that data is added to a stack that is already full, resulting in data covering other memory areas or program crashes. Unexpected access conditions include that a memory address outside the configuration of the memory protection unit is present in the current access memory address, and that the access bus is not accessible, for example, in the case of program task design, a task can only access a certain range of addresses in the memory, for example, 0x 100000-0 x101000, but because the program has an error, the address outside the memory address is accessed, and the erroneous access can be considered as unexpected access.
In step S205, if the first task generates the stack overflow condition or the unexpected access condition, an abort is triggered according to a guarantee mechanism.
Specifically, when a first task, i.e. a task currently running, has stack overflow or unexpected access, an abort may be triggered according to a guarantee mechanism to guarantee stability of the operating system. The guarantee mechanism here refers to triggering an abort flow when a memory address outside the MPU configuration appears in the memory addresses accessed by the task.
The above step S205 is specifically described in the following specific examples:
when a task is to access an address of 0x00000000 to 0x00001000 (assuming that the address is a task stack and gives a read-write permission) and a memory range of 0x84000000 to 0x84100000 (assuming that the address is a code (text) section and gives an execution permission) and an address of 0x40000000 to 0x40000100 (assuming that the address is a peripheral, gives a read-write permission), the memory blocks are dynamically configured in an MPU memory protection unit before the task starts or is switched, when the task is successfully configured, the task is to only access the above address and follows a configuration access requirement, if the task starts to run, only the above address is accessed, and if the stack is to overflow access (actually means that access beyond the task stack address is generated, but since the MPU is started, when the CPU is to read or write the memory block, an abnormal interrupt is triggered), related abnormal interrupt (when the task stack is switched or the memory overflow is detected when the task is switched, and when the stack overflows, the memory beyond the range is directly destroyed), and abnormal interrupt is processed in a user.
Step S206, determining an exception handling mechanism corresponding to the exception type, and handling the exception event according to the exception handling mechanism.
Specifically, the exception handling mechanism may take appropriate measures, such as terminating tasks, logging, or alerting, according to actual situations, to avoid unsafe instruction operations caused by stack overflows or unexpected memory accesses. The exception type and the exception handling mechanism corresponding to the exception type may be set according to actual situations, and are not particularly limited herein.
In a preferred embodiment, when the MPU in the multitasking operating system switches dynamically and an exception occurs, as shown in FIG. 2: when a stack overflow condition or unexpected access condition occurs to a task, triggering an exception and then carrying out an exception interrupt, and at the moment, processing by a user code, namely resetting the task which triggers the exception at present, and continuing to load system task switching and processing; if the task cannot be reset, the user is required to process the reset or send alarm information to the outside.
In some alternative embodiments, as shown in fig. 6: the method further comprises the steps of:
step S301, when a second task preempts the CPU control right of the first task, determining a second memory access area corresponding to the second task from the association table; wherein the second task has a higher priority than the first task.
Step S302, loading a second memory access right corresponding to the second memory access area into a memory protection unit; and the memory protection unit is used for limiting the memory access of the second task according to the second memory access authority.
Step S303, when the execution period of the first task reaches a preset period or a preset event is triggered, determining a third memory access area corresponding to a third task from the association table.
Specifically, the preset event may be that the current task is preempted or the current task is completed, and if the current task is preempted, a memory access area corresponding to the preempted task may be determined from the association table; if the current task is completed, a memory access area corresponding to the next task to be executed can be determined from the association table. Other trigger mechanisms may also be employed, and may be configured in connection with a particular application scenario, without specific limitation herein, such as a semaphore trigger mechanism.
Step S304, loading a third memory access right corresponding to the third memory access area into a memory protection unit; and the memory protection unit is used for limiting the memory access of the third task according to the third memory access authority.
In the above steps S301 to S304, as shown in fig. 2: when the task preemption occurs or the task execution period is reached, task switching is needed, which is specifically as follows:
when a task with a higher priority (namely a second task) preempts the CPU control right of a current running task (namely a first task), determining a second memory access area corresponding to the second task from an association table, loading a second memory access right corresponding to the second memory access area into a memory protection unit, and finally performing memory access restriction on the second task by using the memory protection unit according to the second memory access right; the second task is then executed by switching contexts.
When the task execution period of the currently running task (i.e. the first task) reaches a preset period (the first task can be considered to be completed), a third memory access area corresponding to a third task is required to be determined from an association table according to the next running task (i.e. the third task), then a third memory access right corresponding to the third memory access area is loaded into a memory protection unit, and finally the memory protection unit is utilized to limit memory access of the third task according to the third memory access right; the third task is then performed by switching contexts.
In some alternative embodiments, as shown in fig. 7, the step S103 includes the following steps:
step S1031, suspending the execution state of the previous task, and storing the context of the previous task into the memory.
In step S1032, the context of the target task is retrieved from the memory and restored to the register of the CPU, so as to transfer the controller of the CPU from the previous task to the target task.
In some optional embodiments, when the multi-task system starts a task or switches tasks, determining a target memory access area corresponding to the target task from the association table, and loading memory access rights corresponding to the target memory access area into a memory protection unit, where the determining includes:
when the multi-task system starts a plurality of first tasks simultaneously, performing associated configuration of memory access areas on the plurality of first tasks by using a memory protection unit; the association configuration comprises the allocation of a corresponding memory access area for each task to be executed.
Specifically, through the association configuration of the memory access regions, each first Task can be allocated to a corresponding unique memory access region, for example, task a in fig. 4 corresponds to a Task a memory access region, task B corresponds to a Task B memory access region, and Task C corresponds to a Task C memory access region.
When the multi-task system switches tasks, performing associated configuration of a memory access area on a second task by using a memory protection unit; the second task is the next task.
Specifically, when task switching is performed, the controller of the CPU is transferred from the current running task to the next task to be run, that is, the memory access area is configured in association with the second task through the memory protection unit, and a corresponding memory access area is allocated to the second task.
The dynamic memory protection method provided by the invention has the following technical effects:
1. according to the invention, through dynamic configuration of MPU resources, each task obtains proper memory access authority during running, so that the problem of limited memory protection units in the current MCU is effectively solved.
2. According to the invention, through dynamically distributing MPU resources and memory access control, finer inter-task memory isolation can be realized, each task is ensured to only access the memory area required by the task, and therefore, the stability and the safety of the embedded system are improved.
3. By setting the exception handling mechanism, the invention can monitor and handle the abnormal memory access of the task in time and ensure the stability and reliability of the operating system.
4. The invention can flexibly adapt to the memory access requirements of different tasks by dynamically configuring MPU resources, and provides a more powerful and flexible memory protection mechanism for an embedded system.
The embodiment also provides a dynamic memory protection device, which is used for implementing the above embodiment and the preferred implementation, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a dynamic memory protection device, as shown in fig. 8, including:
the association table loading module is used for pre-loading the association table; the association table comprises a plurality of tasks and a plurality of memory access areas which are in one-to-one correspondence with the plurality of tasks;
the memory configuration module is used for determining a target memory access area corresponding to the target task from the association table when the multi-task system starts the task or switches the task, and loading the memory access authority corresponding to the target memory access area into the memory protection unit; the memory protection unit is used for limiting memory access to the target task according to the memory access authority;
and the task execution module is used for performing context switching processing on the target task based on the CPU so as to execute the target task.
In some alternative embodiments, the apparatus further comprises:
the task judging module is used for judging whether the first task has stack overflow condition or unexpected access condition; the first task is a currently running task;
the abnormal interruption module is used for triggering abnormal interruption according to a guarantee mechanism if the first task generates the stack overflow condition or the unexpected access condition;
the exception handling module is used for determining an exception handling mechanism corresponding to the exception type and handling the exception event according to the exception handling mechanism.
In some alternative embodiments, the unexpected access condition includes the presence of a memory address outside of the memory protection unit configuration in the current access memory address, an address not accessible by the access bus.
In some alternative embodiments, the apparatus further comprises:
the second memory access area determining module is used for determining a second memory access area corresponding to the second task from the association table when the second task preempts the CPU control right of the first task;
the second memory access limiting module is used for loading a second memory access right corresponding to the second memory access area into the memory protection unit; the memory protection unit is used for limiting memory access of the second task according to the second memory access authority;
the third memory access area determining module is used for determining a third memory access area corresponding to a third task from the association table when the execution period of the first task reaches a preset period or a preset event is triggered;
the third memory access limiting module is used for loading a third memory access right corresponding to the third memory access area into the memory protection unit; the memory protection unit is used for limiting memory access of the third task according to the third memory access authority; wherein the second task has a higher priority than the first task.
In some alternative embodiments, the task execution module includes:
the state suspending unit is used for suspending the execution state of the previous task and storing the context of the previous task into the memory;
and the control transfer unit is used for retrieving the context of the target task from the memory and restoring the context to a register of the CPU so as to transfer the controller of the CPU from the last task to the target task.
In some alternative embodiments, the memory configuration module includes:
the first association configuration unit is used for carrying out association configuration of the memory access areas on the plurality of first tasks by using the memory protection unit when the multi-task system simultaneously starts the plurality of first tasks;
the second association configuration unit is used for carrying out association configuration of the memory access area on the second task by using the memory protection unit when the task is switched by the multi-task system; the second task is the next task; the association configuration comprises the allocation of a corresponding memory access area for each task to be executed.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The embodiment of the invention also provides computer equipment, which is provided with the dynamic memory protection device shown in the figure 8.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 9, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 9.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (7)
1. A method for dynamic memory protection, the method comprising:
preloading an association table; the association table comprises a plurality of tasks and a plurality of memory access areas which are in one-to-one correspondence with the plurality of tasks;
when a multi-task system starts a task or switches tasks, determining a target memory access area corresponding to the target task from the association table, and loading memory access rights corresponding to the target memory access area into a memory protection unit; the memory protection unit is used for limiting memory access to the target task according to the memory access authority;
performing context switching processing on the target task based on a CPU (Central processing Unit) to execute the target task;
judging whether the first task has stack overflow or unexpected access; the first task is a currently running task;
triggering abnormal interruption according to a guarantee mechanism if the first task has the stack overflow condition or the unexpected access condition;
determining an exception handling mechanism corresponding to the exception type, and handling exception events according to the exception handling mechanism;
when a second task preempts the CPU control right of the first task, determining a second memory access area corresponding to the second task from the association table;
loading a second memory access right corresponding to the second memory access region into a memory protection unit; the memory protection unit is used for limiting memory access of the second task according to the second memory access authority;
when the execution period of the first task reaches a preset period or a preset event is triggered, determining a third memory access area corresponding to a third task from the association table;
loading a third memory access right corresponding to the third memory access region into a memory protection unit; the memory protection unit is used for limiting memory access of the third task according to the third memory access authority;
wherein the second task has a higher priority than the first task.
2. The method of claim 1, wherein the unexpected access condition includes a presence of a memory address outside of the memory protection unit configuration, an address inaccessible to the access bus, among the currently accessed memory addresses.
3. The method according to claim 1 or 2, wherein performing a context switch process on the target task based on a CPU includes:
suspending the execution state of the previous task and storing the context of the previous task into a memory;
and retrieving the context of the target task from the memory, and restoring the context to a register of the CPU so as to transfer the controller of the CPU from the last task to the target task.
4. The method according to claim 1 or 2, wherein when the multi-tasking system starts a task or switches tasks, determining a target memory access area corresponding to the target task from the association table, and loading the memory access rights corresponding to the target memory access area into a memory protection unit, comprises:
when the multi-task system starts a plurality of first tasks simultaneously, performing associated configuration of memory access areas on the plurality of first tasks by using a memory protection unit;
when the multi-task system switches tasks, performing associated configuration of a memory access area on a second task by using a memory protection unit; the second task is the next task;
the association configuration comprises the allocation of a corresponding memory access area for each task to be executed.
5. A dynamic memory protection device, the device comprising:
the association table loading module is used for pre-loading the association table; the association table comprises a plurality of tasks and a plurality of memory access areas which are in one-to-one correspondence with the plurality of tasks;
the memory configuration module is used for determining a target memory access area corresponding to a target task from the association table when the multi-task system starts the task or switches the task, and loading memory access rights corresponding to the target memory access area into the memory protection unit; the memory protection unit is used for limiting memory access to the target task according to the memory access authority;
the task execution module is used for performing context switching processing on the target task based on the CPU so as to execute the target task;
the task judging module is used for judging whether the first task has stack overflow condition or unexpected access condition; the first task is a currently running task;
the abnormal interruption module is used for triggering abnormal interruption according to a guarantee mechanism if the first task generates the stack overflow condition or the unexpected access condition;
the exception handling module is used for determining an exception handling mechanism corresponding to the exception type and handling the exception event according to the exception handling mechanism;
the second memory access area determining module is used for determining a second memory access area corresponding to the second task from the association table when the second task preempts the CPU control right of the first task;
the second memory access limiting module is used for loading a second memory access right corresponding to the second memory access area into the memory protection unit; the memory protection unit is used for limiting memory access of the second task according to the second memory access authority;
the third memory access area determining module is used for determining a third memory access area corresponding to a third task from the association table when the execution period of the first task reaches a preset period or a preset event is triggered;
the third memory access limiting module is used for loading a third memory access right corresponding to the third memory access area into the memory protection unit; the memory protection unit is used for limiting memory access of the third task according to the third memory access authority; wherein the second task has a higher priority than the first task.
6. A computer device, comprising:
a memory and a processor, the memory and the processor being communicatively coupled to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the dynamic memory protection method of any of claims 1 to 4.
7. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the dynamic memory protection method of any one of claims 1 to 4.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109144715A (en) * | 2017-06-27 | 2019-01-04 | 阿里巴巴集团控股有限公司 | A kind of method, server and the equipment of resource optimization and update |
| CN111984410A (en) * | 2020-08-18 | 2020-11-24 | 上海睿赛德电子科技有限公司 | Memory protection system with low resource occupation in embedded system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1870814B1 (en) * | 2006-06-19 | 2014-08-13 | Texas Instruments France | Method and apparatus for secure demand paging for processor devices |
| GB2422926B (en) * | 2005-02-04 | 2008-10-01 | Advanced Risc Mach Ltd | Data processing apparatus and method for controlling access to memory |
| US11921655B2 (en) * | 2021-05-04 | 2024-03-05 | Stmicroelectronics, Inc. | Dynamic memory protection device system and method |
-
2023
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109144715A (en) * | 2017-06-27 | 2019-01-04 | 阿里巴巴集团控股有限公司 | A kind of method, server and the equipment of resource optimization and update |
| CN111984410A (en) * | 2020-08-18 | 2020-11-24 | 上海睿赛德电子科技有限公司 | Memory protection system with low resource occupation in embedded system |
Non-Patent Citations (1)
| Title |
|---|
| Karim Yagbmour.构建嵌入式LInux系统.中国电力出版社,2004,(第1版),第一至十一章. * |
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