CN117234591B

CN117234591B - Instruction verification method, system, equipment, medium and product

Info

Publication number: CN117234591B
Application number: CN202311137115.0A
Authority: CN
Inventors: 沈秀红; 陆泳; 苟鹏飞; 刘扬帆
Original assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Current assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Priority date: 2023-09-04
Filing date: 2023-09-04
Publication date: 2024-04-16
Anticipated expiration: 2043-09-04
Also published as: CN117234591A

Abstract

The application provides an instruction verification method, an instruction verification system, instruction verification equipment, an instruction verification medium and an instruction verification product. The method comprises the following steps: the excitation generator sends excitation to the to-be-detected cache and the cache model; the excitation is generated based on larx instructions and stcx instructions of a Power instruction set according to preset excitation sending conditions and excitation types; responding to the excitation by the buffer to be tested, and executing the processing to obtain a first processing result; the information collector collects and obtains a first processing result from the cache to be detected and sends the first processing result to the result comparator; responding to the excitation, executing the processing to obtain a second processing result, and sending the second processing result to a result comparator; the result comparator detects whether the first processing result is consistent with the second processing result, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails. The scheme of the application can comprehensively and effectively verify the behavior of the instruction in the cache.

Description

Instruction verification method, system, equipment, medium and product

Technical Field

The present application relates to the field of processor verification, and in particular, to a method, system, device, medium, and product for instruction verification.

Background

The Power instruction set is a simplified instruction set based on a Power architecture developed by IBM corporation, and compared with the X86 architecture, the Power architecture has the biggest characteristics in hardware that the symmetrical multiprocessor technology is adopted, so that the speed of memory access to any CPU can be guaranteed to be the same. Therefore, the Power architecture of the IBM corporation is mainly applied to the high-end server market and has very wide application prospect, and has important application in the domestic key industry.

There is an atomic instruction under the Power instruction set, including two types of instructions, larx (load AND RESERVE) and stcx (store conditional). The larx instruction is a read reservation instruction, and is used for reading data, and setting corresponding reservation stations in the cache according to the current thread, including the settings of a reservation identification bit (flag) and a reservation address (addr); the stcx instruction is a conditional store instruction, which is configured to return a processing result to the core processor according to a reservation identification bit (flag) and a reservation address (addr) of a cache reservation station in the current thread. However, to date, there has been no fully effective method to verify the behavior of both instructions in the Power instruction set larx and stcx described above in the cache.

Disclosure of Invention

The application provides an instruction verification method, an instruction verification system, an instruction verification device, an instruction verification medium and an instruction verification product, which are used for comprehensively and effectively verifying the behavior of an instruction in a cache.

In one aspect, the application provides an instruction verification method, which is applied to an instruction verification system, wherein the instruction verification system comprises an excitation generator, a cache to be tested, a cache model, an information acquisition unit and a result comparator; the method comprises the following steps: the excitation generator sends excitation to the to-be-detected cache and the cache model; the excitation is generated based on larx instructions and stcx instructions of a Power instruction set according to preset excitation sending conditions and excitation types; responding to the excitation by the buffer to be tested, and executing the processing to obtain a first processing result; the information collector collects and obtains a first processing result from the cache to be detected and sends the first processing result to the result comparator; responding to the excitation, executing the processing to obtain a second processing result, and sending the second processing result to a result comparator; the cache model is established based on a cache mechanism and larx instructions and stcx instructions of a Power instruction set and is used for simulating standard cache to execute instruction operation processing on received excitation; the result comparator detects whether the first processing result is consistent with the second processing result, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails.

In one possible implementation, the cache model includes: the system comprises an instruction execution module, a control module, a catalog, a data storage station and a reservation station; the instruction execution module is used for responding larx instructions or stcx instructions, accessing the catalog and executing the execution flow of larx instructions or stcx instructions in the cache model based on cache data in the data storage, wherein the execution flow comprises updating data in a reservation station according to preset reservation setting conditions and reservation emptying conditions; the control module is used for executing maintenance processing on the reservation station according to a preset reservation maintenance condition when detecting that a load request or a noop request exists between the larx instruction and the stcx instruction.

In one possible implementation, the execution flow of larx instructions in the cache model includes: the cache model judges whether the currently received instruction is a larx instruction or not through analysis, if the currently received instruction is a larx instruction, the larx instruction is transmitted to an instruction execution module; the instruction execution module accesses the directory and judges larx whether the instruction hits or not under the cache model; if the result is hit, corresponding data are acquired and returned to the kernel processor, the data are sent to the result comparator as a second processing result, and the entry of the corresponding thread in the reservation station is set according to preset reservation setting conditions and reservation emptying conditions; if the data is not hit, corresponding data is acquired from the next-level cache, the data is written into the data storage and the catalog is updated, the data is returned to the kernel processor, the data is used as a second processing result to be sent to the result comparator, and the entry of the corresponding thread in the reservation station is set according to the preset reservation setting condition and the reservation emptying condition.

In one possible implementation, the execution flow of stcx instructions in the cache model includes: the cache model judges whether the currently received instruction is a stcx instruction or not through analysis, if the currently received instruction is a stcx instruction, the stcx instruction is transmitted to an instruction execution module; the instruction execution module accesses the reservation station, obtains a return result according to the identification bit and the address under the entry of the thread where the stcx instruction is located, sends the return result as a second processing result to the result comparator, and sets the entry of the corresponding thread in the reservation station according to a preset reservation setting condition and a reservation emptying condition; if the returned result is successful, the instruction execution module accesses the directory, and judges whether stcx instructions hit under the cache model; if hit, and hit the state of the data to be the exclusive state, write the data into the data storage; if the data is hit and the hit data is in a shared state, acquiring corresponding data from the next-level cache, writing the data into a data storage and updating the catalog; if not, reporting error.

In one possible implementation, the reservation setting conditions include at least one of: for larx instructions, if the larx instruction hits in the cache model, setting the flag under the entry of the corresponding thread in the reservation station to 1, setting addr to the access address indicated by larx instruction, and reserving the granularity to 64Bytes; for larx instructions, if the larx instruction misses under the cache model and the corresponding data is successfully acquired from the next-level cache, setting the flag under the entry of the corresponding thread in the reservation station to be 1, setting addr to be an access address indicated by larx instructions, and reserving granularity to be 64Bytes; the emptying conditions are maintained, including at least one of the following: for stcx instructions, whether the cache model is hit or not, the entry of the corresponding thread in the reservation station is emptied, and the flag is set to 0; for stcx instructions, if the flag of the non-native thread entry in the reservation station is 1 and the access addresses indicated by addr and stcx instructions are the same at 64Bytes granularity, clearing the reservation station information of the entry; for stcx instructions, a store request is inserted in the same thread, and if the store request hits the addresses of other threads in the reservation station, reservation station information of the other threads is cleared.

In one possible implementation, the maintenance conditions are preserved, including: if a load request is received, the request triggers eviction a behavior, and the data address accessed by the behavior is the same as the address under any entry in the reservation station, the entry is emptied; if a snoop request is received, the type of the snoop request is analyzed, and if the snoop request is used for invalidating any cache data, the address of the cache data is the same as the address under any entry in the reservation station, the entry is emptied.

In one possible implementation, the excitation transmission conditions include: for larx instructions, the following conditions are satisfied: the larx instructions being executed under the same thread are not more than 1, and there are no stcx instructions being executed under the thread; larx instructions under different threads allow for parallel issue, and the addresses indicated by larx instructions under different threads allow for the same; for stcx instructions, the following conditions are satisfied: stcx instructions that are executing under the same thread are not more than 1; and the thread needs to confirm that larx instructions of the same thread are sent to the thread, if larx instructions exist, stcx instructions need to be executed after the larx instructions are executed; if the larx instruction does not exist, the stcx instruction is converted into a stcxfnk instruction type; stcx instructions under different threads allow for parallel issue, and the addresses indicated by stcx instructions under different threads allow for the same.

In one possible implementation, the excitation types include: a directional excitation type and a random excitation type; wherein the directional excitation type comprises at least one of: first directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, and other instructions are not inserted in the middle; second directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, and addresses accessed by store requests are the same as those accessed by larx instructions and stcx instructions; third directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are the same, and access addresses among different threads are random; fourth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are different, and access addresses among different threads are random; fifth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, and addresses accessed by store requests are the same as those accessed by larx instructions and stcx instructions; sixth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a noop request is inserted in the middle, and the addresses accessed by the noop request are the same as those accessed by larx instructions and stcx instructions; seventh directional excitation type: under a single thread, the larx instruction and the stcx instruction are sent in pairs, addresses accessed by the larx instruction and the stcx instruction under the same thread are the same, a load request is inserted in the middle, and data accessed by the larx instruction and the stcx instruction are the same as data accessed by eviction behavior; eighth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a flush request is inserted in the middle, and data accessed by larx instructions and stcx instructions are the same as data accessed by the flush request; the random excitation type satisfies: the same addresses are accessed by larx and stcx instructions under the same thread, and the thread numbers under different threads are random.

In another aspect, the present application further provides an instruction verification system, including: the excitation generator is used for sending excitation to the to-be-detected cache and the cache model; the excitation is generated based on larx instructions and stcx instructions of a Power instruction set according to preset excitation sending conditions and excitation types; the buffer memory to be tested is used for responding to the excitation and executing the processing to obtain a first processing result; the information collector is used for collecting and obtaining a first processing result from the cache to be tested and sending the first processing result to the result comparator; the buffer model is used for responding to the excitation, executing the processing to obtain a second processing result and sending the second processing result to the result comparator; the cache model is established based on a cache mechanism and larx instructions and stcx instructions of a Power instruction set and is used for simulating standard cache to execute instruction operation processing on received excitation; the result comparator is used for detecting whether the first processing result is consistent with the second processing result, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails.

In yet another aspect, the present application provides an electronic device, comprising: a processor, a memory communicatively coupled to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method as before.

In yet another aspect, the present application provides a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, are configured to implement a method as previously described.

In yet another aspect, the application provides a computer program product comprising a computer program which, when executed by a processor, implements a method as before.

In the instruction verification method, system, equipment, medium and product provided by the application, an excitation generator firstly sends excitation to a to-be-detected cache and a cache model; the excitation is generated based on larx instructions and stcx instructions in a Power instruction set according to preset excitation sending conditions and excitation types; responding to the excitation sent by the excitation generator, and obtaining a first processing result after the buffer to be detected is processed; the information collector collects and obtains a first processing result from the cache to be detected and sends the first processing result to the result comparator; responding to the excitation sent by the excitation generator by the buffer model, performing processing to obtain a second processing result, and sending the second processing result to the result comparator; the buffer model is established based on a buffer mechanism and larx instructions and stcx instructions in a Power instruction set and is used for simulating standard buffer to execute instruction operation processing on received excitation; the result comparator detects whether the received first processing result and the received second processing result are consistent, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails. According to the scheme, based on larx instructions and stcx instructions in a Power instruction set, a cache model is set, excitation is sent to the cache model to be tested through an excitation generator, corresponding processing is carried out to obtain a first processing result and a second processing result, the first processing result and the second processing result are then sent to a result comparator for comparison, the behavior of the instructions in the cache can be comprehensively and effectively verified, and the verification method is high in item inheritance and capable of being quickly transplanted to other verification platforms based on UVM verification methodologies.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic flow chart of an instruction verification method according to a first embodiment of the present application;

fig. 2 is a schematic flow chart illustrating an instruction verification method according to a second embodiment of the present application;

A flow diagram of an example provided instruction verification method is schematically shown in fig. 3;

FIG. 4 is a bit timing diagram of the larx instructions and stcx instruction encapsulator in an example;

Fig. 5 is a schematic structural diagram of an instruction verification system according to a third embodiment of the present application;

Fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of systems and methods that are consistent with aspects of the application as detailed in the accompanying claims.

The terms "comprising" and "having" in the present application are used to mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second," etc. are used merely as labels or distinction and do not limit the order or quantity of their objects. Furthermore, the various elements and regions in the figures are only schematically illustrated and are therefore not limited to the dimensions or distances illustrated in the figures. The technical scheme is described in detail below with specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

The Power instruction set is one of the general architectures of several CPUs, is an instruction set architecture based on a RISC architecture, and is not only focused on being implemented on miniaturized and low-Power consumption application equipment, but also fully considers the current market competition environment to realize strong performance, so that the Power instruction set is further developed.

With the rapid development of Power architecture processors and integrated circuit technology, the design scale of current chips is exponentially rising. The increasingly complex processor structure and the diversified extended instruction sets make the processor instruction set verification more and more difficult, so that the verification work on the processor instruction set becomes extremely important after the processor staged design is completed in order to ensure that the processor can execute instructions correctly, but no better method is available at present for effectively verifying the actions of two types of instructions larx and stcx in the cache under the Power instruction set.

The technical content provided by the application aims to solve the technical problems of the related technology. In the embodiment of the application, an excitation generator firstly sends excitation to a to-be-detected cache and a cache model; the excitation is generated based on larx instructions and stcx instructions in a Power instruction set according to preset excitation sending conditions and excitation types; responding to the excitation sent by the excitation generator, and obtaining a first processing result after the buffer to be detected is processed; the information collector collects and obtains a first processing result from the cache to be detected and sends the first processing result to the result comparator; responding to the excitation sent by the excitation generator by the buffer model, performing processing to obtain a second processing result, and sending the second processing result to the result comparator; the buffer model is established based on a buffer mechanism and larx instructions and stcx instructions in a Power instruction set and is used for simulating standard buffer to execute instruction operation processing on received excitation; the result comparator detects whether the received first processing result and the received second processing result are consistent, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails. According to the scheme, based on larx instructions and stcx instructions in a Power instruction set, a cache model is set, excitation is sent to the cache model to be tested through an excitation generator, corresponding processing is carried out to obtain a first processing result and a second processing result, the first processing result and the second processing result are then sent to a result comparator for comparison, the behavior of the instructions in the cache can be comprehensively and effectively verified, and the verification method is high in item inheritance and capable of being quickly transplanted to other verification platforms based on UVM verification methodologies.

Aspects of embodiments of the present application relate to the above considerations. The following describes an example of a solution in connection with some embodiments.

Example 1

Fig. 1 is a schematic flow chart illustrating an instruction verification method according to a first embodiment of the present application, where the execution body of the present example may be an instruction verification system, as shown in fig. 1, and the method includes:

Step 101, an excitation generator sends excitation to a to-be-detected cache and a cache model; the excitation is generated based on larx instructions and stcx instructions of a Power instruction set according to preset excitation sending conditions and excitation types;

102, responding to excitation by the cache to be tested, and executing processing to obtain a first processing result; the information collector collects and obtains a first processing result from the cache to be detected and sends the first processing result to the result comparator;

Step 103, the buffer model responds to the excitation, performs processing to obtain a second processing result, and sends the second processing result to the result comparator; the cache model is established based on a cache mechanism and larx instructions and stcx instructions of a Power instruction set and is used for simulating standard cache to execute instruction operation processing on received excitation;

104, a result comparator detects whether the first processing result is consistent with the second processing result, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails.

In practical application, the execution subject of the method can be an instruction verification system, and various implementation modes can be realized, for example, the method can be realized through a computer program, such as application software and the like; or may be embodied as a medium storing a related computer program, e.g., a usb disk, a cloud disk, etc.; or may also be implemented by physical means, e.g. a chip or the like, incorporating or installing the relevant computer program.

Specifically, the instruction verification method in the invention is based on UVM verification methodology. The UVM verification methodology is a general verification methodology, is a verification platform development framework based on a system-level hardware description language class library, and researchers can build a functional verification environment with a standardized hierarchical structure and interfaces by using reusable components of the verification platform development framework. In this example, the stimulus generator establishes separate encapsulators for larx and stcx instructions, including the encapsulator corresponding to larx instruction and the encapsulator corresponding to stcx instruction, for sending stimulus to the cache under test and the cache model. Wherein each wrapper includes a drive, monitor, interface, and project, etc., wrapper base elements based on UVM verification methodology.

In this example, when the instruction verification is performed, first, an excitation generator needs to send excitation to a to-be-detected cache and a cache model, and at this time, a driver in the wrapper outputs various types of excitation to be sent to the to-be-detected cache model based on larx instructions and stcx instructions in a Power instruction set according to preset excitation sending conditions and excitation types. For example, the excitation types may be a directional excitation type and a random excitation type, and the larx instruction and the stcx instruction may be transmitted in pairs or may be transmitted separately. And secondly, after the buffer to be tested receives the excitation sent by the excitation transmitter, performing corresponding processing to obtain a first processing result, collecting the first processing result from the buffer to be tested by the information collector, and sending the first processing result to the result comparator for subsequent result comparison. After the buffer model receives the excitation sent by the excitation transmitter, the buffer model executes corresponding processing to obtain a second processing result, and the second processing result is directly sent to the result comparator for subsequent result comparison. The buffer model is built based on buffer mechanism and larx instruction and stcx instruction in Power instruction set, and can be used for simulating standard buffer to execute corresponding processing on received excitation. Finally, comparing whether the first processing result is consistent with the second processing result in a result comparator, and if the first processing result is consistent with the second processing result, judging that the verification is successful; if the first processing result and the second processing result are inconsistent, judging that verification fails. For example, the first processing result and the second processing result in the result comparator include the following contents: larx instruction, the size of the obtained data is 128Bytes; stcx status of instruction failure or success; update information of the directory; update information of the data storage; retaining updated information of the station; request information sent over AMBA CHI bus protocol. When the comparison is performed in the result comparator, the comparison is performed in real time, namely in the verification process, and when the first processing result is inconsistent with the second processing result, UVM_ERROR and specific ERROR information are required to be printed, so that the subsequent positioning problem is facilitated.

In the above example, based on larx instructions and stcx instructions in the Power instruction set, a cache model is set, an excitation generator is used to send excitation to the cache model to be tested, corresponding processing is executed to obtain a first processing result and a second processing result, and then the first processing result and the second processing result are sent to a result comparator to be compared, and based on a UVM verification methodology, instruction verification reuse is realized to the greatest extent, so that verification efficiency is improved, and the behavior of instructions in the cache can be comprehensively and effectively verified.

Based on the foregoing examples, in one example, the cache model includes: the system comprises an instruction execution module, a control module, a catalog, a data storage station and a reservation station; the instruction execution module is used for responding larx instructions or stcx instructions, accessing the catalog and executing the execution flow of larx instructions or stcx instructions in the cache model based on cache data in the data storage, wherein the execution flow comprises updating data in a reservation station according to preset reservation setting conditions and reservation emptying conditions; the control module is used for executing maintenance processing on the reservation station according to a preset reservation maintenance condition when detecting that a load request or a noop request exists between the larx instruction and the stcx instruction.

In this example, the cache model is built based on the cache mechanism and larx and stcx instructions in the Power instruction set. The cache model includes an instruction execution module, a control module, a directory, a data store, and a reservation station. The data states in the cache model are initialized at the beginning of verification to UniqueClean, uniqueDirty, sharedClean, sharedDirty, invalid different states. The functions of the instruction execution module include larx instruction and stcx instruction receiving, larx instruction and stcx instruction executing, reservation station maintenance and result data output. The instruction execution module responds to larx instructions in the Power instruction set, accesses a directory in the cache model to judge whether the address accessed by the current larx instruction hits the cache model, executes a corresponding flow according to the situation of hitting the cache model and missing the cache model, and updates data in the reservation station according to preset reservation setting conditions; the instruction execution module responds to stcx instructions in the Power instruction set, firstly accesses a reservation station in the cache model, obtains a return result of the stcx instruction according to the identification bit and the address in the reservation station, judges whether the address accessed by the current stcx instruction hits the cache model or not when the return result is successful, executes corresponding processes according to the conditions of hitting the cache model and not hitting the cache model, and updates data in the reservation station according to preset reservation emptying conditions. When the larx instruction and the stcx instruction are sent in pairs, a load request or a snoop request may be inserted in the middle, the larx instruction cannot hit the cache model, and the stcx instruction also obtains a failed return result, and when the control module detects that the load request or the snoop request exists between the larx instruction and the stcx instruction, the maintenance processing on the reservation station needs to be executed according to a preset reservation maintenance condition. By means of the scheme, the cache model is built, and the behavior of the instruction in the cache can be comprehensively and effectively verified.

In the instruction verification method provided by the embodiment, an excitation generator sends excitation to a to-be-detected cache and a cache model; the excitation is generated based on larx instructions and stcx instructions in a Power instruction set according to preset excitation sending conditions and excitation types; responding to the excitation sent by the excitation generator, and obtaining a first processing result after the buffer to be detected is processed; the information collector collects and obtains a first processing result from the cache to be detected and sends the first processing result to the result comparator; responding to the excitation sent by the excitation generator by the buffer model, performing processing to obtain a second processing result, and sending the second processing result to the result comparator; the buffer model is established based on a buffer mechanism and larx instructions and stcx instructions in a Power instruction set and is used for simulating standard buffer to execute instruction operation processing on received excitation; the result comparator detects whether the received first processing result and the received second processing result are consistent, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails. According to the scheme, based on larx instructions and stcx instructions in a Power instruction set, a cache model is set, excitation is sent to the cache model to be tested through an excitation generator, corresponding processing is carried out to obtain a first processing result and a second processing result, the first processing result and the second processing result are then sent to a result comparator for comparison, the behavior of the instructions in the cache can be comprehensively and effectively verified, and the verification method is high in item inheritance and capable of being quickly transplanted to other verification platforms based on UVM verification methodologies.

Example two

Fig. 2 is a schematic flow chart of an instruction verification method according to a second embodiment of the present application, where the execution body of the present example may be an instruction verification system, as shown in fig. 2, and the execution flow of larx instructions in a cache model includes:

step 201, the cache model determines whether the currently received instruction is a larx instruction by parsing, and if the currently received instruction is a larx instruction, the larx instruction is transmitted to the instruction execution module;

Step 202, an instruction execution module accesses a directory and judges whether larx instructions hit under a cache model; if the result is hit, corresponding data are acquired and returned to the kernel processor, the data are sent to the result comparator as a second processing result, and the entry of the corresponding thread in the reservation station is set according to preset reservation setting conditions and reservation emptying conditions; if the data is not hit, corresponding data is acquired from the next-level cache, the data is written into the data storage and the catalog is updated, the data is returned to the kernel processor, the data is used as a second processing result to be sent to the result comparator, and the entry of the corresponding thread in the reservation station is set according to the preset reservation setting condition and the reservation emptying condition.

Specifically, after receiving the larx instruction sent by the excitation generator, the cache model judges whether the instruction is a larx instruction or not through instruction type analysis, and if the instruction is a larx instruction, the cache model transmits the instruction to the instruction execution module; then the instruction execution module starts to access the catalogue in the cache model to judge whether the address accessed by the current larx instruction hits the cache model or not; when larx instruction hits the cache model, indicating that the data to be accessed is already stored in the cache model, reading the data, returning the data to the kernel processor, sending the data to the result comparator as a second processing result, and setting an entry of a corresponding thread in a reservation station according to a preset reservation setting condition and a reservation emptying condition; when larx instruction does not hit the cache model, it indicates that the data to be accessed does not exist in the cache model, at this time, the instruction execution module needs to send READSHARED request to a next-level cache based on AMBA CHI bus protocol to obtain the corresponding data, where the next-level cache may be a CHI VIP module, when the data to be accessed does not exist in the cache model, the corresponding data may be obtained to the CHI VIP module, after the next-level cache returns the data, the instruction execution module writes the data into a data storage, updates a directory in the cache model, returns the data to a kernel processor, and sends the data as a second processing result to a result comparator, and sets an entry of a corresponding thread in a reservation station according to a preset reservation setting condition and a reservation emptying condition.

In the above example, for two cases of larx instructions hitting the cache model and not hitting the cache model, corresponding processing is performed in the cache model, so that the behavior of the instructions in the cache can be comprehensively and effectively verified.

Fig. 3 is a schematic flow chart illustrating an instruction verification method provided by an example, where the execution body of the example may be an instruction verification system, as shown in fig. 3, and the execution flow of stcx instructions in a cache model includes:

Step 301, the cache model determines whether the currently received instruction is a stcx instruction through analysis, and if the currently received instruction is a stcx instruction, the stcx instruction is transmitted to the instruction execution module;

Step 302, the instruction execution module accesses the reservation station, obtains a return result according to the identification bit and the address under the entry of the thread where the stcx instruction is located, sends the return result as a second processing result to the result comparator, and sets the entry of the corresponding thread in the reservation station according to a preset reservation setting condition and a reservation clearing condition; if the returned result is successful, the instruction execution module accesses the directory, and judges whether stcx instructions hit under the cache model; if hit, and hit the state of the data to be the exclusive state, write the data into the data storage; if the data is hit and the hit data is in a shared state, acquiring corresponding data from the next-level cache, writing the data into a data storage and updating the catalog; if not, reporting error.

Specifically, after receiving the stcx instruction sent by the excitation generator, the cache model judges whether the instruction is a stcx instruction or not through instruction type analysis, and if the instruction is a stcx instruction, the cache model transmits the instruction to the instruction execution module; and the instruction execution module accesses a reservation station in the cache model, obtains a return result according to the identification bit and the address of the thread of the stcx instruction, and when the identification bit of the thread of the stcx instruction is 1 and the address accessed by the stcx instruction is equal to the address of the thread of the stcx instruction on the granularity of 64Bytes, the result returned by the stcx instruction is successful, the other cases are failed, the return result is sent to a result comparator as a second processing result, and the entry of the corresponding thread in the reservation station is set according to a preset reservation setting condition and a reservation clearing condition.

Correspondingly, when the result returned by the stcx instruction is successful, the instruction execution module starts to access the directory in the cache model, judges whether the stcx instruction hits in the cache model, and if not, reports errors, because the stcx instruction must hit the cache model under the condition that the reservation station is successful, otherwise, the hardware problem exists. When stcx instruction hits the cache model and the hit data state is the unique state, the data is directly written into the data storage; when stcx instruction hits the cache model and the hit data state is the shared state, stcx instruction needs to send MakeReadUnique request to the next level cache through AMBA CHI bus protocol, that is, CHI VIP module to obtain the exclusive permission of the data, when MakeReadUnique receives the response of CHI VIP module, stcx instruction can write the data into the directory in the data storage and update the cache model, and change the state of the data in the cache model to UniqueDirty.

In the above example, for two cases of stcx instructions hitting the cache model and not hitting the cache model, corresponding processing is performed in the cache model, so that the behavior of the instructions in the cache can be comprehensively and effectively verified.

On the basis of the foregoing examples, in one example, the set conditions are reserved, including at least one of: for larx instructions, if the larx instruction hits in the cache model, setting the flag under the entry of the corresponding thread in the reservation station to 1, setting addr to the access address indicated by larx instruction, and reserving the granularity to 64Bytes; for larx instructions, if the larx instruction misses under the cache model and the corresponding data is successfully acquired from the next-level cache, setting the flag under the entry of the corresponding thread in the reservation station to be 1, setting addr to be an access address indicated by larx instructions, and reserving granularity to be 64Bytes; the emptying conditions are maintained, including at least one of the following: for stcx instructions, whether the cache model is hit or not, the entry of the corresponding thread in the reservation station is emptied, and the flag is set to 0; for stcx instructions, if the flag of the non-native thread entry in the reservation station is 1 and the access addresses indicated by addr and stcx instructions are the same at 64Bytes granularity, clearing the reservation station information of the entry; for stcx instructions, a store request is inserted in the same thread, and if the store request hits the addresses of other threads in the reservation station, reservation station information of the other threads is cleared.

In this example, the reservation station in the cache model is used to record the reservation identification bits (flag) and the reservation addresses (addr) of different threads, and the cache model in the present instruction verification method supports 8 threads, so the reservation station has 8 entries, each entry including a reservation identification bit and a reservation address.

Wherein, for larx instruction, reservation setting conditions are preset. When the cache model receives larx instructions of a thread, if the larx instructions hit under the cache model, setting a flag under a corresponding thread entry in a reservation station to be 1, setting addr to be an access address indicated by larx instructions, and reserving granularity to be 64Bytes; if the larx instruction misses under the cache model, sending READSHARD a request to obtain data to a next level cache, that is, a CHI VIP module, based on an AMBA CHI bus protocol through an instruction execution module, if the corresponding data is successfully obtained from the next level cache, setting a flag under a corresponding thread entry in a reservation station to be 1, setting addr to be an access address indicated by a larx instruction, and setting the reservation granularity to be 64Bytes.

Correspondingly, a reserved clearing condition is preset for stcx instructions. When the cache model receives a thread stcx instruction, whether the stcx instruction hits or not under the cache model, the entry of the corresponding thread in the reservation station is emptied, and the flag is set to 0; if the flag of the non-thread entry in the reservation station is 1 and the access address indicated by the addr and stcx instruction is the same under the granularity of 64Bytes, clearing the reservation station information of the entry; if a store request is inserted in the same thread that hits on the addresses of other threads in the reservation station, the reservation station information for the other threads is cleared.

In the above example, the reservation setting conditions and the reservation emptying conditions corresponding to the reservation stations in the cache model are set for the larx instruction and the stcx instruction, so that the behavior of the instruction in the cache can be comprehensively and effectively verified.

In one example, maintaining the maintenance condition includes: if a load request is received, the request triggers eviction a behavior, and the data address accessed by the behavior is the same as the address under any entry in the reservation station, the entry is emptied; if a snoop request is received, the type of the snoop request is analyzed, and if the snoop request is used for invalidating any cache data, the address of the cache data is the same as the address under any entry in the reservation station, the entry is emptied.

In this example, the control module is configured to maintain a reservation station in the cache model when a load request trigger eviction is received or a snoop request is received in the cache model. When a load request is received in the cache model and eviction actions are triggered, the data is required to be kicked out of the cache model, the data address accessed by the eviction actions is the same as the address under any one entry in the reservation station, and the entry is emptied; when a snoop request is received in the cache model, the control module needs to analyze the type of the snoop request first, and if the snoop request is used for invalidating any cache data in the cache model, and the addresses of the data under any entry in the reservation station are the same, the entry is emptied. Through the scheme of the example, when the cache model receives a snoop request or triggers eviction behaviors, the reservation maintenance conditions are set, so that the behaviors of the instructions in the cache can be comprehensively and effectively verified.

On the basis of any of the foregoing examples, the excitation transmission condition includes: for larx instructions, the following conditions are satisfied: the larx instructions being executed under the same thread are not more than 1, and there are no stcx instructions being executed under the thread; larx instructions under different threads allow for parallel issue, and the addresses indicated by larx instructions under different threads allow for the same; for stcx instructions, the following conditions are satisfied: stcx instructions that are executing under the same thread are not more than 1; and the thread needs to confirm that larx instructions of the same thread are sent to the thread, if larx instructions exist, stcx instructions need to be executed after the larx instructions are executed; if the larx instruction does not exist, the stcx instruction is converted into a stcxfnk instruction type; stcx instructions under different threads allow for parallel issue, and the addresses indicated by stcx instructions under different threads allow for the same.

Specifically, from the description of the larx instruction in the Power instruction set, the larx instruction must satisfy the following conditions in the dispatch to the cache model: only one larx instruction in the same thread can be executed in the cache model, and larx instructions of the same thread can not be sent until the previous larx instruction is executed; the larx instructions between different threads are not limited, can be sent simultaneously, and the addresses can be the same; prior to issuing larx instructions, it is necessary to ensure that there are no co-threaded stcx instructions in the current cache model that are executing. stcx the instruction must meet the following conditions in sending to the cache model: only one stcx instruction in the same thread can be executed in the cache model, and stcx instructions of the same thread can not be sent until the previous stcx instruction is executed; the stcx instructions between different threads are not limited, can be sent simultaneously, and the addresses can be the same; before stcx instruction is sent, larx instruction with the same thread is required to be sent to a cache model, if not, stcx instruction is required to be converted into stcxfnk instruction type, which means that stcx instruction does not need to check a reservation station and directly returns a failure result; if a larx instruction of the same thread is already sent to the cache model before the stcx instruction is sent, it is necessary to wait until the larx instruction is completed before driving the stcx instruction to the interface signal.

Accordingly, according to the sending conditions of the larx instruction and the stcx instruction, the larx _start, the larx_comp, the stcx_start and the stcx_comp flags are established in the items in the excitation generator, each thread has an independent flag bit for controlling the sending of the larx instruction and the stcx instruction, and the setting of the flag bits satisfies the timing sequence of fig. 4.

Specifically, when larx instruction is sent, larx _start of the thread is set to 1; when the monitor monitors that the larx instruction returns data, the larx instruction is completed, larx _comp is set to 1, and larx _start is set to 0; when the larx instruction or stcx instruction in the same thread is issued, larx _comp is set to 0 and the larx_start remains unchanged. When stcx instruction is issued, stcx _start of the thread is set to 1; when the monitor monitors whether the stcx instruction returns a failed or successful state, it indicates that the stcx instruction is complete, stcx _comp is set to 1, and stcx _start is set to 0; when a new stcx instruction follows, stcx _start of the thread is again set to 1.

When a new larx instruction needs to be sent in the excitation, the driver of the larx instruction firstly checks larx _start and larx_comp states of the thread, if larx _start is 0 or larx _comp is 1, the driver indicates that the larx instruction can be driven to the cache model interface, and if larx _start is 1, the driver of the larx instruction needs to wait for larx _comp of the same thread to be driven to the cache model interface after being 1; the driver then looks at the stcx _start, stcx_comp state of the thread, and when stcx _start is 0 or stcx _comp is 1, the larx instruction can drive to the cache model interface, and if stcx _start is 1, the larx instruction needs to wait for stcx _comp of the same thread to drive to the cache model interface.

When a new stcx instruction needs to be sent in the excitation, the driver of the stcx instruction firstly checks larx _start and larx_comp states of the thread, and if larx _start is 0 and larx _comp is 1, the driver indicates that the instruction of the same thread larx has been executed before, and the current stcx instruction can be driven to a cache model interface; if larx _start is 1, it indicates that there is a co-thread larx instruction executing, and it is necessary to wait until larx _comp is 1 to drive stcx instructions to the cache model interface; if larx _start is 0 and larx _comp is 0, then it indicates that no previously co-threaded larx instruction was executed, and the current stcx instruction needs to be converted to stcxfnk instruction type to be driven to the cache model interface.

In the above example, according to the Power instruction set provision of larx instruction and stcx instruction, the condition that the incentive generator sends the incentive is established, so that the behavior of the instruction in the cache can be effectively verified.

Based on the foregoing examples, in one example, the excitation types include: a directional excitation type and a random excitation type; wherein the directional excitation type comprises at least one of: first directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, and other instructions are not inserted in the middle; second directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, and addresses accessed by store requests are the same as those accessed by larx instructions and stcx instructions; third directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are the same, and access addresses among different threads are random; fourth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are different, and access addresses among different threads are random; fifth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, and addresses accessed by store requests are the same as those accessed by larx instructions and stcx instructions; sixth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a noop request is inserted in the middle, and the addresses accessed by the noop request are the same as those accessed by larx instructions and stcx instructions; seventh directional excitation type: under a single thread, the larx instruction and the stcx instruction are sent in pairs, addresses accessed by the larx instruction and the stcx instruction under the same thread are the same, a load request is inserted in the middle, and data accessed by the larx instruction and the stcx instruction are the same as data accessed by eviction behavior; eighth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a flush request is inserted in the middle, and data accessed by larx instructions and stcx instructions are the same as data accessed by the flush request; the random excitation type satisfies: the same addresses are accessed by larx and stcx instructions under the same thread, and the thread numbers under different threads are random.

In this example, when the stimulus generator sends the stimulus into the cache to be tested and the cache model, the stimulus type may be classified into a directional stimulus type and a random stimulus type. The directional excitation types can be divided into 8 types, including the first excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, and other instructions are not inserted in the middle; second directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, the addresses accessed by the store requests are the same as those accessed by larx instructions and stcx instructions, and a reservation station is cleared by the store requests; third directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are the same, and access addresses among different threads are random; fourth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are different, and access addresses among different threads are random; fifth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, and addresses accessed by store requests are the same as those accessed by larx instructions and stcx instructions; sixth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a noop request is inserted in the middle, the addresses accessed by the noop request are the same as those accessed by larx instructions and stcx instructions, the noop request type is traversed, and a noop invalid request can clear a reservation station; seventh directional excitation type: under a single thread, a larx instruction and a stcx instruction are sent in pairs, addresses accessed by the larx instruction and the stcx instruction under the same thread are the same, a load request is inserted in the middle, eviction behaviors are triggered, and data accessed by the larx instruction and the stcx instruction are the same as data accessed by the eviction behavior; eighth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a flush request is inserted in the middle, and data accessed by larx instructions and stcx instructions are the same as data accessed by the flush request.

Accordingly, random stimulus mixes larx instructions, stcx instructions and other requests sent into the cache model in stimulus, mainly including load requests, store requests, noop requests, barrer class requests, etc. Random excitation does not limit the paired sending of larx and stcx instructions, and may send larx instructions alone, stcx instructions alone, or larx and stcx instructions in pairs. The method only needs to meet the requirement that the addresses accessed by larx instructions and stcx instructions under the same thread are the same, and the thread numbers under different threads are random.

According to the scheme of the example, when the excitation generator sends excitation to the to-be-detected buffer and the buffer model, the excitation under various conditions can be sent, and when the to-be-detected buffer and the buffer model receive excitation under any condition, corresponding processing is executed, so that the behavior of the instruction in the buffer can be comprehensively and effectively verified.

In the instruction verification method provided by the embodiment, corresponding processing flows of larx instructions and stcx instructions in a cache model are executed according to a reservation setting condition, a reservation emptying condition and a reservation maintenance condition of a reservation station in the cache model, and corresponding excitation sending conditions and excitation types are set based on the provision of larx instructions and stcx instructions under a Power instruction set. The scheme of the application can comprehensively and effectively verify the behavior of the instruction in the cache, and the verification method is based on a UVM verification methodology, has high item inheritance and can be quickly transplanted to other verification platforms.

Example III

Fig. 5 schematically illustrates a structural diagram of an instruction verification system according to a third embodiment of the present application, as shown in fig. 5, where the system includes:

an excitation generator 51 for sending excitation to the cache model to be tested; the excitation is generated based on larx instructions and stcx instructions of a Power instruction set according to preset excitation sending conditions and excitation types;

the to-be-tested cache 52 is configured to respond to the excitation and perform a process to obtain a first processing result;

The information collector 53 is configured to collect and obtain a first processing result from the to-be-detected buffer, and send the first processing result to the result comparator;

The buffer model 54 is configured to respond to the excitation, perform a process to obtain a second processing result, and send the second processing result to the result comparator; the cache model is established based on a cache mechanism and larx instructions and stcx instructions of a Power instruction set and is used for simulating standard cache to execute instruction operation processing on received excitation;

A result comparator 55 for detecting whether the first processing result and the second processing result are identical, and if so, determining that the verification is successful; if the verification is inconsistent, judging that the verification fails.

In practical applications, the instruction verification system can be implemented in various ways, for example, by a computer program, for example, application software, etc.; or may be embodied as a medium storing a related computer program, e.g., a usb disk, a cloud disk, etc.; or may also be implemented by physical means, e.g. a chip or the like, incorporating or installing the relevant computer program.

In this example, when the instruction verification is performed, first, an excitation generator needs to send excitation to a to-be-detected cache and a cache model, and at this time, a driver in the wrapper outputs various types of excitation to be sent to the to-be-detected cache model based on larx instructions and stcx instructions in a Power instruction set according to preset excitation sending conditions and excitation types. And secondly, after the buffer to be tested receives the excitation sent by the excitation transmitter, performing corresponding processing to obtain a first processing result, collecting the first processing result from the buffer to be tested by the information collector, and sending the first processing result to the result comparator for subsequent result comparison. After the buffer model receives the excitation sent by the excitation transmitter, the buffer model executes corresponding processing to obtain a second processing result, and the second processing result is directly sent to the result comparator for subsequent result comparison. The buffer model is built based on buffer mechanism and larx instruction and stcx instruction in Power instruction set, and can be used for simulating standard buffer to execute corresponding processing on received excitation. Finally, comparing whether the first processing result is consistent with the second processing result in a result comparator, and if the first processing result is consistent with the second processing result, judging that the verification is successful; if the first processing result and the second processing result are inconsistent, judging that verification fails.

Based on the foregoing examples, in one example, the cache model 54 includes: the system comprises an instruction execution module, a control module, a catalog, a data storage station and a reservation station; the instruction execution module is used for responding larx instructions or stcx instructions, accessing the catalog and executing the execution flow of larx instructions or stcx instructions in the cache model based on cache data in the data storage, wherein the execution flow comprises updating data in a reservation station according to preset reservation setting conditions and reservation emptying conditions; the control module is used for executing maintenance processing on the reservation station according to a preset reservation maintenance condition when detecting that a load request or a noop request exists between the larx instruction and the stcx instruction.

Based on the foregoing example, an instruction execution module is to: the cache model judges whether the currently received instruction is a larx instruction or not through analysis, if the currently received instruction is a larx instruction, the larx instruction is transmitted to an instruction execution module; the instruction execution module accesses the directory and judges larx whether the instruction hits or not under the cache model; if the result is hit, corresponding data are acquired and returned to the kernel processor, the data are sent to the result comparator as a second processing result, and the entry of the corresponding thread in the reservation station is set according to preset reservation setting conditions and reservation emptying conditions; if the data is not hit, corresponding data is acquired from the next-level cache, the data is written into the data storage and the catalog is updated, the data is returned to the kernel processor, the data is used as a second processing result to be sent to the result comparator, and the entry of the corresponding thread in the reservation station is set according to the preset reservation setting condition and the reservation emptying condition.

In one example, an instruction execution module is to: the cache model judges whether the currently received instruction is a stcx instruction or not through analysis, if the currently received instruction is a stcx instruction, the stcx instruction is transmitted to an instruction execution module; the instruction execution module accesses the reservation station, obtains a return result according to the identification bit and the address under the entry of the thread where the stcx instruction is located, sends the return result as a second processing result to the result comparator, and sets the entry of the corresponding thread in the reservation station according to a preset reservation setting condition and a reservation emptying condition; if the returned result is successful, the instruction execution module accesses the directory, and judges whether stcx instructions hit under the cache model; if hit, and hit the state of the data to be the exclusive state, write the data into the data storage; if the data is hit and the hit data is in a shared state, acquiring corresponding data from the next-level cache, writing the data into a data storage and updating the catalog; if not, reporting error.

Accordingly, according to the above-mentioned larx instruction and stcx instruction sending conditions, larx _start, larx_comp, stcx_start and stcx_comp flags are set up in the entries in the stimulus generator, and each thread has an independent flag for controlling the sending of larx instructions and stcx instructions.

In the instruction verification system provided by the embodiment, an excitation generator sends excitation to a to-be-detected cache and a cache model; the excitation is generated based on larx instructions and stcx instructions in a Power instruction set according to preset excitation sending conditions and excitation types; responding to the excitation sent by the excitation generator, and obtaining a first processing result after the buffer to be detected is processed; the information collector collects and obtains a first processing result from the cache to be detected and sends the first processing result to the result comparator; responding to the excitation sent by the excitation generator by the buffer model, performing processing to obtain a second processing result, and sending the second processing result to the result comparator; the buffer model is established based on a buffer mechanism and larx instructions and stcx instructions in a Power instruction set and is used for simulating standard buffer to execute instruction operation processing on received excitation; the result comparator detects whether the received first processing result and the received second processing result are consistent, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails. According to the scheme, based on larx instructions and stcx instructions in a Power instruction set, a cache model is set, excitation is sent to the cache model to be tested through an excitation generator, corresponding processing is carried out to obtain a first processing result and a second processing result, the first processing result and the second processing result are then sent to a result comparator for comparison, the behavior of the instructions in the cache can be comprehensively and effectively verified, and the verification method is high in item inheritance and capable of being quickly transplanted to other verification platforms based on UVM verification methodologies.

Example IV

Fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application, as shown in fig. 6, where the electronic device includes:

A processor 291, the electronic device further comprising a memory 292; a communication interface (Communication Interface) 293 and bus 294 may also be included. The processor 291, the memory 292, and the communication interface 293 may communicate with each other via the bus 294. Communication interface 293 may be used for information transfer. The processor 291 may invoke logic instructions in the memory 292 to perform the methods of the examples described above.

Further, the logic instructions in memory 292 described above may be implemented in the form of software functional units and stored in a computer-readable storage medium when sold or used as a stand-alone product.

The memory 292 is a computer readable storage medium, and may be used to store a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present application. The processor 291 executes functional applications and data processing by running software programs, instructions and modules stored in the memory 292, i.e., implements the methods in the method examples described above.

Memory 292 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created according to the use of the terminal device, etc. Further, memory 292 may include high-speed random access memory, and may also include non-volatile memory.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, are configured to implement the method of any of the examples.

Embodiments of the present application also provide a computer program product for implementing the method of any of the embodiments when the computer program is executed by a processor.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. The instruction verification method is characterized by being applied to an instruction verification system, wherein the instruction verification system comprises an excitation generator, a cache to be tested, a cache model, an information acquisition device and a result comparator; the method comprises the following steps:

The excitation generator sends excitation to the to-be-detected cache and the cache model; the excitation is generated based on larx instructions and stcx instructions of a Power instruction set according to preset excitation sending conditions and excitation types;

Responding the excitation by the buffer to be tested, and executing the processing to obtain a first processing result; the information collector collects the first processing result from the to-be-detected cache and sends the first processing result to the result comparator;

The cache model responds to the excitation, performs processing to obtain a second processing result, and sends the second processing result to the result comparator; the cache model is established based on a cache mechanism and larx instructions and stcx instructions of the Power instruction set and is used for simulating standard cache to execute instruction operation processing on received excitation;

the result comparator detects whether the first processing result and the second processing result are consistent, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails;

The cache model comprises: the system comprises an instruction execution module, a control module, a catalog, a data storage station and a reservation station;

The instruction execution module is used for responding larx instructions or stcx instructions, accessing the catalog and executing the execution flow of the larx instructions or stcx instructions in the cache model based on cache data in the data storage, wherein the execution flow comprises updating data in the reservation station according to preset reservation setting conditions and reservation emptying conditions;

the control module is used for executing maintenance processing of the reservation station according to a preset reservation maintenance condition when detecting that a load request or a snoop request exists between the larx instruction and the stcx instruction;

the excitation transmission condition includes:

For larx instructions, the following conditions are satisfied: the larx instructions being executed under the same thread are not more than 1, and there are no stcx instructions being executed under the thread; larx instructions under different threads allow for parallel issue, and the addresses indicated by larx instructions under different threads allow for the same;

For stcx instructions, the following conditions are satisfied: stcx instructions that are executing under the same thread are not more than 1; and the thread needs to confirm that larx instructions of the same thread are sent to the thread, if larx instructions exist, stcx instructions need to be executed after the larx instructions are executed; if the larx instruction does not exist, the stcx instruction is converted into a stcxfnk instruction type; stcx instructions under different threads allow for parallel issue, and the addresses indicated by stcx instructions under different threads allow for the same.

2. The method of claim 1, wherein the larx instruction execution flow in the cache model comprises:

The cache model judges whether the currently received instruction is a larx instruction or not through analysis, and if the currently received instruction is a larx instruction, the larx instruction is transmitted to the instruction execution module;

The instruction execution module accesses the directory and judges whether the larx instruction hits or not under the cache model; if the result is hit, corresponding data are acquired and returned to the kernel processor, the data are used as the second processing result to be sent to the result comparator, and the entry of the corresponding thread in the reservation station is set according to the preset reservation setting condition and reservation emptying condition; if the data is not hit, corresponding data is acquired from the next-level cache, the data is written into the data storage and the catalog is updated, the data is returned to the kernel processor, the data is used as the second processing result to be sent to the result comparator, and the entry of the corresponding thread in the reservation station is set according to the preset reservation setting condition and reservation emptying condition.

3. The method of claim 2, wherein the stcx instruction execution flow in the cache model comprises:

the cache model judges whether the currently received instruction is a stcx instruction or not through analysis, and if the currently received instruction is a stcx instruction, the stcx instruction is transmitted to the instruction execution module;

The instruction execution module accesses the reservation station, obtains a return result according to the identification bit and the address under the entry of the thread where the stcx instruction is located, sends the return result to the result comparator as a second processing result, and sets the entry of the corresponding thread in the reservation station according to the preset reservation setting condition and reservation clearing condition; if the returned result is successful, the instruction execution module accesses the catalog and judges whether the stcx instruction hits or not under the cache model; if hit, and hit the state of the data to be the exclusive state, write the data into the said data storage; if the data is hit and the hit data is in a shared state, acquiring corresponding data from a next-level cache, writing the data into the data storage and updating the catalog; if not, reporting error.

4. A method according to claim 3, wherein the reservation setting conditions comprise at least one of:

For larx instructions, if the larx instruction hits in the cache model, setting a flag under an entry of a corresponding thread in the reservation station to be 1, setting addr to be an access address indicated by the larx instruction, and reserving the granularity to be 64Bytes;

For larx instructions, if the larx instruction misses in the cache model and the corresponding data is successfully acquired from the next-level cache, setting the flag under the entry of the corresponding thread in the reservation station to be 1, setting addr to be the access address indicated by the larx instruction, and reserving the granularity to be 64Bytes;

the reserved flush condition comprises at least one of the following:

For stcx instructions, whether the cache model is hit or not, the entry of the corresponding thread in the reservation station is cleared, and the flag is set to 0;

for stcx instructions, if the flag of the non-thread entry in the reservation station is 1 and the access addresses indicated by addr and stcx instructions are the same at the granularity of 64Bytes, clearing the reservation station information of the entry;

for stcx instructions, a store request is inserted in the same thread, and if the store request hits the addresses of other threads in the reservation station, reservation station information of other threads is cleared.

5. The method of claim 1, wherein the reservation maintenance condition comprises:

if a load request is received, the request triggers eviction a behavior, and the data address accessed by the behavior is the same as the address under any entry in the reservation station, the entry is emptied;

And if the type of the snoop request is analyzed, and if the snoop request is used for invalidating any cache data and the address of the cache data is the same as the address of any entry in the reservation station, the entry is emptied.

6. The method of claim 1, wherein the excitation type comprises: a directional excitation type and a random excitation type; wherein the directional excitation type comprises at least one of:

First directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, and other instructions are not inserted in the middle;

Second directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, and addresses accessed by store requests are the same as those accessed by larx instructions and stcx instructions;

Third directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are the same, and access addresses among different threads are random;

fourth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same threads are different, and access addresses among different threads are random;

Fifth directional excitation type: under the multithreading, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions are the same, store requests of other threads are inserted in the middle, and addresses accessed by store requests are the same as those accessed by larx instructions and stcx instructions;

sixth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a noop request is inserted in the middle, and the addresses accessed by the noop request are the same as those accessed by larx instructions and stcx instructions;

Seventh directional excitation type: under a single thread, the larx instruction and the stcx instruction are sent in pairs, addresses accessed by the larx instruction and the stcx instruction under the same thread are the same, a load request is inserted in the middle, and data accessed by the larx instruction and the stcx instruction are the same as data accessed by eviction behavior;

eighth directional excitation type: under a single thread, larx instructions and stcx instructions are sent in pairs, addresses accessed by larx instructions and stcx instructions under the same thread are the same, a flush request is inserted in the middle, and data accessed by larx instructions and stcx instructions are the same as data accessed by the flush request;

the random excitation type satisfies: the same addresses are accessed by larx and stcx instructions under the same thread, and the thread numbers under different threads are random.

7. An instruction verification system, the system comprising:

the excitation generator is used for sending excitation to the to-be-detected cache and the cache model; the excitation is generated based on larx instructions and stcx instructions of a Power instruction set according to preset excitation sending conditions and excitation types;

the buffer memory to be tested is used for responding to the excitation and executing the processing to obtain a first processing result;

The information collector is used for collecting and obtaining the first processing result from the to-be-detected cache and sending the first processing result to the result comparator;

The buffer model is used for responding to the excitation, executing the processing to obtain a second processing result and sending the second processing result to the result comparator; the cache model is established based on a cache mechanism and larx instructions and stcx instructions of the Power instruction set and is used for simulating standard cache to execute instruction operation processing on received excitation;

The result comparator is used for detecting whether the first processing result and the second processing result are consistent, and if so, the verification is judged to be successful; if the verification is inconsistent, judging that the verification fails;

The control module is used for executing maintenance processing of the reservation station according to a preset reservation maintenance condition when detecting that a load request or a snoop request exists between the larx instruction and the stcx instruction; the excitation transmission condition includes:

8. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;

the memory stores computer-executable instructions;

The processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1-6.

9. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1-6.

10. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 1-6.