CN117216812B

CN117216812B - Attack detection circuit, chip and electronic equipment

Info

Publication number: CN117216812B
Application number: CN202311464273.7A
Authority: CN
Inventors: 范长永; 王宗岳; 黎福晓
Original assignee: Open Security Research Inc
Current assignee: Open Security Research Inc
Priority date: 2023-11-06
Filing date: 2023-11-06
Publication date: 2024-02-27
Anticipated expiration: 2043-11-06
Also published as: CN117216812A

Abstract

The invention discloses an attack detection circuit, a chip and electronic equipment, which can improve the safety of the chip. The attack detection circuit includes: the device comprises a cyclic shift register and a detection circuit, wherein the cyclic shift register comprises N registers which are connected end to end, the registers of which initial data are a first value and the registers of which initial values are a second value are adjacently arranged, and the N registers are connected with the same control signal source; n is an even number greater than 0; each register in the N registers is used for periodically and synchronously storing the data received by the input end at the output end based on the control signal sent by the control signal source and transmitting the data to the next register so as to enable the cyclic shift register to periodically update N-bit data corresponding to the N registers; and the detection circuit is used for determining that the chip is attacked when detecting that the N-bit data contains a continuous first value or a continuous second value.

Description

Attack detection circuit, chip and electronic equipment

Technical Field

The present invention relates to the field of chip technologies, and in particular, to an attack detection circuit, a chip, and an electronic device.

Background

The common fault injection attack method for the chip is mainly to crack or acquire sensitive information such as a secret key by changing the normal working state of a circuit in the chip. The current attack detection technology detects various fault injections by integrating various sensors in a chip, has high cost and difficult distribution and deployment, and is difficult to effectively protect the whole chip area, thereby reducing the chip safety.

Disclosure of Invention

The embodiment of the invention provides an attack detection circuit, a chip and electronic equipment, which can improve the chip safety.

The technical scheme of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides an attack detection circuit, applied to a chip, including:

the device comprises a cyclic shift register and a detection circuit, wherein the cyclic shift register comprises N registers, the output end of each register in the front N-1 registers of the N registers is connected with the input end of the next register, and the output end of the N register is connected with the input end of the 1 st register; the registers with initial data as a first value and the registers with initial values as a second value in the N registers are adjacently arranged, and the N registers are connected with the same control signal source; n is an even number greater than 0;

each of the N registers is configured to periodically synchronize, based on a control signal provided by the control signal source, storing data received at an input end at an output end, and transmitting the data to a next register, so that the cyclic shift register periodically updates N-bit data corresponding to the N registers;

the detection circuit is used for determining that the chip is attacked under the condition that the N-bit data contains a continuous first value or a continuous second value.

In a second aspect, an embodiment of the present invention provides a chip; the chip comprises at least one attack detection circuit; the attack detection circuit is any attack detection circuit provided by the embodiment of the invention; the at least one attack detection circuit is disposed at least one location within the chip;

the at least one attack detection circuit is used for generating an alarm signal under the condition that the chip is determined to be attacked;

the chip is used for processing the alarm signal.

In a third aspect, an embodiment of the present invention provides an electronic device, where the electronic device includes any one of the chips provided by the embodiment of the present invention.

The embodiment of the invention provides an attack detection circuit, a chip and electronic equipment, wherein a cyclic shift register in the embodiment of the invention comprises an even number of registers which are connected end to end, and N registers are connected with the same control signal source, so that each register in the N registers periodically updates N-bit data by periodically and synchronously storing data received by an input end at an output end and transmitting the data to the next register under the control of a control signal provided by the control signal source. Since the registers of the N registers whose initial data is the first value and the registers whose initial value is the second value are arranged adjacently, the N-bit data updated by the cyclic shift is also arranged adjacently to the first value and the second value under normal conditions, and therefore, in the case where the detection circuit detects that the N-bit data contains the continuous first value or the continuous second value, it can be determined that the chip is attacked. The embodiment of the invention does not directly detect the attack sources such as voltage, temperature, light and the like through the sensor, but detects whether the state of the digital circuit is disturbed and goes wrong, so as to judge whether the chip is attacked. The circuit has low realization cost, small occupied chip area and easy integration, can be independently arranged at any plurality of positions of the chip to increase the attack detection range of the chip, thereby greatly improving the safety of the chip.

Drawings

Fig. 1 is a schematic diagram of an attack detection circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram showing adjacent arrangement of registers with initial data as a first value and registers with initial data as a second value according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a process for shifting data by a cyclic shift register comprising 4 registers according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a second structure of an attack detection circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram III of an attack detection circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an attack detection circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of an attack detection circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a position deployment of at least one attack detection circuit in a chip according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a connection relationship between an attack detection circuit and a signal processing module according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Detailed Description

The present invention will be further described in detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent, and the described embodiments should not be construed as limiting the present invention, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a specific order or sequence, as permitted, to enable embodiments of the invention described herein to be practiced otherwise than as illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to be limiting of the invention.

Common fault injection attack methods for chips include electromagnetic attack, optical attack, voltage burr attack and the like, and the aim is to crack and acquire sensitive information such as keys by changing the normal working state of a circuit. Current attack detection techniques detect various fault injections by integrating multiple sensors in a chip, but each sensor can only detect one fault. For example, to detect voltage attacks, a voltage sensor is usually designed in a chip, and when the voltage is within an allowable range, the sensor does not alarm, and the chip works normally; when an attacker carries out voltage attack on the chip, an external power supply pin inputs voltage exceeding a normal range, the chip is in an attempt to make operation mistakes, sensitive information such as a secret key is obtained by analyzing the error phenomenon, and if the voltage sensor detects that the voltage exceeds the normal range at the moment, an alarm signal is output to enable the chip to be in a safe state such as reset and interruption, so that leakage of the sensitive information is prevented. Similarly, the temperature sensor is used for detecting whether the temperature is abnormal or not, and the light sensor is used for detecting whether the temperature is attacked by laser and visible light or not. A common feature of such sensors is that only one type of attack can be detected, and if multiple fault injection attacks are to be prevented, multiple sensors need to be placed in the chip.

The prior fault attack prevention method based on the sensor has the following defects: 1. the cost is high. The sensor is mostly realized by an analog circuit, the circuit area is large, and a plurality of different sensors are needed to deal with the existing attack means; 2. the distributed deployment is difficult, the analog circuit is provided with a power supply system independent of the digital circuit, so that the chip design is realized conveniently, the chip area is saved, meanwhile, the interference of the digital circuit to the analog circuit is avoided, and the sensor is usually concentrated in a certain fixed area on the chip and cannot be distributed for deployment, so that the whole chip area cannot be effectively protected. If some fault injection attacks such as optical attacks, electromagnetic attacks and the like are implemented at positions far away from the sensor, the fault injection attacks cannot be effectively detected, so that the chip safety is threatened, namely, the chip safety is reduced.

According to the analysis, the result of all injection fault attacks is that the circuit is made to run in error, and by utilizing the characteristic, the embodiment of the invention provides an attack detection circuit, a chip and electronic equipment, which can judge whether the chip is attacked or not based on whether the state of the shift register monitoring circuit is illegally changed, so that the chip safety is improved. The embodiment of the invention can be applied to various scenes of chip security such as cloud servers, post quantum passwords, blockchain passwords, super passwords and the like, and is specifically selected according to actual conditions, and the embodiment of the invention is not limited.

Referring to fig. 1, fig. 1 is a schematic diagram of an attack detection circuit according to an embodiment of the present invention. As shown in fig. 1, the attack detection circuit 1 includes: a cyclic shift register 10 and a detection circuit 11. The cyclic shift register 10 includes N registers, as shown in fig. 1, 2, 3 to N. N is an even number greater than 0.

In the embodiment of the invention, the output end of each register in the front N-1 registers in the N registers is connected with the input end of the next register, and the output end of the N register is connected with the input end of the 1 st register. That is, the N registers are connected end to end. The initial data of each of the N registers is either a first value or a second value. In some embodiments, the initial data refers to data at the output of the register. Among the N registers, a register whose initial data is a first value is arranged adjacent to a register whose initial value is a second value.

In an embodiment of the invention, the first value is different from the second value. In some embodiments, the first value may be 0 and the second value may be 1. Referring to fig. 2, fig. 2 is a schematic diagram illustrating an adjacent arrangement of registers with initial data having a first value and registers with initial data having a second value according to an embodiment of the present invention. In some embodiments, the first value and the second value may take other values, or may take other forms, such as a character form, which is specifically selected according to the actual situation, which is not limited by the embodiment of the present invention.

In the embodiment of the invention, N registers are connected with the same control signal source; the control signal source is used for providing a control signal. That is, the N registers may synchronously receive control signals provided or transmitted by the control signal source. Each of the N registers is configured to periodically synchronize, based on a control signal provided by a control signal source, storing data received at an input terminal at an output terminal, and transmitting the data to a next register, so that the cyclic shift register 10 periodically updates N-bit data corresponding to the N registers.

In the embodiment of the present invention, each of N registers synchronously stores data received at its own input terminal in an output terminal under the action of a control signal, and synchronously transfers the data to the next register through the output terminal, thereby completing a data shift, and the cyclic shift register 10 updates N-bit data corresponding to the N registers through a data shift. Each register periodically performs the above-described data shift operation in synchronization, so that the cyclic shift register 10 periodically updates the N-bit data.

It will be appreciated that since the N registers are connected end to end and the register whose initial data is the first value and the register whose initial value is the second value are arranged adjacently, the circuit operates normally without the chip being attacked, and each time each of the N registers performs a data shift under the action of the control signal, the N-bit data obtained by the cyclic shift register 10 is also arranged adjacently to the first value and the second value. For example, taking 4 registers as an example, referring to fig. 3, fig. 3 is a schematic diagram of a process of shifting data by using a cyclic shift register including 4 registers according to an embodiment of the present invention. As shown in fig. 3, the N registers may include: the first register, i.e. register 31, the second register, i.e. register 32, the third register, i.e. register 33, and the fourth register, i.e. register 34. Taking initial data of the register 31 as 0, initial data of the register 32 as 1, initial data of the register 33 as 0, and initial data of the register 34 as 1 as an example; that is, taking the initial N-bit data as 0101 as an example, when the control signals are received by the register 31, the register 32, the register 33, and the register 34, for the first data shift operation, the data received by the input terminal of the register 31 is 1 (i.e., the initial data of the register 34), the data received by the input terminal of the register 32 is 0 (i.e., the initial data of the register 31), the data received by the input terminal of the register 33 is 1 (i.e., the initial data of the register 32), and the data received by the input terminal of the register 34 is 0 (i.e., the initial data of the register 33). The registers 31, 32, 33 and 34 store the data received at their own input terminals to their output terminals in synchronization, thereby updating the N-bit data to 1010. The registers 31, 32, 33 and 34 continue to synchronously transfer the data stored in the output terminal to the next register connected to them (the next register connected to the register 34 is the register 31), and the next data is input when the next register shifts the data, so that the next data shift can be continuously performed at 1010, for example, 0101 is obtained by the next data shift, 1010 is obtained by the data shift at 0101, and so on. It can be seen that the circuit shown in fig. 3 is in normal operation, the data at the input and output of each register always remains in the opposite state during each data shift, i.e. no consecutive 0 or consecutive 1 occurs.

In some embodiments, the registers may include: the type of registers such as D flip-flops, JK flip-flops, latches, etc. are specifically selected according to practical situations, and the embodiment of the present invention is not limited.

In the embodiment of the present invention, based on the configuration and the working process of the initial data of the above-mentioned cyclic shift register 10, the cyclic shift register 10 performs cyclic shift based on its own initial data, and N bits of data obtained by each cyclic shift are adjacently arranged with a first value and a second value. Therefore, the detection circuit 11 can determine whether the chip is attacked by detecting whether the continuous first value or the continuous second value is contained in the N-bit data. In some embodiments, in the event that no consecutive first value or consecutive second value is contained in the N-bit data, the detection circuit 11 determines that the chip is not currently under attack. In some embodiments, the detection circuit 11 determines that the chip is under attack in case it detects that the N-bit data contains a consecutive first value or a consecutive second value. Here, the detection circuit 11, in the case where it detects that the N-bit data contains the consecutive first value or the consecutive second value, indicates that one or more registers in the cyclic shift register 10 are affected by an external attack to cause a data state error, so that it can be determined that the chip is attacked.

In some embodiments, the detection circuit 11 may read the data of each register through a software module and/or a hardware module, analyze and detect whether the N-bit data contains a continuous first value or a continuous second value. The detection function of the continuous first value or the continuous second value may be implemented in a circuit operation manner, and specifically selected according to the actual situation, and the embodiment of the present invention is not limited.

It should be noted that, in order to ensure that the N bits of data updated each time are adjacently arranged between the first value and the second value in the normal operating state of the cyclic shift register 10, the number of the first values and the second values at the output ends of the N registers needs to be ensured to be the same. If the number of registers is an odd number, for example 3, taking 010 as an example 3-bit initial data corresponding to 3 registers, then, based on 010, when shifting data for the first time, the input of the first register is output 0 of the third register, the input of the second register is output 0 of the first register, the input of the third register is output 1 of the second register, and the 3-bit data obtained by shifting data for the first time is 001. Data such as 100 and 010 can be obtained by continuing data shift based on 001. It can be seen that when the number of registers is odd, the input end and the output end of a certain register may be the same (e.g. 001 or 100), so that the detection circuit 11 misjudges that the chip is attacked. Therefore, the number of registers in the embodiment of the present invention must be even, that is, N must be an even number greater than 0, and the embodiment of the present invention does not limit the maximum number of even N.

It can be understood that the cyclic shift register in the embodiment of the present invention includes an even number of registers connected end to end, where the N registers are connected to the same control signal source, so that each of the N registers periodically stores data received at an input end in an output end and transmits the data to a next register under the control of a control signal provided by the control signal source, so as to implement a periodic cyclic shift operation, so that the cyclic shift register periodically updates N bits of data. Since the registers of the N registers whose initial data is the first value and the registers whose initial value is the second value are arranged adjacently, the N-bit data updated by the cyclic shift is also arranged adjacently to the first value and the second value under normal conditions, and therefore, in the case where the detection circuit detects that the N-bit data contains the continuous first value or the continuous second value, it can be determined that the chip is attacked. The embodiment of the invention does not directly detect the attack sources such as voltage, temperature, light and the like through the sensor, but detects whether the state of the digital circuit is disturbed and goes wrong, so as to judge whether the chip is attacked. The circuit has low realization cost, small occupied chip area and easy integration, can be independently arranged at any plurality of positions of the chip to increase the attack detection range of the chip, thereby greatly improving the safety of the chip.

In some embodiments, the detection circuit 11 may include: n exclusive or gates 110. Referring to fig. 4, fig. 4 is a schematic diagram of a second structure of an attack detection circuit according to an embodiment of the present invention. As shown in fig. 4, the N exclusive or gates 110 may include: exclusive or gate 1, exclusive or gate 2, exclusive or gate 3 to exclusive or gate N; each exclusive-or gate circuit corresponds to one register in the N registers, and two input ends of each exclusive-or gate circuit are respectively connected with the input end and the output end of the corresponding register. That is, the input end and the output end of each register in the N registers are respectively connected with two input ends of an exclusive OR gate.

In the embodiment of the present invention, each of the N exclusive or circuits 110 is configured to perform exclusive or processing on data at two input ends of the N exclusive or circuits, and output a third value or a fourth value. Wherein the third value characterizes that the data of the two input ends of the exclusive-OR gate are the same; the fourth value characterizes the difference in data at the two inputs of the exclusive or gate.

In the embodiment of the invention, the exclusive-or circuit can output a third value by performing exclusive-or processing on the data of the two input ends if the data of the two input ends are the same. And if the data of the two input ends are different, the exclusive OR circuit outputs a fourth value through exclusive OR processing. Here, the third value is different from the fourth value. The third value may be the same as or different from the first value, and the fourth value may be the same as or different from the second value, which is specifically selected according to the actual situation, which is not limited by the embodiment of the present invention. Illustratively, the third value may be 0 or false and the fourth value may be 1 or true.

In some embodiments, each of the N exclusive or circuits 110 is configured to exclusive-or data at two input terminals thereof, and output a third value when the data at the two input terminals are the same. The detection circuit 11 is further configured to determine that the chip is attacked if the data output by the N exclusive or circuits 110 includes a third value.

In the embodiment of the present invention, the third value output by the exclusive-or circuit characterizes that the data at the two input ends are the same, that is, the data at the input end and the output end of the register connected by the exclusive-or circuit are the same, which results in that the N-bit data corresponding to the cyclic shift register 10 includes a continuous first value or a continuous second value. Therefore, in the case where the data output from the N xor gate circuits 110 includes the third value, the detection circuit 11 determines that the chip is attacked. Here, the data output from the N exclusive or gates 110 includes data output from each of the N exclusive or gates 110.

In some embodiments, the detection circuit 11 is further configured to determine that the chip is not attacked if the data output by each of the N xor gates 110 is a fourth value; the fourth value characterizes the difference in data at the two inputs of the exclusive or circuit. That is, if the data output by each of the N xor circuits 110 is the fourth value, which means that the data at the input end and the output end of the register connected by each xor circuit are different, the cyclic shift register shifts the N-bit data with the first value and the second value arranged adjacently in the normal state, so that it can be determined that the chip is not attacked at present.

For example, in the case that the chip is not attacked, each register operates normally, and the data of the input end and the output end of each register are different, then the data output by each of the N exclusive or gates is 1. Under the condition that the chip is attacked, the data of one or more registers in the N registers are abnormal, the input end and the output end of the register with abnormal data are the same, and therefore the data output by the exclusive OR gate connected with the register with abnormal data are 0. In this way, in the case where 0 is included in the data output from the N exclusive or gates, it can be determined that the chip is attacked.

In some embodiments, the detection circuit 11 may analyze and detect whether the data output by the N xor gates 110 includes the third value by reading the data at the output of each xor gate. The detection circuit 11 in fig. 4 may receive the data output from the N output terminals of the N exclusive or gates 110 through a software module and/or a hardware module connected to the N output terminals of the N exclusive or gates 110, and analyze whether the third value is included therein. Alternatively, it is also possible to detect whether the data output by the N exclusive or gate circuits includes the third value or not by means of circuit operation. The embodiment of the present invention is not limited, and is specifically selected according to the actual situation.

It can be understood that the embodiment of the invention judges whether the state of the cyclic shift register is correct or not through the exclusive-or gate circuit, so as to judge whether the chip is attacked by fault injection, thereby realizing the attack detection of the chip in a digital circuit mode, needing no sensor, being not limited by the chip manufacturing process, not changing the chip design flow, being easy to integrate, small in occupied area and low in cost, and making up the defect that the traditional sensor can only detect the limited area of the chip, being capable of being deployed at any position of the chip, greatly improving the fault attack resistance of the chip, and further improving the security of the chip.

In some embodiments, the detection circuit 11 may further include: and a nand gate 111. Based on fig. 4, referring to fig. 5, fig. 5 is a schematic diagram of a structure of an attack detection circuit according to an embodiment of the present invention. As shown in fig. 5, N output terminals of the N exclusive or gates 110 are connected to input terminals of the nand gate 111. That is, the N exclusive or gates 110 may input the data output from each exclusive or gate to the nand gate 111 through the N output terminals.

In the embodiment of the present invention, the nand gate 111 may perform a nand operation on the data at the input end, and output a nand operation result. When the data at the input of the nand gate 111, that is, when the N exclusive or gate 110 outputs are all the fourth values, the nand operation outputs the third value, and when the data at the input of the nand gate 111 includes the third value, the nand operation outputs the fourth value. Illustratively, the third value may be 0 and the fourth value may be 1.

In some embodiments, the nand gate 111 is configured to output a fourth value when the data output by the N xor gates 110 includes a third value, that is, when the data at the input terminal of the nand gate 111 includes the third value.

In some embodiments, the detection circuit 11 is further configured to determine that the chip is attacked if the nand gate 111 outputs the fourth value.

In the embodiment of the present invention, when the data output by the N xor circuits 110 includes the third value, it is indicated that the register connected to one or more xor circuits in the N xor circuits 110 has the same illegal state as the data at the output end, and the N-bit data of the cyclic shift register has the continuous first value or second value. The nand gate 111 performs a nand operation on the data output from the N exclusive or gates 110, and outputs a fourth value. The detection circuit can determine that the cyclic shift register is interfered by the attack under the condition that the NAND gate circuit outputs the fourth value, and a data state error occurs, so that the chip is determined to be attacked.

In some embodiments, the nand gate 111 is further configured to output a third value when the data output by the N xor gates 110 are all of the fourth value, that is, when the data at the input ends of the nand gate 111 are all of the fourth value.

In some embodiments, the detection circuit 11 is further configured to determine that the chip is not attacked if the nand gate 111 outputs the third value.

It should be noted that, in some embodiments, the detection circuit 11 may also include: n exclusive OR gate circuits and NOR gate circuits. The two input ends of each of the N exclusive OR gate circuits are respectively connected with the input end and the output end of each of the N registers; each exclusive-or gate circuit is configured to output a fourth value when the data of the input terminal and the output terminal of the register to which it is connected are the same, that is, when the data of the two input terminals are the same; in case the data at the input and the output of the register to which it is connected are different, i.e. the data at the two inputs thereof are different, a third value is output. The N output ends of the N exclusive OR gate circuits are connected with the input end of the NOR gate circuit, and the NOR gate circuit is used for outputting a third value when the data output by the N exclusive OR gate circuits contain a fourth value; alternatively, when the data output from the N exclusive or gates are all the third values, the fourth value is output. In this way, the detection circuit 11 can determine that the chip is attacked in the case where the nor gate outputs the fourth value.

It can be understood that the embodiment of the invention judges whether the state of the cyclic shift register is correct or not through the exclusive-or gate circuit and the NAND gate circuit, so as to judge whether the chip is attacked by fault injection, thereby realizing the attack detection of the chip in a digital circuit mode, avoiding the dependence on a sensor, not being limited by the chip manufacturing process, not changing the chip design flow, being easy to integrate, small in occupied area and low in cost, and compensating the defect that the traditional sensor can only detect the limited area of the chip, being capable of being deployed at any position of the chip, greatly improving the fault attack resistance of the chip, and further improving the safety of the chip.

In some embodiments, the N registers include: n D flip-flops; the control signal source is positioned in the chip; each D trigger in the N D triggers is connected with a control signal source through a reset end or a set end; the D trigger connected with the control signal source through the reset end is adjacently arranged with the D trigger connected with the control signal source through the set end. The control signal source is used for setting initial data corresponding to each D trigger in the N D triggers by sending a control signal, namely setting the data of the output end of each D trigger in the N D triggers as the initial data corresponding to the trigger.

In the embodiment of the invention, the register in the cyclic shift register can be realized by a D trigger. Each D trigger comprises an input end, an output end, a reset end and a set end. The reset terminal is used for setting the initial data of the D trigger where the reset terminal is located to be a first value under the condition that the control signal is received, and the set terminal is used for setting the initial data of the D trigger where the reset terminal is located to be a second value under the condition that the control signal is received. In this way, since the D flip-flops connected to the control signal source through the reset terminal are adjacently arranged with the D flip-flops connected to the control signal source through the set terminal, the control signal source can enable the D flip-flops of which the initial data is the first value and the initial data is the second value to be adjacently arranged by sending the control signal to the N D flip-flops and setting the initial data of each D flip-flop of the N D flip-flops.

In some embodiments, the control signal source may perform data initialization of the cyclic shift register 10 by sending a control signal, and thus the cyclic shift register 10 may perform data shifting based on initial data of which the first value and the second value are adjacently arranged, and the detection circuit 11 detects whether the chip is attacked according to the periodically updated N-bit data.

In some embodiments, in the case of determining that the chip is attacked, the data state of the cyclic shift register 10 is in an error or illegal state at this time, and cannot be automatically restored to the normal data state in which the first value and the second value are adjacently arranged. The control signal source can reset the data of the cyclic shift register 10 by sending a control signal, so that the data can be recovered from an error or illegal state, and the subsequent chip attack detection can be continued.

In some embodiments, N D flip-flops are connected to the same clock source; the clock source is positioned in the chip; the clock source is used for providing a clock cycle signal for synchronization for each of the N D flip-flops.

In the embodiment of the invention, each D flip-flop further includes a clock terminal, and the clock terminal of each D flip-flop in the N D flip-flops is connected to the same clock source. The clock source is located inside the chip and is not controlled or affected by the outside. The clock source generates a clock cycle signal with which each D flip-flop can synchronize the data shift. For example, each D flip-flop may have a rising edge of a clock cycle signal as a periodic trigger signal, and the N D flip-flops shift data synchronously at the rising edge of each clock cycle signal.

Referring to fig. 6, fig. 6 is a schematic diagram of an attack detection circuit according to an embodiment of the present invention. As shown in fig. 6, the N D flip-flops described above may include 4D flip-flops shown in fig. 6: d flip-flop 610, D flip-flop 611, D flip-flop 612, and D flip-flop 613. Each D trigger comprises an input end, an output end, a clock end, a setting end and a resetting end. The input end of the D flip-flop 610 is connected to the output end of the D flip-flop 613, the output end of the D flip-flop 610 is connected to the input end of the D flip-flop 611, the output end of the D flip-flop 611 is connected to the input end of the D flip-flop 612, and the output end of the D flip-flop 612 is connected to the input end of the D flip-flop 613. The initial data of D flip-flop 610 may be 0, the initial data of D flip-flop 611 may be 1, the initial data of D flip-flop 612 may be 0, and the initial data of D flip-flop 613 may be 1. I.e. the initial data of the 4D flip-flops are 0101 adjacently arranged. Here, 0 corresponds to a first value, and 1 corresponds to a second value.

As shown in fig. 6, the control signal source 60 is connected to the reset terminal of the D flip-flop 610; the control signal source 60 is connected to the set end of the D flip-flop 611, the control signal source 60 is connected to the reset end of the D flip-flop 612, and the control signal source 60 is connected to the set end of the D flip-flop 613. Namely, the D trigger connected with the control signal source through the reset end and the D trigger connected with the control signal source through the set end are adjacently arranged. The clock terminals of each of the D flip-flops 610, 611, 612, and 613 are connected to the same clock source (not shown). The D flip-flop 610, the D flip-flop 611, the D flip-flop 612, and the D flip-flop 613 are configured to periodically synchronize, based on a control signal sent by the control signal source 60, storing data received at an input terminal thereof at an output terminal thereof according to a clock period signal provided by the clock source, and transmitting the data to a next D flip-flop to periodically update 4-bit data corresponding to the 4D flip-flops, thereby implementing cyclic data shift.

As shown in fig. 6, the N xor gates 110 may include: exclusive or gate 620, exclusive or gate 621, exclusive or gate 622, and exclusive or gate 623. Wherein the input and output of the D flip-flop 610 are connected to two inputs of the xor gate 620; the input and output of the D flip-flop 611 are connected to the two inputs of the exclusive OR gate 621; the input and output of the D flip-flop 612 are connected to the two inputs of the xor gate 622; the input and output of the D flip-flop 613 are connected to the two inputs of the exclusive or gate 623. The exclusive or circuit 620, the exclusive or circuit 621, the exclusive or circuit 622, and the exclusive or circuit 623 are configured to output 1 (corresponding to a fourth value) when the data of the input terminal and the output terminal of the D flip-flop to which they are connected are different, and output 0 (corresponding to a third value) when the data of the input terminal and the output terminal of the D flip-flop to which they are connected are the same.

As shown in fig. 6, the output terminals of the exclusive or circuits 620, 621, 622 and 623 are connected to the input terminal of the nand gate 624. A nand gate 624 for performing a nand operation on the data output from the xor circuits 620, 621, 622, and 623, and outputting a 1 when the data output from the xor circuits 620, 621, 622, and 623 contains 0; when the data output from the exclusive or gate 620, the exclusive or gate 621, the exclusive or gate 622, and the exclusive or gate 623 are all 1, 0 is output. In some embodiments, 0 represents a low level signal and 1 represents a high level signal, then when the nand gate 624 outputs a low level signal, it may be determined that the chip is not under attack; when the nand gate 624 outputs a high level signal, it is determined that the chip is attacked, and the high level signal output from the nand gate 624 may be used as an alarm signal.

In the embodiment of the present invention, based on fig. 6, referring to fig. 7, fig. 7 is a schematic diagram of an operation timing sequence of an attack detection circuit according to the embodiment of the present invention. In fig. 7, the flip-flop data state characterizes the 4-bit data corresponding to the 4D flip-flops in fig. 6. S0 represents a level signal output by the exclusive or circuit 620, S1 represents a level signal output by the exclusive or circuit 621; s2 represents a level signal output by the exclusive OR gate 622; s3 represents the signal output by the exclusive or gate 623. S4 represents the level signal output by the nand gate 624. Here, the low level signal indicates that the data output by the digital circuit is 0, and the high level signal indicates that the data output by the digital circuit is 1.

As shown in fig. 7, in the 1 st clock cycle and the 2 nd clock cycle, the control signal is a low level signal, that is, the control signal source does not send out the control signal, and the attack detection circuit does not start attack detection. At this time, the data stored in the 4D flip-flops are all initial data, and the corresponding 4-bit data is 0101. The data output from the exclusive or gate 620, the exclusive or gate 621, the exclusive or gate 622, and the exclusive or gate 623 are all 1, and the corresponding S0, S1, S2, and S3 are all high level signals. The data output by the nand gate 624 is 0, corresponding to S4 being a low signal.

As shown in fig. 7, at the rising edge of the 3 rd clock cycle, the control signal source sends out a high level signal as the control signal, and the 4D flip-flops shift synchronous data with the rising edge of each clock cycle as the periodic trigger signal in the high level time of the control signal, obtain 1010 from 0101 at the 3 rd clock cycle, obtain 0101 from 1010 at the 4 th clock cycle, and obtain 1010 from 0101 at the 5 th clock cycle. It can be seen that if the chip is not attacked, the cyclic shift registers corresponding to the 4D flip-flops will always be cyclically shifted according to this state, and the data at the input and output of each D flip-flop will always remain in the opposite state. In this way, S0, S1, S2, and S3 corresponding to the exclusive or gate 623 are high-level signals, and S4 corresponding to the nand gate 624 is a low-level signal, in the exclusive or gate 620, the exclusive or gate 621, and the exclusive or gate 622.

As shown in fig. 7, at the 6 th clock cycle, the 4-bit data corresponding to the 4D flip-flops becomes 1011, and consecutive 1 s appear, that is, the data at the input and output of the D flip-flop 610 are the same, and the data at the input and output of the D flip-flop 613 are the same. Thus, the exclusive or gate 620 connected to the D flip-flop 610 outputs 0, and the exclusive or gate 623 connected to the D flip-flop 613 outputs 0, i.e., S0 and S3 are pulled from the high level signal to the low level signal. Since S0 and S3 become low-level signals, S4 corresponding to the nand gate 624 is pulled up to high-level signals, so that S4 of the high-level signals can be used as an alarm signal to prompt that the chip is attacked.

At the 7 th clock cycle, the 4D flip-flops are cyclically shifted based on 1011 to 1101 such that S0 and S1 are low and S4 remains high. The cyclic shift at clock cycle 8 results in 1110 such that S1 and S2 are low and S4 remains high. The 4-bit data corresponding to the 4D flip-flops in each subsequent clock cycle will be continuously 1, so that at least 2 of the S0 to S3 signals are 0, and thus S4 remains high. Only after the control signal source is reset from low level to high level, the 4D triggers can be restored to the initial data of 0101 again so as to carry out the next chip attack detection.

It can be understood that, unlike the conventional shift register, the normal state transition of the cyclic shift register in the embodiment of the present invention is not controlled externally, the clock and the control signal are both from the inside of the chip, and the initial data are generated by respectively controlling the set end and the reset end of the D flip-flop through the control signal. Thus, unless attacked externally. The normal state transition of the cyclic shift register in the embodiment of the present invention is that the first value and the second value are adjacently arranged, for example, N-bit data updated each time are adjacently arranged with 0 and 1. Once the illegal data state (such as continuous 0 or continuous 1) is entered, the chip is detected and determined to be attacked, thereby triggering an alarm signal. The embodiment of the invention has low realization cost and is easy to be deployed in a large area, thereby greatly improving the safety of the chip.

Based on the above attack detection circuit, an embodiment of the present invention provides a chip including at least one attack detection circuit described in any of the foregoing embodiments, the at least one attack detection circuit being disposed at least one location within the chip. Referring to fig. 8, fig. 8 is a schematic diagram of a position deployment of at least one attack detection circuit in a chip according to an embodiment of the present invention. As shown in fig. 8, the chip 8 includes an attack detection circuit 81, an attack detection circuit 82, an attack detection circuit 83, an attack detection circuit 84, and an attack detection circuit 85. The attack detection circuit 81, the attack detection circuit 82, the attack detection circuit 83, the attack detection circuit 84, and the attack detection circuit 85 are disposed at different positions of the chip 8, respectively. In some embodiments, a greater number of attack detection circuits may be included in the chip 8, and the embodiment of the present invention is not limited, and specifically selected according to the actual situation.

In some embodiments, at least one attack detection circuit is configured to generate an alert signal to indicate that the chip is currently under attack if it is determined that the chip is under attack; in this way, the chip can process the alarm signal. It should be noted that the alarm signal generated by the at least one attack detection circuit may be one or more, and the chip processes the alarm signal when receiving or detecting any alarm signal.

In some embodiments, the chip may perform a corresponding operation according to a preset security policy in the case of detecting or receiving the alarm signal. For example, the chip may cease operation and enter a secure state in response to the alert signal. Referring to fig. 9, fig. 9 is a schematic diagram of a connection relationship between an attack detection circuit and a signal processing module according to an embodiment of the present invention. As shown in fig. 9, at least one attack detection circuit in the chip may include: attack detection circuit 901, attack detection circuit 902, and attack detection circuit 903; the attack detection circuit 901, the attack detection circuit 902 and the attack detection circuit 903 are connected with a signal processing module 910 in a chip, and one or more alarm signals are generated when one or more of the attack detection circuit 901, the attack detection circuit 902 and the attack detection circuit 903 determines that the chip is attacked by detecting the data state of the cyclic shift register. The signal processing module 910 in the chip may respond to the alarm signal to stop the chip and enter a safe state, such as triggering a chip reset or interrupt, to prevent leakage of sensitive information and fail a fault attack.

In an actual scene, when an attacker attacks a chip, because the specific position of a target circuit to be attacked in the chip cannot be judged, or because the attack to one or a plurality of transistors cannot be accurately controlled, the attack attempt can be carried out continuously only in each area of the chip, but the embodiment of the invention distributes the attack detection circuit in each area of the chip, once the attacker attacks the area where the attack detection circuit is located, the state of a cyclic shift register in the attack detection circuit is wrong, the chip can be detected to be attacked at present, and then an alarm is triggered.

In some embodiments, the attack detection circuit can be used as an independent circuit module to perform attack detection without affecting the original circuit structure of the chip, so that at least one attack detection circuit can be flexibly deployed at a plurality of positions in the chip, and the protection range of the chip is enlarged. Illustratively, at least one attack detection circuit may be mixed with other circuits in the chip, hidden in various areas of the chip, to provide protection for chip security. Or, in the area with higher security requirement, such as a memory for storing sensitive information, some attack detection circuits can be deployed more, or the attack detection circuits and the cryptographic operation module are mixed together, so that the protection of the circuit is enhanced. Alternatively, the attack detection circuit may be disposed as a dummy cell (dummy cell) in a chip spare position to save chip cost and the like. The embodiment of the present invention is not limited, and is specifically selected according to the actual situation.

It can be understood that the attack detection circuit in the embodiment of the invention is realized based on a digital circuit, has small area and low cost, is independent to form a module, does not change the design flow of the chip, is easy to integrate, can be deployed at any plurality of positions of the chip, and increases the attack detection range, thereby greatly improving the attack detection capability of the chip and further improving the safety of the chip.

In some embodiments, at least one attack detection circuit corresponds to at least one alert number; the chip further comprises: a signal processing module; and each attack detection circuit in the at least one attack detection circuit is used for generating an alarm signal corresponding to each attack detection circuit according to the alarm number corresponding to the attack detection circuit and sending the alarm signal to the signal processing module under the condition that the chip is determined to be attacked.

And the signal processing module is also used for processing each alarm signal according to the alarm number of each alarm signal in the at least one alarm signal under the condition that the at least one alarm signal is received.

In the embodiment of the invention, at least one attack detection circuit in the chip can be numbered in advance, namely, the at least one attack detection circuit corresponds to at least one alarm number; at least one alarm number is preset. Since the at least one attack detection circuit is disposed at least one location on the chip, it is understood that the at least one alert number may also characterize or correspond to the at least one location on the chip.

In the embodiment of the invention, each attack detection circuit in at least one attack detection circuit can determine that the chip is attacked under the condition that the cyclic shift register in the attack detection circuit has a continuous first value or a continuous second value. The attack detection circuit can generate a corresponding alarm signal according to the alarm number corresponding to the attack detection circuit and send the alarm signal to the signal processing module of the chip.

In the embodiment of the invention, the signal processing module of the chip can determine the processing mode of each alarm signal according to the alarm number of each alarm signal in at least one alarm signal under the condition of receiving at least one alarm signal, and process each alarm signal according to the determined processing mode. Wherein the at least one alert signal may be sent by one or more of the at least one attack detection circuits.

In some embodiments, the at least one alert number may correspond to at least one preset processing mode. For example, since at least one alarm number represents at least one location on the chip, different preset processing modes can be configured according to different security policies for different locations. In this way, when the alarm signal containing the alarm number is received, the alarm signal can be processed according to the preset processing mode corresponding to the security policy matched with the position represented by the alarm number, so that when the attack on different positions of the chip is detected, different processing modes can be adopted, and the flexibility of the attack resistance mode is improved.

In some examples, the chip may also combine with a software and hardware module of the electronic device, and perform alarm prompting in at least one mode according to the alarm signal. For example, the software and hardware module of the electronic device may be used to report the alarm signal to the upper layer interface for displaying an alarm, so as to prompt the user of the electronic device that the chip in the electronic device is currently attacked. The invention can also be used or combined with a sound module, a light module and the like on the electronic equipment to carry out alarm prompt and the like, and the alarm prompt and the like are specifically selected according to actual conditions, and the embodiment of the invention is not limited.

In some embodiments, a schematic structural diagram of a chip provided in an embodiment of the present invention may be shown in fig. 10. The chip 9 includes: at least one attack detection circuit 90, a memory 91 and a processor 92. Wherein at least one attack detection circuit 90 is electrically or data connected to a processor 92; the memory 91 and the processor 92 are connected by a communication bus 93; at least one attack detection circuit 80 for generating an alarm signal in case it is determined that the chip is attacked; a memory 91 for storing executable instructions; a processor 92 for processing the alert signal by executing the executable instructions stored in the memory 91.

In some embodiments, the processor 92 is further configured to, in the event that at least one alert signal is received, process each alert signal according to an alert number for each of the at least one alert signal.

In some embodiments, the processor 92 is further configured to control the chip to stop operating and enter a secure state in response to the alarm signal.

In some embodiments, the processor 92 is further configured to alert the user in at least one form based on the alert signal.

Based on the foregoing embodiments, an electronic device is provided in the embodiments of the present invention, where the electronic device includes any of the chips described in the foregoing embodiments, and may, for example, include at least one attack detection circuit 90, a memory 91, and a processor 92 as shown in the chip 9 in fig. 10.

In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

As an example, the executable instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a hypertext markup language (Hyper Text Markup Language, HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).

As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or, alternatively, distributed across multiple sites and interconnected by a communication network.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and scope of the present invention are included in the protection scope of the present invention.

Claims

1. An attack detection circuit for use with a chip, the circuit comprising:

the device comprises a cyclic shift register and a detection circuit, wherein the cyclic shift register comprises N registers, the output end of each register in the front N-1 registers of the N registers is connected with the input end of the next register, and the output end of the N register is connected with the input end of the 1 st register; the registers with initial data as a first value and the registers with initial values as a second value in the N registers are adjacently arranged, and the N registers are connected with the same control signal source; n is an even number greater than 0; the control signal source is positioned in the chip;

The control signal source is used for resetting data of the cyclic shift register by sending a control signal so that the cyclic shift register performs data shift based on initial data adjacently arranged by a first value and a second value;

2. The circuit of claim 1, wherein the detection circuit comprises: n exclusive OR gate circuits; the input end and the output end of each register in the N registers are respectively connected with two input ends of an exclusive OR gate;

each of the N exclusive or circuits is configured to perform exclusive or processing on data of two input ends of the N exclusive or circuits, and output a third value when the data of the two input ends are the same;

And the detection circuit is also used for determining that the chip is attacked under the condition that the data output by the N exclusive OR gate circuits contain the third value.

3. The circuit of claim 2, wherein the detection circuit further comprises: the N output ends of the N exclusive OR gates are connected with the input end of the NAND gate;

the NAND gate is used for outputting a fourth value when the data output by the N exclusive OR gates contain the third value;

the detection circuit is further configured to determine that the chip is attacked when the nand gate outputs the fourth value.

4. A circuit according to any one of claims 1-3, wherein the N registers comprise: n D flip-flops; each D trigger in the N D triggers is connected with the control signal source through a reset end or a set end; the D trigger connected with the control signal source through the reset end is adjacently arranged with the D trigger connected with the control signal source through the set end;

the control signal source is used for setting initial data corresponding to each D trigger in the N D triggers by sending the control signal; wherein,

The reset terminal is used for setting the initial data of the D trigger to the first value under the condition that the control signal is received;

the setting terminal is used for setting the initial data of the D trigger to the second value under the condition that the control signal is received.

5. The circuit of claim 4, wherein the N D flip-flops are connected to the same clock source; the clock source is positioned inside the chip;

the clock source is configured to provide a clock cycle signal for synchronization for each D flip-flop of the N D flip-flops.

6. A chip comprising at least one attack detection circuit according to any of claims 1-5; at least one attack detection circuit is disposed at least one location within the chip;

the chip is used for processing the alarm signal.

7. The chip of claim 6, wherein the at least one attack detection circuit corresponds to at least one alert number; the chip further includes: a signal processing module;

Each attack detection circuit in the at least one attack detection circuit is used for generating an alarm signal corresponding to each attack detection circuit according to an alarm number corresponding to the chip under the condition that the chip is determined to be attacked, and sending the alarm signal to the signal processing module;

the signal processing module is further configured to, when at least one alarm signal is received, process each alarm signal according to an alarm number of each alarm signal in the at least one alarm signal.

8. The chip of claim 6, wherein the chip further comprises a plurality of chips,

the chip is also used for responding to the alarm signal, stopping operation and entering a safe state.

9. The chip according to any one of claims 6 to 8, wherein,

the chip is also used for carrying out alarm prompt in at least one form according to the alarm signal.

10. An electronic device, the electronic device comprising: the chip of any one of claims 6-9.